Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-2.6] / drivers / video / nvidia / nv_hw.c
1  /***************************************************************************\
2 |*                                                                           *|
3 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
4 |*                                                                           *|
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12 |*     as follows:                                                           *|
13 |*                                                                           *|
14 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
15 |*                                                                           *|
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37 |*                                                                           *|
38  \***************************************************************************/
39
40 /*
41  * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42  * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43  * where the source code is provided "as is" without warranty of any kind.
44  * The only usage restriction is for the copyright notices to be retained
45  * whenever code is used.
46  *
47  * Antonino Daplas <adaplas@pol.net> 2005-03-11
48  */
49
50 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.4 2003/11/03 05:11:25 tsi Exp $ */
51
52 #include <linux/pci.h>
53 #include "nv_type.h"
54 #include "nv_local.h"
55 #include "nv_proto.h"
56
57 void NVLockUnlock(struct nvidia_par *par, int Lock)
58 {
59         u8 cr11;
60
61         VGA_WR08(par->PCIO, 0x3D4, 0x1F);
62         VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
63
64         VGA_WR08(par->PCIO, 0x3D4, 0x11);
65         cr11 = VGA_RD08(par->PCIO, 0x3D5);
66         if (Lock)
67                 cr11 |= 0x80;
68         else
69                 cr11 &= ~0x80;
70         VGA_WR08(par->PCIO, 0x3D5, cr11);
71 }
72
73 int NVShowHideCursor(struct nvidia_par *par, int ShowHide)
74 {
75         int cur = par->CurrentState->cursor1;
76
77         par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) |
78             (ShowHide & 0x01);
79         VGA_WR08(par->PCIO, 0x3D4, 0x31);
80         VGA_WR08(par->PCIO, 0x3D5, par->CurrentState->cursor1);
81
82         if (par->Architecture == NV_ARCH_40)
83                 NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300));
84
85         return (cur & 0x01);
86 }
87
88 /****************************************************************************\
89 *                                                                            *
90 * The video arbitration routines calculate some "magic" numbers.  Fixes      *
91 * the snow seen when accessing the framebuffer without it.                   *
92 * It just works (I hope).                                                    *
93 *                                                                            *
94 \****************************************************************************/
95
96 typedef struct {
97         int graphics_lwm;
98         int video_lwm;
99         int graphics_burst_size;
100         int video_burst_size;
101         int valid;
102 } nv4_fifo_info;
103
104 typedef struct {
105         int pclk_khz;
106         int mclk_khz;
107         int nvclk_khz;
108         char mem_page_miss;
109         char mem_latency;
110         int memory_width;
111         char enable_video;
112         char gr_during_vid;
113         char pix_bpp;
114         char mem_aligned;
115         char enable_mp;
116 } nv4_sim_state;
117
118 typedef struct {
119         int graphics_lwm;
120         int video_lwm;
121         int graphics_burst_size;
122         int video_burst_size;
123         int valid;
124 } nv10_fifo_info;
125
126 typedef struct {
127         int pclk_khz;
128         int mclk_khz;
129         int nvclk_khz;
130         char mem_page_miss;
131         char mem_latency;
132         int memory_type;
133         int memory_width;
134         char enable_video;
135         char gr_during_vid;
136         char pix_bpp;
137         char mem_aligned;
138         char enable_mp;
139 } nv10_sim_state;
140
141 static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk,
142                         unsigned int *NVClk)
143 {
144         unsigned int pll, N, M, MB, NB, P;
145
146         if (par->Architecture >= NV_ARCH_40) {
147                 pll = NV_RD32(par->PMC, 0x4020);
148                 P = (pll >> 16) & 0x07;
149                 pll = NV_RD32(par->PMC, 0x4024);
150                 M = pll & 0xFF;
151                 N = (pll >> 8) & 0xFF;
152                 if (((par->Chipset & 0xfff0) == 0x0290) ||
153                         ((par->Chipset & 0xfff0) == 0x0390) ||
154                         ((par->Chipset & 0xfff0) == 0x02E0)) {
155                         MB = 1;
156                         NB = 1;
157                 } else {
158                         MB = (pll >> 16) & 0xFF;
159                         NB = (pll >> 24) & 0xFF;
160                 }
161                 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
162
163                 pll = NV_RD32(par->PMC, 0x4000);
164                 P = (pll >> 16) & 0x03;
165                 pll = NV_RD32(par->PMC, 0x4004);
166                 M = pll & 0xFF;
167                 N = (pll >> 8) & 0xFF;
168                 MB = (pll >> 16) & 0xFF;
169                 NB = (pll >> 24) & 0xFF;
170
171                 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
172         } else if (par->twoStagePLL) {
173                 pll = NV_RD32(par->PRAMDAC0, 0x0504);
174                 M = pll & 0xFF;
175                 N = (pll >> 8) & 0xFF;
176                 P = (pll >> 16) & 0x0F;
177                 pll = NV_RD32(par->PRAMDAC0, 0x0574);
178                 if (pll & 0x80000000) {
179                         MB = pll & 0xFF;
180                         NB = (pll >> 8) & 0xFF;
181                 } else {
182                         MB = 1;
183                         NB = 1;
184                 }
185                 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
186
187                 pll = NV_RD32(par->PRAMDAC0, 0x0500);
188                 M = pll & 0xFF;
189                 N = (pll >> 8) & 0xFF;
190                 P = (pll >> 16) & 0x0F;
191                 pll = NV_RD32(par->PRAMDAC0, 0x0570);
192                 if (pll & 0x80000000) {
193                         MB = pll & 0xFF;
194                         NB = (pll >> 8) & 0xFF;
195                 } else {
196                         MB = 1;
197                         NB = 1;
198                 }
199                 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
200         } else
201             if (((par->Chipset & 0x0ff0) == 0x0300) ||
202                 ((par->Chipset & 0x0ff0) == 0x0330)) {
203                 pll = NV_RD32(par->PRAMDAC0, 0x0504);
204                 M = pll & 0x0F;
205                 N = (pll >> 8) & 0xFF;
206                 P = (pll >> 16) & 0x07;
207                 if (pll & 0x00000080) {
208                         MB = (pll >> 4) & 0x07;
209                         NB = (pll >> 19) & 0x1f;
210                 } else {
211                         MB = 1;
212                         NB = 1;
213                 }
214                 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
215
216                 pll = NV_RD32(par->PRAMDAC0, 0x0500);
217                 M = pll & 0x0F;
218                 N = (pll >> 8) & 0xFF;
219                 P = (pll >> 16) & 0x07;
220                 if (pll & 0x00000080) {
221                         MB = (pll >> 4) & 0x07;
222                         NB = (pll >> 19) & 0x1f;
223                 } else {
224                         MB = 1;
225                         NB = 1;
226                 }
227                 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
228         } else {
229                 pll = NV_RD32(par->PRAMDAC0, 0x0504);
230                 M = pll & 0xFF;
231                 N = (pll >> 8) & 0xFF;
232                 P = (pll >> 16) & 0x0F;
233                 *MClk = (N * par->CrystalFreqKHz / M) >> P;
234
235                 pll = NV_RD32(par->PRAMDAC0, 0x0500);
236                 M = pll & 0xFF;
237                 N = (pll >> 8) & 0xFF;
238                 P = (pll >> 16) & 0x0F;
239                 *NVClk = (N * par->CrystalFreqKHz / M) >> P;
240         }
241 }
242
243 static void nv4CalcArbitration(nv4_fifo_info * fifo, nv4_sim_state * arb)
244 {
245         int data, pagemiss, cas, width, video_enable, bpp;
246         int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
247         int found, mclk_extra, mclk_loop, cbs, m1, p1;
248         int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
249         int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
250         int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt, clwm;
251
252         fifo->valid = 1;
253         pclk_freq = arb->pclk_khz;
254         mclk_freq = arb->mclk_khz;
255         nvclk_freq = arb->nvclk_khz;
256         pagemiss = arb->mem_page_miss;
257         cas = arb->mem_latency;
258         width = arb->memory_width >> 6;
259         video_enable = arb->enable_video;
260         bpp = arb->pix_bpp;
261         mp_enable = arb->enable_mp;
262         clwm = 0;
263         vlwm = 0;
264         cbs = 128;
265         pclks = 2;
266         nvclks = 2;
267         nvclks += 2;
268         nvclks += 1;
269         mclks = 5;
270         mclks += 3;
271         mclks += 1;
272         mclks += cas;
273         mclks += 1;
274         mclks += 1;
275         mclks += 1;
276         mclks += 1;
277         mclk_extra = 3;
278         nvclks += 2;
279         nvclks += 1;
280         nvclks += 1;
281         nvclks += 1;
282         if (mp_enable)
283                 mclks += 4;
284         nvclks += 0;
285         pclks += 0;
286         found = 0;
287         vbs = 0;
288         while (found != 1) {
289                 fifo->valid = 1;
290                 found = 1;
291                 mclk_loop = mclks + mclk_extra;
292                 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
293                 us_n = nvclks * 1000 * 1000 / nvclk_freq;
294                 us_p = nvclks * 1000 * 1000 / pclk_freq;
295                 if (video_enable) {
296                         video_drain_rate = pclk_freq * 2;
297                         crtc_drain_rate = pclk_freq * bpp / 8;
298                         vpagemiss = 2;
299                         vpagemiss += 1;
300                         crtpagemiss = 2;
301                         vpm_us =
302                             (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
303                         if (nvclk_freq * 2 > mclk_freq * width)
304                                 video_fill_us =
305                                     cbs * 1000 * 1000 / 16 / nvclk_freq;
306                         else
307                                 video_fill_us =
308                                     cbs * 1000 * 1000 / (8 * width) /
309                                     mclk_freq;
310                         us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
311                         vlwm = us_video * video_drain_rate / (1000 * 1000);
312                         vlwm++;
313                         vbs = 128;
314                         if (vlwm > 128)
315                                 vbs = 64;
316                         if (vlwm > (256 - 64))
317                                 vbs = 32;
318                         if (nvclk_freq * 2 > mclk_freq * width)
319                                 video_fill_us =
320                                     vbs * 1000 * 1000 / 16 / nvclk_freq;
321                         else
322                                 video_fill_us =
323                                     vbs * 1000 * 1000 / (8 * width) /
324                                     mclk_freq;
325                         cpm_us =
326                             crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
327                         us_crt =
328                             us_video + video_fill_us + cpm_us + us_m + us_n +
329                             us_p;
330                         clwm = us_crt * crtc_drain_rate / (1000 * 1000);
331                         clwm++;
332                 } else {
333                         crtc_drain_rate = pclk_freq * bpp / 8;
334                         crtpagemiss = 2;
335                         crtpagemiss += 1;
336                         cpm_us =
337                             crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
338                         us_crt = cpm_us + us_m + us_n + us_p;
339                         clwm = us_crt * crtc_drain_rate / (1000 * 1000);
340                         clwm++;
341                 }
342                 m1 = clwm + cbs - 512;
343                 p1 = m1 * pclk_freq / mclk_freq;
344                 p1 = p1 * bpp / 8;
345                 if ((p1 < m1) && (m1 > 0)) {
346                         fifo->valid = 0;
347                         found = 0;
348                         if (mclk_extra == 0)
349                                 found = 1;
350                         mclk_extra--;
351                 } else if (video_enable) {
352                         if ((clwm > 511) || (vlwm > 255)) {
353                                 fifo->valid = 0;
354                                 found = 0;
355                                 if (mclk_extra == 0)
356                                         found = 1;
357                                 mclk_extra--;
358                         }
359                 } else {
360                         if (clwm > 519) {
361                                 fifo->valid = 0;
362                                 found = 0;
363                                 if (mclk_extra == 0)
364                                         found = 1;
365                                 mclk_extra--;
366                         }
367                 }
368                 if (clwm < 384)
369                         clwm = 384;
370                 if (vlwm < 128)
371                         vlwm = 128;
372                 data = (int)(clwm);
373                 fifo->graphics_lwm = data;
374                 fifo->graphics_burst_size = 128;
375                 data = (int)((vlwm + 15));
376                 fifo->video_lwm = data;
377                 fifo->video_burst_size = vbs;
378         }
379 }
380
381 static void nv4UpdateArbitrationSettings(unsigned VClk,
382                                          unsigned pixelDepth,
383                                          unsigned *burst,
384                                          unsigned *lwm, struct nvidia_par *par)
385 {
386         nv4_fifo_info fifo_data;
387         nv4_sim_state sim_data;
388         unsigned int MClk, NVClk, cfg1;
389
390         nvGetClocks(par, &MClk, &NVClk);
391
392         cfg1 = NV_RD32(par->PFB, 0x00000204);
393         sim_data.pix_bpp = (char)pixelDepth;
394         sim_data.enable_video = 0;
395         sim_data.enable_mp = 0;
396         sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
397             128 : 64;
398         sim_data.mem_latency = (char)cfg1 & 0x0F;
399         sim_data.mem_aligned = 1;
400         sim_data.mem_page_miss =
401             (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
402         sim_data.gr_during_vid = 0;
403         sim_data.pclk_khz = VClk;
404         sim_data.mclk_khz = MClk;
405         sim_data.nvclk_khz = NVClk;
406         nv4CalcArbitration(&fifo_data, &sim_data);
407         if (fifo_data.valid) {
408                 int b = fifo_data.graphics_burst_size >> 4;
409                 *burst = 0;
410                 while (b >>= 1)
411                         (*burst)++;
412                 *lwm = fifo_data.graphics_lwm >> 3;
413         }
414 }
415
416 static void nv10CalcArbitration(nv10_fifo_info * fifo, nv10_sim_state * arb)
417 {
418         int data, pagemiss, width, video_enable, bpp;
419         int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
420         int nvclk_fill;
421         int found, mclk_extra, mclk_loop, cbs, m1;
422         int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
423         int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
424         int vus_m;
425         int vpm_us, us_video, cpm_us, us_crt, clwm;
426         int clwm_rnd_down;
427         int m2us, us_pipe_min, p1clk, p2;
428         int min_mclk_extra;
429         int us_min_mclk_extra;
430
431         fifo->valid = 1;
432         pclk_freq = arb->pclk_khz;      /* freq in KHz */
433         mclk_freq = arb->mclk_khz;
434         nvclk_freq = arb->nvclk_khz;
435         pagemiss = arb->mem_page_miss;
436         width = arb->memory_width / 64;
437         video_enable = arb->enable_video;
438         bpp = arb->pix_bpp;
439         mp_enable = arb->enable_mp;
440         clwm = 0;
441
442         cbs = 512;
443
444         pclks = 4;      /* lwm detect. */
445
446         nvclks = 3;     /* lwm -> sync. */
447         nvclks += 2;    /* fbi bus cycles (1 req + 1 busy) */
448         /* 2 edge sync.  may be very close to edge so just put one. */
449         mclks = 1;
450         mclks += 1;     /* arb_hp_req */
451         mclks += 5;     /* ap_hp_req   tiling pipeline */
452
453         mclks += 2;     /* tc_req     latency fifo */
454         mclks += 2;     /* fb_cas_n_  memory request to fbio block */
455         mclks += 7;     /* sm_d_rdv   data returned from fbio block */
456
457         /* fb.rd.d.Put_gc   need to accumulate 256 bits for read */
458         if (arb->memory_type == 0)
459                 if (arb->memory_width == 64)    /* 64 bit bus */
460                         mclks += 4;
461                 else
462                         mclks += 2;
463         else if (arb->memory_width == 64)       /* 64 bit bus */
464                 mclks += 2;
465         else
466                 mclks += 1;
467
468         if ((!video_enable) && (arb->memory_width == 128)) {
469                 mclk_extra = (bpp == 32) ? 31 : 42;     /* Margin of error */
470                 min_mclk_extra = 17;
471         } else {
472                 mclk_extra = (bpp == 32) ? 8 : 4;       /* Margin of error */
473                 /* mclk_extra = 4; *//* Margin of error */
474                 min_mclk_extra = 18;
475         }
476
477         /* 2 edge sync.  may be very close to edge so just put one. */
478         nvclks += 1;
479         nvclks += 1;            /* fbi_d_rdv_n */
480         nvclks += 1;            /* Fbi_d_rdata */
481         nvclks += 1;            /* crtfifo load */
482
483         if (mp_enable)
484                 mclks += 4;     /* Mp can get in with a burst of 8. */
485         /* Extra clocks determined by heuristics */
486
487         nvclks += 0;
488         pclks += 0;
489         found = 0;
490         while (found != 1) {
491                 fifo->valid = 1;
492                 found = 1;
493                 mclk_loop = mclks + mclk_extra;
494                 /* Mclk latency in us */
495                 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
496                 /* Minimum Mclk latency in us */
497                 us_m_min = mclks * 1000 * 1000 / mclk_freq;
498                 us_min_mclk_extra = min_mclk_extra * 1000 * 1000 / mclk_freq;
499                 /* nvclk latency in us */
500                 us_n = nvclks * 1000 * 1000 / nvclk_freq;
501                 /* nvclk latency in us */
502                 us_p = pclks * 1000 * 1000 / pclk_freq;
503                 us_pipe_min = us_m_min + us_n + us_p;
504
505                 /* Mclk latency in us */
506                 vus_m = mclk_loop * 1000 * 1000 / mclk_freq;
507
508                 if (video_enable) {
509                         crtc_drain_rate = pclk_freq * bpp / 8;  /* MB/s */
510
511                         vpagemiss = 1;  /* self generating page miss */
512                         vpagemiss += 1; /* One higher priority before */
513
514                         crtpagemiss = 2;        /* self generating page miss */
515                         if (mp_enable)
516                                 crtpagemiss += 1;       /* if MA0 conflict */
517
518                         vpm_us =
519                             (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
520
521                         /* Video has separate read return path */
522                         us_video = vpm_us + vus_m;
523
524                         cpm_us =
525                             crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
526                         /* Wait for video */
527                         us_crt = us_video
528                             + cpm_us    /* CRT Page miss */
529                             + us_m + us_n + us_p        /* other latency */
530                             ;
531
532                         clwm = us_crt * crtc_drain_rate / (1000 * 1000);
533                         /* fixed point <= float_point - 1.  Fixes that */
534                         clwm++;
535                 } else {
536                     /* bpp * pclk/8 */
537                         crtc_drain_rate = pclk_freq * bpp / 8;
538
539                         crtpagemiss = 1;        /* self generating page miss */
540                         crtpagemiss += 1;       /* MA0 page miss */
541                         if (mp_enable)
542                                 crtpagemiss += 1;       /* if MA0 conflict */
543                         cpm_us =
544                             crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
545                         us_crt = cpm_us + us_m + us_n + us_p;
546                         clwm = us_crt * crtc_drain_rate / (1000 * 1000);
547                         /* fixed point <= float_point - 1.  Fixes that */
548                         clwm++;
549
550                         /* Finally, a heuristic check when width == 64 bits */
551                         if (width == 1) {
552                                 nvclk_fill = nvclk_freq * 8;
553                                 if (crtc_drain_rate * 100 >= nvclk_fill * 102)
554                                         /*Large number to fail */
555                                         clwm = 0xfff;
556
557                                 else if (crtc_drain_rate * 100 >=
558                                          nvclk_fill * 98) {
559                                         clwm = 1024;
560                                         cbs = 512;
561                                 }
562                         }
563                 }
564
565                 /*
566                    Overfill check:
567                  */
568
569                 clwm_rnd_down = ((int)clwm / 8) * 8;
570                 if (clwm_rnd_down < clwm)
571                         clwm += 8;
572
573                 m1 = clwm + cbs - 1024; /* Amount of overfill */
574                 m2us = us_pipe_min + us_min_mclk_extra;
575
576                 /* pclk cycles to drain */
577                 p1clk = m2us * pclk_freq / (1000 * 1000);
578                 p2 = p1clk * bpp / 8;   /* bytes drained. */
579
580                 if ((p2 < m1) && (m1 > 0)) {
581                         fifo->valid = 0;
582                         found = 0;
583                         if (min_mclk_extra == 0) {
584                                 if (cbs <= 32) {
585                                         /* Can't adjust anymore! */
586                                         found = 1;
587                                 } else {
588                                         /* reduce the burst size */
589                                         cbs = cbs / 2;
590                                 }
591                         } else {
592                                 min_mclk_extra--;
593                         }
594                 } else {
595                         if (clwm > 1023) {      /* Have some margin */
596                                 fifo->valid = 0;
597                                 found = 0;
598                                 if (min_mclk_extra == 0)
599                                         /* Can't adjust anymore! */
600                                         found = 1;
601                                 else
602                                         min_mclk_extra--;
603                         }
604                 }
605
606                 if (clwm < (1024 - cbs + 8))
607                         clwm = 1024 - cbs + 8;
608                 data = (int)(clwm);
609                 /*  printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n",
610                     clwm, data ); */
611                 fifo->graphics_lwm = data;
612                 fifo->graphics_burst_size = cbs;
613
614                 fifo->video_lwm = 1024;
615                 fifo->video_burst_size = 512;
616         }
617 }
618
619 static void nv10UpdateArbitrationSettings(unsigned VClk,
620                                           unsigned pixelDepth,
621                                           unsigned *burst,
622                                           unsigned *lwm,
623                                           struct nvidia_par *par)
624 {
625         nv10_fifo_info fifo_data;
626         nv10_sim_state sim_data;
627         unsigned int MClk, NVClk, cfg1;
628
629         nvGetClocks(par, &MClk, &NVClk);
630
631         cfg1 = NV_RD32(par->PFB, 0x0204);
632         sim_data.pix_bpp = (char)pixelDepth;
633         sim_data.enable_video = 1;
634         sim_data.enable_mp = 0;
635         sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0;
636         sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
637             128 : 64;
638         sim_data.mem_latency = (char)cfg1 & 0x0F;
639         sim_data.mem_aligned = 1;
640         sim_data.mem_page_miss =
641             (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
642         sim_data.gr_during_vid = 0;
643         sim_data.pclk_khz = VClk;
644         sim_data.mclk_khz = MClk;
645         sim_data.nvclk_khz = NVClk;
646         nv10CalcArbitration(&fifo_data, &sim_data);
647         if (fifo_data.valid) {
648                 int b = fifo_data.graphics_burst_size >> 4;
649                 *burst = 0;
650                 while (b >>= 1)
651                         (*burst)++;
652                 *lwm = fifo_data.graphics_lwm >> 3;
653         }
654 }
655
656 static void nv30UpdateArbitrationSettings (
657     struct nvidia_par *par,
658     unsigned int      *burst,
659     unsigned int      *lwm
660 )
661 {
662     unsigned int MClk, NVClk;
663     unsigned int fifo_size, burst_size, graphics_lwm;
664
665     fifo_size = 2048;
666     burst_size = 512;
667     graphics_lwm = fifo_size - burst_size;
668
669     nvGetClocks(par, &MClk, &NVClk);
670
671     *burst = 0;
672     burst_size >>= 5;
673     while(burst_size >>= 1) (*burst)++;
674     *lwm = graphics_lwm >> 3;
675 }
676
677 static void nForceUpdateArbitrationSettings(unsigned VClk,
678                                             unsigned pixelDepth,
679                                             unsigned *burst,
680                                             unsigned *lwm,
681                                             struct nvidia_par *par)
682 {
683         nv10_fifo_info fifo_data;
684         nv10_sim_state sim_data;
685         unsigned int M, N, P, pll, MClk, NVClk, memctrl;
686         struct pci_dev *dev;
687
688         if ((par->Chipset & 0x0FF0) == 0x01A0) {
689                 unsigned int uMClkPostDiv;
690                 dev = pci_get_bus_and_slot(0, 3);
691                 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
692                 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
693
694                 if (!uMClkPostDiv)
695                         uMClkPostDiv = 4;
696                 MClk = 400000 / uMClkPostDiv;
697         } else {
698                 dev = pci_get_bus_and_slot(0, 5);
699                 pci_read_config_dword(dev, 0x4c, &MClk);
700                 MClk /= 1000;
701         }
702         pci_dev_put(dev);
703         pll = NV_RD32(par->PRAMDAC0, 0x0500);
704         M = (pll >> 0) & 0xFF;
705         N = (pll >> 8) & 0xFF;
706         P = (pll >> 16) & 0x0F;
707         NVClk = (N * par->CrystalFreqKHz / M) >> P;
708         sim_data.pix_bpp = (char)pixelDepth;
709         sim_data.enable_video = 0;
710         sim_data.enable_mp = 0;
711         dev = pci_get_bus_and_slot(0, 1);
712         pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
713         pci_dev_put(dev);
714         sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
715         sim_data.memory_width = 64;
716
717         dev = pci_get_bus_and_slot(0, 3);
718         pci_read_config_dword(dev, 0, &memctrl);
719         pci_dev_put(dev);
720         memctrl >>= 16;
721
722         if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
723                 int dimm[3];
724
725                 dev = pci_get_bus_and_slot(0, 2);
726                 pci_read_config_dword(dev, 0x40, &dimm[0]);
727                 dimm[0] = (dimm[0] >> 8) & 0x4f;
728                 pci_read_config_dword(dev, 0x44, &dimm[1]);
729                 dimm[1] = (dimm[1] >> 8) & 0x4f;
730                 pci_read_config_dword(dev, 0x48, &dimm[2]);
731                 dimm[2] = (dimm[2] >> 8) & 0x4f;
732
733                 if ((dimm[0] + dimm[1]) != dimm[2]) {
734                         printk("nvidiafb: your nForce DIMMs are not arranged "
735                                "in optimal banks!\n");
736                 }
737                 pci_dev_put(dev);
738         }
739
740         sim_data.mem_latency = 3;
741         sim_data.mem_aligned = 1;
742         sim_data.mem_page_miss = 10;
743         sim_data.gr_during_vid = 0;
744         sim_data.pclk_khz = VClk;
745         sim_data.mclk_khz = MClk;
746         sim_data.nvclk_khz = NVClk;
747         nv10CalcArbitration(&fifo_data, &sim_data);
748         if (fifo_data.valid) {
749                 int b = fifo_data.graphics_burst_size >> 4;
750                 *burst = 0;
751                 while (b >>= 1)
752                         (*burst)++;
753                 *lwm = fifo_data.graphics_lwm >> 3;
754         }
755 }
756
757 /****************************************************************************\
758 *                                                                            *
759 *                          RIVA Mode State Routines                          *
760 *                                                                            *
761 \****************************************************************************/
762
763 /*
764  * Calculate the Video Clock parameters for the PLL.
765  */
766 static void CalcVClock(int clockIn,
767                        int *clockOut, u32 * pllOut, struct nvidia_par *par)
768 {
769         unsigned lowM, highM;
770         unsigned DeltaNew, DeltaOld;
771         unsigned VClk, Freq;
772         unsigned M, N, P;
773
774         DeltaOld = 0xFFFFFFFF;
775
776         VClk = (unsigned)clockIn;
777
778         if (par->CrystalFreqKHz == 13500) {
779                 lowM = 7;
780                 highM = 13;
781         } else {
782                 lowM = 8;
783                 highM = 14;
784         }
785
786         for (P = 0; P <= 4; P++) {
787                 Freq = VClk << P;
788                 if ((Freq >= 128000) && (Freq <= 350000)) {
789                         for (M = lowM; M <= highM; M++) {
790                                 N = ((VClk << P) * M) / par->CrystalFreqKHz;
791                                 if (N <= 255) {
792                                         Freq =
793                                             ((par->CrystalFreqKHz * N) /
794                                              M) >> P;
795                                         if (Freq > VClk)
796                                                 DeltaNew = Freq - VClk;
797                                         else
798                                                 DeltaNew = VClk - Freq;
799                                         if (DeltaNew < DeltaOld) {
800                                                 *pllOut =
801                                                     (P << 16) | (N << 8) | M;
802                                                 *clockOut = Freq;
803                                                 DeltaOld = DeltaNew;
804                                         }
805                                 }
806                         }
807                 }
808         }
809 }
810
811 static void CalcVClock2Stage(int clockIn,
812                              int *clockOut,
813                              u32 * pllOut,
814                              u32 * pllBOut, struct nvidia_par *par)
815 {
816         unsigned DeltaNew, DeltaOld;
817         unsigned VClk, Freq;
818         unsigned M, N, P;
819
820         DeltaOld = 0xFFFFFFFF;
821
822         *pllBOut = 0x80000401;  /* fixed at x4 for now */
823
824         VClk = (unsigned)clockIn;
825
826         for (P = 0; P <= 6; P++) {
827                 Freq = VClk << P;
828                 if ((Freq >= 400000) && (Freq <= 1000000)) {
829                         for (M = 1; M <= 13; M++) {
830                                 N = ((VClk << P) * M) /
831                                     (par->CrystalFreqKHz << 2);
832                                 if ((N >= 5) && (N <= 255)) {
833                                         Freq =
834                                             (((par->CrystalFreqKHz << 2) * N) /
835                                              M) >> P;
836                                         if (Freq > VClk)
837                                                 DeltaNew = Freq - VClk;
838                                         else
839                                                 DeltaNew = VClk - Freq;
840                                         if (DeltaNew < DeltaOld) {
841                                                 *pllOut =
842                                                     (P << 16) | (N << 8) | M;
843                                                 *clockOut = Freq;
844                                                 DeltaOld = DeltaNew;
845                                         }
846                                 }
847                         }
848                 }
849         }
850 }
851
852 /*
853  * Calculate extended mode parameters (SVGA) and save in a
854  * mode state structure.
855  */
856 void NVCalcStateExt(struct nvidia_par *par,
857                     RIVA_HW_STATE * state,
858                     int bpp,
859                     int width,
860                     int hDisplaySize, int height, int dotClock, int flags)
861 {
862         int pixelDepth, VClk = 0;
863         /*
864          * Save mode parameters.
865          */
866         state->bpp = bpp;       /* this is not bitsPerPixel, it's 8,15,16,32 */
867         state->width = width;
868         state->height = height;
869         /*
870          * Extended RIVA registers.
871          */
872         pixelDepth = (bpp + 1) / 8;
873         if (par->twoStagePLL)
874                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB,
875                                  par);
876         else
877                 CalcVClock(dotClock, &VClk, &state->pll, par);
878
879         switch (par->Architecture) {
880         case NV_ARCH_04:
881                 nv4UpdateArbitrationSettings(VClk,
882                                              pixelDepth * 8,
883                                              &(state->arbitration0),
884                                              &(state->arbitration1), par);
885                 state->cursor0 = 0x00;
886                 state->cursor1 = 0xbC;
887                 if (flags & FB_VMODE_DOUBLE)
888                         state->cursor1 |= 2;
889                 state->cursor2 = 0x00000000;
890                 state->pllsel = 0x10000700;
891                 state->config = 0x00001114;
892                 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
893                 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
894                 break;
895         case NV_ARCH_10:
896         case NV_ARCH_20:
897         case NV_ARCH_30:
898         default:
899                 if ((par->Chipset & 0xfff0) == 0x0240) {
900                         state->arbitration0 = 256;
901                         state->arbitration1 = 0x0480;
902                 } else if (((par->Chipset & 0xffff) == 0x01A0) ||
903                     ((par->Chipset & 0xffff) == 0x01f0)) {
904                         nForceUpdateArbitrationSettings(VClk,
905                                                         pixelDepth * 8,
906                                                         &(state->arbitration0),
907                                                         &(state->arbitration1),
908                                                         par);
909                 } else if (par->Architecture < NV_ARCH_30) {
910                         nv10UpdateArbitrationSettings(VClk,
911                                                       pixelDepth * 8,
912                                                       &(state->arbitration0),
913                                                       &(state->arbitration1),
914                                                       par);
915                 } else {
916                         nv30UpdateArbitrationSettings(par,
917                                                       &(state->arbitration0),
918                                                       &(state->arbitration1));
919                 }
920
921                 state->cursor0 = 0x80 | (par->CursorStart >> 17);
922                 state->cursor1 = (par->CursorStart >> 11) << 2;
923                 state->cursor2 = par->CursorStart >> 24;
924                 if (flags & FB_VMODE_DOUBLE)
925                         state->cursor1 |= 2;
926                 state->pllsel = 0x10000700;
927                 state->config = NV_RD32(par->PFB, 0x00000200);
928                 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
929                 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
930                 break;
931         }
932
933         if (bpp != 8)           /* DirectColor */
934                 state->general |= 0x00000030;
935
936         state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
937         state->pixel = (pixelDepth > 2) ? 3 : pixelDepth;
938 }
939
940 void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
941 {
942         int i;
943
944         NV_WR32(par->PMC, 0x0140, 0x00000000);
945         NV_WR32(par->PMC, 0x0200, 0xFFFF00FF);
946         NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF);
947
948         NV_WR32(par->PTIMER, 0x0200 * 4, 0x00000008);
949         NV_WR32(par->PTIMER, 0x0210 * 4, 0x00000003);
950         NV_WR32(par->PTIMER, 0x0140 * 4, 0x00000000);
951         NV_WR32(par->PTIMER, 0x0100 * 4, 0xFFFFFFFF);
952
953         if (par->Architecture == NV_ARCH_04) {
954                 NV_WR32(par->PFB, 0x0200, state->config);
955         } else if ((par->Architecture < NV_ARCH_40) ||
956                    (par->Chipset & 0xfff0) == 0x0040) {
957                 for (i = 0; i < 8; i++) {
958                         NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0);
959                         NV_WR32(par->PFB, 0x0244 + (i * 0x10),
960                                 par->FbMapSize - 1);
961                 }
962         } else {
963                 int regions = 12;
964
965                 if (((par->Chipset & 0xfff0) == 0x0090) ||
966                     ((par->Chipset & 0xfff0) == 0x01D0) ||
967                     ((par->Chipset & 0xfff0) == 0x02E0) ||
968                     ((par->Chipset & 0xfff0) == 0x0290))
969                         regions = 15;
970                 for(i = 0; i < regions; i++) {
971                         NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
972                         NV_WR32(par->PFB, 0x0604 + (i * 0x10),
973                                 par->FbMapSize - 1);
974                 }
975         }
976
977         if (par->Architecture >= NV_ARCH_40) {
978                 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
979                 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x00101202);
980                 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
981                 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x00101204);
982                 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
983                 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x00101206);
984                 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
985                 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x00101208);
986                 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
987                 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x0010120A);
988                 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
989                 NV_WR32(par->PRAMIN, 0x000B * 4, 0x0010120C);
990                 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
991                 NV_WR32(par->PRAMIN, 0x000D * 4, 0x0010120E);
992                 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
993                 NV_WR32(par->PRAMIN, 0x000F * 4, 0x00101210);
994                 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
995                 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
996                 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
997                 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x02080062);
998                 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
999                 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00001200);
1000                 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00001200);
1001                 NV_WR32(par->PRAMIN, 0x080C * 4, 0x00000000);
1002                 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000000);
1003                 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x02080043);
1004                 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1005                 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1006                 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1007                 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x00000000);
1008                 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1009                 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x02080044);
1010                 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x02000000);
1011                 NV_WR32(par->PRAMIN, 0x081A * 4, 0x00000000);
1012                 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1013                 NV_WR32(par->PRAMIN, 0x081C * 4, 0x00000000);
1014                 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000000);
1015                 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x02080019);
1016                 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1017                 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x00000000);
1018                 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1019                 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00000000);
1020                 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00000000);
1021                 NV_WR32(par->PRAMIN, 0x0828 * 4, 0x020A005C);
1022                 NV_WR32(par->PRAMIN, 0x0829 * 4, 0x00000000);
1023                 NV_WR32(par->PRAMIN, 0x082A * 4, 0x00000000);
1024                 NV_WR32(par->PRAMIN, 0x082B * 4, 0x00000000);
1025                 NV_WR32(par->PRAMIN, 0x082C * 4, 0x00000000);
1026                 NV_WR32(par->PRAMIN, 0x082D * 4, 0x00000000);
1027                 NV_WR32(par->PRAMIN, 0x0830 * 4, 0x0208009F);
1028                 NV_WR32(par->PRAMIN, 0x0831 * 4, 0x00000000);
1029                 NV_WR32(par->PRAMIN, 0x0832 * 4, 0x00001200);
1030                 NV_WR32(par->PRAMIN, 0x0833 * 4, 0x00001200);
1031                 NV_WR32(par->PRAMIN, 0x0834 * 4, 0x00000000);
1032                 NV_WR32(par->PRAMIN, 0x0835 * 4, 0x00000000);
1033                 NV_WR32(par->PRAMIN, 0x0838 * 4, 0x0208004A);
1034                 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x02000000);
1035                 NV_WR32(par->PRAMIN, 0x083A * 4, 0x00000000);
1036                 NV_WR32(par->PRAMIN, 0x083B * 4, 0x00000000);
1037                 NV_WR32(par->PRAMIN, 0x083C * 4, 0x00000000);
1038                 NV_WR32(par->PRAMIN, 0x083D * 4, 0x00000000);
1039                 NV_WR32(par->PRAMIN, 0x0840 * 4, 0x02080077);
1040                 NV_WR32(par->PRAMIN, 0x0841 * 4, 0x00000000);
1041                 NV_WR32(par->PRAMIN, 0x0842 * 4, 0x00001200);
1042                 NV_WR32(par->PRAMIN, 0x0843 * 4, 0x00001200);
1043                 NV_WR32(par->PRAMIN, 0x0844 * 4, 0x00000000);
1044                 NV_WR32(par->PRAMIN, 0x0845 * 4, 0x00000000);
1045                 NV_WR32(par->PRAMIN, 0x084C * 4, 0x00003002);
1046                 NV_WR32(par->PRAMIN, 0x084D * 4, 0x00007FFF);
1047                 NV_WR32(par->PRAMIN, 0x084E * 4,
1048                         par->FbUsableSize | 0x00000002);
1049
1050 #ifdef __BIG_ENDIAN
1051                 NV_WR32(par->PRAMIN, 0x080A * 4,
1052                         NV_RD32(par->PRAMIN, 0x080A * 4) | 0x01000000);
1053                 NV_WR32(par->PRAMIN, 0x0812 * 4,
1054                         NV_RD32(par->PRAMIN, 0x0812 * 4) | 0x01000000);
1055                 NV_WR32(par->PRAMIN, 0x081A * 4,
1056                         NV_RD32(par->PRAMIN, 0x081A * 4) | 0x01000000);
1057                 NV_WR32(par->PRAMIN, 0x0822 * 4,
1058                         NV_RD32(par->PRAMIN, 0x0822 * 4) | 0x01000000);
1059                 NV_WR32(par->PRAMIN, 0x082A * 4,
1060                         NV_RD32(par->PRAMIN, 0x082A * 4) | 0x01000000);
1061                 NV_WR32(par->PRAMIN, 0x0832 * 4,
1062                         NV_RD32(par->PRAMIN, 0x0832 * 4) | 0x01000000);
1063                 NV_WR32(par->PRAMIN, 0x083A * 4,
1064                         NV_RD32(par->PRAMIN, 0x083A * 4) | 0x01000000);
1065                 NV_WR32(par->PRAMIN, 0x0842 * 4,
1066                         NV_RD32(par->PRAMIN, 0x0842 * 4) | 0x01000000);
1067                 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x01000000);
1068                 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x01000000);
1069 #endif
1070         } else {
1071                 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
1072                 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x80011201);
1073                 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
1074                 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x80011202);
1075                 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
1076                 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x80011203);
1077                 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
1078                 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x80011204);
1079                 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
1080                 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x80011205);
1081                 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
1082                 NV_WR32(par->PRAMIN, 0x000B * 4, 0x80011206);
1083                 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
1084                 NV_WR32(par->PRAMIN, 0x000D * 4, 0x80011207);
1085                 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
1086                 NV_WR32(par->PRAMIN, 0x000F * 4, 0x80011208);
1087                 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
1088                 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
1089                 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
1090                 NV_WR32(par->PRAMIN, 0x0803 * 4, 0x00000002);
1091                 if (par->Architecture >= NV_ARCH_10)
1092                         NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008062);
1093                 else
1094                         NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008042);
1095                 NV_WR32(par->PRAMIN, 0x0805 * 4, 0x00000000);
1096                 NV_WR32(par->PRAMIN, 0x0806 * 4, 0x12001200);
1097                 NV_WR32(par->PRAMIN, 0x0807 * 4, 0x00000000);
1098                 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x01008043);
1099                 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
1100                 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00000000);
1101                 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00000000);
1102                 NV_WR32(par->PRAMIN, 0x080C * 4, 0x01008044);
1103                 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000002);
1104                 NV_WR32(par->PRAMIN, 0x080E * 4, 0x00000000);
1105                 NV_WR32(par->PRAMIN, 0x080F * 4, 0x00000000);
1106                 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x01008019);
1107                 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1108                 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1109                 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1110                 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x0100A05C);
1111                 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1112                 NV_WR32(par->PRAMIN, 0x0816 * 4, 0x00000000);
1113                 NV_WR32(par->PRAMIN, 0x0817 * 4, 0x00000000);
1114                 if (par->WaitVSyncPossible)
1115                         NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100809F);
1116                 else
1117                         NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100805F);
1118                 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x00000000);
1119                 NV_WR32(par->PRAMIN, 0x081A * 4, 0x12001200);
1120                 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1121                 NV_WR32(par->PRAMIN, 0x081C * 4, 0x0100804A);
1122                 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000002);
1123                 NV_WR32(par->PRAMIN, 0x081E * 4, 0x00000000);
1124                 NV_WR32(par->PRAMIN, 0x081F * 4, 0x00000000);
1125                 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x01018077);
1126                 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1127                 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x12001200);
1128                 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1129                 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00003002);
1130                 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00007FFF);
1131                 NV_WR32(par->PRAMIN, 0x0826 * 4,
1132                         par->FbUsableSize | 0x00000002);
1133                 NV_WR32(par->PRAMIN, 0x0827 * 4, 0x00000002);
1134 #ifdef __BIG_ENDIAN
1135                 NV_WR32(par->PRAMIN, 0x0804 * 4,
1136                         NV_RD32(par->PRAMIN, 0x0804 * 4) | 0x00080000);
1137                 NV_WR32(par->PRAMIN, 0x0808 * 4,
1138                         NV_RD32(par->PRAMIN, 0x0808 * 4) | 0x00080000);
1139                 NV_WR32(par->PRAMIN, 0x080C * 4,
1140                         NV_RD32(par->PRAMIN, 0x080C * 4) | 0x00080000);
1141                 NV_WR32(par->PRAMIN, 0x0810 * 4,
1142                         NV_RD32(par->PRAMIN, 0x0810 * 4) | 0x00080000);
1143                 NV_WR32(par->PRAMIN, 0x0814 * 4,
1144                         NV_RD32(par->PRAMIN, 0x0814 * 4) | 0x00080000);
1145                 NV_WR32(par->PRAMIN, 0x0818 * 4,
1146                         NV_RD32(par->PRAMIN, 0x0818 * 4) | 0x00080000);
1147                 NV_WR32(par->PRAMIN, 0x081C * 4,
1148                         NV_RD32(par->PRAMIN, 0x081C * 4) | 0x00080000);
1149                 NV_WR32(par->PRAMIN, 0x0820 * 4,
1150                         NV_RD32(par->PRAMIN, 0x0820 * 4) | 0x00080000);
1151                 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000001);
1152                 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000001);
1153 #endif
1154         }
1155         if (par->Architecture < NV_ARCH_10) {
1156                 if ((par->Chipset & 0x0fff) == 0x0020) {
1157                         NV_WR32(par->PRAMIN, 0x0824 * 4,
1158                                 NV_RD32(par->PRAMIN, 0x0824 * 4) | 0x00020000);
1159                         NV_WR32(par->PRAMIN, 0x0826 * 4,
1160                                 NV_RD32(par->PRAMIN,
1161                                         0x0826 * 4) + par->FbAddress);
1162                 }
1163                 NV_WR32(par->PGRAPH, 0x0080, 0x000001FF);
1164                 NV_WR32(par->PGRAPH, 0x0080, 0x1230C000);
1165                 NV_WR32(par->PGRAPH, 0x0084, 0x72111101);
1166                 NV_WR32(par->PGRAPH, 0x0088, 0x11D5F071);
1167                 NV_WR32(par->PGRAPH, 0x008C, 0x0004FF31);
1168                 NV_WR32(par->PGRAPH, 0x008C, 0x4004FF31);
1169                 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1170                 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1171                 NV_WR32(par->PGRAPH, 0x0170, 0x10010100);
1172                 NV_WR32(par->PGRAPH, 0x0710, 0xFFFFFFFF);
1173                 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1174                 NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1175                 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1176         } else {
1177                 NV_WR32(par->PGRAPH, 0x0080, 0xFFFFFFFF);
1178                 NV_WR32(par->PGRAPH, 0x0080, 0x00000000);
1179
1180                 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1181                 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1182                 NV_WR32(par->PGRAPH, 0x0144, 0x10010100);
1183                 NV_WR32(par->PGRAPH, 0x0714, 0xFFFFFFFF);
1184                 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1185                 NV_WR32(par->PGRAPH, 0x0710,
1186                         NV_RD32(par->PGRAPH, 0x0710) & 0x0007ff00);
1187                 NV_WR32(par->PGRAPH, 0x0710,
1188                         NV_RD32(par->PGRAPH, 0x0710) | 0x00020100);
1189
1190                 if (par->Architecture == NV_ARCH_10) {
1191                         NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1192                         NV_WR32(par->PGRAPH, 0x0088, 0x24E00810);
1193                         NV_WR32(par->PGRAPH, 0x008C, 0x55DE0030);
1194
1195                         for (i = 0; i < 32; i++)
1196                                 NV_WR32(&par->PGRAPH[(0x0B00 / 4) + i], 0,
1197                                         NV_RD32(&par->PFB[(0x0240 / 4) + i],
1198                                                 0));
1199
1200                         NV_WR32(par->PGRAPH, 0x640, 0);
1201                         NV_WR32(par->PGRAPH, 0x644, 0);
1202                         NV_WR32(par->PGRAPH, 0x684, par->FbMapSize - 1);
1203                         NV_WR32(par->PGRAPH, 0x688, par->FbMapSize - 1);
1204
1205                         NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1206                         NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1207                 } else {
1208                         if (par->Architecture >= NV_ARCH_40) {
1209                                 u32 tmp;
1210
1211                                 NV_WR32(par->PGRAPH, 0x0084, 0x401287c0);
1212                                 NV_WR32(par->PGRAPH, 0x008C, 0x60de8051);
1213                                 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1214                                 NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f);
1215
1216                                 tmp = NV_RD32(par->REGS, 0x1540) & 0xff;
1217                                 for(i = 0; tmp && !(tmp & 1); tmp >>= 1, i++);
1218                                 NV_WR32(par->PGRAPH, 0x5000, i);
1219
1220                                 if ((par->Chipset & 0xfff0) == 0x0040) {
1221                                         NV_WR32(par->PGRAPH, 0x09b0,
1222                                                 0x83280fff);
1223                                         NV_WR32(par->PGRAPH, 0x09b4,
1224                                                 0x000000a0);
1225                                 } else {
1226                                         NV_WR32(par->PGRAPH, 0x0820,
1227                                                 0x83280eff);
1228                                         NV_WR32(par->PGRAPH, 0x0824,
1229                                                 0x000000a0);
1230                                 }
1231
1232                                 switch (par->Chipset & 0xfff0) {
1233                                 case 0x0040:
1234                                 case 0x0210:
1235                                         NV_WR32(par->PGRAPH, 0x09b8,
1236                                                 0x0078e366);
1237                                         NV_WR32(par->PGRAPH, 0x09bc,
1238                                                 0x0000014c);
1239                                         NV_WR32(par->PFB, 0x033C,
1240                                                 NV_RD32(par->PFB, 0x33C) &
1241                                                 0xffff7fff);
1242                                         break;
1243                                 case 0x00C0:
1244                                 case 0x0120:
1245                                         NV_WR32(par->PGRAPH, 0x0828,
1246                                                 0x007596ff);
1247                                         NV_WR32(par->PGRAPH, 0x082C,
1248                                                 0x00000108);
1249                                         break;
1250                                 case 0x0160:
1251                                 case 0x01D0:
1252                                 case 0x0240:
1253                                         NV_WR32(par->PMC, 0x1700,
1254                                                 NV_RD32(par->PFB, 0x020C));
1255                                         NV_WR32(par->PMC, 0x1704, 0);
1256                                         NV_WR32(par->PMC, 0x1708, 0);
1257                                         NV_WR32(par->PMC, 0x170C,
1258                                                 NV_RD32(par->PFB, 0x020C));
1259                                         NV_WR32(par->PGRAPH, 0x0860, 0);
1260                                         NV_WR32(par->PGRAPH, 0x0864, 0);
1261                                         NV_WR32(par->PRAMDAC, 0x0608,
1262                                                 NV_RD32(par->PRAMDAC,
1263                                                         0x0608) | 0x00100000);
1264                                         break;
1265                                 case 0x0140:
1266                                         NV_WR32(par->PGRAPH, 0x0828,
1267                                                 0x0072cb77);
1268                                         NV_WR32(par->PGRAPH, 0x082C,
1269                                                 0x00000108);
1270                                         break;
1271                                 case 0x0220:
1272                                 case 0x0230:
1273                                         NV_WR32(par->PGRAPH, 0x0860, 0);
1274                                         NV_WR32(par->PGRAPH, 0x0864, 0);
1275                                         NV_WR32(par->PRAMDAC, 0x0608,
1276                                                 NV_RD32(par->PRAMDAC, 0x0608) |
1277                                                 0x00100000);
1278                                         break;
1279                                 case 0x0090:
1280                                 case 0x02E0:
1281                                 case 0x0290:
1282                                         NV_WR32(par->PRAMDAC, 0x0608,
1283                                                 NV_RD32(par->PRAMDAC, 0x0608) |
1284                                                 0x00100000);
1285                                         NV_WR32(par->PGRAPH, 0x0828,
1286                                                 0x07830610);
1287                                         NV_WR32(par->PGRAPH, 0x082C,
1288                                                 0x0000016A);
1289                                         break;
1290                                 default:
1291                                         break;
1292                                 };
1293
1294                                 NV_WR32(par->PGRAPH, 0x0b38, 0x2ffff800);
1295                                 NV_WR32(par->PGRAPH, 0x0b3c, 0x00006000);
1296                                 NV_WR32(par->PGRAPH, 0x032C, 0x01000000);
1297                                 NV_WR32(par->PGRAPH, 0x0220, 0x00001200);
1298                         } else if (par->Architecture == NV_ARCH_30) {
1299                                 NV_WR32(par->PGRAPH, 0x0084, 0x40108700);
1300                                 NV_WR32(par->PGRAPH, 0x0890, 0x00140000);
1301                                 NV_WR32(par->PGRAPH, 0x008C, 0xf00e0431);
1302                                 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1303                                 NV_WR32(par->PGRAPH, 0x0610, 0xf04b1f36);
1304                                 NV_WR32(par->PGRAPH, 0x0B80, 0x1002d888);
1305                                 NV_WR32(par->PGRAPH, 0x0B88, 0x62ff007f);
1306                         } else {
1307                                 NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1308                                 NV_WR32(par->PGRAPH, 0x008C, 0xF20E0431);
1309                                 NV_WR32(par->PGRAPH, 0x0090, 0x00000000);
1310                                 NV_WR32(par->PGRAPH, 0x009C, 0x00000040);
1311
1312                                 if ((par->Chipset & 0x0ff0) >= 0x0250) {
1313                                         NV_WR32(par->PGRAPH, 0x0890,
1314                                                 0x00080000);
1315                                         NV_WR32(par->PGRAPH, 0x0610,
1316                                                 0x304B1FB6);
1317                                         NV_WR32(par->PGRAPH, 0x0B80,
1318                                                 0x18B82880);
1319                                         NV_WR32(par->PGRAPH, 0x0B84,
1320                                                 0x44000000);
1321                                         NV_WR32(par->PGRAPH, 0x0098,
1322                                                 0x40000080);
1323                                         NV_WR32(par->PGRAPH, 0x0B88,
1324                                                 0x000000ff);
1325                                 } else {
1326                                         NV_WR32(par->PGRAPH, 0x0880,
1327                                                 0x00080000);
1328                                         NV_WR32(par->PGRAPH, 0x0094,
1329                                                 0x00000005);
1330                                         NV_WR32(par->PGRAPH, 0x0B80,
1331                                                 0x45CAA208);
1332                                         NV_WR32(par->PGRAPH, 0x0B84,
1333                                                 0x24000000);
1334                                         NV_WR32(par->PGRAPH, 0x0098,
1335                                                 0x00000040);
1336                                         NV_WR32(par->PGRAPH, 0x0750,
1337                                                 0x00E00038);
1338                                         NV_WR32(par->PGRAPH, 0x0754,
1339                                                 0x00000030);
1340                                         NV_WR32(par->PGRAPH, 0x0750,
1341                                                 0x00E10038);
1342                                         NV_WR32(par->PGRAPH, 0x0754,
1343                                                 0x00000030);
1344                                 }
1345                         }
1346
1347                         if ((par->Architecture < NV_ARCH_40) ||
1348                             ((par->Chipset & 0xfff0) == 0x0040)) {
1349                                 for (i = 0; i < 32; i++) {
1350                                         NV_WR32(par->PGRAPH, 0x0900 + i*4,
1351                                                 NV_RD32(par->PFB, 0x0240 +i*4));
1352                                         NV_WR32(par->PGRAPH, 0x6900 + i*4,
1353                                                 NV_RD32(par->PFB, 0x0240 +i*4));
1354                                 }
1355                         } else {
1356                                 if (((par->Chipset & 0xfff0) == 0x0090) ||
1357                                     ((par->Chipset & 0xfff0) == 0x01D0) ||
1358                                     ((par->Chipset & 0xfff0) == 0x02E0) ||
1359                                     ((par->Chipset & 0xfff0) == 0x0290)) {
1360                                         for (i = 0; i < 60; i++) {
1361                                                 NV_WR32(par->PGRAPH,
1362                                                         0x0D00 + i*4,
1363                                                         NV_RD32(par->PFB,
1364                                                                 0x0600 + i*4));
1365                                                 NV_WR32(par->PGRAPH,
1366                                                         0x6900 + i*4,
1367                                                         NV_RD32(par->PFB,
1368                                                                 0x0600 + i*4));
1369                                         }
1370                                 } else {
1371                                         for (i = 0; i < 48; i++) {
1372                                                 NV_WR32(par->PGRAPH,
1373                                                         0x0900 + i*4,
1374                                                         NV_RD32(par->PFB,
1375                                                                 0x0600 + i*4));
1376                                                 if(((par->Chipset & 0xfff0)
1377                                                     != 0x0160) &&
1378                                                    ((par->Chipset & 0xfff0)
1379                                                     != 0x0220) &&
1380                                                    ((par->Chipset & 0xfff0)
1381                                                     != 0x240))
1382                                                         NV_WR32(par->PGRAPH,
1383                                                                 0x6900 + i*4,
1384                                                                 NV_RD32(par->PFB,
1385                                                                         0x0600 + i*4));
1386                                         }
1387                                 }
1388                         }
1389
1390                         if (par->Architecture >= NV_ARCH_40) {
1391                                 if ((par->Chipset & 0xfff0) == 0x0040) {
1392                                         NV_WR32(par->PGRAPH, 0x09A4,
1393                                                 NV_RD32(par->PFB, 0x0200));
1394                                         NV_WR32(par->PGRAPH, 0x09A8,
1395                                                 NV_RD32(par->PFB, 0x0204));
1396                                         NV_WR32(par->PGRAPH, 0x69A4,
1397                                                 NV_RD32(par->PFB, 0x0200));
1398                                         NV_WR32(par->PGRAPH, 0x69A8,
1399                                                 NV_RD32(par->PFB, 0x0204));
1400
1401                                         NV_WR32(par->PGRAPH, 0x0820, 0);
1402                                         NV_WR32(par->PGRAPH, 0x0824, 0);
1403                                         NV_WR32(par->PGRAPH, 0x0864,
1404                                                 par->FbMapSize - 1);
1405                                         NV_WR32(par->PGRAPH, 0x0868,
1406                                                 par->FbMapSize - 1);
1407                                 } else {
1408                                         if ((par->Chipset & 0xfff0) == 0x0090 ||
1409                                             (par->Chipset & 0xfff0) == 0x01D0 ||
1410                                             (par->Chipset & 0xfff0) == 0x02E0 ||
1411                                             (par->Chipset & 0xfff0) == 0x0290) {
1412                                                 NV_WR32(par->PGRAPH, 0x0DF0,
1413                                                         NV_RD32(par->PFB, 0x0200));
1414                                                 NV_WR32(par->PGRAPH, 0x0DF4,
1415                                                         NV_RD32(par->PFB, 0x0204));
1416                                         } else {
1417                                                 NV_WR32(par->PGRAPH, 0x09F0,
1418                                                         NV_RD32(par->PFB, 0x0200));
1419                                                 NV_WR32(par->PGRAPH, 0x09F4,
1420                                                         NV_RD32(par->PFB, 0x0204));
1421                                         }
1422                                         NV_WR32(par->PGRAPH, 0x69F0,
1423                                                 NV_RD32(par->PFB, 0x0200));
1424                                         NV_WR32(par->PGRAPH, 0x69F4,
1425                                                 NV_RD32(par->PFB, 0x0204));
1426
1427                                         NV_WR32(par->PGRAPH, 0x0840, 0);
1428                                         NV_WR32(par->PGRAPH, 0x0844, 0);
1429                                         NV_WR32(par->PGRAPH, 0x08a0,
1430                                                 par->FbMapSize - 1);
1431                                         NV_WR32(par->PGRAPH, 0x08a4,
1432                                                 par->FbMapSize - 1);
1433                                 }
1434                         } else {
1435                                 NV_WR32(par->PGRAPH, 0x09A4,
1436                                         NV_RD32(par->PFB, 0x0200));
1437                                 NV_WR32(par->PGRAPH, 0x09A8,
1438                                         NV_RD32(par->PFB, 0x0204));
1439                                 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0000);
1440                                 NV_WR32(par->PGRAPH, 0x0754,
1441                                         NV_RD32(par->PFB, 0x0200));
1442                                 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0004);
1443                                 NV_WR32(par->PGRAPH, 0x0754,
1444                                         NV_RD32(par->PFB, 0x0204));
1445
1446                                 NV_WR32(par->PGRAPH, 0x0820, 0);
1447                                 NV_WR32(par->PGRAPH, 0x0824, 0);
1448                                 NV_WR32(par->PGRAPH, 0x0864,
1449                                         par->FbMapSize - 1);
1450                                 NV_WR32(par->PGRAPH, 0x0868,
1451                                         par->FbMapSize - 1);
1452                         }
1453                         NV_WR32(par->PGRAPH, 0x0B20, 0x00000000);
1454                         NV_WR32(par->PGRAPH, 0x0B04, 0xFFFFFFFF);
1455                 }
1456         }
1457         NV_WR32(par->PGRAPH, 0x053C, 0);
1458         NV_WR32(par->PGRAPH, 0x0540, 0);
1459         NV_WR32(par->PGRAPH, 0x0544, 0x00007FFF);
1460         NV_WR32(par->PGRAPH, 0x0548, 0x00007FFF);
1461
1462         NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000000);
1463         NV_WR32(par->PFIFO, 0x0141 * 4, 0x00000001);
1464         NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000000);
1465         NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000000);
1466         if (par->Architecture >= NV_ARCH_40)
1467                 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00010000);
1468         else
1469                 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00000100);
1470         NV_WR32(par->PFIFO, 0x0490 * 4, 0x00000000);
1471         NV_WR32(par->PFIFO, 0x0491 * 4, 0x00000000);
1472         if (par->Architecture >= NV_ARCH_40)
1473                 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001213);
1474         else
1475                 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001209);
1476         NV_WR32(par->PFIFO, 0x0400 * 4, 0x00000000);
1477         NV_WR32(par->PFIFO, 0x0414 * 4, 0x00000000);
1478         NV_WR32(par->PFIFO, 0x0084 * 4, 0x03000100);
1479         NV_WR32(par->PFIFO, 0x0085 * 4, 0x00000110);
1480         NV_WR32(par->PFIFO, 0x0086 * 4, 0x00000112);
1481         NV_WR32(par->PFIFO, 0x0143 * 4, 0x0000FFFF);
1482         NV_WR32(par->PFIFO, 0x0496 * 4, 0x0000FFFF);
1483         NV_WR32(par->PFIFO, 0x0050 * 4, 0x00000000);
1484         NV_WR32(par->PFIFO, 0x0040 * 4, 0xFFFFFFFF);
1485         NV_WR32(par->PFIFO, 0x0415 * 4, 0x00000001);
1486         NV_WR32(par->PFIFO, 0x048C * 4, 0x00000000);
1487         NV_WR32(par->PFIFO, 0x04A0 * 4, 0x00000000);
1488 #ifdef __BIG_ENDIAN
1489         NV_WR32(par->PFIFO, 0x0489 * 4, 0x800F0078);
1490 #else
1491         NV_WR32(par->PFIFO, 0x0489 * 4, 0x000F0078);
1492 #endif
1493         NV_WR32(par->PFIFO, 0x0488 * 4, 0x00000001);
1494         NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000001);
1495         NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000001);
1496         NV_WR32(par->PFIFO, 0x0495 * 4, 0x00000001);
1497         NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000001);
1498         if (par->Architecture >= NV_ARCH_10) {
1499                 if (par->twoHeads) {
1500                         NV_WR32(par->PCRTC0, 0x0860, state->head);
1501                         NV_WR32(par->PCRTC0, 0x2860, state->head2);
1502                 }
1503                 NV_WR32(par->PRAMDAC, 0x0404, NV_RD32(par->PRAMDAC, 0x0404) |
1504                         (1 << 25));
1505
1506                 NV_WR32(par->PMC, 0x8704, 1);
1507                 NV_WR32(par->PMC, 0x8140, 0);
1508                 NV_WR32(par->PMC, 0x8920, 0);
1509                 NV_WR32(par->PMC, 0x8924, 0);
1510                 NV_WR32(par->PMC, 0x8908, par->FbMapSize - 1);
1511                 NV_WR32(par->PMC, 0x890C, par->FbMapSize - 1);
1512                 NV_WR32(par->PMC, 0x1588, 0);
1513
1514                 NV_WR32(par->PCRTC, 0x0810, state->cursorConfig);
1515                 NV_WR32(par->PCRTC, 0x0830, state->displayV - 3);
1516                 NV_WR32(par->PCRTC, 0x0834, state->displayV - 1);
1517
1518                 if (par->FlatPanel) {
1519                         if ((par->Chipset & 0x0ff0) == 0x0110) {
1520                                 NV_WR32(par->PRAMDAC, 0x0528, state->dither);
1521                         } else if (par->twoHeads) {
1522                                 NV_WR32(par->PRAMDAC, 0x083C, state->dither);
1523                         }
1524
1525                         VGA_WR08(par->PCIO, 0x03D4, 0x53);
1526                         VGA_WR08(par->PCIO, 0x03D5, state->timingH);
1527                         VGA_WR08(par->PCIO, 0x03D4, 0x54);
1528                         VGA_WR08(par->PCIO, 0x03D5, state->timingV);
1529                         VGA_WR08(par->PCIO, 0x03D4, 0x21);
1530                         VGA_WR08(par->PCIO, 0x03D5, 0xfa);
1531                 }
1532
1533                 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1534                 VGA_WR08(par->PCIO, 0x03D5, state->extra);
1535         }
1536
1537         VGA_WR08(par->PCIO, 0x03D4, 0x19);
1538         VGA_WR08(par->PCIO, 0x03D5, state->repaint0);
1539         VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1540         VGA_WR08(par->PCIO, 0x03D5, state->repaint1);
1541         VGA_WR08(par->PCIO, 0x03D4, 0x25);
1542         VGA_WR08(par->PCIO, 0x03D5, state->screen);
1543         VGA_WR08(par->PCIO, 0x03D4, 0x28);
1544         VGA_WR08(par->PCIO, 0x03D5, state->pixel);
1545         VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1546         VGA_WR08(par->PCIO, 0x03D5, state->horiz);
1547         VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1548         VGA_WR08(par->PCIO, 0x03D5, state->fifo);
1549         VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1550         VGA_WR08(par->PCIO, 0x03D5, state->arbitration0);
1551         VGA_WR08(par->PCIO, 0x03D4, 0x20);
1552         VGA_WR08(par->PCIO, 0x03D5, state->arbitration1);
1553
1554         if(par->Architecture >= NV_ARCH_30) {
1555                 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1556                 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1 >> 8);
1557         }
1558
1559         VGA_WR08(par->PCIO, 0x03D4, 0x30);
1560         VGA_WR08(par->PCIO, 0x03D5, state->cursor0);
1561         VGA_WR08(par->PCIO, 0x03D4, 0x31);
1562         VGA_WR08(par->PCIO, 0x03D5, state->cursor1);
1563         VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1564         VGA_WR08(par->PCIO, 0x03D5, state->cursor2);
1565         VGA_WR08(par->PCIO, 0x03D4, 0x39);
1566         VGA_WR08(par->PCIO, 0x03D5, state->interlace);
1567
1568         if (!par->FlatPanel) {
1569                 NV_WR32(par->PRAMDAC0, 0x050C, state->pllsel);
1570                 NV_WR32(par->PRAMDAC0, 0x0508, state->vpll);
1571                 if (par->twoHeads)
1572                         NV_WR32(par->PRAMDAC0, 0x0520, state->vpll2);
1573                 if (par->twoStagePLL) {
1574                         NV_WR32(par->PRAMDAC0, 0x0578, state->vpllB);
1575                         NV_WR32(par->PRAMDAC0, 0x057C, state->vpll2B);
1576                 }
1577         } else {
1578                 NV_WR32(par->PRAMDAC, 0x0848, state->scale);
1579                 NV_WR32(par->PRAMDAC, 0x0828, state->crtcSync +
1580                         par->PanelTweak);
1581         }
1582
1583         NV_WR32(par->PRAMDAC, 0x0600, state->general);
1584
1585         NV_WR32(par->PCRTC, 0x0140, 0);
1586         NV_WR32(par->PCRTC, 0x0100, 1);
1587
1588         par->CurrentState = state;
1589 }
1590
1591 void NVUnloadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) {
1592         VGA_WR08(par->PCIO, 0x03D4, 0x19);
1593         state->repaint0 = VGA_RD08(par->PCIO, 0x03D5);
1594         VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1595         state->repaint1 = VGA_RD08(par->PCIO, 0x03D5);
1596         VGA_WR08(par->PCIO, 0x03D4, 0x25);
1597         state->screen = VGA_RD08(par->PCIO, 0x03D5);
1598         VGA_WR08(par->PCIO, 0x03D4, 0x28);
1599         state->pixel = VGA_RD08(par->PCIO, 0x03D5);
1600         VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1601         state->horiz = VGA_RD08(par->PCIO, 0x03D5);
1602         VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1603         state->fifo         = VGA_RD08(par->PCIO, 0x03D5);
1604         VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1605         state->arbitration0 = VGA_RD08(par->PCIO, 0x03D5);
1606         VGA_WR08(par->PCIO, 0x03D4, 0x20);
1607         state->arbitration1 = VGA_RD08(par->PCIO, 0x03D5);
1608
1609         if(par->Architecture >= NV_ARCH_30) {
1610                 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1611                 state->arbitration1 |= (VGA_RD08(par->PCIO, 0x03D5) & 1) << 8;
1612         }
1613
1614         VGA_WR08(par->PCIO, 0x03D4, 0x30);
1615         state->cursor0 = VGA_RD08(par->PCIO, 0x03D5);
1616         VGA_WR08(par->PCIO, 0x03D4, 0x31);
1617         state->cursor1 = VGA_RD08(par->PCIO, 0x03D5);
1618         VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1619         state->cursor2 = VGA_RD08(par->PCIO, 0x03D5);
1620         VGA_WR08(par->PCIO, 0x03D4, 0x39);
1621         state->interlace = VGA_RD08(par->PCIO, 0x03D5);
1622         state->vpll = NV_RD32(par->PRAMDAC0, 0x0508);
1623         if (par->twoHeads)
1624                 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
1625         if (par->twoStagePLL) {
1626                 state->vpllB = NV_RD32(par->PRAMDAC0, 0x0578);
1627                 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
1628         }
1629         state->pllsel = NV_RD32(par->PRAMDAC0, 0x050C);
1630         state->general = NV_RD32(par->PRAMDAC, 0x0600);
1631         state->scale = NV_RD32(par->PRAMDAC, 0x0848);
1632         state->config = NV_RD32(par->PFB, 0x0200);
1633
1634         if (par->Architecture >= NV_ARCH_10) {
1635                 if (par->twoHeads) {
1636                         state->head = NV_RD32(par->PCRTC0, 0x0860);
1637                         state->head2 = NV_RD32(par->PCRTC0, 0x2860);
1638                         VGA_WR08(par->PCIO, 0x03D4, 0x44);
1639                         state->crtcOwner = VGA_RD08(par->PCIO, 0x03D5);
1640                 }
1641                 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1642                 state->extra = VGA_RD08(par->PCIO, 0x03D5);
1643                 state->cursorConfig = NV_RD32(par->PCRTC, 0x0810);
1644
1645                 if ((par->Chipset & 0x0ff0) == 0x0110) {
1646                         state->dither = NV_RD32(par->PRAMDAC, 0x0528);
1647                 } else if (par->twoHeads) {
1648                         state->dither = NV_RD32(par->PRAMDAC, 0x083C);
1649                 }
1650
1651                 if (par->FlatPanel) {
1652                         VGA_WR08(par->PCIO, 0x03D4, 0x53);
1653                         state->timingH = VGA_RD08(par->PCIO, 0x03D5);
1654                         VGA_WR08(par->PCIO, 0x03D4, 0x54);
1655                         state->timingV = VGA_RD08(par->PCIO, 0x03D5);
1656                 }
1657         }
1658 }
1659
1660 void NVSetStartAddress(struct nvidia_par *par, u32 start)
1661 {
1662         NV_WR32(par->PCRTC, 0x800, start);
1663 }