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   1 /* smp.c: Sparc64 SMP support.
   2  *
   3  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/sched.h>
   9 #include <linux/mm.h>
  10 #include <linux/pagemap.h>
  11 #include <linux/threads.h>
  12 #include <linux/smp.h>
  13 #include <linux/smp_lock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/fs.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/cache.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/profile.h>
  24 #include <linux/bootmem.h>
  25
  26 #include <asm/head.h>
  27 #include <asm/ptrace.h>
  28 #include <asm/atomic.h>
  29 #include <asm/tlbflush.h>
  30 #include <asm/mmu_context.h>
  31 #include <asm/cpudata.h>
  32
  33 #include <asm/irq.h>
  34 #include <asm/page.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/oplib.h>
  37 #include <asm/uaccess.h>
  38 #include <asm/timer.h>
  39 #include <asm/starfire.h>
  40 #include <asm/tlb.h>
  41
  42 extern int linux_num_cpus;
  43 extern void calibrate_delay(void);
  44
  45 /* Please don't make this stuff initdata!!!  --DaveM */
  46 static unsigned char boot_cpu_id;
  47
  48 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
  49 cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
  50 static cpumask_t smp_commenced_mask;
  51 static cpumask_t cpu_callout_map;
  52
  53 void smp_info(struct seq_file *m)
  54 {
  55         int i;
  56
  57         seq_printf(m, "State:\n");
  58         for (i = 0; i < NR_CPUS; i++) {
  59                 if (cpu_online(i))
  60                         seq_printf(m,
  61                                    "CPU%d:\t\tonline\n", i);
  62         }
  63 }
  64
  65 void smp_bogo(struct seq_file *m)
  66 {
  67         int i;
  68
  69         for (i = 0; i < NR_CPUS; i++)
  70                 if (cpu_online(i))
  71                         seq_printf(m,
  72                                    "Cpu%dBogo\t: %lu.%02lu\n"
  73                                    "Cpu%dClkTck\t: %016lx\n",
  74                                    i, cpu_data(i).udelay_val / (500000/HZ),
  75                                    (cpu_data(i).udelay_val / (5000/HZ)) % 100,
  76                                    i, cpu_data(i).clock_tick);
  77 }
  78
  79 void __init smp_store_cpu_info(int id)
  80 {
  81         int cpu_node;
  82
  83         /* multiplier and counter set by
  84            smp_setup_percpu_timer()  */
  85         cpu_data(id).udelay_val                 = loops_per_jiffy;
  86
  87         cpu_find_by_mid(id, &cpu_node);
  88         cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
  89                                                      "clock-frequency", 0);
  90
  91         cpu_data(id).pgcache_size               = 0;
  92         cpu_data(id).pte_cache[0]               = NULL;
  93         cpu_data(id).pte_cache[1]               = NULL;
  94         cpu_data(id).pgd_cache                  = NULL;
  95         cpu_data(id).idle_volume                = 1;
  96
  97         cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
  98                                                       16 * 1024);
  99         cpu_data(id).dcache_line_size =
 100                 prom_getintdefault(cpu_node, "dcache-line-size", 32);
 101         cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
 102                                                       16 * 1024);
 103         cpu_data(id).icache_line_size =
 104                 prom_getintdefault(cpu_node, "icache-line-size", 32);
 105         cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
 106                                                       4 * 1024 * 1024);
 107         cpu_data(id).ecache_line_size =
 108                 prom_getintdefault(cpu_node, "ecache-line-size", 64);
 109         printk("CPU[%d]: Caches "
 110                "D[sz(%d):line_sz(%d)] "
 111                "I[sz(%d):line_sz(%d)] "
 112                "E[sz(%d):line_sz(%d)]\n",
 113                id,
 114                cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
 115                cpu_data(id).icache_size, cpu_data(id).icache_line_size,
 116                cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
 117 }
 118
 119 static void smp_setup_percpu_timer(void);
 120
 121 static volatile unsigned long callin_flag = 0;
 122
 123 extern void inherit_locked_prom_mappings(int save_p);
 124
 125 static inline void cpu_setup_percpu_base(unsigned long cpu_id)
 126 {
 127         __asm__ __volatile__("mov       %0, %%g5\n\t"
 128                              "stxa      %0, [%1] %2\n\t"
 129                              "membar    #Sync"
 130                              : /* no outputs */
 131                              : "r" (__per_cpu_offset(cpu_id)),
 132                                "r" (TSB_REG), "i" (ASI_IMMU));
 133 }
 134
 135 void __init smp_callin(void)
 136 {
 137         int cpuid = hard_smp_processor_id();
 138
 139         inherit_locked_prom_mappings(0);
 140
 141         __flush_tlb_all();
 142
 143         cpu_setup_percpu_base(cpuid);
 144
 145         smp_setup_percpu_timer();
 146
 147         if (cheetah_pcache_forced_on)
 148                 cheetah_enable_pcache();
 149
 150         local_irq_enable();
 151
 152         calibrate_delay();
 153         smp_store_cpu_info(cpuid);
 154         callin_flag = 1;
 155         __asm__ __volatile__("membar #Sync\n\t"
 156                              "flush  %%g6" : : : "memory");
 157
 158         /* Clear this or we will die instantly when we
 159          * schedule back to this idler...
 160          */
 161         current_thread_info()->new_child = 0;
 162
 163         /* Attach to the address space of init_task. */
 164         atomic_inc(&init_mm.mm_count);
 165         current->active_mm = &init_mm;
 166
 167         while (!cpu_isset(cpuid, smp_commenced_mask))
 168                 rmb();
 169
 170         cpu_set(cpuid, cpu_online_map);
 171 }
 172
 173 void cpu_panic(void)
 174 {
 175         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
 176         panic("SMP bolixed\n");
 177 }
 178
 179 static unsigned long current_tick_offset __read_mostly;
 180
 181 /* This tick register synchronization scheme is taken entirely from
 182  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
 183  *
 184  * The only change I've made is to rework it so that the master
 185  * initiates the synchonization instead of the slave. -DaveM
 186  */
 187
 188 #define MASTER  0
 189 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
 190
 191 #define NUM_ROUNDS      64      /* magic value */
 192 #define NUM_ITERS       5       /* likewise */
 193
 194 static DEFINE_SPINLOCK(itc_sync_lock);
 195 static unsigned long go[SLAVE + 1];
 196
 197 #define DEBUG_TICK_SYNC 0
 198
 199 static inline long get_delta (long *rt, long *master)
 200 {
 201         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
 202         unsigned long tcenter, t0, t1, tm;
 203         unsigned long i;
 204
 205         for (i = 0; i < NUM_ITERS; i++) {
 206                 t0 = tick_ops->get_tick();
 207                 go[MASTER] = 1;
 208                 membar_storeload();
 209                 while (!(tm = go[SLAVE]))
 210                         rmb();
 211                 go[SLAVE] = 0;
 212                 wmb();
 213                 t1 = tick_ops->get_tick();
 214
 215                 if (t1 - t0 < best_t1 - best_t0)
 216                         best_t0 = t0, best_t1 = t1, best_tm = tm;
 217         }
 218
 219         *rt = best_t1 - best_t0;
 220         *master = best_tm - best_t0;
 221
 222         /* average best_t0 and best_t1 without overflow: */
 223         tcenter = (best_t0/2 + best_t1/2);
 224         if (best_t0 % 2 + best_t1 % 2 == 2)
 225                 tcenter++;
 226         return tcenter - best_tm;
 227 }
 228
 229 void smp_synchronize_tick_client(void)
 230 {
 231         long i, delta, adj, adjust_latency = 0, done = 0;
 232         unsigned long flags, rt, master_time_stamp, bound;
 233 #if DEBUG_TICK_SYNC
 234         struct {
 235                 long rt;        /* roundtrip time */
 236                 long master;    /* master's timestamp */
 237                 long diff;      /* difference between midpoint and master's timestamp */
 238                 long lat;       /* estimate of itc adjustment latency */
 239         } t[NUM_ROUNDS];
 240 #endif
 241
 242         go[MASTER] = 1;
 243
 244         while (go[MASTER])
 245                 rmb();
 246
 247         local_irq_save(flags);
 248         {
 249                 for (i = 0; i < NUM_ROUNDS; i++) {
 250                         delta = get_delta(&rt, &master_time_stamp);
 251                         if (delta == 0) {
 252                                 done = 1;       /* let's lock on to this... */
 253                                 bound = rt;
 254                         }
 255
 256                         if (!done) {
 257                                 if (i > 0) {
 258                                         adjust_latency += -delta;
 259                                         adj = -delta + adjust_latency/4;
 260                                 } else
 261                                         adj = -delta;
 262
 263                                 tick_ops->add_tick(adj, current_tick_offset);
 264                         }
 265 #if DEBUG_TICK_SYNC
 266                         t[i].rt = rt;
 267                         t[i].master = master_time_stamp;
 268                         t[i].diff = delta;
 269                         t[i].lat = adjust_latency/4;
 270 #endif
 271                 }
 272         }
 273         local_irq_restore(flags);
 274
 275 #if DEBUG_TICK_SYNC
 276         for (i = 0; i < NUM_ROUNDS; i++)
 277                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
 278                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
 279 #endif
 280
 281         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
 282                "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
 283 }
 284
 285 static void smp_start_sync_tick_client(int cpu);
 286
 287 static void smp_synchronize_one_tick(int cpu)
 288 {
 289         unsigned long flags, i;
 290
 291         go[MASTER] = 0;
 292
 293         smp_start_sync_tick_client(cpu);
 294
 295         /* wait for client to be ready */
 296         while (!go[MASTER])
 297                 rmb();
 298
 299         /* now let the client proceed into his loop */
 300         go[MASTER] = 0;
 301         membar_storeload();
 302
 303         spin_lock_irqsave(&itc_sync_lock, flags);
 304         {
 305                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
 306                         while (!go[MASTER])
 307                                 rmb();
 308                         go[MASTER] = 0;
 309                         wmb();
 310                         go[SLAVE] = tick_ops->get_tick();
 311                         membar_storeload();
 312                 }
 313         }
 314         spin_unlock_irqrestore(&itc_sync_lock, flags);
 315 }
 316
 317 extern unsigned long sparc64_cpu_startup;
 318
 319 /* The OBP cpu startup callback truncates the 3rd arg cookie to
 320  * 32-bits (I think) so to be safe we have it read the pointer
 321  * contained here so we work on >4GB machines. -DaveM
 322  */
 323 static struct thread_info *cpu_new_thread = NULL;
 324
 325 static int __devinit smp_boot_one_cpu(unsigned int cpu)
 326 {
 327         unsigned long entry =
 328                 (unsigned long)(&sparc64_cpu_startup);
 329         unsigned long cookie =
 330                 (unsigned long)(&cpu_new_thread);
 331         struct task_struct *p;
 332         int timeout, ret, cpu_node;
 333
 334         p = fork_idle(cpu);
 335         callin_flag = 0;
 336         cpu_new_thread = p->thread_info;
 337         cpu_set(cpu, cpu_callout_map);
 338
 339         cpu_find_by_mid(cpu, &cpu_node);
 340         prom_startcpu(cpu_node, entry, cookie);
 341
 342         for (timeout = 0; timeout < 5000000; timeout++) {
 343                 if (callin_flag)
 344                         break;
 345                 udelay(100);
 346         }
 347         if (callin_flag) {
 348                 ret = 0;
 349         } else {
 350                 printk("Processor %d is stuck.\n", cpu);
 351                 cpu_clear(cpu, cpu_callout_map);
 352                 ret = -ENODEV;
 353         }
 354         cpu_new_thread = NULL;
 355
 356         return ret;
 357 }
 358
 359 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
 360 {
 361         u64 result, target;
 362         int stuck, tmp;
 363
 364         if (this_is_starfire) {
 365                 /* map to real upaid */
 366                 cpu = (((cpu & 0x3c) << 1) |
 367                         ((cpu & 0x40) >> 4) |
 368                         (cpu & 0x3));
 369         }
 370
 371         target = (cpu << 14) | 0x70;
 372 again:
 373         /* Ok, this is the real Spitfire Errata #54.
 374          * One must read back from a UDB internal register
 375          * after writes to the UDB interrupt dispatch, but
 376          * before the membar Sync for that write.
 377          * So we use the high UDB control register (ASI 0x7f,
 378          * ADDR 0x20) for the dummy read. -DaveM
 379          */
 380         tmp = 0x40;
 381         __asm__ __volatile__(
 382         "wrpr   %1, %2, %%pstate\n\t"
 383         "stxa   %4, [%0] %3\n\t"
 384         "stxa   %5, [%0+%8] %3\n\t"
 385         "add    %0, %8, %0\n\t"
 386         "stxa   %6, [%0+%8] %3\n\t"
 387         "membar #Sync\n\t"
 388         "stxa   %%g0, [%7] %3\n\t"
 389         "membar #Sync\n\t"
 390         "mov    0x20, %%g1\n\t"
 391         "ldxa   [%%g1] 0x7f, %%g0\n\t"
 392         "membar #Sync"
 393         : "=r" (tmp)
 394         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
 395           "r" (data0), "r" (data1), "r" (data2), "r" (target),
 396           "r" (0x10), "0" (tmp)
 397         : "g1");
 398
 399         /* NOTE: PSTATE_IE is still clear. */
 400         stuck = 100000;
 401         do {
 402                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 403                         : "=r" (result)
 404                         : "i" (ASI_INTR_DISPATCH_STAT));
 405                 if (result == 0) {
 406                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 407                                              : : "r" (pstate));
 408                         return;
 409                 }
 410                 stuck -= 1;
 411                 if (stuck == 0)
 412                         break;
 413         } while (result & 0x1);
 414         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 415                              : : "r" (pstate));
 416         if (stuck == 0) {
 417                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 418                        smp_processor_id(), result);
 419         } else {
 420                 udelay(2);
 421                 goto again;
 422         }
 423 }
 424
 425 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 426 {
 427         u64 pstate;
 428         int i;
 429
 430         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 431         for_each_cpu_mask(i, mask)
 432                 spitfire_xcall_helper(data0, data1, data2, pstate, i);
 433 }
 434
 435 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
 436  * packet, but we have no use for that.  However we do take advantage of
 437  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
 438  */
 439 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 440 {
 441         u64 pstate, ver;
 442         int nack_busy_id, is_jalapeno;
 443
 444         if (cpus_empty(mask))
 445                 return;
 446
 447         /* Unfortunately, someone at Sun had the brilliant idea to make the
 448          * busy/nack fields hard-coded by ITID number for this Ultra-III
 449          * derivative processor.
 450          */
 451         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 452         is_jalapeno = ((ver >> 32) == 0x003e0016);
 453
 454         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 455
 456 retry:
 457         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
 458                              : : "r" (pstate), "i" (PSTATE_IE));
 459
 460         /* Setup the dispatch data registers. */
 461         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
 462                              "stxa      %1, [%4] %6\n\t"
 463                              "stxa      %2, [%5] %6\n\t"
 464                              "membar    #Sync\n\t"
 465                              : /* no outputs */
 466                              : "r" (data0), "r" (data1), "r" (data2),
 467                                "r" (0x40), "r" (0x50), "r" (0x60),
 468                                "i" (ASI_INTR_W));
 469
 470         nack_busy_id = 0;
 471         {
 472                 int i;
 473
 474                 for_each_cpu_mask(i, mask) {
 475                         u64 target = (i << 14) | 0x70;
 476
 477                         if (!is_jalapeno)
 478                                 target |= (nack_busy_id << 24);
 479                         __asm__ __volatile__(
 480                                 "stxa   %%g0, [%0] %1\n\t"
 481                                 "membar #Sync\n\t"
 482                                 : /* no outputs */
 483                                 : "r" (target), "i" (ASI_INTR_W));
 484                         nack_busy_id++;
 485                 }
 486         }
 487
 488         /* Now, poll for completion. */
 489         {
 490                 u64 dispatch_stat;
 491                 long stuck;
 492
 493                 stuck = 100000 * nack_busy_id;
 494                 do {
 495                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
 496                                              : "=r" (dispatch_stat)
 497                                              : "i" (ASI_INTR_DISPATCH_STAT));
 498                         if (dispatch_stat == 0UL) {
 499                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 500                                                      : : "r" (pstate));
 501                                 return;
 502                         }
 503                         if (!--stuck)
 504                                 break;
 505                 } while (dispatch_stat & 0x5555555555555555UL);
 506
 507                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 508                                      : : "r" (pstate));
 509
 510                 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
 511                         /* Busy bits will not clear, continue instead
 512                          * of freezing up on this cpu.
 513                          */
 514                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 515                                smp_processor_id(), dispatch_stat);
 516                 } else {
 517                         int i, this_busy_nack = 0;
 518
 519                         /* Delay some random time with interrupts enabled
 520                          * to prevent deadlock.
 521                          */
 522                         udelay(2 * nack_busy_id);
 523
 524                         /* Clear out the mask bits for cpus which did not
 525                          * NACK us.
 526                          */
 527                         for_each_cpu_mask(i, mask) {
 528                                 u64 check_mask;
 529
 530                                 if (is_jalapeno)
 531                                         check_mask = (0x2UL << (2*i));
 532                                 else
 533                                         check_mask = (0x2UL <<
 534                                                       this_busy_nack);
 535                                 if ((dispatch_stat & check_mask) == 0)
 536                                         cpu_clear(i, mask);
 537                                 this_busy_nack += 2;
 538                         }
 539
 540                         goto retry;
 541                 }
 542         }
 543 }
 544
 545 /* Send cross call to all processors mentioned in MASK
 546  * except self.
 547  */
 548 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
 549 {
 550         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
 551         int this_cpu = get_cpu();
 552
 553         cpus_and(mask, mask, cpu_online_map);
 554         cpu_clear(this_cpu, mask);
 555
 556         if (tlb_type == spitfire)
 557                 spitfire_xcall_deliver(data0, data1, data2, mask);
 558         else
 559                 cheetah_xcall_deliver(data0, data1, data2, mask);
 560         /* NOTE: Caller runs local copy on master. */
 561
 562         put_cpu();
 563 }
 564
 565 extern unsigned long xcall_sync_tick;
 566
 567 static void smp_start_sync_tick_client(int cpu)
 568 {
 569         cpumask_t mask = cpumask_of_cpu(cpu);
 570
 571         smp_cross_call_masked(&xcall_sync_tick,
 572                               0, 0, 0, mask);
 573 }
 574
 575 /* Send cross call to all processors except self. */
 576 #define smp_cross_call(func, ctx, data1, data2) \
 577         smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
 578
 579 struct call_data_struct {
 580         void (*func) (void *info);
 581         void *info;
 582         atomic_t finished;
 583         int wait;
 584 };
 585
 586 static DEFINE_SPINLOCK(call_lock);
 587 static struct call_data_struct *call_data;
 588
 589 extern unsigned long xcall_call_function;
 590
 591 /*
 592  * You must not call this function with disabled interrupts or from a
 593  * hardware interrupt handler or from a bottom half handler.
 594  */
 595 int smp_call_function(void (*func)(void *info), void *info,
 596                       int nonatomic, int wait)
 597 {
 598         struct call_data_struct data;
 599         int cpus = num_online_cpus() - 1;
 600         long timeout;
 601
 602         if (!cpus)
 603                 return 0;
 604
 605         /* Can deadlock when called with interrupts disabled */
 606         WARN_ON(irqs_disabled());
 607
 608         data.func = func;
 609         data.info = info;
 610         atomic_set(&data.finished, 0);
 611         data.wait = wait;
 612
 613         spin_lock(&call_lock);
 614
 615         call_data = &data;
 616
 617         smp_cross_call(&xcall_call_function, 0, 0, 0);
 618
 619         /*
 620          * Wait for other cpus to complete function or at
 621          * least snap the call data.
 622          */
 623         timeout = 1000000;
 624         while (atomic_read(&data.finished) != cpus) {
 625                 if (--timeout <= 0)
 626                         goto out_timeout;
 627                 barrier();
 628                 udelay(1);
 629         }
 630
 631         spin_unlock(&call_lock);
 632
 633         return 0;
 634
 635 out_timeout:
 636         spin_unlock(&call_lock);
 637         printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n",
 638                (long) num_online_cpus() - 1L,
 639                (long) atomic_read(&data.finished));
 640         return 0;
 641 }
 642
 643 void smp_call_function_client(int irq, struct pt_regs *regs)
 644 {
 645         void (*func) (void *info) = call_data->func;
 646         void *info = call_data->info;
 647
 648         clear_softint(1 << irq);
 649         if (call_data->wait) {
 650                 /* let initiator proceed only after completion */
 651                 func(info);
 652                 atomic_inc(&call_data->finished);
 653         } else {
 654                 /* let initiator proceed after getting data */
 655                 atomic_inc(&call_data->finished);
 656                 func(info);
 657         }
 658 }
 659
 660 extern unsigned long xcall_flush_tlb_mm;
 661 extern unsigned long xcall_flush_tlb_pending;
 662 extern unsigned long xcall_flush_tlb_kernel_range;
 663 extern unsigned long xcall_flush_tlb_all_spitfire;
 664 extern unsigned long xcall_flush_tlb_all_cheetah;
 665 extern unsigned long xcall_report_regs;
 666 extern unsigned long xcall_receive_signal;
 667
 668 #ifdef DCACHE_ALIASING_POSSIBLE
 669 extern unsigned long xcall_flush_dcache_page_cheetah;
 670 #endif
 671 extern unsigned long xcall_flush_dcache_page_spitfire;
 672
 673 #ifdef CONFIG_DEBUG_DCFLUSH
 674 extern atomic_t dcpage_flushes;
 675 extern atomic_t dcpage_flushes_xcall;
 676 #endif
 677
 678 static __inline__ void __local_flush_dcache_page(struct page *page)
 679 {
 680 #ifdef DCACHE_ALIASING_POSSIBLE
 681         __flush_dcache_page(page_address(page),
 682                             ((tlb_type == spitfire) &&
 683                              page_mapping(page) != NULL));
 684 #else
 685         if (page_mapping(page) != NULL &&
 686             tlb_type == spitfire)
 687                 __flush_icache_page(__pa(page_address(page)));
 688 #endif
 689 }
 690
 691 void smp_flush_dcache_page_impl(struct page *page, int cpu)
 692 {
 693         cpumask_t mask = cpumask_of_cpu(cpu);
 694         int this_cpu = get_cpu();
 695
 696 #ifdef CONFIG_DEBUG_DCFLUSH
 697         atomic_inc(&dcpage_flushes);
 698 #endif
 699         if (cpu == this_cpu) {
 700                 __local_flush_dcache_page(page);
 701         } else if (cpu_online(cpu)) {
 702                 void *pg_addr = page_address(page);
 703                 u64 data0;
 704
 705                 if (tlb_type == spitfire) {
 706                         data0 =
 707                                 ((u64)&xcall_flush_dcache_page_spitfire);
 708                         if (page_mapping(page) != NULL)
 709                                 data0 |= ((u64)1 << 32);
 710                         spitfire_xcall_deliver(data0,
 711                                                __pa(pg_addr),
 712                                                (u64) pg_addr,
 713                                                mask);
 714                 } else {
 715 #ifdef DCACHE_ALIASING_POSSIBLE
 716                         data0 =
 717                                 ((u64)&xcall_flush_dcache_page_cheetah);
 718                         cheetah_xcall_deliver(data0,
 719                                               __pa(pg_addr),
 720                                               0, mask);
 721 #endif
 722                 }
 723 #ifdef CONFIG_DEBUG_DCFLUSH
 724                 atomic_inc(&dcpage_flushes_xcall);
 725 #endif
 726         }
 727
 728         put_cpu();
 729 }
 730
 731 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
 732 {
 733         void *pg_addr = page_address(page);
 734         cpumask_t mask = cpu_online_map;
 735         u64 data0;
 736         int this_cpu = get_cpu();
 737
 738         cpu_clear(this_cpu, mask);
 739
 740 #ifdef CONFIG_DEBUG_DCFLUSH
 741         atomic_inc(&dcpage_flushes);
 742 #endif
 743         if (cpus_empty(mask))
 744                 goto flush_self;
 745         if (tlb_type == spitfire) {
 746                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 747                 if (page_mapping(page) != NULL)
 748                         data0 |= ((u64)1 << 32);
 749                 spitfire_xcall_deliver(data0,
 750                                        __pa(pg_addr),
 751                                        (u64) pg_addr,
 752                                        mask);
 753         } else {
 754 #ifdef DCACHE_ALIASING_POSSIBLE
 755                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 756                 cheetah_xcall_deliver(data0,
 757                                       __pa(pg_addr),
 758                                       0, mask);
 759 #endif
 760         }
 761 #ifdef CONFIG_DEBUG_DCFLUSH
 762         atomic_inc(&dcpage_flushes_xcall);
 763 #endif
 764  flush_self:
 765         __local_flush_dcache_page(page);
 766
 767         put_cpu();
 768 }
 769
 770 void smp_receive_signal(int cpu)
 771 {
 772         cpumask_t mask = cpumask_of_cpu(cpu);
 773
 774         if (cpu_online(cpu)) {
 775                 u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff);
 776
 777                 if (tlb_type == spitfire)
 778                         spitfire_xcall_deliver(data0, 0, 0, mask);
 779                 else
 780                         cheetah_xcall_deliver(data0, 0, 0, mask);
 781         }
 782 }
 783
 784 void smp_receive_signal_client(int irq, struct pt_regs *regs)
 785 {
 786         /* Just return, rtrap takes care of the rest. */
 787         clear_softint(1 << irq);
 788 }
 789
 790 void smp_report_regs(void)
 791 {
 792         smp_cross_call(&xcall_report_regs, 0, 0, 0);
 793 }
 794
 795 void smp_flush_tlb_all(void)
 796 {
 797         if (tlb_type == spitfire)
 798                 smp_cross_call(&xcall_flush_tlb_all_spitfire, 0, 0, 0);
 799         else
 800                 smp_cross_call(&xcall_flush_tlb_all_cheetah, 0, 0, 0);
 801         __flush_tlb_all();
 802 }
 803
 804 /* We know that the window frames of the user have been flushed
 805  * to the stack before we get here because all callers of us
 806  * are flush_tlb_*() routines, and these run after flush_cache_*()
 807  * which performs the flushw.
 808  *
 809  * The SMP TLB coherency scheme we use works as follows:
 810  *
 811  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
 812  *    space has (potentially) executed on, this is the heuristic
 813  *    we use to avoid doing cross calls.
 814  *
 815  *    Also, for flushing from kswapd and also for clones, we
 816  *    use cpu_vm_mask as the list of cpus to make run the TLB.
 817  *
 818  * 2) TLB context numbers are shared globally across all processors
 819  *    in the system, this allows us to play several games to avoid
 820  *    cross calls.
 821  *
 822  *    One invariant is that when a cpu switches to a process, and
 823  *    that processes tsk->active_mm->cpu_vm_mask does not have the
 824  *    current cpu's bit set, that tlb context is flushed locally.
 825  *
 826  *    If the address space is non-shared (ie. mm->count == 1) we avoid
 827  *    cross calls when we want to flush the currently running process's
 828  *    tlb state.  This is done by clearing all cpu bits except the current
 829  *    processor's in current->active_mm->cpu_vm_mask and performing the
 830  *    flush locally only.  This will force any subsequent cpus which run
 831  *    this task to flush the context from the local tlb if the process
 832  *    migrates to another cpu (again).
 833  *
 834  * 3) For shared address spaces (threads) and swapping we bite the
 835  *    bullet for most cases and perform the cross call (but only to
 836  *    the cpus listed in cpu_vm_mask).
 837  *
 838  *    The performance gain from "optimizing" away the cross call for threads is
 839  *    questionable (in theory the big win for threads is the massive sharing of
 840  *    address space state across processors).
 841  */
 842
 843 /* This currently is only used by the hugetlb arch pre-fault
 844  * hook on UltraSPARC-III+ and later when changing the pagesize
 845  * bits of the context register for an address space.
 846  */
 847 void smp_flush_tlb_mm(struct mm_struct *mm)
 848 {
 849         u32 ctx = CTX_HWBITS(mm->context);
 850         int cpu = get_cpu();
 851
 852         if (atomic_read(&mm->mm_users) == 1) {
 853                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
 854                 goto local_flush_and_out;
 855         }
 856
 857         smp_cross_call_masked(&xcall_flush_tlb_mm,
 858                               ctx, 0, 0,
 859                               mm->cpu_vm_mask);
 860
 861 local_flush_and_out:
 862         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
 863
 864         put_cpu();
 865 }
 866
 867 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
 868 {
 869         u32 ctx = CTX_HWBITS(mm->context);
 870         int cpu = get_cpu();
 871
 872         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
 873                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
 874         else
 875                 smp_cross_call_masked(&xcall_flush_tlb_pending,
 876                                       ctx, nr, (unsigned long) vaddrs,
 877                                       mm->cpu_vm_mask);
 878
 879         __flush_tlb_pending(ctx, nr, vaddrs);
 880
 881         put_cpu();
 882 }
 883
 884 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
 885 {
 886         start &= PAGE_MASK;
 887         end    = PAGE_ALIGN(end);
 888         if (start != end) {
 889                 smp_cross_call(&xcall_flush_tlb_kernel_range,
 890                                0, start, end);
 891
 892                 __flush_tlb_kernel_range(start, end);
 893         }
 894 }
 895
 896 /* CPU capture. */
 897 /* #define CAPTURE_DEBUG */
 898 extern unsigned long xcall_capture;
 899
 900 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
 901 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
 902 static unsigned long penguins_are_doing_time;
 903
 904 void smp_capture(void)
 905 {
 906         int result = atomic_add_ret(1, &smp_capture_depth);
 907
 908         if (result == 1) {
 909                 int ncpus = num_online_cpus();
 910
 911 #ifdef CAPTURE_DEBUG
 912                 printk("CPU[%d]: Sending penguins to jail...",
 913                        smp_processor_id());
 914 #endif
 915                 penguins_are_doing_time = 1;
 916                 membar_storestore_loadstore();
 917                 atomic_inc(&smp_capture_registry);
 918                 smp_cross_call(&xcall_capture, 0, 0, 0);
 919                 while (atomic_read(&smp_capture_registry) != ncpus)
 920                         rmb();
 921 #ifdef CAPTURE_DEBUG
 922                 printk("done\n");
 923 #endif
 924         }
 925 }
 926
 927 void smp_release(void)
 928 {
 929         if (atomic_dec_and_test(&smp_capture_depth)) {
 930 #ifdef CAPTURE_DEBUG
 931                 printk("CPU[%d]: Giving pardon to "
 932                        "imprisoned penguins\n",
 933                        smp_processor_id());
 934 #endif
 935                 penguins_are_doing_time = 0;
 936                 membar_storeload_storestore();
 937                 atomic_dec(&smp_capture_registry);
 938         }
 939 }
 940
 941 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
 942  * can service tlb flush xcalls...
 943  */
 944 extern void prom_world(int);
 945 extern void save_alternate_globals(unsigned long *);
 946 extern void restore_alternate_globals(unsigned long *);
 947 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
 948 {
 949         unsigned long global_save[24];
 950
 951         clear_softint(1 << irq);
 952
 953         preempt_disable();
 954
 955         __asm__ __volatile__("flushw");
 956         save_alternate_globals(global_save);
 957         prom_world(1);
 958         atomic_inc(&smp_capture_registry);
 959         membar_storeload_storestore();
 960         while (penguins_are_doing_time)
 961                 rmb();
 962         restore_alternate_globals(global_save);
 963         atomic_dec(&smp_capture_registry);
 964         prom_world(0);
 965
 966         preempt_enable();
 967 }
 968
 969 #define prof_multiplier(__cpu)          cpu_data(__cpu).multiplier
 970 #define prof_counter(__cpu)             cpu_data(__cpu).counter
 971
 972 void smp_percpu_timer_interrupt(struct pt_regs *regs)
 973 {
 974         unsigned long compare, tick, pstate;
 975         int cpu = smp_processor_id();
 976         int user = user_mode(regs);
 977
 978         /*
 979          * Check for level 14 softint.
 980          */
 981         {
 982                 unsigned long tick_mask = tick_ops->softint_mask;
 983
 984                 if (!(get_softint() & tick_mask)) {
 985                         extern void handler_irq(int, struct pt_regs *);
 986
 987                         handler_irq(14, regs);
 988                         return;
 989                 }
 990                 clear_softint(tick_mask);
 991         }
 992
 993         do {
 994                 profile_tick(CPU_PROFILING, regs);
 995                 if (!--prof_counter(cpu)) {
 996                         irq_enter();
 997
 998                         if (cpu == boot_cpu_id) {
 999                                 kstat_this_cpu.irqs[0]++;
1000                                 timer_tick_interrupt(regs);
1001                         }
1002
1003                         update_process_times(user);
1004
1005                         irq_exit();
1006
1007                         prof_counter(cpu) = prof_multiplier(cpu);
1008                 }
1009
1010                 /* Guarantee that the following sequences execute
1011                  * uninterrupted.
1012                  */
1013                 __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1014                                      "wrpr      %0, %1, %%pstate"
1015                                      : "=r" (pstate)
1016                                      : "i" (PSTATE_IE));
1017
1018                 compare = tick_ops->add_compare(current_tick_offset);
1019                 tick = tick_ops->get_tick();
1020
1021                 /* Restore PSTATE_IE. */
1022                 __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1023                                      : /* no outputs */
1024                                      : "r" (pstate));
1025         } while (time_after_eq(tick, compare));
1026 }
1027
1028 static void __init smp_setup_percpu_timer(void)
1029 {
1030         int cpu = smp_processor_id();
1031         unsigned long pstate;
1032
1033         prof_counter(cpu) = prof_multiplier(cpu) = 1;
1034
1035         /* Guarantee that the following sequences execute
1036          * uninterrupted.
1037          */
1038         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1039                              "wrpr      %0, %1, %%pstate"
1040                              : "=r" (pstate)
1041                              : "i" (PSTATE_IE));
1042
1043         tick_ops->init_tick(current_tick_offset);
1044
1045         /* Restore PSTATE_IE. */
1046         __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1047                              : /* no outputs */
1048                              : "r" (pstate));
1049 }
1050
1051 void __init smp_tick_init(void)
1052 {
1053         boot_cpu_id = hard_smp_processor_id();
1054         current_tick_offset = timer_tick_offset;
1055
1056         cpu_set(boot_cpu_id, cpu_online_map);
1057         prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
1058 }
1059
1060 /* /proc/profile writes can call this, don't __init it please. */
1061 static DEFINE_SPINLOCK(prof_setup_lock);
1062
1063 int setup_profiling_timer(unsigned int multiplier)
1064 {
1065         unsigned long flags;
1066         int i;
1067
1068         if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
1069                 return -EINVAL;
1070
1071         spin_lock_irqsave(&prof_setup_lock, flags);
1072         for (i = 0; i < NR_CPUS; i++)
1073                 prof_multiplier(i) = multiplier;
1074         current_tick_offset = (timer_tick_offset / multiplier);
1075         spin_unlock_irqrestore(&prof_setup_lock, flags);
1076
1077         return 0;
1078 }
1079
1080 void __init smp_prepare_cpus(unsigned int max_cpus)
1081 {
1082         int instance, mid;
1083
1084         instance = 0;
1085         while (!cpu_find_by_instance(instance, NULL, &mid)) {
1086                 if (mid < max_cpus)
1087                         cpu_set(mid, phys_cpu_present_map);
1088                 instance++;
1089         }
1090
1091         if (num_possible_cpus() > max_cpus) {
1092                 instance = 0;
1093                 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1094                         if (mid != boot_cpu_id) {
1095                                 cpu_clear(mid, phys_cpu_present_map);
1096                                 if (num_possible_cpus() <= max_cpus)
1097                                         break;
1098                         }
1099                         instance++;
1100                 }
1101         }
1102
1103         smp_store_cpu_info(boot_cpu_id);
1104 }
1105
1106 void __devinit smp_prepare_boot_cpu(void)
1107 {
1108         if (hard_smp_processor_id() >= NR_CPUS) {
1109                 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1110                 prom_halt();
1111         }
1112
1113         current_thread_info()->cpu = hard_smp_processor_id();
1114
1115         cpu_set(smp_processor_id(), cpu_online_map);
1116         cpu_set(smp_processor_id(), phys_cpu_present_map);
1117 }
1118
1119 int __devinit __cpu_up(unsigned int cpu)
1120 {
1121         int ret = smp_boot_one_cpu(cpu);
1122
1123         if (!ret) {
1124                 cpu_set(cpu, smp_commenced_mask);
1125                 while (!cpu_isset(cpu, cpu_online_map))
1126                         mb();
1127                 if (!cpu_isset(cpu, cpu_online_map)) {
1128                         ret = -ENODEV;
1129                 } else {
1130                         smp_synchronize_one_tick(cpu);
1131                 }
1132         }
1133         return ret;
1134 }
1135
1136 void __init smp_cpus_done(unsigned int max_cpus)
1137 {
1138         unsigned long bogosum = 0;
1139         int i;
1140
1141         for (i = 0; i < NR_CPUS; i++) {
1142                 if (cpu_online(i))
1143                         bogosum += cpu_data(i).udelay_val;
1144         }
1145         printk("Total of %ld processors activated "
1146                "(%lu.%02lu BogoMIPS).\n",
1147                (long) num_online_cpus(),
1148                bogosum/(500000/HZ),
1149                (bogosum/(5000/HZ))%100);
1150 }
1151
1152 /* This needn't do anything as we do not sleep the cpu
1153  * inside of the idler task, so an interrupt is not needed
1154  * to get a clean fast response.
1155  *
1156  * XXX Reverify this assumption... -DaveM
1157  *
1158  * Addendum: We do want it to do something for the signal
1159  *           delivery case, we detect that by just seeing
1160  *           if we are trying to send this to an idler or not.
1161  */
1162 void smp_send_reschedule(int cpu)
1163 {
1164         if (cpu_data(cpu).idle_volume == 0)
1165                 smp_receive_signal(cpu);
1166 }
1167
1168 /* This is a nop because we capture all other cpus
1169  * anyways when making the PROM active.
1170  */
1171 void smp_send_stop(void)
1172 {
1173 }
1174
1175 unsigned long __per_cpu_base __read_mostly;
1176 unsigned long __per_cpu_shift __read_mostly;
1177
1178 EXPORT_SYMBOL(__per_cpu_base);
1179 EXPORT_SYMBOL(__per_cpu_shift);
1180
1181 void __init setup_per_cpu_areas(void)
1182 {
1183         unsigned long goal, size, i;
1184         char *ptr;
1185         /* Created by linker magic */
1186         extern char __per_cpu_start[], __per_cpu_end[];
1187
1188         /* Copy section for each CPU (we discard the original) */
1189         goal = ALIGN(__per_cpu_end - __per_cpu_start, PAGE_SIZE);
1190
1191 #ifdef CONFIG_MODULES
1192         if (goal < PERCPU_ENOUGH_ROOM)
1193                 goal = PERCPU_ENOUGH_ROOM;
1194 #endif
1195         __per_cpu_shift = 0;
1196         for (size = 1UL; size < goal; size <<= 1UL)
1197                 __per_cpu_shift++;
1198
1199         /* Make sure the resulting __per_cpu_base value
1200          * will fit in the 43-bit sign extended IMMU
1201          * TSB register.
1202          */
1203         ptr = __alloc_bootmem(size * NR_CPUS, PAGE_SIZE,
1204                               (unsigned long) __per_cpu_start);
1205
1206         __per_cpu_base = ptr - __per_cpu_start;
1207
1208         if ((__per_cpu_shift < PAGE_SHIFT) ||
1209             (__per_cpu_base & ~PAGE_MASK) ||
1210             (__per_cpu_base != (((long) __per_cpu_base << 20) >> 20))) {
1211                 prom_printf("PER_CPU: Invalid layout, "
1212                             "ptr[%p] shift[%lx] base[%lx]\n",
1213                             ptr, __per_cpu_shift, __per_cpu_base);
1214                 prom_halt();
1215         }
1216
1217         for (i = 0; i < NR_CPUS; i++, ptr += size)
1218                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1219
1220         /* Finally, load in the boot cpu's base value.
1221          * We abuse the IMMU TSB register for trap handler
1222          * entry and exit loading of %g5.  That is why it
1223          * has to be page aligned.
1224          */
1225         cpu_setup_percpu_base(hard_smp_processor_id());
1226 }