1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
5 #include <linux/delay.h>
8 #include <asm/alternative.h>
9 #include <asm/cpufeature.h>
10 #include <asm/processor.h>
11 #include <asm/apicdef.h>
12 #include <asm/atomic.h>
13 #include <asm/fixmap.h>
14 #include <asm/mpspec.h>
15 #include <asm/system.h>
18 #define ARCH_APICTIMER_STOPS_ON_C3 1
24 #define APIC_VERBOSE 1
28 * Define the default level of output to be very little
29 * This can be turned up by using apic=verbose for more
30 * information and apic=debug for _lots_ of information.
31 * apic_verbosity is defined in apic.c
33 #define apic_printk(v, s, a...) do { \
34 if ((v) <= apic_verbosity) \
39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
40 extern void generic_apic_probe(void);
42 static inline void generic_apic_probe(void)
47 #ifdef CONFIG_X86_LOCAL_APIC
49 extern unsigned int apic_verbosity;
50 extern int local_apic_timer_c2_ok;
52 extern int disable_apic;
55 extern void __inquire_remote_apic(int apicid);
56 #else /* CONFIG_SMP */
57 static inline void __inquire_remote_apic(int apicid)
60 #endif /* CONFIG_SMP */
62 static inline void default_inquire_remote_apic(int apicid)
64 if (apic_verbosity >= APIC_DEBUG)
65 __inquire_remote_apic(apicid);
69 * Basic functions accessing APICs.
71 #ifdef CONFIG_PARAVIRT
72 #include <asm/paravirt.h>
74 #define setup_boot_clock setup_boot_APIC_clock
75 #define setup_secondary_clock setup_secondary_APIC_clock
78 extern int is_vsmp_box(void);
79 extern void xapic_wait_icr_idle(void);
80 extern u32 safe_xapic_wait_icr_idle(void);
81 extern void xapic_icr_write(u32, u32);
82 extern int setup_profiling_timer(unsigned int);
84 static inline void native_apic_mem_write(u32 reg, u32 v)
86 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
88 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
89 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
90 ASM_OUTPUT2("0" (v), "m" (*addr)));
93 static inline u32 native_apic_mem_read(u32 reg)
95 return *((volatile u32 *)(APIC_BASE + reg));
98 extern void native_apic_wait_icr_idle(void);
99 extern u32 native_safe_apic_wait_icr_idle(void);
100 extern void native_apic_icr_write(u32 low, u32 id);
101 extern u64 native_apic_icr_read(void);
103 #ifdef CONFIG_X86_X2APIC
104 static inline void native_apic_msr_write(u32 reg, u32 v)
106 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
110 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
113 static inline u32 native_apic_msr_read(u32 reg)
120 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
124 static inline void native_x2apic_wait_icr_idle(void)
126 /* no need to wait for icr idle in x2apic */
130 static inline u32 native_safe_x2apic_wait_icr_idle(void)
132 /* no need to wait for icr idle in x2apic */
136 static inline void native_x2apic_icr_write(u32 low, u32 id)
138 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
141 static inline u64 native_x2apic_icr_read(void)
145 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
149 extern int x2apic, x2apic_phys;
150 extern void check_x2apic(void);
151 extern void enable_x2apic(void);
152 extern void enable_IR_x2apic(void);
153 extern void x2apic_icr_write(u32 low, u32 id);
154 static inline int x2apic_enabled(void)
161 rdmsr(MSR_IA32_APICBASE, msr, msr2);
162 if (msr & X2APIC_ENABLE)
167 static inline void check_x2apic(void)
170 static inline void enable_x2apic(void)
173 static inline void enable_IR_x2apic(void)
176 static inline int x2apic_enabled(void)
182 extern int get_physical_broadcast(void);
184 #ifdef CONFIG_X86_X2APIC
185 static inline void ack_x2APIC_irq(void)
187 /* Docs say use 0 for future compatibility */
188 native_apic_msr_write(APIC_EOI, 0);
192 extern int lapic_get_maxlvt(void);
193 extern void clear_local_APIC(void);
194 extern void connect_bsp_APIC(void);
195 extern void disconnect_bsp_APIC(int virt_wire_setup);
196 extern void disable_local_APIC(void);
197 extern void lapic_shutdown(void);
198 extern int verify_local_APIC(void);
199 extern void cache_APIC_registers(void);
200 extern void sync_Arb_IDs(void);
201 extern void init_bsp_APIC(void);
202 extern void setup_local_APIC(void);
203 extern void end_local_APIC_setup(void);
204 extern void init_apic_mappings(void);
205 extern void setup_boot_APIC_clock(void);
206 extern void setup_secondary_APIC_clock(void);
207 extern int APIC_init_uniprocessor(void);
208 extern void enable_NMI_through_LVT0(void);
211 * On 32bit this is mach-xxx local
214 extern void early_init_lapic_mapping(void);
215 extern int apic_is_clustered_box(void);
217 static inline int apic_is_clustered_box(void)
223 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
224 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
227 #else /* !CONFIG_X86_LOCAL_APIC */
228 static inline void lapic_shutdown(void) { }
229 #define local_apic_timer_c2_ok 1
230 static inline void init_apic_mappings(void) { }
231 static inline void disable_local_APIC(void) { }
233 #endif /* !CONFIG_X86_LOCAL_APIC */
236 #define SET_APIC_ID(x) (apic->set_apic_id(x))
242 * Copyright 2004 James Cleverdon, IBM.
243 * Subject to the GNU Public License, v.2
245 * Generic APIC sub-arch data struct.
247 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
248 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
255 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
256 int (*apic_id_registered)(void);
258 u32 irq_delivery_mode;
261 const struct cpumask *(*target_cpus)(void);
266 unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
267 unsigned long (*check_apicid_present)(int apicid);
269 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
270 void (*init_apic_ldr)(void);
272 physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
274 void (*setup_apic_routing)(void);
275 int (*multi_timer_check)(int apic, int irq);
276 int (*apicid_to_node)(int logical_apicid);
277 int (*cpu_to_logical_apicid)(int cpu);
278 int (*cpu_present_to_apicid)(int mps_cpu);
279 physid_mask_t (*apicid_to_cpu_present)(int phys_apicid);
280 void (*setup_portio_remap)(void);
281 int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
282 void (*enable_apic_mode)(void);
283 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
286 * When one of the next two hooks returns 1 the apic
287 * is switched to this. Essentially they are additional
290 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
292 unsigned int (*get_apic_id)(unsigned long x);
293 unsigned long (*set_apic_id)(unsigned int id);
294 unsigned long apic_id_mask;
296 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
297 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
298 const struct cpumask *andmask);
301 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
302 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
304 void (*send_IPI_allbutself)(int vector);
305 void (*send_IPI_all)(int vector);
306 void (*send_IPI_self)(int vector);
308 /* wakeup_secondary_cpu */
309 int (*wakeup_cpu)(int apicid, unsigned long start_eip);
311 int trampoline_phys_low;
312 int trampoline_phys_high;
314 void (*wait_for_init_deassert)(atomic_t *deassert);
315 void (*smp_callin_clear_local_apic)(void);
316 void (*inquire_remote_apic)(int apicid);
319 u32 (*read)(u32 reg);
320 void (*write)(u32 reg, u32 v);
321 u64 (*icr_read)(void);
322 void (*icr_write)(u32 low, u32 high);
323 void (*wait_icr_idle)(void);
324 u32 (*safe_wait_icr_idle)(void);
327 extern struct apic *apic;
329 static inline u32 apic_read(u32 reg)
331 return apic->read(reg);
334 static inline void apic_write(u32 reg, u32 val)
336 apic->write(reg, val);
339 static inline u64 apic_icr_read(void)
341 return apic->icr_read();
344 static inline void apic_icr_write(u32 low, u32 high)
346 apic->icr_write(low, high);
349 static inline void apic_wait_icr_idle(void)
351 apic->wait_icr_idle();
354 static inline u32 safe_apic_wait_icr_idle(void)
356 return apic->safe_wait_icr_idle();
360 static inline void ack_APIC_irq(void)
363 * ack_APIC_irq() actually gets compiled as a single instruction
367 /* Docs say use 0 for future compatibility */
368 apic_write(APIC_EOI, 0);
371 static inline unsigned default_get_apic_id(unsigned long x)
373 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
376 return (x >> 24) & 0xFF;
378 return (x >> 24) & 0x0F;
382 * Warm reset vector default position:
384 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
385 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
388 extern void es7000_update_apic_to_cluster(void);
390 extern struct apic apic_flat;
391 extern struct apic apic_physflat;
392 extern struct apic apic_x2apic_cluster;
393 extern struct apic apic_x2apic_phys;
394 extern int default_acpi_madt_oem_check(char *, char *);
396 extern void apic_send_IPI_self(int vector);
398 extern struct apic apic_x2apic_uv_x;
399 DECLARE_PER_CPU(int, x2apic_extra_bits);
401 extern int default_cpu_present_to_apicid(int mps_cpu);
402 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
405 static inline void default_wait_for_init_deassert(atomic_t *deassert)
407 while (!atomic_read(deassert))
412 extern void generic_bigsmp_probe(void);
415 #ifdef CONFIG_X86_LOCAL_APIC
419 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
421 static inline const struct cpumask *default_target_cpus(void)
424 return cpu_online_mask;
426 return cpumask_of(0);
430 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
433 static inline unsigned int read_apic_id(void)
437 reg = apic_read(APIC_ID);
439 return apic->get_apic_id(reg);
442 extern void default_setup_apic_routing(void);
446 * Set up the logical destination ID.
448 * Intel recommends to set DFR, LDR and TPR before enabling
449 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
450 * document number 292116). So here it goes...
452 extern void default_init_apic_ldr(void);
454 static inline int default_apic_id_registered(void)
456 return physid_isset(read_apic_id(), phys_cpu_present_map);
459 static inline unsigned int
460 default_cpu_mask_to_apicid(const struct cpumask *cpumask)
462 return cpumask_bits(cpumask)[0];
465 static inline unsigned int
466 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
467 const struct cpumask *andmask)
469 unsigned long mask1 = cpumask_bits(cpumask)[0];
470 unsigned long mask2 = cpumask_bits(andmask)[0];
471 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
473 return (unsigned int)(mask1 & mask2 & mask3);
476 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
478 return cpuid_apic >> index_msb;
481 extern int default_apicid_to_node(int logical_apicid);
485 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
487 return physid_isset(apicid, bitmap);
490 static inline unsigned long default_check_apicid_present(int bit)
492 return physid_isset(bit, phys_cpu_present_map);
495 static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
500 /* Mapping from cpu number to logical apicid */
501 static inline int default_cpu_to_logical_apicid(int cpu)
506 static inline int __default_cpu_present_to_apicid(int mps_cpu)
508 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
509 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
515 __default_check_phys_apicid_present(int boot_cpu_physical_apicid)
517 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
521 static inline int default_cpu_present_to_apicid(int mps_cpu)
523 return __default_cpu_present_to_apicid(mps_cpu);
527 default_check_phys_apicid_present(int boot_cpu_physical_apicid)
529 return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
532 extern int default_cpu_present_to_apicid(int mps_cpu);
533 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
536 static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
538 return physid_mask_of_physid(phys_apicid);
541 #endif /* CONFIG_X86_LOCAL_APIC */
544 extern u8 cpu_2_logical_apicid[NR_CPUS];
547 #endif /* _ASM_X86_APIC_H */