Merge git://git.kernel.org/pub/scm/linux/kernel/git/steve/gfs2-2.6-nmw
[linux-2.6] / drivers / firewire / fw-ohci.c
1 /*
2  * Driver for OHCI 1394 controllers
3  *
4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software Foundation,
18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/mm.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/spinlock.h>
32
33 #include <asm/page.h>
34 #include <asm/system.h>
35
36 #ifdef CONFIG_PPC_PMAC
37 #include <asm/pmac_feature.h>
38 #endif
39
40 #include "fw-ohci.h"
41 #include "fw-transaction.h"
42
43 #define DESCRIPTOR_OUTPUT_MORE          0
44 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
45 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
46 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
47 #define DESCRIPTOR_STATUS               (1 << 11)
48 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
49 #define DESCRIPTOR_PING                 (1 << 7)
50 #define DESCRIPTOR_YY                   (1 << 6)
51 #define DESCRIPTOR_NO_IRQ               (0 << 4)
52 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
53 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
54 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
55 #define DESCRIPTOR_WAIT                 (3 << 0)
56
57 struct descriptor {
58         __le16 req_count;
59         __le16 control;
60         __le32 data_address;
61         __le32 branch_address;
62         __le16 res_count;
63         __le16 transfer_status;
64 } __attribute__((aligned(16)));
65
66 struct db_descriptor {
67         __le16 first_size;
68         __le16 control;
69         __le16 second_req_count;
70         __le16 first_req_count;
71         __le32 branch_address;
72         __le16 second_res_count;
73         __le16 first_res_count;
74         __le32 reserved0;
75         __le32 first_buffer;
76         __le32 second_buffer;
77         __le32 reserved1;
78 } __attribute__((aligned(16)));
79
80 #define CONTROL_SET(regs)       (regs)
81 #define CONTROL_CLEAR(regs)     ((regs) + 4)
82 #define COMMAND_PTR(regs)       ((regs) + 12)
83 #define CONTEXT_MATCH(regs)     ((regs) + 16)
84
85 struct ar_buffer {
86         struct descriptor descriptor;
87         struct ar_buffer *next;
88         __le32 data[0];
89 };
90
91 struct ar_context {
92         struct fw_ohci *ohci;
93         struct ar_buffer *current_buffer;
94         struct ar_buffer *last_buffer;
95         void *pointer;
96         u32 regs;
97         struct tasklet_struct tasklet;
98 };
99
100 struct context;
101
102 typedef int (*descriptor_callback_t)(struct context *ctx,
103                                      struct descriptor *d,
104                                      struct descriptor *last);
105
106 /*
107  * A buffer that contains a block of DMA-able coherent memory used for
108  * storing a portion of a DMA descriptor program.
109  */
110 struct descriptor_buffer {
111         struct list_head list;
112         dma_addr_t buffer_bus;
113         size_t buffer_size;
114         size_t used;
115         struct descriptor buffer[0];
116 };
117
118 struct context {
119         struct fw_ohci *ohci;
120         u32 regs;
121         int total_allocation;
122
123         /*
124          * List of page-sized buffers for storing DMA descriptors.
125          * Head of list contains buffers in use and tail of list contains
126          * free buffers.
127          */
128         struct list_head buffer_list;
129
130         /*
131          * Pointer to a buffer inside buffer_list that contains the tail
132          * end of the current DMA program.
133          */
134         struct descriptor_buffer *buffer_tail;
135
136         /*
137          * The descriptor containing the branch address of the first
138          * descriptor that has not yet been filled by the device.
139          */
140         struct descriptor *last;
141
142         /*
143          * The last descriptor in the DMA program.  It contains the branch
144          * address that must be updated upon appending a new descriptor.
145          */
146         struct descriptor *prev;
147
148         descriptor_callback_t callback;
149
150         struct tasklet_struct tasklet;
151 };
152
153 #define IT_HEADER_SY(v)          ((v) <<  0)
154 #define IT_HEADER_TCODE(v)       ((v) <<  4)
155 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
156 #define IT_HEADER_TAG(v)         ((v) << 14)
157 #define IT_HEADER_SPEED(v)       ((v) << 16)
158 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
159
160 struct iso_context {
161         struct fw_iso_context base;
162         struct context context;
163         int excess_bytes;
164         void *header;
165         size_t header_length;
166 };
167
168 #define CONFIG_ROM_SIZE 1024
169
170 struct fw_ohci {
171         struct fw_card card;
172
173         u32 version;
174         __iomem char *registers;
175         dma_addr_t self_id_bus;
176         __le32 *self_id_cpu;
177         struct tasklet_struct bus_reset_tasklet;
178         int node_id;
179         int generation;
180         int request_generation;
181         u32 bus_seconds;
182         bool old_uninorth;
183
184         /*
185          * Spinlock for accessing fw_ohci data.  Never call out of
186          * this driver with this lock held.
187          */
188         spinlock_t lock;
189         u32 self_id_buffer[512];
190
191         /* Config rom buffers */
192         __be32 *config_rom;
193         dma_addr_t config_rom_bus;
194         __be32 *next_config_rom;
195         dma_addr_t next_config_rom_bus;
196         u32 next_header;
197
198         struct ar_context ar_request_ctx;
199         struct ar_context ar_response_ctx;
200         struct context at_request_ctx;
201         struct context at_response_ctx;
202
203         u32 it_context_mask;
204         struct iso_context *it_context_list;
205         u32 ir_context_mask;
206         struct iso_context *ir_context_list;
207 };
208
209 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
210 {
211         return container_of(card, struct fw_ohci, card);
212 }
213
214 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
215 #define IR_CONTEXT_BUFFER_FILL          0x80000000
216 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
217 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
218 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
219 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
220
221 #define CONTEXT_RUN     0x8000
222 #define CONTEXT_WAKE    0x1000
223 #define CONTEXT_DEAD    0x0800
224 #define CONTEXT_ACTIVE  0x0400
225
226 #define OHCI1394_MAX_AT_REQ_RETRIES     0x2
227 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
228 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
229
230 #define FW_OHCI_MAJOR                   240
231 #define OHCI1394_REGISTER_SIZE          0x800
232 #define OHCI_LOOP_COUNT                 500
233 #define OHCI1394_PCI_HCI_Control        0x40
234 #define SELF_ID_BUF_SIZE                0x800
235 #define OHCI_TCODE_PHY_PACKET           0x0e
236 #define OHCI_VERSION_1_1                0x010010
237
238 static char ohci_driver_name[] = KBUILD_MODNAME;
239
240 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
241 {
242         writel(data, ohci->registers + offset);
243 }
244
245 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
246 {
247         return readl(ohci->registers + offset);
248 }
249
250 static inline void flush_writes(const struct fw_ohci *ohci)
251 {
252         /* Do a dummy read to flush writes. */
253         reg_read(ohci, OHCI1394_Version);
254 }
255
256 static int
257 ohci_update_phy_reg(struct fw_card *card, int addr,
258                     int clear_bits, int set_bits)
259 {
260         struct fw_ohci *ohci = fw_ohci(card);
261         u32 val, old;
262
263         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
264         flush_writes(ohci);
265         msleep(2);
266         val = reg_read(ohci, OHCI1394_PhyControl);
267         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
268                 fw_error("failed to set phy reg bits.\n");
269                 return -EBUSY;
270         }
271
272         old = OHCI1394_PhyControl_ReadData(val);
273         old = (old & ~clear_bits) | set_bits;
274         reg_write(ohci, OHCI1394_PhyControl,
275                   OHCI1394_PhyControl_Write(addr, old));
276
277         return 0;
278 }
279
280 static int ar_context_add_page(struct ar_context *ctx)
281 {
282         struct device *dev = ctx->ohci->card.device;
283         struct ar_buffer *ab;
284         dma_addr_t uninitialized_var(ab_bus);
285         size_t offset;
286
287         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
288         if (ab == NULL)
289                 return -ENOMEM;
290
291         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
292         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
293                                                     DESCRIPTOR_STATUS |
294                                                     DESCRIPTOR_BRANCH_ALWAYS);
295         offset = offsetof(struct ar_buffer, data);
296         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
297         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
298         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
299         ab->descriptor.branch_address = 0;
300
301         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
302         ctx->last_buffer->next = ab;
303         ctx->last_buffer = ab;
304
305         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
306         flush_writes(ctx->ohci);
307
308         return 0;
309 }
310
311 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
312 #define cond_le32_to_cpu(v) \
313         (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
314 #else
315 #define cond_le32_to_cpu(v) le32_to_cpu(v)
316 #endif
317
318 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
319 {
320         struct fw_ohci *ohci = ctx->ohci;
321         struct fw_packet p;
322         u32 status, length, tcode;
323
324         p.header[0] = cond_le32_to_cpu(buffer[0]);
325         p.header[1] = cond_le32_to_cpu(buffer[1]);
326         p.header[2] = cond_le32_to_cpu(buffer[2]);
327
328         tcode = (p.header[0] >> 4) & 0x0f;
329         switch (tcode) {
330         case TCODE_WRITE_QUADLET_REQUEST:
331         case TCODE_READ_QUADLET_RESPONSE:
332                 p.header[3] = (__force __u32) buffer[3];
333                 p.header_length = 16;
334                 p.payload_length = 0;
335                 break;
336
337         case TCODE_READ_BLOCK_REQUEST :
338                 p.header[3] = cond_le32_to_cpu(buffer[3]);
339                 p.header_length = 16;
340                 p.payload_length = 0;
341                 break;
342
343         case TCODE_WRITE_BLOCK_REQUEST:
344         case TCODE_READ_BLOCK_RESPONSE:
345         case TCODE_LOCK_REQUEST:
346         case TCODE_LOCK_RESPONSE:
347                 p.header[3] = cond_le32_to_cpu(buffer[3]);
348                 p.header_length = 16;
349                 p.payload_length = p.header[3] >> 16;
350                 break;
351
352         case TCODE_WRITE_RESPONSE:
353         case TCODE_READ_QUADLET_REQUEST:
354         case OHCI_TCODE_PHY_PACKET:
355                 p.header_length = 12;
356                 p.payload_length = 0;
357                 break;
358         }
359
360         p.payload = (void *) buffer + p.header_length;
361
362         /* FIXME: What to do about evt_* errors? */
363         length = (p.header_length + p.payload_length + 3) / 4;
364         status = cond_le32_to_cpu(buffer[length]);
365
366         p.ack        = ((status >> 16) & 0x1f) - 16;
367         p.speed      = (status >> 21) & 0x7;
368         p.timestamp  = status & 0xffff;
369         p.generation = ohci->request_generation;
370
371         /*
372          * The OHCI bus reset handler synthesizes a phy packet with
373          * the new generation number when a bus reset happens (see
374          * section 8.4.2.3).  This helps us determine when a request
375          * was received and make sure we send the response in the same
376          * generation.  We only need this for requests; for responses
377          * we use the unique tlabel for finding the matching
378          * request.
379          */
380
381         if (p.ack + 16 == 0x09)
382                 ohci->request_generation = (p.header[2] >> 16) & 0xff;
383         else if (ctx == &ohci->ar_request_ctx)
384                 fw_core_handle_request(&ohci->card, &p);
385         else
386                 fw_core_handle_response(&ohci->card, &p);
387
388         return buffer + length + 1;
389 }
390
391 static void ar_context_tasklet(unsigned long data)
392 {
393         struct ar_context *ctx = (struct ar_context *)data;
394         struct fw_ohci *ohci = ctx->ohci;
395         struct ar_buffer *ab;
396         struct descriptor *d;
397         void *buffer, *end;
398
399         ab = ctx->current_buffer;
400         d = &ab->descriptor;
401
402         if (d->res_count == 0) {
403                 size_t size, rest, offset;
404                 dma_addr_t start_bus;
405                 void *start;
406
407                 /*
408                  * This descriptor is finished and we may have a
409                  * packet split across this and the next buffer. We
410                  * reuse the page for reassembling the split packet.
411                  */
412
413                 offset = offsetof(struct ar_buffer, data);
414                 start = buffer = ab;
415                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
416
417                 ab = ab->next;
418                 d = &ab->descriptor;
419                 size = buffer + PAGE_SIZE - ctx->pointer;
420                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
421                 memmove(buffer, ctx->pointer, size);
422                 memcpy(buffer + size, ab->data, rest);
423                 ctx->current_buffer = ab;
424                 ctx->pointer = (void *) ab->data + rest;
425                 end = buffer + size + rest;
426
427                 while (buffer < end)
428                         buffer = handle_ar_packet(ctx, buffer);
429
430                 dma_free_coherent(ohci->card.device, PAGE_SIZE,
431                                   start, start_bus);
432                 ar_context_add_page(ctx);
433         } else {
434                 buffer = ctx->pointer;
435                 ctx->pointer = end =
436                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
437
438                 while (buffer < end)
439                         buffer = handle_ar_packet(ctx, buffer);
440         }
441 }
442
443 static int
444 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
445 {
446         struct ar_buffer ab;
447
448         ctx->regs        = regs;
449         ctx->ohci        = ohci;
450         ctx->last_buffer = &ab;
451         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
452
453         ar_context_add_page(ctx);
454         ar_context_add_page(ctx);
455         ctx->current_buffer = ab.next;
456         ctx->pointer = ctx->current_buffer->data;
457
458         return 0;
459 }
460
461 static void ar_context_run(struct ar_context *ctx)
462 {
463         struct ar_buffer *ab = ctx->current_buffer;
464         dma_addr_t ab_bus;
465         size_t offset;
466
467         offset = offsetof(struct ar_buffer, data);
468         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
469
470         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
471         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
472         flush_writes(ctx->ohci);
473 }
474
475 static struct descriptor *
476 find_branch_descriptor(struct descriptor *d, int z)
477 {
478         int b, key;
479
480         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
481         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
482
483         /* figure out which descriptor the branch address goes in */
484         if (z == 2 && (b == 3 || key == 2))
485                 return d;
486         else
487                 return d + z - 1;
488 }
489
490 static void context_tasklet(unsigned long data)
491 {
492         struct context *ctx = (struct context *) data;
493         struct descriptor *d, *last;
494         u32 address;
495         int z;
496         struct descriptor_buffer *desc;
497
498         desc = list_entry(ctx->buffer_list.next,
499                         struct descriptor_buffer, list);
500         last = ctx->last;
501         while (last->branch_address != 0) {
502                 struct descriptor_buffer *old_desc = desc;
503                 address = le32_to_cpu(last->branch_address);
504                 z = address & 0xf;
505                 address &= ~0xf;
506
507                 /* If the branch address points to a buffer outside of the
508                  * current buffer, advance to the next buffer. */
509                 if (address < desc->buffer_bus ||
510                                 address >= desc->buffer_bus + desc->used)
511                         desc = list_entry(desc->list.next,
512                                         struct descriptor_buffer, list);
513                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
514                 last = find_branch_descriptor(d, z);
515
516                 if (!ctx->callback(ctx, d, last))
517                         break;
518
519                 if (old_desc != desc) {
520                         /* If we've advanced to the next buffer, move the
521                          * previous buffer to the free list. */
522                         unsigned long flags;
523                         old_desc->used = 0;
524                         spin_lock_irqsave(&ctx->ohci->lock, flags);
525                         list_move_tail(&old_desc->list, &ctx->buffer_list);
526                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
527                 }
528                 ctx->last = last;
529         }
530 }
531
532 /*
533  * Allocate a new buffer and add it to the list of free buffers for this
534  * context.  Must be called with ohci->lock held.
535  */
536 static int
537 context_add_buffer(struct context *ctx)
538 {
539         struct descriptor_buffer *desc;
540         dma_addr_t uninitialized_var(bus_addr);
541         int offset;
542
543         /*
544          * 16MB of descriptors should be far more than enough for any DMA
545          * program.  This will catch run-away userspace or DoS attacks.
546          */
547         if (ctx->total_allocation >= 16*1024*1024)
548                 return -ENOMEM;
549
550         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
551                         &bus_addr, GFP_ATOMIC);
552         if (!desc)
553                 return -ENOMEM;
554
555         offset = (void *)&desc->buffer - (void *)desc;
556         desc->buffer_size = PAGE_SIZE - offset;
557         desc->buffer_bus = bus_addr + offset;
558         desc->used = 0;
559
560         list_add_tail(&desc->list, &ctx->buffer_list);
561         ctx->total_allocation += PAGE_SIZE;
562
563         return 0;
564 }
565
566 static int
567 context_init(struct context *ctx, struct fw_ohci *ohci,
568              u32 regs, descriptor_callback_t callback)
569 {
570         ctx->ohci = ohci;
571         ctx->regs = regs;
572         ctx->total_allocation = 0;
573
574         INIT_LIST_HEAD(&ctx->buffer_list);
575         if (context_add_buffer(ctx) < 0)
576                 return -ENOMEM;
577
578         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
579                         struct descriptor_buffer, list);
580
581         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
582         ctx->callback = callback;
583
584         /*
585          * We put a dummy descriptor in the buffer that has a NULL
586          * branch address and looks like it's been sent.  That way we
587          * have a descriptor to append DMA programs to.
588          */
589         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
590         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
591         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
592         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
593         ctx->last = ctx->buffer_tail->buffer;
594         ctx->prev = ctx->buffer_tail->buffer;
595
596         return 0;
597 }
598
599 static void
600 context_release(struct context *ctx)
601 {
602         struct fw_card *card = &ctx->ohci->card;
603         struct descriptor_buffer *desc, *tmp;
604
605         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
606                 dma_free_coherent(card->device, PAGE_SIZE, desc,
607                         desc->buffer_bus -
608                         ((void *)&desc->buffer - (void *)desc));
609 }
610
611 /* Must be called with ohci->lock held */
612 static struct descriptor *
613 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
614 {
615         struct descriptor *d = NULL;
616         struct descriptor_buffer *desc = ctx->buffer_tail;
617
618         if (z * sizeof(*d) > desc->buffer_size)
619                 return NULL;
620
621         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
622                 /* No room for the descriptor in this buffer, so advance to the
623                  * next one. */
624
625                 if (desc->list.next == &ctx->buffer_list) {
626                         /* If there is no free buffer next in the list,
627                          * allocate one. */
628                         if (context_add_buffer(ctx) < 0)
629                                 return NULL;
630                 }
631                 desc = list_entry(desc->list.next,
632                                 struct descriptor_buffer, list);
633                 ctx->buffer_tail = desc;
634         }
635
636         d = desc->buffer + desc->used / sizeof(*d);
637         memset(d, 0, z * sizeof(*d));
638         *d_bus = desc->buffer_bus + desc->used;
639
640         return d;
641 }
642
643 static void context_run(struct context *ctx, u32 extra)
644 {
645         struct fw_ohci *ohci = ctx->ohci;
646
647         reg_write(ohci, COMMAND_PTR(ctx->regs),
648                   le32_to_cpu(ctx->last->branch_address));
649         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
650         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
651         flush_writes(ohci);
652 }
653
654 static void context_append(struct context *ctx,
655                            struct descriptor *d, int z, int extra)
656 {
657         dma_addr_t d_bus;
658         struct descriptor_buffer *desc = ctx->buffer_tail;
659
660         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
661
662         desc->used += (z + extra) * sizeof(*d);
663         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
664         ctx->prev = find_branch_descriptor(d, z);
665
666         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
667         flush_writes(ctx->ohci);
668 }
669
670 static void context_stop(struct context *ctx)
671 {
672         u32 reg;
673         int i;
674
675         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
676         flush_writes(ctx->ohci);
677
678         for (i = 0; i < 10; i++) {
679                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
680                 if ((reg & CONTEXT_ACTIVE) == 0)
681                         break;
682
683                 fw_notify("context_stop: still active (0x%08x)\n", reg);
684                 mdelay(1);
685         }
686 }
687
688 struct driver_data {
689         struct fw_packet *packet;
690 };
691
692 /*
693  * This function apppends a packet to the DMA queue for transmission.
694  * Must always be called with the ochi->lock held to ensure proper
695  * generation handling and locking around packet queue manipulation.
696  */
697 static int
698 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
699 {
700         struct fw_ohci *ohci = ctx->ohci;
701         dma_addr_t d_bus, uninitialized_var(payload_bus);
702         struct driver_data *driver_data;
703         struct descriptor *d, *last;
704         __le32 *header;
705         int z, tcode;
706         u32 reg;
707
708         d = context_get_descriptors(ctx, 4, &d_bus);
709         if (d == NULL) {
710                 packet->ack = RCODE_SEND_ERROR;
711                 return -1;
712         }
713
714         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
715         d[0].res_count = cpu_to_le16(packet->timestamp);
716
717         /*
718          * The DMA format for asyncronous link packets is different
719          * from the IEEE1394 layout, so shift the fields around
720          * accordingly.  If header_length is 8, it's a PHY packet, to
721          * which we need to prepend an extra quadlet.
722          */
723
724         header = (__le32 *) &d[1];
725         if (packet->header_length > 8) {
726                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
727                                         (packet->speed << 16));
728                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
729                                         (packet->header[0] & 0xffff0000));
730                 header[2] = cpu_to_le32(packet->header[2]);
731
732                 tcode = (packet->header[0] >> 4) & 0x0f;
733                 if (TCODE_IS_BLOCK_PACKET(tcode))
734                         header[3] = cpu_to_le32(packet->header[3]);
735                 else
736                         header[3] = (__force __le32) packet->header[3];
737
738                 d[0].req_count = cpu_to_le16(packet->header_length);
739         } else {
740                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
741                                         (packet->speed << 16));
742                 header[1] = cpu_to_le32(packet->header[0]);
743                 header[2] = cpu_to_le32(packet->header[1]);
744                 d[0].req_count = cpu_to_le16(12);
745         }
746
747         driver_data = (struct driver_data *) &d[3];
748         driver_data->packet = packet;
749         packet->driver_data = driver_data;
750
751         if (packet->payload_length > 0) {
752                 payload_bus =
753                         dma_map_single(ohci->card.device, packet->payload,
754                                        packet->payload_length, DMA_TO_DEVICE);
755                 if (dma_mapping_error(payload_bus)) {
756                         packet->ack = RCODE_SEND_ERROR;
757                         return -1;
758                 }
759
760                 d[2].req_count    = cpu_to_le16(packet->payload_length);
761                 d[2].data_address = cpu_to_le32(payload_bus);
762                 last = &d[2];
763                 z = 3;
764         } else {
765                 last = &d[0];
766                 z = 2;
767         }
768
769         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
770                                      DESCRIPTOR_IRQ_ALWAYS |
771                                      DESCRIPTOR_BRANCH_ALWAYS);
772
773         /* FIXME: Document how the locking works. */
774         if (ohci->generation != packet->generation) {
775                 if (packet->payload_length > 0)
776                         dma_unmap_single(ohci->card.device, payload_bus,
777                                          packet->payload_length, DMA_TO_DEVICE);
778                 packet->ack = RCODE_GENERATION;
779                 return -1;
780         }
781
782         context_append(ctx, d, z, 4 - z);
783
784         /* If the context isn't already running, start it up. */
785         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
786         if ((reg & CONTEXT_RUN) == 0)
787                 context_run(ctx, 0);
788
789         return 0;
790 }
791
792 static int handle_at_packet(struct context *context,
793                             struct descriptor *d,
794                             struct descriptor *last)
795 {
796         struct driver_data *driver_data;
797         struct fw_packet *packet;
798         struct fw_ohci *ohci = context->ohci;
799         dma_addr_t payload_bus;
800         int evt;
801
802         if (last->transfer_status == 0)
803                 /* This descriptor isn't done yet, stop iteration. */
804                 return 0;
805
806         driver_data = (struct driver_data *) &d[3];
807         packet = driver_data->packet;
808         if (packet == NULL)
809                 /* This packet was cancelled, just continue. */
810                 return 1;
811
812         payload_bus = le32_to_cpu(last->data_address);
813         if (payload_bus != 0)
814                 dma_unmap_single(ohci->card.device, payload_bus,
815                                  packet->payload_length, DMA_TO_DEVICE);
816
817         evt = le16_to_cpu(last->transfer_status) & 0x1f;
818         packet->timestamp = le16_to_cpu(last->res_count);
819
820         switch (evt) {
821         case OHCI1394_evt_timeout:
822                 /* Async response transmit timed out. */
823                 packet->ack = RCODE_CANCELLED;
824                 break;
825
826         case OHCI1394_evt_flushed:
827                 /*
828                  * The packet was flushed should give same error as
829                  * when we try to use a stale generation count.
830                  */
831                 packet->ack = RCODE_GENERATION;
832                 break;
833
834         case OHCI1394_evt_missing_ack:
835                 /*
836                  * Using a valid (current) generation count, but the
837                  * node is not on the bus or not sending acks.
838                  */
839                 packet->ack = RCODE_NO_ACK;
840                 break;
841
842         case ACK_COMPLETE + 0x10:
843         case ACK_PENDING + 0x10:
844         case ACK_BUSY_X + 0x10:
845         case ACK_BUSY_A + 0x10:
846         case ACK_BUSY_B + 0x10:
847         case ACK_DATA_ERROR + 0x10:
848         case ACK_TYPE_ERROR + 0x10:
849                 packet->ack = evt - 0x10;
850                 break;
851
852         default:
853                 packet->ack = RCODE_SEND_ERROR;
854                 break;
855         }
856
857         packet->callback(packet, &ohci->card, packet->ack);
858
859         return 1;
860 }
861
862 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
863 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
864 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
865 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
866 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
867
868 static void
869 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
870 {
871         struct fw_packet response;
872         int tcode, length, i;
873
874         tcode = HEADER_GET_TCODE(packet->header[0]);
875         if (TCODE_IS_BLOCK_PACKET(tcode))
876                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
877         else
878                 length = 4;
879
880         i = csr - CSR_CONFIG_ROM;
881         if (i + length > CONFIG_ROM_SIZE) {
882                 fw_fill_response(&response, packet->header,
883                                  RCODE_ADDRESS_ERROR, NULL, 0);
884         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
885                 fw_fill_response(&response, packet->header,
886                                  RCODE_TYPE_ERROR, NULL, 0);
887         } else {
888                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
889                                  (void *) ohci->config_rom + i, length);
890         }
891
892         fw_core_handle_response(&ohci->card, &response);
893 }
894
895 static void
896 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
897 {
898         struct fw_packet response;
899         int tcode, length, ext_tcode, sel;
900         __be32 *payload, lock_old;
901         u32 lock_arg, lock_data;
902
903         tcode = HEADER_GET_TCODE(packet->header[0]);
904         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
905         payload = packet->payload;
906         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
907
908         if (tcode == TCODE_LOCK_REQUEST &&
909             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
910                 lock_arg = be32_to_cpu(payload[0]);
911                 lock_data = be32_to_cpu(payload[1]);
912         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
913                 lock_arg = 0;
914                 lock_data = 0;
915         } else {
916                 fw_fill_response(&response, packet->header,
917                                  RCODE_TYPE_ERROR, NULL, 0);
918                 goto out;
919         }
920
921         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
922         reg_write(ohci, OHCI1394_CSRData, lock_data);
923         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
924         reg_write(ohci, OHCI1394_CSRControl, sel);
925
926         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
927                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
928         else
929                 fw_notify("swap not done yet\n");
930
931         fw_fill_response(&response, packet->header,
932                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
933  out:
934         fw_core_handle_response(&ohci->card, &response);
935 }
936
937 static void
938 handle_local_request(struct context *ctx, struct fw_packet *packet)
939 {
940         u64 offset;
941         u32 csr;
942
943         if (ctx == &ctx->ohci->at_request_ctx) {
944                 packet->ack = ACK_PENDING;
945                 packet->callback(packet, &ctx->ohci->card, packet->ack);
946         }
947
948         offset =
949                 ((unsigned long long)
950                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
951                 packet->header[2];
952         csr = offset - CSR_REGISTER_BASE;
953
954         /* Handle config rom reads. */
955         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
956                 handle_local_rom(ctx->ohci, packet, csr);
957         else switch (csr) {
958         case CSR_BUS_MANAGER_ID:
959         case CSR_BANDWIDTH_AVAILABLE:
960         case CSR_CHANNELS_AVAILABLE_HI:
961         case CSR_CHANNELS_AVAILABLE_LO:
962                 handle_local_lock(ctx->ohci, packet, csr);
963                 break;
964         default:
965                 if (ctx == &ctx->ohci->at_request_ctx)
966                         fw_core_handle_request(&ctx->ohci->card, packet);
967                 else
968                         fw_core_handle_response(&ctx->ohci->card, packet);
969                 break;
970         }
971
972         if (ctx == &ctx->ohci->at_response_ctx) {
973                 packet->ack = ACK_COMPLETE;
974                 packet->callback(packet, &ctx->ohci->card, packet->ack);
975         }
976 }
977
978 static void
979 at_context_transmit(struct context *ctx, struct fw_packet *packet)
980 {
981         unsigned long flags;
982         int retval;
983
984         spin_lock_irqsave(&ctx->ohci->lock, flags);
985
986         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
987             ctx->ohci->generation == packet->generation) {
988                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
989                 handle_local_request(ctx, packet);
990                 return;
991         }
992
993         retval = at_context_queue_packet(ctx, packet);
994         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
995
996         if (retval < 0)
997                 packet->callback(packet, &ctx->ohci->card, packet->ack);
998
999 }
1000
1001 static void bus_reset_tasklet(unsigned long data)
1002 {
1003         struct fw_ohci *ohci = (struct fw_ohci *)data;
1004         int self_id_count, i, j, reg;
1005         int generation, new_generation;
1006         unsigned long flags;
1007         void *free_rom = NULL;
1008         dma_addr_t free_rom_bus = 0;
1009
1010         reg = reg_read(ohci, OHCI1394_NodeID);
1011         if (!(reg & OHCI1394_NodeID_idValid)) {
1012                 fw_notify("node ID not valid, new bus reset in progress\n");
1013                 return;
1014         }
1015         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1016                 fw_notify("malconfigured bus\n");
1017                 return;
1018         }
1019         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1020                                OHCI1394_NodeID_nodeNumber);
1021
1022         /*
1023          * The count in the SelfIDCount register is the number of
1024          * bytes in the self ID receive buffer.  Since we also receive
1025          * the inverted quadlets and a header quadlet, we shift one
1026          * bit extra to get the actual number of self IDs.
1027          */
1028
1029         self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
1030         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1031         rmb();
1032
1033         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1034                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
1035                         fw_error("inconsistent self IDs\n");
1036                 ohci->self_id_buffer[j] =
1037                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1038         }
1039         rmb();
1040
1041         /*
1042          * Check the consistency of the self IDs we just read.  The
1043          * problem we face is that a new bus reset can start while we
1044          * read out the self IDs from the DMA buffer. If this happens,
1045          * the DMA buffer will be overwritten with new self IDs and we
1046          * will read out inconsistent data.  The OHCI specification
1047          * (section 11.2) recommends a technique similar to
1048          * linux/seqlock.h, where we remember the generation of the
1049          * self IDs in the buffer before reading them out and compare
1050          * it to the current generation after reading them out.  If
1051          * the two generations match we know we have a consistent set
1052          * of self IDs.
1053          */
1054
1055         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1056         if (new_generation != generation) {
1057                 fw_notify("recursive bus reset detected, "
1058                           "discarding self ids\n");
1059                 return;
1060         }
1061
1062         /* FIXME: Document how the locking works. */
1063         spin_lock_irqsave(&ohci->lock, flags);
1064
1065         ohci->generation = generation;
1066         context_stop(&ohci->at_request_ctx);
1067         context_stop(&ohci->at_response_ctx);
1068         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1069
1070         /*
1071          * This next bit is unrelated to the AT context stuff but we
1072          * have to do it under the spinlock also.  If a new config rom
1073          * was set up before this reset, the old one is now no longer
1074          * in use and we can free it. Update the config rom pointers
1075          * to point to the current config rom and clear the
1076          * next_config_rom pointer so a new udpate can take place.
1077          */
1078
1079         if (ohci->next_config_rom != NULL) {
1080                 if (ohci->next_config_rom != ohci->config_rom) {
1081                         free_rom      = ohci->config_rom;
1082                         free_rom_bus  = ohci->config_rom_bus;
1083                 }
1084                 ohci->config_rom      = ohci->next_config_rom;
1085                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1086                 ohci->next_config_rom = NULL;
1087
1088                 /*
1089                  * Restore config_rom image and manually update
1090                  * config_rom registers.  Writing the header quadlet
1091                  * will indicate that the config rom is ready, so we
1092                  * do that last.
1093                  */
1094                 reg_write(ohci, OHCI1394_BusOptions,
1095                           be32_to_cpu(ohci->config_rom[2]));
1096                 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1097                 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1098         }
1099
1100         spin_unlock_irqrestore(&ohci->lock, flags);
1101
1102         if (free_rom)
1103                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1104                                   free_rom, free_rom_bus);
1105
1106         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1107                                  self_id_count, ohci->self_id_buffer);
1108 }
1109
1110 static irqreturn_t irq_handler(int irq, void *data)
1111 {
1112         struct fw_ohci *ohci = data;
1113         u32 event, iso_event, cycle_time;
1114         int i;
1115
1116         event = reg_read(ohci, OHCI1394_IntEventClear);
1117
1118         if (!event || !~event)
1119                 return IRQ_NONE;
1120
1121         reg_write(ohci, OHCI1394_IntEventClear, event);
1122
1123         if (event & OHCI1394_selfIDComplete)
1124                 tasklet_schedule(&ohci->bus_reset_tasklet);
1125
1126         if (event & OHCI1394_RQPkt)
1127                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1128
1129         if (event & OHCI1394_RSPkt)
1130                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1131
1132         if (event & OHCI1394_reqTxComplete)
1133                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1134
1135         if (event & OHCI1394_respTxComplete)
1136                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1137
1138         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1139         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1140
1141         while (iso_event) {
1142                 i = ffs(iso_event) - 1;
1143                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1144                 iso_event &= ~(1 << i);
1145         }
1146
1147         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1148         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1149
1150         while (iso_event) {
1151                 i = ffs(iso_event) - 1;
1152                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1153                 iso_event &= ~(1 << i);
1154         }
1155
1156         if (unlikely(event & OHCI1394_postedWriteErr))
1157                 fw_error("PCI posted write error\n");
1158
1159         if (unlikely(event & OHCI1394_cycleTooLong)) {
1160                 if (printk_ratelimit())
1161                         fw_notify("isochronous cycle too long\n");
1162                 reg_write(ohci, OHCI1394_LinkControlSet,
1163                           OHCI1394_LinkControl_cycleMaster);
1164         }
1165
1166         if (event & OHCI1394_cycle64Seconds) {
1167                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1168                 if ((cycle_time & 0x80000000) == 0)
1169                         ohci->bus_seconds++;
1170         }
1171
1172         return IRQ_HANDLED;
1173 }
1174
1175 static int software_reset(struct fw_ohci *ohci)
1176 {
1177         int i;
1178
1179         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1180
1181         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1182                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1183                      OHCI1394_HCControl_softReset) == 0)
1184                         return 0;
1185                 msleep(1);
1186         }
1187
1188         return -EBUSY;
1189 }
1190
1191 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1192 {
1193         struct fw_ohci *ohci = fw_ohci(card);
1194         struct pci_dev *dev = to_pci_dev(card->device);
1195
1196         if (software_reset(ohci)) {
1197                 fw_error("Failed to reset ohci card.\n");
1198                 return -EBUSY;
1199         }
1200
1201         /*
1202          * Now enable LPS, which we need in order to start accessing
1203          * most of the registers.  In fact, on some cards (ALI M5251),
1204          * accessing registers in the SClk domain without LPS enabled
1205          * will lock up the machine.  Wait 50msec to make sure we have
1206          * full link enabled.
1207          */
1208         reg_write(ohci, OHCI1394_HCControlSet,
1209                   OHCI1394_HCControl_LPS |
1210                   OHCI1394_HCControl_postedWriteEnable);
1211         flush_writes(ohci);
1212         msleep(50);
1213
1214         reg_write(ohci, OHCI1394_HCControlClear,
1215                   OHCI1394_HCControl_noByteSwapData);
1216
1217         reg_write(ohci, OHCI1394_LinkControlSet,
1218                   OHCI1394_LinkControl_rcvSelfID |
1219                   OHCI1394_LinkControl_cycleTimerEnable |
1220                   OHCI1394_LinkControl_cycleMaster);
1221
1222         reg_write(ohci, OHCI1394_ATRetries,
1223                   OHCI1394_MAX_AT_REQ_RETRIES |
1224                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1225                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1226
1227         ar_context_run(&ohci->ar_request_ctx);
1228         ar_context_run(&ohci->ar_response_ctx);
1229
1230         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1231         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1232         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1233         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1234         reg_write(ohci, OHCI1394_IntMaskSet,
1235                   OHCI1394_selfIDComplete |
1236                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1237                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1238                   OHCI1394_isochRx | OHCI1394_isochTx |
1239                   OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1240                   OHCI1394_cycle64Seconds | OHCI1394_masterIntEnable);
1241
1242         /* Activate link_on bit and contender bit in our self ID packets.*/
1243         if (ohci_update_phy_reg(card, 4, 0,
1244                                 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1245                 return -EIO;
1246
1247         /*
1248          * When the link is not yet enabled, the atomic config rom
1249          * update mechanism described below in ohci_set_config_rom()
1250          * is not active.  We have to update ConfigRomHeader and
1251          * BusOptions manually, and the write to ConfigROMmap takes
1252          * effect immediately.  We tie this to the enabling of the
1253          * link, so we have a valid config rom before enabling - the
1254          * OHCI requires that ConfigROMhdr and BusOptions have valid
1255          * values before enabling.
1256          *
1257          * However, when the ConfigROMmap is written, some controllers
1258          * always read back quadlets 0 and 2 from the config rom to
1259          * the ConfigRomHeader and BusOptions registers on bus reset.
1260          * They shouldn't do that in this initial case where the link
1261          * isn't enabled.  This means we have to use the same
1262          * workaround here, setting the bus header to 0 and then write
1263          * the right values in the bus reset tasklet.
1264          */
1265
1266         if (config_rom) {
1267                 ohci->next_config_rom =
1268                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1269                                            &ohci->next_config_rom_bus,
1270                                            GFP_KERNEL);
1271                 if (ohci->next_config_rom == NULL)
1272                         return -ENOMEM;
1273
1274                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1275                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1276         } else {
1277                 /*
1278                  * In the suspend case, config_rom is NULL, which
1279                  * means that we just reuse the old config rom.
1280                  */
1281                 ohci->next_config_rom = ohci->config_rom;
1282                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1283         }
1284
1285         ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1286         ohci->next_config_rom[0] = 0;
1287         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1288         reg_write(ohci, OHCI1394_BusOptions,
1289                   be32_to_cpu(ohci->next_config_rom[2]));
1290         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1291
1292         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1293
1294         if (request_irq(dev->irq, irq_handler,
1295                         IRQF_SHARED, ohci_driver_name, ohci)) {
1296                 fw_error("Failed to allocate shared interrupt %d.\n",
1297                          dev->irq);
1298                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1299                                   ohci->config_rom, ohci->config_rom_bus);
1300                 return -EIO;
1301         }
1302
1303         reg_write(ohci, OHCI1394_HCControlSet,
1304                   OHCI1394_HCControl_linkEnable |
1305                   OHCI1394_HCControl_BIBimageValid);
1306         flush_writes(ohci);
1307
1308         /*
1309          * We are ready to go, initiate bus reset to finish the
1310          * initialization.
1311          */
1312
1313         fw_core_initiate_bus_reset(&ohci->card, 1);
1314
1315         return 0;
1316 }
1317
1318 static int
1319 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1320 {
1321         struct fw_ohci *ohci;
1322         unsigned long flags;
1323         int retval = -EBUSY;
1324         __be32 *next_config_rom;
1325         dma_addr_t uninitialized_var(next_config_rom_bus);
1326
1327         ohci = fw_ohci(card);
1328
1329         /*
1330          * When the OHCI controller is enabled, the config rom update
1331          * mechanism is a bit tricky, but easy enough to use.  See
1332          * section 5.5.6 in the OHCI specification.
1333          *
1334          * The OHCI controller caches the new config rom address in a
1335          * shadow register (ConfigROMmapNext) and needs a bus reset
1336          * for the changes to take place.  When the bus reset is
1337          * detected, the controller loads the new values for the
1338          * ConfigRomHeader and BusOptions registers from the specified
1339          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1340          * shadow register. All automatically and atomically.
1341          *
1342          * Now, there's a twist to this story.  The automatic load of
1343          * ConfigRomHeader and BusOptions doesn't honor the
1344          * noByteSwapData bit, so with a be32 config rom, the
1345          * controller will load be32 values in to these registers
1346          * during the atomic update, even on litte endian
1347          * architectures.  The workaround we use is to put a 0 in the
1348          * header quadlet; 0 is endian agnostic and means that the
1349          * config rom isn't ready yet.  In the bus reset tasklet we
1350          * then set up the real values for the two registers.
1351          *
1352          * We use ohci->lock to avoid racing with the code that sets
1353          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1354          */
1355
1356         next_config_rom =
1357                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1358                                    &next_config_rom_bus, GFP_KERNEL);
1359         if (next_config_rom == NULL)
1360                 return -ENOMEM;
1361
1362         spin_lock_irqsave(&ohci->lock, flags);
1363
1364         if (ohci->next_config_rom == NULL) {
1365                 ohci->next_config_rom = next_config_rom;
1366                 ohci->next_config_rom_bus = next_config_rom_bus;
1367
1368                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1369                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1370                                   length * 4);
1371
1372                 ohci->next_header = config_rom[0];
1373                 ohci->next_config_rom[0] = 0;
1374
1375                 reg_write(ohci, OHCI1394_ConfigROMmap,
1376                           ohci->next_config_rom_bus);
1377                 retval = 0;
1378         }
1379
1380         spin_unlock_irqrestore(&ohci->lock, flags);
1381
1382         /*
1383          * Now initiate a bus reset to have the changes take
1384          * effect. We clean up the old config rom memory and DMA
1385          * mappings in the bus reset tasklet, since the OHCI
1386          * controller could need to access it before the bus reset
1387          * takes effect.
1388          */
1389         if (retval == 0)
1390                 fw_core_initiate_bus_reset(&ohci->card, 1);
1391         else
1392                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1393                                   next_config_rom, next_config_rom_bus);
1394
1395         return retval;
1396 }
1397
1398 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1399 {
1400         struct fw_ohci *ohci = fw_ohci(card);
1401
1402         at_context_transmit(&ohci->at_request_ctx, packet);
1403 }
1404
1405 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1406 {
1407         struct fw_ohci *ohci = fw_ohci(card);
1408
1409         at_context_transmit(&ohci->at_response_ctx, packet);
1410 }
1411
1412 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1413 {
1414         struct fw_ohci *ohci = fw_ohci(card);
1415         struct context *ctx = &ohci->at_request_ctx;
1416         struct driver_data *driver_data = packet->driver_data;
1417         int retval = -ENOENT;
1418
1419         tasklet_disable(&ctx->tasklet);
1420
1421         if (packet->ack != 0)
1422                 goto out;
1423
1424         driver_data->packet = NULL;
1425         packet->ack = RCODE_CANCELLED;
1426         packet->callback(packet, &ohci->card, packet->ack);
1427         retval = 0;
1428
1429  out:
1430         tasklet_enable(&ctx->tasklet);
1431
1432         return retval;
1433 }
1434
1435 static int
1436 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1437 {
1438         struct fw_ohci *ohci = fw_ohci(card);
1439         unsigned long flags;
1440         int n, retval = 0;
1441
1442         /*
1443          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1444          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1445          */
1446
1447         spin_lock_irqsave(&ohci->lock, flags);
1448
1449         if (ohci->generation != generation) {
1450                 retval = -ESTALE;
1451                 goto out;
1452         }
1453
1454         /*
1455          * Note, if the node ID contains a non-local bus ID, physical DMA is
1456          * enabled for _all_ nodes on remote buses.
1457          */
1458
1459         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1460         if (n < 32)
1461                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1462         else
1463                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1464
1465         flush_writes(ohci);
1466  out:
1467         spin_unlock_irqrestore(&ohci->lock, flags);
1468         return retval;
1469 }
1470
1471 static u64
1472 ohci_get_bus_time(struct fw_card *card)
1473 {
1474         struct fw_ohci *ohci = fw_ohci(card);
1475         u32 cycle_time;
1476         u64 bus_time;
1477
1478         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1479         bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1480
1481         return bus_time;
1482 }
1483
1484 static int handle_ir_dualbuffer_packet(struct context *context,
1485                                        struct descriptor *d,
1486                                        struct descriptor *last)
1487 {
1488         struct iso_context *ctx =
1489                 container_of(context, struct iso_context, context);
1490         struct db_descriptor *db = (struct db_descriptor *) d;
1491         __le32 *ir_header;
1492         size_t header_length;
1493         void *p, *end;
1494         int i;
1495
1496         if (db->first_res_count != 0 && db->second_res_count != 0) {
1497                 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1498                         /* This descriptor isn't done yet, stop iteration. */
1499                         return 0;
1500                 }
1501                 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1502         }
1503
1504         header_length = le16_to_cpu(db->first_req_count) -
1505                 le16_to_cpu(db->first_res_count);
1506
1507         i = ctx->header_length;
1508         p = db + 1;
1509         end = p + header_length;
1510         while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1511                 /*
1512                  * The iso header is byteswapped to little endian by
1513                  * the controller, but the remaining header quadlets
1514                  * are big endian.  We want to present all the headers
1515                  * as big endian, so we have to swap the first
1516                  * quadlet.
1517                  */
1518                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1519                 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1520                 i += ctx->base.header_size;
1521                 ctx->excess_bytes +=
1522                         (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1523                 p += ctx->base.header_size + 4;
1524         }
1525         ctx->header_length = i;
1526
1527         ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1528                 le16_to_cpu(db->second_res_count);
1529
1530         if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1531                 ir_header = (__le32 *) (db + 1);
1532                 ctx->base.callback(&ctx->base,
1533                                    le32_to_cpu(ir_header[0]) & 0xffff,
1534                                    ctx->header_length, ctx->header,
1535                                    ctx->base.callback_data);
1536                 ctx->header_length = 0;
1537         }
1538
1539         return 1;
1540 }
1541
1542 static int handle_ir_packet_per_buffer(struct context *context,
1543                                        struct descriptor *d,
1544                                        struct descriptor *last)
1545 {
1546         struct iso_context *ctx =
1547                 container_of(context, struct iso_context, context);
1548         struct descriptor *pd;
1549         __le32 *ir_header;
1550         void *p;
1551         int i;
1552
1553         for (pd = d; pd <= last; pd++) {
1554                 if (pd->transfer_status)
1555                         break;
1556         }
1557         if (pd > last)
1558                 /* Descriptor(s) not done yet, stop iteration */
1559                 return 0;
1560
1561         i   = ctx->header_length;
1562         p   = last + 1;
1563
1564         if (ctx->base.header_size > 0 &&
1565                         i + ctx->base.header_size <= PAGE_SIZE) {
1566                 /*
1567                  * The iso header is byteswapped to little endian by
1568                  * the controller, but the remaining header quadlets
1569                  * are big endian.  We want to present all the headers
1570                  * as big endian, so we have to swap the first quadlet.
1571                  */
1572                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1573                 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1574                 ctx->header_length += ctx->base.header_size;
1575         }
1576
1577         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1578                 ir_header = (__le32 *) p;
1579                 ctx->base.callback(&ctx->base,
1580                                    le32_to_cpu(ir_header[0]) & 0xffff,
1581                                    ctx->header_length, ctx->header,
1582                                    ctx->base.callback_data);
1583                 ctx->header_length = 0;
1584         }
1585
1586         return 1;
1587 }
1588
1589 static int handle_it_packet(struct context *context,
1590                             struct descriptor *d,
1591                             struct descriptor *last)
1592 {
1593         struct iso_context *ctx =
1594                 container_of(context, struct iso_context, context);
1595
1596         if (last->transfer_status == 0)
1597                 /* This descriptor isn't done yet, stop iteration. */
1598                 return 0;
1599
1600         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1601                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1602                                    0, NULL, ctx->base.callback_data);
1603
1604         return 1;
1605 }
1606
1607 static struct fw_iso_context *
1608 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1609 {
1610         struct fw_ohci *ohci = fw_ohci(card);
1611         struct iso_context *ctx, *list;
1612         descriptor_callback_t callback;
1613         u32 *mask, regs;
1614         unsigned long flags;
1615         int index, retval = -ENOMEM;
1616
1617         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1618                 mask = &ohci->it_context_mask;
1619                 list = ohci->it_context_list;
1620                 callback = handle_it_packet;
1621         } else {
1622                 mask = &ohci->ir_context_mask;
1623                 list = ohci->ir_context_list;
1624                 if (ohci->version >= OHCI_VERSION_1_1)
1625                         callback = handle_ir_dualbuffer_packet;
1626                 else
1627                         callback = handle_ir_packet_per_buffer;
1628         }
1629
1630         spin_lock_irqsave(&ohci->lock, flags);
1631         index = ffs(*mask) - 1;
1632         if (index >= 0)
1633                 *mask &= ~(1 << index);
1634         spin_unlock_irqrestore(&ohci->lock, flags);
1635
1636         if (index < 0)
1637                 return ERR_PTR(-EBUSY);
1638
1639         if (type == FW_ISO_CONTEXT_TRANSMIT)
1640                 regs = OHCI1394_IsoXmitContextBase(index);
1641         else
1642                 regs = OHCI1394_IsoRcvContextBase(index);
1643
1644         ctx = &list[index];
1645         memset(ctx, 0, sizeof(*ctx));
1646         ctx->header_length = 0;
1647         ctx->header = (void *) __get_free_page(GFP_KERNEL);
1648         if (ctx->header == NULL)
1649                 goto out;
1650
1651         retval = context_init(&ctx->context, ohci, regs, callback);
1652         if (retval < 0)
1653                 goto out_with_header;
1654
1655         return &ctx->base;
1656
1657  out_with_header:
1658         free_page((unsigned long)ctx->header);
1659  out:
1660         spin_lock_irqsave(&ohci->lock, flags);
1661         *mask |= 1 << index;
1662         spin_unlock_irqrestore(&ohci->lock, flags);
1663
1664         return ERR_PTR(retval);
1665 }
1666
1667 static int ohci_start_iso(struct fw_iso_context *base,
1668                           s32 cycle, u32 sync, u32 tags)
1669 {
1670         struct iso_context *ctx = container_of(base, struct iso_context, base);
1671         struct fw_ohci *ohci = ctx->context.ohci;
1672         u32 control, match;
1673         int index;
1674
1675         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1676                 index = ctx - ohci->it_context_list;
1677                 match = 0;
1678                 if (cycle >= 0)
1679                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1680                                 (cycle & 0x7fff) << 16;
1681
1682                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1683                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1684                 context_run(&ctx->context, match);
1685         } else {
1686                 index = ctx - ohci->ir_context_list;
1687                 control = IR_CONTEXT_ISOCH_HEADER;
1688                 if (ohci->version >= OHCI_VERSION_1_1)
1689                         control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1690                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1691                 if (cycle >= 0) {
1692                         match |= (cycle & 0x07fff) << 12;
1693                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1694                 }
1695
1696                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1697                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1698                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1699                 context_run(&ctx->context, control);
1700         }
1701
1702         return 0;
1703 }
1704
1705 static int ohci_stop_iso(struct fw_iso_context *base)
1706 {
1707         struct fw_ohci *ohci = fw_ohci(base->card);
1708         struct iso_context *ctx = container_of(base, struct iso_context, base);
1709         int index;
1710
1711         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1712                 index = ctx - ohci->it_context_list;
1713                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1714         } else {
1715                 index = ctx - ohci->ir_context_list;
1716                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1717         }
1718         flush_writes(ohci);
1719         context_stop(&ctx->context);
1720
1721         return 0;
1722 }
1723
1724 static void ohci_free_iso_context(struct fw_iso_context *base)
1725 {
1726         struct fw_ohci *ohci = fw_ohci(base->card);
1727         struct iso_context *ctx = container_of(base, struct iso_context, base);
1728         unsigned long flags;
1729         int index;
1730
1731         ohci_stop_iso(base);
1732         context_release(&ctx->context);
1733         free_page((unsigned long)ctx->header);
1734
1735         spin_lock_irqsave(&ohci->lock, flags);
1736
1737         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1738                 index = ctx - ohci->it_context_list;
1739                 ohci->it_context_mask |= 1 << index;
1740         } else {
1741                 index = ctx - ohci->ir_context_list;
1742                 ohci->ir_context_mask |= 1 << index;
1743         }
1744
1745         spin_unlock_irqrestore(&ohci->lock, flags);
1746 }
1747
1748 static int
1749 ohci_queue_iso_transmit(struct fw_iso_context *base,
1750                         struct fw_iso_packet *packet,
1751                         struct fw_iso_buffer *buffer,
1752                         unsigned long payload)
1753 {
1754         struct iso_context *ctx = container_of(base, struct iso_context, base);
1755         struct descriptor *d, *last, *pd;
1756         struct fw_iso_packet *p;
1757         __le32 *header;
1758         dma_addr_t d_bus, page_bus;
1759         u32 z, header_z, payload_z, irq;
1760         u32 payload_index, payload_end_index, next_page_index;
1761         int page, end_page, i, length, offset;
1762
1763         /*
1764          * FIXME: Cycle lost behavior should be configurable: lose
1765          * packet, retransmit or terminate..
1766          */
1767
1768         p = packet;
1769         payload_index = payload;
1770
1771         if (p->skip)
1772                 z = 1;
1773         else
1774                 z = 2;
1775         if (p->header_length > 0)
1776                 z++;
1777
1778         /* Determine the first page the payload isn't contained in. */
1779         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1780         if (p->payload_length > 0)
1781                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1782         else
1783                 payload_z = 0;
1784
1785         z += payload_z;
1786
1787         /* Get header size in number of descriptors. */
1788         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
1789
1790         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
1791         if (d == NULL)
1792                 return -ENOMEM;
1793
1794         if (!p->skip) {
1795                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1796                 d[0].req_count = cpu_to_le16(8);
1797
1798                 header = (__le32 *) &d[1];
1799                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
1800                                         IT_HEADER_TAG(p->tag) |
1801                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
1802                                         IT_HEADER_CHANNEL(ctx->base.channel) |
1803                                         IT_HEADER_SPEED(ctx->base.speed));
1804                 header[1] =
1805                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
1806                                                           p->payload_length));
1807         }
1808
1809         if (p->header_length > 0) {
1810                 d[2].req_count    = cpu_to_le16(p->header_length);
1811                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
1812                 memcpy(&d[z], p->header, p->header_length);
1813         }
1814
1815         pd = d + z - payload_z;
1816         payload_end_index = payload_index + p->payload_length;
1817         for (i = 0; i < payload_z; i++) {
1818                 page               = payload_index >> PAGE_SHIFT;
1819                 offset             = payload_index & ~PAGE_MASK;
1820                 next_page_index    = (page + 1) << PAGE_SHIFT;
1821                 length             =
1822                         min(next_page_index, payload_end_index) - payload_index;
1823                 pd[i].req_count    = cpu_to_le16(length);
1824
1825                 page_bus = page_private(buffer->pages[page]);
1826                 pd[i].data_address = cpu_to_le32(page_bus + offset);
1827
1828                 payload_index += length;
1829         }
1830
1831         if (p->interrupt)
1832                 irq = DESCRIPTOR_IRQ_ALWAYS;
1833         else
1834                 irq = DESCRIPTOR_NO_IRQ;
1835
1836         last = z == 2 ? d : d + z - 1;
1837         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1838                                      DESCRIPTOR_STATUS |
1839                                      DESCRIPTOR_BRANCH_ALWAYS |
1840                                      irq);
1841
1842         context_append(&ctx->context, d, z, header_z);
1843
1844         return 0;
1845 }
1846
1847 static int
1848 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
1849                                   struct fw_iso_packet *packet,
1850                                   struct fw_iso_buffer *buffer,
1851                                   unsigned long payload)
1852 {
1853         struct iso_context *ctx = container_of(base, struct iso_context, base);
1854         struct db_descriptor *db = NULL;
1855         struct descriptor *d;
1856         struct fw_iso_packet *p;
1857         dma_addr_t d_bus, page_bus;
1858         u32 z, header_z, length, rest;
1859         int page, offset, packet_count, header_size;
1860
1861         /*
1862          * FIXME: Cycle lost behavior should be configurable: lose
1863          * packet, retransmit or terminate..
1864          */
1865
1866         p = packet;
1867         z = 2;
1868
1869         /*
1870          * The OHCI controller puts the status word in the header
1871          * buffer too, so we need 4 extra bytes per packet.
1872          */
1873         packet_count = p->header_length / ctx->base.header_size;
1874         header_size = packet_count * (ctx->base.header_size + 4);
1875
1876         /* Get header size in number of descriptors. */
1877         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
1878         page     = payload >> PAGE_SHIFT;
1879         offset   = payload & ~PAGE_MASK;
1880         rest     = p->payload_length;
1881
1882         /* FIXME: make packet-per-buffer/dual-buffer a context option */
1883         while (rest > 0) {
1884                 d = context_get_descriptors(&ctx->context,
1885                                             z + header_z, &d_bus);
1886                 if (d == NULL)
1887                         return -ENOMEM;
1888
1889                 db = (struct db_descriptor *) d;
1890                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1891                                           DESCRIPTOR_BRANCH_ALWAYS);
1892                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1893                 if (p->skip && rest == p->payload_length) {
1894                         db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
1895                         db->first_req_count = db->first_size;
1896                 } else {
1897                         db->first_req_count = cpu_to_le16(header_size);
1898                 }
1899                 db->first_res_count = db->first_req_count;
1900                 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
1901
1902                 if (p->skip && rest == p->payload_length)
1903                         length = 4;
1904                 else if (offset + rest < PAGE_SIZE)
1905                         length = rest;
1906                 else
1907                         length = PAGE_SIZE - offset;
1908
1909                 db->second_req_count = cpu_to_le16(length);
1910                 db->second_res_count = db->second_req_count;
1911                 page_bus = page_private(buffer->pages[page]);
1912                 db->second_buffer = cpu_to_le32(page_bus + offset);
1913
1914                 if (p->interrupt && length == rest)
1915                         db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
1916
1917                 context_append(&ctx->context, d, z, header_z);
1918                 offset = (offset + length) & ~PAGE_MASK;
1919                 rest -= length;
1920                 if (offset == 0)
1921                         page++;
1922         }
1923
1924         return 0;
1925 }
1926
1927 static int
1928 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
1929                                          struct fw_iso_packet *packet,
1930                                          struct fw_iso_buffer *buffer,
1931                                          unsigned long payload)
1932 {
1933         struct iso_context *ctx = container_of(base, struct iso_context, base);
1934         struct descriptor *d = NULL, *pd = NULL;
1935         struct fw_iso_packet *p = packet;
1936         dma_addr_t d_bus, page_bus;
1937         u32 z, header_z, rest;
1938         int i, j, length;
1939         int page, offset, packet_count, header_size, payload_per_buffer;
1940
1941         /*
1942          * The OHCI controller puts the status word in the
1943          * buffer too, so we need 4 extra bytes per packet.
1944          */
1945         packet_count = p->header_length / ctx->base.header_size;
1946         header_size  = ctx->base.header_size + 4;
1947
1948         /* Get header size in number of descriptors. */
1949         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
1950         page     = payload >> PAGE_SHIFT;
1951         offset   = payload & ~PAGE_MASK;
1952         payload_per_buffer = p->payload_length / packet_count;
1953
1954         for (i = 0; i < packet_count; i++) {
1955                 /* d points to the header descriptor */
1956                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
1957                 d = context_get_descriptors(&ctx->context,
1958                                 z + header_z, &d_bus);
1959                 if (d == NULL)
1960                         return -ENOMEM;
1961
1962                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
1963                                               DESCRIPTOR_INPUT_MORE);
1964                 if (p->skip && i == 0)
1965                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
1966                 d->req_count    = cpu_to_le16(header_size);
1967                 d->res_count    = d->req_count;
1968                 d->transfer_status = 0;
1969                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
1970
1971                 rest = payload_per_buffer;
1972                 for (j = 1; j < z; j++) {
1973                         pd = d + j;
1974                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
1975                                                   DESCRIPTOR_INPUT_MORE);
1976
1977                         if (offset + rest < PAGE_SIZE)
1978                                 length = rest;
1979                         else
1980                                 length = PAGE_SIZE - offset;
1981                         pd->req_count = cpu_to_le16(length);
1982                         pd->res_count = pd->req_count;
1983                         pd->transfer_status = 0;
1984
1985                         page_bus = page_private(buffer->pages[page]);
1986                         pd->data_address = cpu_to_le32(page_bus + offset);
1987
1988                         offset = (offset + length) & ~PAGE_MASK;
1989                         rest -= length;
1990                         if (offset == 0)
1991                                 page++;
1992                 }
1993                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
1994                                           DESCRIPTOR_INPUT_LAST |
1995                                           DESCRIPTOR_BRANCH_ALWAYS);
1996                 if (p->interrupt && i == packet_count - 1)
1997                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
1998
1999                 context_append(&ctx->context, d, z, header_z);
2000         }
2001
2002         return 0;
2003 }
2004
2005 static int
2006 ohci_queue_iso(struct fw_iso_context *base,
2007                struct fw_iso_packet *packet,
2008                struct fw_iso_buffer *buffer,
2009                unsigned long payload)
2010 {
2011         struct iso_context *ctx = container_of(base, struct iso_context, base);
2012         unsigned long flags;
2013         int retval;
2014
2015         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2016         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2017                 retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
2018         else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
2019                 retval = ohci_queue_iso_receive_dualbuffer(base, packet,
2020                                                          buffer, payload);
2021         else
2022                 retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2023                                                                 buffer,
2024                                                                 payload);
2025         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2026
2027         return retval;
2028 }
2029
2030 static const struct fw_card_driver ohci_driver = {
2031         .name                   = ohci_driver_name,
2032         .enable                 = ohci_enable,
2033         .update_phy_reg         = ohci_update_phy_reg,
2034         .set_config_rom         = ohci_set_config_rom,
2035         .send_request           = ohci_send_request,
2036         .send_response          = ohci_send_response,
2037         .cancel_packet          = ohci_cancel_packet,
2038         .enable_phys_dma        = ohci_enable_phys_dma,
2039         .get_bus_time           = ohci_get_bus_time,
2040
2041         .allocate_iso_context   = ohci_allocate_iso_context,
2042         .free_iso_context       = ohci_free_iso_context,
2043         .queue_iso              = ohci_queue_iso,
2044         .start_iso              = ohci_start_iso,
2045         .stop_iso               = ohci_stop_iso,
2046 };
2047
2048 static int __devinit
2049 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
2050 {
2051         struct fw_ohci *ohci;
2052         u32 bus_options, max_receive, link_speed;
2053         u64 guid;
2054         int err;
2055         size_t size;
2056
2057 #ifdef CONFIG_PPC_PMAC
2058         /* Necessary on some machines if fw-ohci was loaded/ unloaded before */
2059         if (machine_is(powermac)) {
2060                 struct device_node *ofn = pci_device_to_OF_node(dev);
2061
2062                 if (ofn) {
2063                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2064                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2065                 }
2066         }
2067 #endif /* CONFIG_PPC_PMAC */
2068
2069         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2070         if (ohci == NULL) {
2071                 fw_error("Could not malloc fw_ohci data.\n");
2072                 return -ENOMEM;
2073         }
2074
2075         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2076
2077         err = pci_enable_device(dev);
2078         if (err) {
2079                 fw_error("Failed to enable OHCI hardware.\n");
2080                 goto fail_put_card;
2081         }
2082
2083         pci_set_master(dev);
2084         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2085         pci_set_drvdata(dev, ohci);
2086
2087 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2088         ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2089                              dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2090 #endif
2091         spin_lock_init(&ohci->lock);
2092
2093         tasklet_init(&ohci->bus_reset_tasklet,
2094                      bus_reset_tasklet, (unsigned long)ohci);
2095
2096         err = pci_request_region(dev, 0, ohci_driver_name);
2097         if (err) {
2098                 fw_error("MMIO resource unavailable\n");
2099                 goto fail_disable;
2100         }
2101
2102         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2103         if (ohci->registers == NULL) {
2104                 fw_error("Failed to remap registers\n");
2105                 err = -ENXIO;
2106                 goto fail_iomem;
2107         }
2108
2109         ar_context_init(&ohci->ar_request_ctx, ohci,
2110                         OHCI1394_AsReqRcvContextControlSet);
2111
2112         ar_context_init(&ohci->ar_response_ctx, ohci,
2113                         OHCI1394_AsRspRcvContextControlSet);
2114
2115         context_init(&ohci->at_request_ctx, ohci,
2116                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2117
2118         context_init(&ohci->at_response_ctx, ohci,
2119                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2120
2121         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2122         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2123         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2124         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2125         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2126
2127         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2128         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2129         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2130         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2131         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2132
2133         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2134                 fw_error("Out of memory for it/ir contexts.\n");
2135                 err = -ENOMEM;
2136                 goto fail_registers;
2137         }
2138
2139         /* self-id dma buffer allocation */
2140         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2141                                                SELF_ID_BUF_SIZE,
2142                                                &ohci->self_id_bus,
2143                                                GFP_KERNEL);
2144         if (ohci->self_id_cpu == NULL) {
2145                 fw_error("Out of memory for self ID buffer.\n");
2146                 err = -ENOMEM;
2147                 goto fail_registers;
2148         }
2149
2150         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2151         max_receive = (bus_options >> 12) & 0xf;
2152         link_speed = bus_options & 0x7;
2153         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2154                 reg_read(ohci, OHCI1394_GUIDLo);
2155
2156         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2157         if (err < 0)
2158                 goto fail_self_id;
2159
2160         ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2161         fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2162                   dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
2163         return 0;
2164
2165  fail_self_id:
2166         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2167                           ohci->self_id_cpu, ohci->self_id_bus);
2168  fail_registers:
2169         kfree(ohci->it_context_list);
2170         kfree(ohci->ir_context_list);
2171         pci_iounmap(dev, ohci->registers);
2172  fail_iomem:
2173         pci_release_region(dev, 0);
2174  fail_disable:
2175         pci_disable_device(dev);
2176  fail_put_card:
2177         fw_card_put(&ohci->card);
2178
2179         return err;
2180 }
2181
2182 static void pci_remove(struct pci_dev *dev)
2183 {
2184         struct fw_ohci *ohci;
2185
2186         ohci = pci_get_drvdata(dev);
2187         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2188         flush_writes(ohci);
2189         fw_core_remove_card(&ohci->card);
2190
2191         /*
2192          * FIXME: Fail all pending packets here, now that the upper
2193          * layers can't queue any more.
2194          */
2195
2196         software_reset(ohci);
2197         free_irq(dev->irq, ohci);
2198         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2199                           ohci->self_id_cpu, ohci->self_id_bus);
2200         kfree(ohci->it_context_list);
2201         kfree(ohci->ir_context_list);
2202         pci_iounmap(dev, ohci->registers);
2203         pci_release_region(dev, 0);
2204         pci_disable_device(dev);
2205         fw_card_put(&ohci->card);
2206
2207 #ifdef CONFIG_PPC_PMAC
2208         /* On UniNorth, power down the cable and turn off the chip clock
2209          * to save power on laptops */
2210         if (machine_is(powermac)) {
2211                 struct device_node *ofn = pci_device_to_OF_node(dev);
2212
2213                 if (ofn) {
2214                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2215                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2216                 }
2217         }
2218 #endif /* CONFIG_PPC_PMAC */
2219
2220         fw_notify("Removed fw-ohci device.\n");
2221 }
2222
2223 #ifdef CONFIG_PM
2224 static int pci_suspend(struct pci_dev *pdev, pm_message_t state)
2225 {
2226         struct fw_ohci *ohci = pci_get_drvdata(pdev);
2227         int err;
2228
2229         software_reset(ohci);
2230         free_irq(pdev->irq, ohci);
2231         err = pci_save_state(pdev);
2232         if (err) {
2233                 fw_error("pci_save_state failed\n");
2234                 return err;
2235         }
2236         err = pci_set_power_state(pdev, pci_choose_state(pdev, state));
2237         if (err)
2238                 fw_error("pci_set_power_state failed with %d\n", err);
2239
2240 /* PowerMac suspend code comes last */
2241 #ifdef CONFIG_PPC_PMAC
2242         if (machine_is(powermac)) {
2243                 struct device_node *ofn = pci_device_to_OF_node(pdev);
2244
2245                 if (ofn)
2246                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2247         }
2248 #endif /* CONFIG_PPC_PMAC */
2249
2250         return 0;
2251 }
2252
2253 static int pci_resume(struct pci_dev *pdev)
2254 {
2255         struct fw_ohci *ohci = pci_get_drvdata(pdev);
2256         int err;
2257
2258 /* PowerMac resume code comes first */
2259 #ifdef CONFIG_PPC_PMAC
2260         if (machine_is(powermac)) {
2261                 struct device_node *ofn = pci_device_to_OF_node(pdev);
2262
2263                 if (ofn)
2264                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2265         }
2266 #endif /* CONFIG_PPC_PMAC */
2267
2268         pci_set_power_state(pdev, PCI_D0);
2269         pci_restore_state(pdev);
2270         err = pci_enable_device(pdev);
2271         if (err) {
2272                 fw_error("pci_enable_device failed\n");
2273                 return err;
2274         }
2275
2276         return ohci_enable(&ohci->card, NULL, 0);
2277 }
2278 #endif
2279
2280 static struct pci_device_id pci_table[] = {
2281         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2282         { }
2283 };
2284
2285 MODULE_DEVICE_TABLE(pci, pci_table);
2286
2287 static struct pci_driver fw_ohci_pci_driver = {
2288         .name           = ohci_driver_name,
2289         .id_table       = pci_table,
2290         .probe          = pci_probe,
2291         .remove         = pci_remove,
2292 #ifdef CONFIG_PM
2293         .resume         = pci_resume,
2294         .suspend        = pci_suspend,
2295 #endif
2296 };
2297
2298 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2299 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2300 MODULE_LICENSE("GPL");
2301
2302 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2303 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2304 MODULE_ALIAS("ohci1394");
2305 #endif
2306
2307 static int __init fw_ohci_init(void)
2308 {
2309         return pci_register_driver(&fw_ohci_pci_driver);
2310 }
2311
2312 static void __exit fw_ohci_cleanup(void)
2313 {
2314         pci_unregister_driver(&fw_ohci_pci_driver);
2315 }
2316
2317 module_init(fw_ohci_init);
2318 module_exit(fw_ohci_cleanup);