git.oblomov.eu Git - linux-2.6/blob - drivers/media/video/cx88/cx88-mpeg.c

   1 /*
   2  * $Id: cx88-mpeg.c,v 1.31 2005/07/07 14:17:47 mchehab Exp $
   3  *
   4  *  Support for the mpeg transport stream transfers
   5  *  PCI function #2 of the cx2388x.
   6  *
   7  *    (c) 2004 Jelle Foks <jelle@foks.8m.com>
   8  *    (c) 2004 Chris Pascoe <c.pascoe@itee.uq.edu.au>
   9  *    (c) 2004 Gerd Knorr <kraxel@bytesex.org>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2 of the License, or
  14  *  (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; if not, write to the Free Software
  23  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/init.h>
  29 #include <linux/device.h>
  30 #include <linux/interrupt.h>
  31 #include <asm/delay.h>
  32
  33 #include "cx88.h"
  34
  35 /* ------------------------------------------------------------------ */
  36
  37 MODULE_DESCRIPTION("mpeg driver for cx2388x based TV cards");
  38 MODULE_AUTHOR("Jelle Foks <jelle@foks.8m.com>");
  39 MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
  40 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
  41 MODULE_LICENSE("GPL");
  42
  43 static unsigned int debug = 0;
  44 module_param(debug,int,0644);
  45 MODULE_PARM_DESC(debug,"enable debug messages [mpeg]");
  46
  47 #define dprintk(level,fmt, arg...)      if (debug >= level) \
  48         printk(KERN_DEBUG "%s/2: " fmt, dev->core->name , ## arg)
  49
  50 /* ------------------------------------------------------------------ */
  51
  52 static int cx8802_start_dma(struct cx8802_dev    *dev,
  53                             struct cx88_dmaqueue *q,
  54                             struct cx88_buffer   *buf)
  55 {
  56         struct cx88_core *core = dev->core;
  57
  58         dprintk(0, "cx8802_start_dma %d\n", buf->vb.width);
  59
  60         /* setup fifo + format */
  61         cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28],
  62                                 dev->ts_packet_size, buf->risc.dma);
  63
  64         /* write TS length to chip */
  65         cx_write(MO_TS_LNGTH, buf->vb.width);
  66
  67         /* FIXME: this needs a review.
  68          * also: move to cx88-blackbird + cx88-dvb source files? */
  69
  70         if (cx88_boards[core->board].dvb) {
  71                 /* negedge driven & software reset */
  72                 cx_write(TS_GEN_CNTRL, 0x0040 | dev->ts_gen_cntrl);
  73                 udelay(100);
  74                 cx_write(MO_PINMUX_IO, 0x00);
  75                 cx_write(TS_HW_SOP_CNTRL,0x47<<16|188<<4|0x01);
  76                 if ((core->board == CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q) ||
  77                     (core->board == CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T)) {
  78                         cx_write(TS_SOP_STAT, 1<<13);
  79                 } else {
  80                         cx_write(TS_SOP_STAT, 0x00);
  81                 }
  82                 cx_write(TS_GEN_CNTRL, dev->ts_gen_cntrl);
  83                 udelay(100);
  84         }
  85
  86         if (cx88_boards[core->board].blackbird) {
  87                 cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */
  88
  89                 // cx_write(TS_F2_CMD_STAT_MM, 0x2900106); /* F2_CMD_STAT_MM defaults + master + memory space */
  90                 cx_write(TS_GEN_CNTRL, 0x46); /* punctured clock TS & posedge driven & software reset */
  91                 udelay(100);
  92
  93                 cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */
  94                 //cx_write(TS_HW_SOP_CNTRL, 0x2F0BC0); /* mpeg start byte ts: 0x2F0BC0 ? */
  95                 cx_write(TS_VALERR_CNTRL, 0x2000);
  96
  97                 cx_write(TS_GEN_CNTRL, 0x06); /* punctured clock TS & posedge driven */
  98                 udelay(100);
  99         }
 100
 101         /* reset counter */
 102         cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET);
 103         q->count = 1;
 104
 105         /* enable irqs */
 106         dprintk( 0, "setting the interrupt mask\n" );
 107         cx_set(MO_PCI_INTMSK, core->pci_irqmask | 0x04);
 108         cx_set(MO_TS_INTMSK,  0x1f0011);
 109         //cx_write(MO_TS_INTMSK,  0x0f0011);
 110
 111         /* start dma */
 112         cx_set(MO_DEV_CNTRL2, (1<<5));
 113         cx_set(MO_TS_DMACNTRL, 0x11);
 114         return 0;
 115 }
 116
 117 static int cx8802_stop_dma(struct cx8802_dev *dev)
 118 {
 119         struct cx88_core *core = dev->core;
 120         dprintk( 0, "cx8802_stop_dma\n" );
 121
 122         /* stop dma */
 123         cx_clear(MO_TS_DMACNTRL, 0x11);
 124
 125         /* disable irqs */
 126         cx_clear(MO_PCI_INTMSK, 0x000004);
 127         cx_clear(MO_TS_INTMSK, 0x1f0011);
 128
 129         /* Reset the controller */
 130         cx_write(TS_GEN_CNTRL, 0xcd);
 131         return 0;
 132 }
 133
 134 static int cx8802_restart_queue(struct cx8802_dev    *dev,
 135                                 struct cx88_dmaqueue *q)
 136 {
 137         struct cx88_buffer *buf;
 138         struct list_head *item;
 139
 140         dprintk( 0, "cx8802_restart_queue\n" );
 141         if (list_empty(&q->active))
 142         {
 143                 dprintk( 0, "cx8802_restart_queue: queue is empty\n" );
 144                 return 0;
 145         }
 146
 147         buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
 148         dprintk(2,"restart_queue [%p/%d]: restart dma\n",
 149                 buf, buf->vb.i);
 150         cx8802_start_dma(dev, q, buf);
 151         list_for_each(item,&q->active) {
 152                 buf = list_entry(item, struct cx88_buffer, vb.queue);
 153                 buf->count = q->count++;
 154         }
 155         mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
 156         return 0;
 157 }
 158
 159 /* ------------------------------------------------------------------ */
 160
 161 int cx8802_buf_prepare(struct cx8802_dev *dev, struct cx88_buffer *buf)
 162 {
 163         int size = dev->ts_packet_size * dev->ts_packet_count;
 164         int rc;
 165
 166         dprintk(1, "%s: %p\n", __FUNCTION__, buf);
 167         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
 168                 return -EINVAL;
 169
 170         if (STATE_NEEDS_INIT == buf->vb.state) {
 171                 buf->vb.width  = dev->ts_packet_size;
 172                 buf->vb.height = dev->ts_packet_count;
 173                 buf->vb.size   = size;
 174                 buf->vb.field  = V4L2_FIELD_TOP;
 175
 176                 if (0 != (rc = videobuf_iolock(dev->pci,&buf->vb,NULL)))
 177                         goto fail;
 178                 cx88_risc_databuffer(dev->pci, &buf->risc,
 179                                      buf->vb.dma.sglist,
 180                                      buf->vb.width, buf->vb.height);
 181         }
 182         buf->vb.state = STATE_PREPARED;
 183         return 0;
 184
 185  fail:
 186         cx88_free_buffer(dev->pci,buf);
 187         return rc;
 188 }
 189
 190 void cx8802_buf_queue(struct cx8802_dev *dev, struct cx88_buffer *buf)
 191 {
 192         struct cx88_buffer    *prev;
 193         struct cx88_dmaqueue  *q    = &dev->mpegq;
 194
 195         dprintk( 1, "cx8802_buf_queue\n" );
 196         /* add jump to stopper */
 197         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
 198         buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
 199
 200         if (list_empty(&q->active)) {
 201                 dprintk( 0, "queue is empty - first active\n" );
 202                 list_add_tail(&buf->vb.queue,&q->active);
 203                 cx8802_start_dma(dev, q, buf);
 204                 buf->vb.state = STATE_ACTIVE;
 205                 buf->count    = q->count++;
 206                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
 207                 dprintk(0,"[%p/%d] %s - first active\n",
 208                         buf, buf->vb.i, __FUNCTION__);
 209                 //udelay(100);
 210
 211         } else {
 212                 dprintk( 1, "queue is not empty - append to active\n" );
 213                 prev = list_entry(q->active.prev, struct cx88_buffer, vb.queue);
 214                 list_add_tail(&buf->vb.queue,&q->active);
 215                 buf->vb.state = STATE_ACTIVE;
 216                 buf->count    = q->count++;
 217                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
 218                 dprintk( 1, "[%p/%d] %s - append to active\n",
 219                         buf, buf->vb.i, __FUNCTION__);
 220                 //udelay(100);
 221         }
 222 }
 223
 224 /* ----------------------------------------------------------- */
 225
 226 static void do_cancel_buffers(struct cx8802_dev *dev, char *reason, int restart)
 227 {
 228         struct cx88_dmaqueue *q = &dev->mpegq;
 229         struct cx88_buffer *buf;
 230         unsigned long flags;
 231
 232         spin_lock_irqsave(&dev->slock,flags);
 233         while (!list_empty(&q->active)) {
 234                 buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
 235                 list_del(&buf->vb.queue);
 236                 buf->vb.state = STATE_ERROR;
 237                 wake_up(&buf->vb.done);
 238                 dprintk(1,"[%p/%d] %s - dma=0x%08lx\n",
 239                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
 240         }
 241         if (restart)
 242         {
 243                 dprintk(0, "restarting queue\n" );
 244                 cx8802_restart_queue(dev,q);
 245         }
 246         spin_unlock_irqrestore(&dev->slock,flags);
 247 }
 248
 249 void cx8802_cancel_buffers(struct cx8802_dev *dev)
 250 {
 251         struct cx88_dmaqueue *q = &dev->mpegq;
 252
 253         dprintk( 1, "cx8802_cancel_buffers" );
 254         del_timer_sync(&q->timeout);
 255         cx8802_stop_dma(dev);
 256         do_cancel_buffers(dev,"cancel",0);
 257 }
 258
 259 static void cx8802_timeout(unsigned long data)
 260 {
 261         struct cx8802_dev *dev = (struct cx8802_dev*)data;
 262
 263         dprintk(0, "%s\n",__FUNCTION__);
 264
 265         if (debug)
 266                 cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
 267         cx8802_stop_dma(dev);
 268         do_cancel_buffers(dev,"timeout",1);
 269 }
 270
 271 static char *cx88_mpeg_irqs[32] = {
 272         "ts_risci1", NULL, NULL, NULL,
 273         "ts_risci2", NULL, NULL, NULL,
 274         "ts_oflow",  NULL, NULL, NULL,
 275         "ts_sync",   NULL, NULL, NULL,
 276         "opc_err", "par_err", "rip_err", "pci_abort",
 277         "ts_err?",
 278 };
 279
 280 static void cx8802_mpeg_irq(struct cx8802_dev *dev)
 281 {
 282         struct cx88_core *core = dev->core;
 283         u32 status, mask, count;
 284
 285         dprintk( 1, "cx8802_mpeg_irq\n" );
 286         status = cx_read(MO_TS_INTSTAT);
 287         mask   = cx_read(MO_TS_INTMSK);
 288         if (0 == (status & mask))
 289                 return;
 290
 291         cx_write(MO_TS_INTSTAT, status);
 292
 293         if (debug || (status & mask & ~0xff))
 294                 cx88_print_irqbits(core->name, "irq mpeg ",
 295                                    cx88_mpeg_irqs, status, mask);
 296
 297         /* risc op code error */
 298         if (status & (1 << 16)) {
 299                 printk(KERN_WARNING "%s: mpeg risc op code error\n",core->name);
 300                 cx_clear(MO_TS_DMACNTRL, 0x11);
 301                 cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
 302         }
 303
 304         /* risc1 y */
 305         if (status & 0x01) {
 306                 dprintk( 1, "wake up\n" );
 307                 spin_lock(&dev->slock);
 308                 count = cx_read(MO_TS_GPCNT);
 309                 cx88_wakeup(dev->core, &dev->mpegq, count);
 310                 spin_unlock(&dev->slock);
 311         }
 312
 313         /* risc2 y */
 314         if (status & 0x10) {
 315                 spin_lock(&dev->slock);
 316                 cx8802_restart_queue(dev,&dev->mpegq);
 317                 spin_unlock(&dev->slock);
 318         }
 319
 320         /* other general errors */
 321         if (status & 0x1f0100) {
 322                 dprintk( 0, "general errors: 0x%08x\n", status & 0x1f0100 );
 323                 spin_lock(&dev->slock);
 324                 cx8802_stop_dma(dev);
 325                 cx8802_restart_queue(dev,&dev->mpegq);
 326                 spin_unlock(&dev->slock);
 327         }
 328 }
 329
 330 #define MAX_IRQ_LOOP 10
 331
 332 static irqreturn_t cx8802_irq(int irq, void *dev_id, struct pt_regs *regs)
 333 {
 334         struct cx8802_dev *dev = dev_id;
 335         struct cx88_core *core = dev->core;
 336         u32 status;
 337         int loop, handled = 0;
 338
 339         for (loop = 0; loop < MAX_IRQ_LOOP; loop++) {
 340                 status = cx_read(MO_PCI_INTSTAT) & (core->pci_irqmask | 0x04);
 341                 if (0 == status)
 342                         goto out;
 343                 dprintk( 1, "cx8802_irq\n" );
 344                 dprintk( 1, "    loop: %d/%d\n", loop, MAX_IRQ_LOOP );
 345                 dprintk( 1, "    status: %d\n", status );
 346                 handled = 1;
 347                 cx_write(MO_PCI_INTSTAT, status);
 348
 349                 if (status & core->pci_irqmask)
 350                         cx88_core_irq(core,status);
 351                 if (status & 0x04)
 352                         cx8802_mpeg_irq(dev);
 353         };
 354         if (MAX_IRQ_LOOP == loop) {
 355                 dprintk( 0, "clearing mask\n" );
 356                 printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n",
 357                        core->name);
 358                 cx_write(MO_PCI_INTMSK,0);
 359         }
 360
 361  out:
 362         return IRQ_RETVAL(handled);
 363 }
 364
 365 /* ----------------------------------------------------------- */
 366 /* exported stuff                                              */
 367
 368 int cx8802_init_common(struct cx8802_dev *dev)
 369 {
 370         struct cx88_core *core = dev->core;
 371         int err;
 372
 373         /* pci init */
 374         if (pci_enable_device(dev->pci))
 375                 return -EIO;
 376         pci_set_master(dev->pci);
 377         if (!pci_dma_supported(dev->pci,0xffffffff)) {
 378                 printk("%s/2: Oops: no 32bit PCI DMA ???\n",dev->core->name);
 379                 return -EIO;
 380         }
 381
 382         pci_read_config_byte(dev->pci, PCI_CLASS_REVISION, &dev->pci_rev);
 383         pci_read_config_byte(dev->pci, PCI_LATENCY_TIMER,  &dev->pci_lat);
 384         printk(KERN_INFO "%s/2: found at %s, rev: %d, irq: %d, "
 385                "latency: %d, mmio: 0x%lx\n", dev->core->name,
 386                pci_name(dev->pci), dev->pci_rev, dev->pci->irq,
 387                dev->pci_lat,pci_resource_start(dev->pci,0));
 388
 389         /* initialize driver struct */
 390         init_MUTEX(&dev->lock);
 391         spin_lock_init(&dev->slock);
 392
 393         /* init dma queue */
 394         INIT_LIST_HEAD(&dev->mpegq.active);
 395         INIT_LIST_HEAD(&dev->mpegq.queued);
 396         dev->mpegq.timeout.function = cx8802_timeout;
 397         dev->mpegq.timeout.data     = (unsigned long)dev;
 398         init_timer(&dev->mpegq.timeout);
 399         cx88_risc_stopper(dev->pci,&dev->mpegq.stopper,
 400                           MO_TS_DMACNTRL,0x11,0x00);
 401
 402         /* get irq */
 403         err = request_irq(dev->pci->irq, cx8802_irq,
 404                           SA_SHIRQ | SA_INTERRUPT, dev->core->name, dev);
 405         if (err < 0) {
 406                 printk(KERN_ERR "%s: can't get IRQ %d\n",
 407                        dev->core->name, dev->pci->irq);
 408                 return err;
 409         }
 410         cx_set(MO_PCI_INTMSK, core->pci_irqmask);
 411
 412         /* everything worked */
 413         pci_set_drvdata(dev->pci,dev);
 414         return 0;
 415 }
 416
 417 void cx8802_fini_common(struct cx8802_dev *dev)
 418 {
 419         dprintk( 2, "cx8802_fini_common\n" );
 420         cx8802_stop_dma(dev);
 421         pci_disable_device(dev->pci);
 422
 423         /* unregister stuff */
 424         free_irq(dev->pci->irq, dev);
 425         pci_set_drvdata(dev->pci, NULL);
 426
 427         /* free memory */
 428         btcx_riscmem_free(dev->pci,&dev->mpegq.stopper);
 429 }
 430
 431 /* ----------------------------------------------------------- */
 432
 433 int cx8802_suspend_common(struct pci_dev *pci_dev, pm_message_t state)
 434 {
 435         struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
 436         struct cx88_core *core = dev->core;
 437
 438         /* stop mpeg dma */
 439         spin_lock(&dev->slock);
 440         if (!list_empty(&dev->mpegq.active)) {
 441                 dprintk( 2, "suspend\n" );
 442                 printk("%s: suspend mpeg\n", core->name);
 443                 cx8802_stop_dma(dev);
 444                 del_timer(&dev->mpegq.timeout);
 445         }
 446         spin_unlock(&dev->slock);
 447
 448         /* FIXME -- shutdown device */
 449         cx88_shutdown(dev->core);
 450
 451         pci_save_state(pci_dev);
 452         if (0 != pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state))) {
 453                 pci_disable_device(pci_dev);
 454                 dev->state.disabled = 1;
 455         }
 456         return 0;
 457 }
 458
 459 int cx8802_resume_common(struct pci_dev *pci_dev)
 460 {
 461         struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
 462         struct cx88_core *core = dev->core;
 463
 464         if (dev->state.disabled) {
 465                 pci_enable_device(pci_dev);
 466                 dev->state.disabled = 0;
 467         }
 468         pci_set_power_state(pci_dev, PCI_D0);
 469         pci_restore_state(pci_dev);
 470
 471         /* FIXME: re-initialize hardware */
 472         cx88_reset(dev->core);
 473
 474         /* restart video+vbi capture */
 475         spin_lock(&dev->slock);
 476         if (!list_empty(&dev->mpegq.active)) {
 477                 printk("%s: resume mpeg\n", core->name);
 478                 cx8802_restart_queue(dev,&dev->mpegq);
 479         }
 480         spin_unlock(&dev->slock);
 481
 482         return 0;
 483 }
 484
 485 /* ----------------------------------------------------------- */
 486
 487 EXPORT_SYMBOL(cx8802_buf_prepare);
 488 EXPORT_SYMBOL(cx8802_buf_queue);
 489 EXPORT_SYMBOL(cx8802_cancel_buffers);
 490
 491 EXPORT_SYMBOL(cx8802_init_common);
 492 EXPORT_SYMBOL(cx8802_fini_common);
 493
 494 EXPORT_SYMBOL(cx8802_suspend_common);
 495 EXPORT_SYMBOL(cx8802_resume_common);
 496
 497 /* ----------------------------------------------------------- */
 498 /*
 499  * Local variables:
 500  * c-basic-offset: 8
 501  * End:
 502  * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
 503  */