git.oblomov.eu Git - linux-2.6/blob - drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004, 2005 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12 #include "bnx2.h"
  13 #include "bnx2_fw.h"
  14
  15 #define DRV_MODULE_NAME         "bnx2"
  16 #define PFX DRV_MODULE_NAME     ": "
  17 #define DRV_MODULE_VERSION      "1.2.20"
  18 #define DRV_MODULE_RELDATE      "August 22, 2005"
  19
  20 #define RUN_AT(x) (jiffies + (x))
  21
  22 /* Time in jiffies before concluding the transmitter is hung. */
  23 #define TX_TIMEOUT  (5*HZ)
  24
  25 static char version[] __devinitdata =
  26         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  27
  28 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  29 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver");
  30 MODULE_LICENSE("GPL");
  31 MODULE_VERSION(DRV_MODULE_VERSION);
  32
  33 static int disable_msi = 0;
  34
  35 module_param(disable_msi, int, 0);
  36 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  37
  38 typedef enum {
  39         BCM5706 = 0,
  40         NC370T,
  41         NC370I,
  42         BCM5706S,
  43         NC370F,
  44 } board_t;
  45
  46 /* indexed by board_t, above */
  47 static struct {
  48         char *name;
  49 } board_info[] __devinitdata = {
  50         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  51         { "HP NC370T Multifunction Gigabit Server Adapter" },
  52         { "HP NC370i Multifunction Gigabit Server Adapter" },
  53         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
  54         { "HP NC370F Multifunction Gigabit Server Adapter" },
  55         };
  56
  57 static struct pci_device_id bnx2_pci_tbl[] = {
  58         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  59           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
  60         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  61           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
  62         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  63           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
  64         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  65           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
  66         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  67           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
  68         { 0, }
  69 };
  70
  71 static struct flash_spec flash_table[] =
  72 {
  73         /* Slow EEPROM */
  74         {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400,
  75          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  76          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  77          "EEPROM - slow"},
  78         /* Fast EEPROM */
  79         {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400,
  80          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  81          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  82          "EEPROM - fast"},
  83         /* ATMEL AT45DB011B (buffered flash) */
  84         {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400,
  85          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  86          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
  87          "Buffered flash"},
  88         /* Saifun SA25F005 (non-buffered flash) */
  89         /* strap, cfg1, & write1 need updates */
  90         {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406,
  91          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  92          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
  93          "Non-buffered flash (64kB)"},
  94         /* Saifun SA25F010 (non-buffered flash) */
  95         /* strap, cfg1, & write1 need updates */
  96         {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406,
  97          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  98          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
  99          "Non-buffered flash (128kB)"},
 100         /* Saifun SA25F020 (non-buffered flash) */
 101         /* strap, cfg1, & write1 need updates */
 102         {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406,
 103          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 104          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 105          "Non-buffered flash (256kB)"},
 106 };
 107
 108 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 109
 110 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
 111 {
 112         u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
 113
 114         if (diff > MAX_TX_DESC_CNT)
 115                 diff = (diff & MAX_TX_DESC_CNT) - 1;
 116         return (bp->tx_ring_size - diff);
 117 }
 118
 119 static u32
 120 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 121 {
 122         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 123         return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
 124 }
 125
 126 static void
 127 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 128 {
 129         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 130         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 131 }
 132
 133 static void
 134 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 135 {
 136         offset += cid_addr;
 137         REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 138         REG_WR(bp, BNX2_CTX_DATA, val);
 139 }
 140
 141 static int
 142 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 143 {
 144         u32 val1;
 145         int i, ret;
 146
 147         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 148                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 149                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 150
 151                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 152                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 153
 154                 udelay(40);
 155         }
 156
 157         val1 = (bp->phy_addr << 21) | (reg << 16) |
 158                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 159                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 160         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 161
 162         for (i = 0; i < 50; i++) {
 163                 udelay(10);
 164
 165                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 166                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 167                         udelay(5);
 168
 169                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 170                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 171
 172                         break;
 173                 }
 174         }
 175
 176         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 177                 *val = 0x0;
 178                 ret = -EBUSY;
 179         }
 180         else {
 181                 *val = val1;
 182                 ret = 0;
 183         }
 184
 185         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 186                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 187                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 188
 189                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 190                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 191
 192                 udelay(40);
 193         }
 194
 195         return ret;
 196 }
 197
 198 static int
 199 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 200 {
 201         u32 val1;
 202         int i, ret;
 203
 204         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 205                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 206                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 207
 208                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 209                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 210
 211                 udelay(40);
 212         }
 213
 214         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 215                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 216                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 217         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 218
 219         for (i = 0; i < 50; i++) {
 220                 udelay(10);
 221
 222                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 223                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 224                         udelay(5);
 225                         break;
 226                 }
 227         }
 228
 229         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 230                 ret = -EBUSY;
 231         else
 232                 ret = 0;
 233
 234         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 235                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 236                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 237
 238                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 239                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 240
 241                 udelay(40);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 bnx2_disable_int(struct bnx2 *bp)
 249 {
 250         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 251                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 252         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 253 }
 254
 255 static void
 256 bnx2_enable_int(struct bnx2 *bp)
 257 {
 258         u32 val;
 259
 260         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 261                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
 262
 263         val = REG_RD(bp, BNX2_HC_COMMAND);
 264         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
 265 }
 266
 267 static void
 268 bnx2_disable_int_sync(struct bnx2 *bp)
 269 {
 270         atomic_inc(&bp->intr_sem);
 271         bnx2_disable_int(bp);
 272         synchronize_irq(bp->pdev->irq);
 273 }
 274
 275 static void
 276 bnx2_netif_stop(struct bnx2 *bp)
 277 {
 278         bnx2_disable_int_sync(bp);
 279         if (netif_running(bp->dev)) {
 280                 netif_poll_disable(bp->dev);
 281                 netif_tx_disable(bp->dev);
 282                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 283         }
 284 }
 285
 286 static void
 287 bnx2_netif_start(struct bnx2 *bp)
 288 {
 289         if (atomic_dec_and_test(&bp->intr_sem)) {
 290                 if (netif_running(bp->dev)) {
 291                         netif_wake_queue(bp->dev);
 292                         netif_poll_enable(bp->dev);
 293                         bnx2_enable_int(bp);
 294                 }
 295         }
 296 }
 297
 298 static void
 299 bnx2_free_mem(struct bnx2 *bp)
 300 {
 301         if (bp->stats_blk) {
 302                 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
 303                                     bp->stats_blk, bp->stats_blk_mapping);
 304                 bp->stats_blk = NULL;
 305         }
 306         if (bp->status_blk) {
 307                 pci_free_consistent(bp->pdev, sizeof(struct status_block),
 308                                     bp->status_blk, bp->status_blk_mapping);
 309                 bp->status_blk = NULL;
 310         }
 311         if (bp->tx_desc_ring) {
 312                 pci_free_consistent(bp->pdev,
 313                                     sizeof(struct tx_bd) * TX_DESC_CNT,
 314                                     bp->tx_desc_ring, bp->tx_desc_mapping);
 315                 bp->tx_desc_ring = NULL;
 316         }
 317         if (bp->tx_buf_ring) {
 318                 kfree(bp->tx_buf_ring);
 319                 bp->tx_buf_ring = NULL;
 320         }
 321         if (bp->rx_desc_ring) {
 322                 pci_free_consistent(bp->pdev,
 323                                     sizeof(struct rx_bd) * RX_DESC_CNT,
 324                                     bp->rx_desc_ring, bp->rx_desc_mapping);
 325                 bp->rx_desc_ring = NULL;
 326         }
 327         if (bp->rx_buf_ring) {
 328                 kfree(bp->rx_buf_ring);
 329                 bp->rx_buf_ring = NULL;
 330         }
 331 }
 332
 333 static int
 334 bnx2_alloc_mem(struct bnx2 *bp)
 335 {
 336         bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
 337                                      GFP_KERNEL);
 338         if (bp->tx_buf_ring == NULL)
 339                 return -ENOMEM;
 340
 341         memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
 342         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
 343                                                 sizeof(struct tx_bd) *
 344                                                 TX_DESC_CNT,
 345                                                 &bp->tx_desc_mapping);
 346         if (bp->tx_desc_ring == NULL)
 347                 goto alloc_mem_err;
 348
 349         bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
 350                                      GFP_KERNEL);
 351         if (bp->rx_buf_ring == NULL)
 352                 goto alloc_mem_err;
 353
 354         memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
 355         bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
 356                                                 sizeof(struct rx_bd) *
 357                                                 RX_DESC_CNT,
 358                                                 &bp->rx_desc_mapping);
 359         if (bp->rx_desc_ring == NULL)
 360                 goto alloc_mem_err;
 361
 362         bp->status_blk = pci_alloc_consistent(bp->pdev,
 363                                               sizeof(struct status_block),
 364                                               &bp->status_blk_mapping);
 365         if (bp->status_blk == NULL)
 366                 goto alloc_mem_err;
 367
 368         memset(bp->status_blk, 0, sizeof(struct status_block));
 369
 370         bp->stats_blk = pci_alloc_consistent(bp->pdev,
 371                                              sizeof(struct statistics_block),
 372                                              &bp->stats_blk_mapping);
 373         if (bp->stats_blk == NULL)
 374                 goto alloc_mem_err;
 375
 376         memset(bp->stats_blk, 0, sizeof(struct statistics_block));
 377
 378         return 0;
 379
 380 alloc_mem_err:
 381         bnx2_free_mem(bp);
 382         return -ENOMEM;
 383 }
 384
 385 static void
 386 bnx2_report_link(struct bnx2 *bp)
 387 {
 388         if (bp->link_up) {
 389                 netif_carrier_on(bp->dev);
 390                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
 391
 392                 printk("%d Mbps ", bp->line_speed);
 393
 394                 if (bp->duplex == DUPLEX_FULL)
 395                         printk("full duplex");
 396                 else
 397                         printk("half duplex");
 398
 399                 if (bp->flow_ctrl) {
 400                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 401                                 printk(", receive ");
 402                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 403                                         printk("& transmit ");
 404                         }
 405                         else {
 406                                 printk(", transmit ");
 407                         }
 408                         printk("flow control ON");
 409                 }
 410                 printk("\n");
 411         }
 412         else {
 413                 netif_carrier_off(bp->dev);
 414                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
 415         }
 416 }
 417
 418 static void
 419 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 420 {
 421         u32 local_adv, remote_adv;
 422
 423         bp->flow_ctrl = 0;
 424         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 425                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 426
 427                 if (bp->duplex == DUPLEX_FULL) {
 428                         bp->flow_ctrl = bp->req_flow_ctrl;
 429                 }
 430                 return;
 431         }
 432
 433         if (bp->duplex != DUPLEX_FULL) {
 434                 return;
 435         }
 436
 437         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 438         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 439
 440         if (bp->phy_flags & PHY_SERDES_FLAG) {
 441                 u32 new_local_adv = 0;
 442                 u32 new_remote_adv = 0;
 443
 444                 if (local_adv & ADVERTISE_1000XPAUSE)
 445                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 446                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 447                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 448                 if (remote_adv & ADVERTISE_1000XPAUSE)
 449                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 450                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 451                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 452
 453                 local_adv = new_local_adv;
 454                 remote_adv = new_remote_adv;
 455         }
 456
 457         /* See Table 28B-3 of 802.3ab-1999 spec. */
 458         if (local_adv & ADVERTISE_PAUSE_CAP) {
 459                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 460                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 461                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 462                         }
 463                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 464                                 bp->flow_ctrl = FLOW_CTRL_RX;
 465                         }
 466                 }
 467                 else {
 468                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 469                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 470                         }
 471                 }
 472         }
 473         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 474                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 475                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 476
 477                         bp->flow_ctrl = FLOW_CTRL_TX;
 478                 }
 479         }
 480 }
 481
 482 static int
 483 bnx2_serdes_linkup(struct bnx2 *bp)
 484 {
 485         u32 bmcr, local_adv, remote_adv, common;
 486
 487         bp->link_up = 1;
 488         bp->line_speed = SPEED_1000;
 489
 490         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 491         if (bmcr & BMCR_FULLDPLX) {
 492                 bp->duplex = DUPLEX_FULL;
 493         }
 494         else {
 495                 bp->duplex = DUPLEX_HALF;
 496         }
 497
 498         if (!(bmcr & BMCR_ANENABLE)) {
 499                 return 0;
 500         }
 501
 502         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 503         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 504
 505         common = local_adv & remote_adv;
 506         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
 507
 508                 if (common & ADVERTISE_1000XFULL) {
 509                         bp->duplex = DUPLEX_FULL;
 510                 }
 511                 else {
 512                         bp->duplex = DUPLEX_HALF;
 513                 }
 514         }
 515
 516         return 0;
 517 }
 518
 519 static int
 520 bnx2_copper_linkup(struct bnx2 *bp)
 521 {
 522         u32 bmcr;
 523
 524         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 525         if (bmcr & BMCR_ANENABLE) {
 526                 u32 local_adv, remote_adv, common;
 527
 528                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
 529                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
 530
 531                 common = local_adv & (remote_adv >> 2);
 532                 if (common & ADVERTISE_1000FULL) {
 533                         bp->line_speed = SPEED_1000;
 534                         bp->duplex = DUPLEX_FULL;
 535                 }
 536                 else if (common & ADVERTISE_1000HALF) {
 537                         bp->line_speed = SPEED_1000;
 538                         bp->duplex = DUPLEX_HALF;
 539                 }
 540                 else {
 541                         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 542                         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 543
 544                         common = local_adv & remote_adv;
 545                         if (common & ADVERTISE_100FULL) {
 546                                 bp->line_speed = SPEED_100;
 547                                 bp->duplex = DUPLEX_FULL;
 548                         }
 549                         else if (common & ADVERTISE_100HALF) {
 550                                 bp->line_speed = SPEED_100;
 551                                 bp->duplex = DUPLEX_HALF;
 552                         }
 553                         else if (common & ADVERTISE_10FULL) {
 554                                 bp->line_speed = SPEED_10;
 555                                 bp->duplex = DUPLEX_FULL;
 556                         }
 557                         else if (common & ADVERTISE_10HALF) {
 558                                 bp->line_speed = SPEED_10;
 559                                 bp->duplex = DUPLEX_HALF;
 560                         }
 561                         else {
 562                                 bp->line_speed = 0;
 563                                 bp->link_up = 0;
 564                         }
 565                 }
 566         }
 567         else {
 568                 if (bmcr & BMCR_SPEED100) {
 569                         bp->line_speed = SPEED_100;
 570                 }
 571                 else {
 572                         bp->line_speed = SPEED_10;
 573                 }
 574                 if (bmcr & BMCR_FULLDPLX) {
 575                         bp->duplex = DUPLEX_FULL;
 576                 }
 577                 else {
 578                         bp->duplex = DUPLEX_HALF;
 579                 }
 580         }
 581
 582         return 0;
 583 }
 584
 585 static int
 586 bnx2_set_mac_link(struct bnx2 *bp)
 587 {
 588         u32 val;
 589
 590         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
 591         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
 592                 (bp->duplex == DUPLEX_HALF)) {
 593                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
 594         }
 595
 596         /* Configure the EMAC mode register. */
 597         val = REG_RD(bp, BNX2_EMAC_MODE);
 598
 599         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
 600                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK);
 601
 602         if (bp->link_up) {
 603                 if (bp->line_speed != SPEED_1000)
 604                         val |= BNX2_EMAC_MODE_PORT_MII;
 605                 else
 606                         val |= BNX2_EMAC_MODE_PORT_GMII;
 607         }
 608         else {
 609                 val |= BNX2_EMAC_MODE_PORT_GMII;
 610         }
 611
 612         /* Set the MAC to operate in the appropriate duplex mode. */
 613         if (bp->duplex == DUPLEX_HALF)
 614                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
 615         REG_WR(bp, BNX2_EMAC_MODE, val);
 616
 617         /* Enable/disable rx PAUSE. */
 618         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
 619
 620         if (bp->flow_ctrl & FLOW_CTRL_RX)
 621                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
 622         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
 623
 624         /* Enable/disable tx PAUSE. */
 625         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
 626         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
 627
 628         if (bp->flow_ctrl & FLOW_CTRL_TX)
 629                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
 630         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
 631
 632         /* Acknowledge the interrupt. */
 633         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
 634
 635         return 0;
 636 }
 637
 638 static int
 639 bnx2_set_link(struct bnx2 *bp)
 640 {
 641         u32 bmsr;
 642         u8 link_up;
 643
 644         if (bp->loopback == MAC_LOOPBACK) {
 645                 bp->link_up = 1;
 646                 return 0;
 647         }
 648
 649         link_up = bp->link_up;
 650
 651         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 652         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 653
 654         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 655             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
 656                 u32 val;
 657
 658                 val = REG_RD(bp, BNX2_EMAC_STATUS);
 659                 if (val & BNX2_EMAC_STATUS_LINK)
 660                         bmsr |= BMSR_LSTATUS;
 661                 else
 662                         bmsr &= ~BMSR_LSTATUS;
 663         }
 664
 665         if (bmsr & BMSR_LSTATUS) {
 666                 bp->link_up = 1;
 667
 668                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 669                         bnx2_serdes_linkup(bp);
 670                 }
 671                 else {
 672                         bnx2_copper_linkup(bp);
 673                 }
 674                 bnx2_resolve_flow_ctrl(bp);
 675         }
 676         else {
 677                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 678                         (bp->autoneg & AUTONEG_SPEED)) {
 679
 680                         u32 bmcr;
 681
 682                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 683                         if (!(bmcr & BMCR_ANENABLE)) {
 684                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
 685                                         BMCR_ANENABLE);
 686                         }
 687                 }
 688                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
 689                 bp->link_up = 0;
 690         }
 691
 692         if (bp->link_up != link_up) {
 693                 bnx2_report_link(bp);
 694         }
 695
 696         bnx2_set_mac_link(bp);
 697
 698         return 0;
 699 }
 700
 701 static int
 702 bnx2_reset_phy(struct bnx2 *bp)
 703 {
 704         int i;
 705         u32 reg;
 706
 707         bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
 708
 709 #define PHY_RESET_MAX_WAIT 100
 710         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
 711                 udelay(10);
 712
 713                 bnx2_read_phy(bp, MII_BMCR, &reg);
 714                 if (!(reg & BMCR_RESET)) {
 715                         udelay(20);
 716                         break;
 717                 }
 718         }
 719         if (i == PHY_RESET_MAX_WAIT) {
 720                 return -EBUSY;
 721         }
 722         return 0;
 723 }
 724
 725 static u32
 726 bnx2_phy_get_pause_adv(struct bnx2 *bp)
 727 {
 728         u32 adv = 0;
 729
 730         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
 731                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
 732
 733                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 734                         adv = ADVERTISE_1000XPAUSE;
 735                 }
 736                 else {
 737                         adv = ADVERTISE_PAUSE_CAP;
 738                 }
 739         }
 740         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
 741                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 742                         adv = ADVERTISE_1000XPSE_ASYM;
 743                 }
 744                 else {
 745                         adv = ADVERTISE_PAUSE_ASYM;
 746                 }
 747         }
 748         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
 749                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 750                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
 751                 }
 752                 else {
 753                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 754                 }
 755         }
 756         return adv;
 757 }
 758
 759 static int
 760 bnx2_setup_serdes_phy(struct bnx2 *bp)
 761 {
 762         u32 adv, bmcr;
 763         u32 new_adv = 0;
 764
 765         if (!(bp->autoneg & AUTONEG_SPEED)) {
 766                 u32 new_bmcr;
 767
 768                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
 769                 new_bmcr = bmcr & ~BMCR_ANENABLE;
 770                 new_bmcr |= BMCR_SPEED1000;
 771                 if (bp->req_duplex == DUPLEX_FULL) {
 772                         new_bmcr |= BMCR_FULLDPLX;
 773                 }
 774                 else {
 775                         new_bmcr &= ~BMCR_FULLDPLX;
 776                 }
 777                 if (new_bmcr != bmcr) {
 778                         /* Force a link down visible on the other side */
 779                         if (bp->link_up) {
 780                                 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
 781                                 adv &= ~(ADVERTISE_1000XFULL |
 782                                         ADVERTISE_1000XHALF);
 783                                 bnx2_write_phy(bp, MII_ADVERTISE, adv);
 784                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
 785                                         BMCR_ANRESTART | BMCR_ANENABLE);
 786
 787                                 bp->link_up = 0;
 788                                 netif_carrier_off(bp->dev);
 789                         }
 790                         bnx2_write_phy(bp, MII_BMCR, new_bmcr);
 791                 }
 792                 return 0;
 793         }
 794
 795         if (bp->advertising & ADVERTISED_1000baseT_Full)
 796                 new_adv |= ADVERTISE_1000XFULL;
 797
 798         new_adv |= bnx2_phy_get_pause_adv(bp);
 799
 800         bnx2_read_phy(bp, MII_ADVERTISE, &adv);
 801         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 802
 803         bp->serdes_an_pending = 0;
 804         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
 805                 /* Force a link down visible on the other side */
 806                 if (bp->link_up) {
 807                         int i;
 808
 809                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
 810                         for (i = 0; i < 110; i++) {
 811                                 udelay(100);
 812                         }
 813                 }
 814
 815                 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
 816                 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
 817                         BMCR_ANENABLE);
 818                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
 819                         /* Speed up link-up time when the link partner
 820                          * does not autonegotiate which is very common
 821                          * in blade servers. Some blade servers use
 822                          * IPMI for kerboard input and it's important
 823                          * to minimize link disruptions. Autoneg. involves
 824                          * exchanging base pages plus 3 next pages and
 825                          * normally completes in about 120 msec.
 826                          */
 827                         bp->current_interval = SERDES_AN_TIMEOUT;
 828                         bp->serdes_an_pending = 1;
 829                         mod_timer(&bp->timer, jiffies + bp->current_interval);
 830                 }
 831         }
 832
 833         return 0;
 834 }
 835
 836 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
 837         (ADVERTISED_1000baseT_Full)
 838
 839 #define ETHTOOL_ALL_COPPER_SPEED                                        \
 840         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
 841         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
 842         ADVERTISED_1000baseT_Full)
 843
 844 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
 845         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
 846
 847 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
 848
 849 static int
 850 bnx2_setup_copper_phy(struct bnx2 *bp)
 851 {
 852         u32 bmcr;
 853         u32 new_bmcr;
 854
 855         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 856
 857         if (bp->autoneg & AUTONEG_SPEED) {
 858                 u32 adv_reg, adv1000_reg;
 859                 u32 new_adv_reg = 0;
 860                 u32 new_adv1000_reg = 0;
 861
 862                 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
 863                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
 864                         ADVERTISE_PAUSE_ASYM);
 865
 866                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
 867                 adv1000_reg &= PHY_ALL_1000_SPEED;
 868
 869                 if (bp->advertising & ADVERTISED_10baseT_Half)
 870                         new_adv_reg |= ADVERTISE_10HALF;
 871                 if (bp->advertising & ADVERTISED_10baseT_Full)
 872                         new_adv_reg |= ADVERTISE_10FULL;
 873                 if (bp->advertising & ADVERTISED_100baseT_Half)
 874                         new_adv_reg |= ADVERTISE_100HALF;
 875                 if (bp->advertising & ADVERTISED_100baseT_Full)
 876                         new_adv_reg |= ADVERTISE_100FULL;
 877                 if (bp->advertising & ADVERTISED_1000baseT_Full)
 878                         new_adv1000_reg |= ADVERTISE_1000FULL;
 879
 880                 new_adv_reg |= ADVERTISE_CSMA;
 881
 882                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
 883
 884                 if ((adv1000_reg != new_adv1000_reg) ||
 885                         (adv_reg != new_adv_reg) ||
 886                         ((bmcr & BMCR_ANENABLE) == 0)) {
 887
 888                         bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
 889                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
 890                         bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
 891                                 BMCR_ANENABLE);
 892                 }
 893                 else if (bp->link_up) {
 894                         /* Flow ctrl may have changed from auto to forced */
 895                         /* or vice-versa. */
 896
 897                         bnx2_resolve_flow_ctrl(bp);
 898                         bnx2_set_mac_link(bp);
 899                 }
 900                 return 0;
 901         }
 902
 903         new_bmcr = 0;
 904         if (bp->req_line_speed == SPEED_100) {
 905                 new_bmcr |= BMCR_SPEED100;
 906         }
 907         if (bp->req_duplex == DUPLEX_FULL) {
 908                 new_bmcr |= BMCR_FULLDPLX;
 909         }
 910         if (new_bmcr != bmcr) {
 911                 u32 bmsr;
 912                 int i = 0;
 913
 914                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
 915                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
 916
 917                 if (bmsr & BMSR_LSTATUS) {
 918                         /* Force link down */
 919                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
 920                         do {
 921                                 udelay(100);
 922                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
 923                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
 924                                 i++;
 925                         } while ((bmsr & BMSR_LSTATUS) && (i < 620));
 926                 }
 927
 928                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
 929
 930                 /* Normally, the new speed is setup after the link has
 931                  * gone down and up again. In some cases, link will not go
 932                  * down so we need to set up the new speed here.
 933                  */
 934                 if (bmsr & BMSR_LSTATUS) {
 935                         bp->line_speed = bp->req_line_speed;
 936                         bp->duplex = bp->req_duplex;
 937                         bnx2_resolve_flow_ctrl(bp);
 938                         bnx2_set_mac_link(bp);
 939                 }
 940         }
 941         return 0;
 942 }
 943
 944 static int
 945 bnx2_setup_phy(struct bnx2 *bp)
 946 {
 947         if (bp->loopback == MAC_LOOPBACK)
 948                 return 0;
 949
 950         if (bp->phy_flags & PHY_SERDES_FLAG) {
 951                 return (bnx2_setup_serdes_phy(bp));
 952         }
 953         else {
 954                 return (bnx2_setup_copper_phy(bp));
 955         }
 956 }
 957
 958 static int
 959 bnx2_init_serdes_phy(struct bnx2 *bp)
 960 {
 961         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
 962
 963         if (CHIP_NUM(bp) == CHIP_NUM_5706) {
 964                 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
 965         }
 966
 967         if (bp->dev->mtu > 1500) {
 968                 u32 val;
 969
 970                 /* Set extended packet length bit */
 971                 bnx2_write_phy(bp, 0x18, 0x7);
 972                 bnx2_read_phy(bp, 0x18, &val);
 973                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
 974
 975                 bnx2_write_phy(bp, 0x1c, 0x6c00);
 976                 bnx2_read_phy(bp, 0x1c, &val);
 977                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
 978         }
 979         else {
 980                 u32 val;
 981
 982                 bnx2_write_phy(bp, 0x18, 0x7);
 983                 bnx2_read_phy(bp, 0x18, &val);
 984                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
 985
 986                 bnx2_write_phy(bp, 0x1c, 0x6c00);
 987                 bnx2_read_phy(bp, 0x1c, &val);
 988                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
 989         }
 990
 991         return 0;
 992 }
 993
 994 static int
 995 bnx2_init_copper_phy(struct bnx2 *bp)
 996 {
 997         bp->phy_flags |= PHY_CRC_FIX_FLAG;
 998
 999         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1000                 bnx2_write_phy(bp, 0x18, 0x0c00);
1001                 bnx2_write_phy(bp, 0x17, 0x000a);
1002                 bnx2_write_phy(bp, 0x15, 0x310b);
1003                 bnx2_write_phy(bp, 0x17, 0x201f);
1004                 bnx2_write_phy(bp, 0x15, 0x9506);
1005                 bnx2_write_phy(bp, 0x17, 0x401f);
1006                 bnx2_write_phy(bp, 0x15, 0x14e2);
1007                 bnx2_write_phy(bp, 0x18, 0x0400);
1008         }
1009
1010         if (bp->dev->mtu > 1500) {
1011                 u32 val;
1012
1013                 /* Set extended packet length bit */
1014                 bnx2_write_phy(bp, 0x18, 0x7);
1015                 bnx2_read_phy(bp, 0x18, &val);
1016                 bnx2_write_phy(bp, 0x18, val | 0x4000);
1017
1018                 bnx2_read_phy(bp, 0x10, &val);
1019                 bnx2_write_phy(bp, 0x10, val | 0x1);
1020         }
1021         else {
1022                 u32 val;
1023
1024                 bnx2_write_phy(bp, 0x18, 0x7);
1025                 bnx2_read_phy(bp, 0x18, &val);
1026                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1027
1028                 bnx2_read_phy(bp, 0x10, &val);
1029                 bnx2_write_phy(bp, 0x10, val & ~0x1);
1030         }
1031
1032         return 0;
1033 }
1034
1035
1036 static int
1037 bnx2_init_phy(struct bnx2 *bp)
1038 {
1039         u32 val;
1040         int rc = 0;
1041
1042         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1043         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1044
1045         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1046
1047         bnx2_reset_phy(bp);
1048
1049         bnx2_read_phy(bp, MII_PHYSID1, &val);
1050         bp->phy_id = val << 16;
1051         bnx2_read_phy(bp, MII_PHYSID2, &val);
1052         bp->phy_id |= val & 0xffff;
1053
1054         if (bp->phy_flags & PHY_SERDES_FLAG) {
1055                 rc = bnx2_init_serdes_phy(bp);
1056         }
1057         else {
1058                 rc = bnx2_init_copper_phy(bp);
1059         }
1060
1061         bnx2_setup_phy(bp);
1062
1063         return rc;
1064 }
1065
1066 static int
1067 bnx2_set_mac_loopback(struct bnx2 *bp)
1068 {
1069         u32 mac_mode;
1070
1071         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1072         mac_mode &= ~BNX2_EMAC_MODE_PORT;
1073         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1074         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1075         bp->link_up = 1;
1076         return 0;
1077 }
1078
1079 static int
1080 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
1081 {
1082         int i;
1083         u32 val;
1084
1085         if (bp->fw_timed_out)
1086                 return -EBUSY;
1087
1088         bp->fw_wr_seq++;
1089         msg_data |= bp->fw_wr_seq;
1090
1091         REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1092
1093         /* wait for an acknowledgement. */
1094         for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
1095                 udelay(5);
1096
1097                 val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);
1098
1099                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1100                         break;
1101         }
1102
1103         /* If we timed out, inform the firmware that this is the case. */
1104         if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
1105                 ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
1106
1107                 msg_data &= ~BNX2_DRV_MSG_CODE;
1108                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1109
1110                 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1111
1112                 bp->fw_timed_out = 1;
1113
1114                 return -EBUSY;
1115         }
1116
1117         return 0;
1118 }
1119
1120 static void
1121 bnx2_init_context(struct bnx2 *bp)
1122 {
1123         u32 vcid;
1124
1125         vcid = 96;
1126         while (vcid) {
1127                 u32 vcid_addr, pcid_addr, offset;
1128
1129                 vcid--;
1130
1131                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1132                         u32 new_vcid;
1133
1134                         vcid_addr = GET_PCID_ADDR(vcid);
1135                         if (vcid & 0x8) {
1136                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1137                         }
1138                         else {
1139                                 new_vcid = vcid;
1140                         }
1141                         pcid_addr = GET_PCID_ADDR(new_vcid);
1142                 }
1143                 else {
1144                         vcid_addr = GET_CID_ADDR(vcid);
1145                         pcid_addr = vcid_addr;
1146                 }
1147
1148                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1149                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1150
1151                 /* Zero out the context. */
1152                 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1153                         CTX_WR(bp, 0x00, offset, 0);
1154                 }
1155
1156                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1157                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1158         }
1159 }
1160
1161 static int
1162 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1163 {
1164         u16 *good_mbuf;
1165         u32 good_mbuf_cnt;
1166         u32 val;
1167
1168         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1169         if (good_mbuf == NULL) {
1170                 printk(KERN_ERR PFX "Failed to allocate memory in "
1171                                     "bnx2_alloc_bad_rbuf\n");
1172                 return -ENOMEM;
1173         }
1174
1175         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1176                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1177
1178         good_mbuf_cnt = 0;
1179
1180         /* Allocate a bunch of mbufs and save the good ones in an array. */
1181         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1182         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1183                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1184
1185                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1186
1187                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1188
1189                 /* The addresses with Bit 9 set are bad memory blocks. */
1190                 if (!(val & (1 << 9))) {
1191                         good_mbuf[good_mbuf_cnt] = (u16) val;
1192                         good_mbuf_cnt++;
1193                 }
1194
1195                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1196         }
1197
1198         /* Free the good ones back to the mbuf pool thus discarding
1199          * all the bad ones. */
1200         while (good_mbuf_cnt) {
1201                 good_mbuf_cnt--;
1202
1203                 val = good_mbuf[good_mbuf_cnt];
1204                 val = (val << 9) | val | 1;
1205
1206                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1207         }
1208         kfree(good_mbuf);
1209         return 0;
1210 }
1211
1212 static void
1213 bnx2_set_mac_addr(struct bnx2 *bp)
1214 {
1215         u32 val;
1216         u8 *mac_addr = bp->dev->dev_addr;
1217
1218         val = (mac_addr[0] << 8) | mac_addr[1];
1219
1220         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1221
1222         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1223                 (mac_addr[4] << 8) | mac_addr[5];
1224
1225         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1226 }
1227
1228 static inline int
1229 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1230 {
1231         struct sk_buff *skb;
1232         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1233         dma_addr_t mapping;
1234         struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1235         unsigned long align;
1236
1237         skb = dev_alloc_skb(bp->rx_buf_size);
1238         if (skb == NULL) {
1239                 return -ENOMEM;
1240         }
1241
1242         if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1243                 skb_reserve(skb, 8 - align);
1244         }
1245
1246         skb->dev = bp->dev;
1247         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1248                 PCI_DMA_FROMDEVICE);
1249
1250         rx_buf->skb = skb;
1251         pci_unmap_addr_set(rx_buf, mapping, mapping);
1252
1253         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1254         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1255
1256         bp->rx_prod_bseq += bp->rx_buf_use_size;
1257
1258         return 0;
1259 }
1260
1261 static void
1262 bnx2_phy_int(struct bnx2 *bp)
1263 {
1264         u32 new_link_state, old_link_state;
1265
1266         new_link_state = bp->status_blk->status_attn_bits &
1267                 STATUS_ATTN_BITS_LINK_STATE;
1268         old_link_state = bp->status_blk->status_attn_bits_ack &
1269                 STATUS_ATTN_BITS_LINK_STATE;
1270         if (new_link_state != old_link_state) {
1271                 if (new_link_state) {
1272                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1273                                 STATUS_ATTN_BITS_LINK_STATE);
1274                 }
1275                 else {
1276                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1277                                 STATUS_ATTN_BITS_LINK_STATE);
1278                 }
1279                 bnx2_set_link(bp);
1280         }
1281 }
1282
1283 static void
1284 bnx2_tx_int(struct bnx2 *bp)
1285 {
1286         u16 hw_cons, sw_cons, sw_ring_cons;
1287         int tx_free_bd = 0;
1288
1289         hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1290         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1291                 hw_cons++;
1292         }
1293         sw_cons = bp->tx_cons;
1294
1295         while (sw_cons != hw_cons) {
1296                 struct sw_bd *tx_buf;
1297                 struct sk_buff *skb;
1298                 int i, last;
1299
1300                 sw_ring_cons = TX_RING_IDX(sw_cons);
1301
1302                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1303                 skb = tx_buf->skb;
1304 #ifdef BCM_TSO
1305                 /* partial BD completions possible with TSO packets */
1306                 if (skb_shinfo(skb)->tso_size) {
1307                         u16 last_idx, last_ring_idx;
1308
1309                         last_idx = sw_cons +
1310                                 skb_shinfo(skb)->nr_frags + 1;
1311                         last_ring_idx = sw_ring_cons +
1312                                 skb_shinfo(skb)->nr_frags + 1;
1313                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1314                                 last_idx++;
1315                         }
1316                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1317                                 break;
1318                         }
1319                 }
1320 #endif
1321                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1322                         skb_headlen(skb), PCI_DMA_TODEVICE);
1323
1324                 tx_buf->skb = NULL;
1325                 last = skb_shinfo(skb)->nr_frags;
1326
1327                 for (i = 0; i < last; i++) {
1328                         sw_cons = NEXT_TX_BD(sw_cons);
1329
1330                         pci_unmap_page(bp->pdev,
1331                                 pci_unmap_addr(
1332                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1333                                         mapping),
1334                                 skb_shinfo(skb)->frags[i].size,
1335                                 PCI_DMA_TODEVICE);
1336                 }
1337
1338                 sw_cons = NEXT_TX_BD(sw_cons);
1339
1340                 tx_free_bd += last + 1;
1341
1342                 dev_kfree_skb_irq(skb);
1343
1344                 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1345                 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1346                         hw_cons++;
1347                 }
1348         }
1349
1350         bp->tx_cons = sw_cons;
1351
1352         if (unlikely(netif_queue_stopped(bp->dev))) {
1353                 spin_lock(&bp->tx_lock);
1354                 if ((netif_queue_stopped(bp->dev)) &&
1355                     (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
1356
1357                         netif_wake_queue(bp->dev);
1358                 }
1359                 spin_unlock(&bp->tx_lock);
1360         }
1361 }
1362
1363 static inline void
1364 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1365         u16 cons, u16 prod)
1366 {
1367         struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1368         struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1369         struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1370         struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1371
1372         pci_dma_sync_single_for_device(bp->pdev,
1373                 pci_unmap_addr(cons_rx_buf, mapping),
1374                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1375
1376         prod_rx_buf->skb = cons_rx_buf->skb;
1377         pci_unmap_addr_set(prod_rx_buf, mapping,
1378                         pci_unmap_addr(cons_rx_buf, mapping));
1379
1380         memcpy(prod_bd, cons_bd, 8);
1381
1382         bp->rx_prod_bseq += bp->rx_buf_use_size;
1383
1384 }
1385
1386 static int
1387 bnx2_rx_int(struct bnx2 *bp, int budget)
1388 {
1389         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1390         struct l2_fhdr *rx_hdr;
1391         int rx_pkt = 0;
1392
1393         hw_cons = bp->status_blk->status_rx_quick_consumer_index0;
1394         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1395                 hw_cons++;
1396         }
1397         sw_cons = bp->rx_cons;
1398         sw_prod = bp->rx_prod;
1399
1400         /* Memory barrier necessary as speculative reads of the rx
1401          * buffer can be ahead of the index in the status block
1402          */
1403         rmb();
1404         while (sw_cons != hw_cons) {
1405                 unsigned int len;
1406                 u16 status;
1407                 struct sw_bd *rx_buf;
1408                 struct sk_buff *skb;
1409
1410                 sw_ring_cons = RX_RING_IDX(sw_cons);
1411                 sw_ring_prod = RX_RING_IDX(sw_prod);
1412
1413                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1414                 skb = rx_buf->skb;
1415                 pci_dma_sync_single_for_cpu(bp->pdev,
1416                         pci_unmap_addr(rx_buf, mapping),
1417                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1418
1419                 rx_hdr = (struct l2_fhdr *) skb->data;
1420                 len = rx_hdr->l2_fhdr_pkt_len - 4;
1421
1422                 if (rx_hdr->l2_fhdr_errors &
1423                         (L2_FHDR_ERRORS_BAD_CRC |
1424                         L2_FHDR_ERRORS_PHY_DECODE |
1425                         L2_FHDR_ERRORS_ALIGNMENT |
1426                         L2_FHDR_ERRORS_TOO_SHORT |
1427                         L2_FHDR_ERRORS_GIANT_FRAME)) {
1428
1429                         goto reuse_rx;
1430                 }
1431
1432                 /* Since we don't have a jumbo ring, copy small packets
1433                  * if mtu > 1500
1434                  */
1435                 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1436                         struct sk_buff *new_skb;
1437
1438                         new_skb = dev_alloc_skb(len + 2);
1439                         if (new_skb == NULL)
1440                                 goto reuse_rx;
1441
1442                         /* aligned copy */
1443                         memcpy(new_skb->data,
1444                                 skb->data + bp->rx_offset - 2,
1445                                 len + 2);
1446
1447                         skb_reserve(new_skb, 2);
1448                         skb_put(new_skb, len);
1449                         new_skb->dev = bp->dev;
1450
1451                         bnx2_reuse_rx_skb(bp, skb,
1452                                 sw_ring_cons, sw_ring_prod);
1453
1454                         skb = new_skb;
1455                 }
1456                 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1457                         pci_unmap_single(bp->pdev,
1458                                 pci_unmap_addr(rx_buf, mapping),
1459                                 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1460
1461                         skb_reserve(skb, bp->rx_offset);
1462                         skb_put(skb, len);
1463                 }
1464                 else {
1465 reuse_rx:
1466                         bnx2_reuse_rx_skb(bp, skb,
1467                                 sw_ring_cons, sw_ring_prod);
1468                         goto next_rx;
1469                 }
1470
1471                 skb->protocol = eth_type_trans(skb, bp->dev);
1472
1473                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1474                         (htons(skb->protocol) != 0x8100)) {
1475
1476                         dev_kfree_skb_irq(skb);
1477                         goto next_rx;
1478
1479                 }
1480
1481                 status = rx_hdr->l2_fhdr_status;
1482                 skb->ip_summed = CHECKSUM_NONE;
1483                 if (bp->rx_csum &&
1484                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1485                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
1486
1487                         u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
1488
1489                         if (cksum == 0xffff)
1490                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1491                 }
1492
1493 #ifdef BCM_VLAN
1494                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1495                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1496                                 rx_hdr->l2_fhdr_vlan_tag);
1497                 }
1498                 else
1499 #endif
1500                         netif_receive_skb(skb);
1501
1502                 bp->dev->last_rx = jiffies;
1503                 rx_pkt++;
1504
1505 next_rx:
1506                 rx_buf->skb = NULL;
1507
1508                 sw_cons = NEXT_RX_BD(sw_cons);
1509                 sw_prod = NEXT_RX_BD(sw_prod);
1510
1511                 if ((rx_pkt == budget))
1512                         break;
1513         }
1514         bp->rx_cons = sw_cons;
1515         bp->rx_prod = sw_prod;
1516
1517         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1518
1519         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1520
1521         mmiowb();
1522
1523         return rx_pkt;
1524
1525 }
1526
1527 /* MSI ISR - The only difference between this and the INTx ISR
1528  * is that the MSI interrupt is always serviced.
1529  */
1530 static irqreturn_t
1531 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1532 {
1533         struct net_device *dev = dev_instance;
1534         struct bnx2 *bp = dev->priv;
1535
1536         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1537                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1538                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1539
1540         /* Return here if interrupt is disabled. */
1541         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1542                 return IRQ_HANDLED;
1543
1544         netif_rx_schedule(dev);
1545
1546         return IRQ_HANDLED;
1547 }
1548
1549 static irqreturn_t
1550 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1551 {
1552         struct net_device *dev = dev_instance;
1553         struct bnx2 *bp = dev->priv;
1554
1555         /* When using INTx, it is possible for the interrupt to arrive
1556          * at the CPU before the status block posted prior to the
1557          * interrupt. Reading a register will flush the status block.
1558          * When using MSI, the MSI message will always complete after
1559          * the status block write.
1560          */
1561         if ((bp->status_blk->status_idx == bp->last_status_idx) ||
1562             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1563              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1564                 return IRQ_NONE;
1565
1566         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1567                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1568                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1569
1570         /* Return here if interrupt is shared and is disabled. */
1571         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1572                 return IRQ_HANDLED;
1573
1574         netif_rx_schedule(dev);
1575
1576         return IRQ_HANDLED;
1577 }
1578
1579 static int
1580 bnx2_poll(struct net_device *dev, int *budget)
1581 {
1582         struct bnx2 *bp = dev->priv;
1583         int rx_done = 1;
1584
1585         bp->last_status_idx = bp->status_blk->status_idx;
1586
1587         rmb();
1588         if ((bp->status_blk->status_attn_bits &
1589                 STATUS_ATTN_BITS_LINK_STATE) !=
1590                 (bp->status_blk->status_attn_bits_ack &
1591                 STATUS_ATTN_BITS_LINK_STATE)) {
1592
1593                 spin_lock(&bp->phy_lock);
1594                 bnx2_phy_int(bp);
1595                 spin_unlock(&bp->phy_lock);
1596         }
1597
1598         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) {
1599                 bnx2_tx_int(bp);
1600         }
1601
1602         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
1603                 int orig_budget = *budget;
1604                 int work_done;
1605
1606                 if (orig_budget > dev->quota)
1607                         orig_budget = dev->quota;
1608
1609                 work_done = bnx2_rx_int(bp, orig_budget);
1610                 *budget -= work_done;
1611                 dev->quota -= work_done;
1612
1613                 if (work_done >= orig_budget) {
1614                         rx_done = 0;
1615                 }
1616         }
1617
1618         if (rx_done) {
1619                 netif_rx_complete(dev);
1620                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1621                         BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1622                         bp->last_status_idx);
1623                 return 0;
1624         }
1625
1626         return 1;
1627 }
1628
1629 /* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1630  * from set_multicast.
1631  */
1632 static void
1633 bnx2_set_rx_mode(struct net_device *dev)
1634 {
1635         struct bnx2 *bp = dev->priv;
1636         u32 rx_mode, sort_mode;
1637         int i;
1638
1639         spin_lock_bh(&bp->phy_lock);
1640
1641         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1642                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1643         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1644 #ifdef BCM_VLAN
1645         if (!bp->vlgrp) {
1646                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1647         }
1648 #else
1649         rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1650 #endif
1651         if (dev->flags & IFF_PROMISC) {
1652                 /* Promiscuous mode. */
1653                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1654                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1655         }
1656         else if (dev->flags & IFF_ALLMULTI) {
1657                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1658                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1659                                0xffffffff);
1660                 }
1661                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1662         }
1663         else {
1664                 /* Accept one or more multicast(s). */
1665                 struct dev_mc_list *mclist;
1666                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1667                 u32 regidx;
1668                 u32 bit;
1669                 u32 crc;
1670
1671                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1672
1673                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1674                      i++, mclist = mclist->next) {
1675
1676                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1677                         bit = crc & 0xff;
1678                         regidx = (bit & 0xe0) >> 5;
1679                         bit &= 0x1f;
1680                         mc_filter[regidx] |= (1 << bit);
1681                 }
1682
1683                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1684                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1685                                mc_filter[i]);
1686                 }
1687
1688                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1689         }
1690
1691         if (rx_mode != bp->rx_mode) {
1692                 bp->rx_mode = rx_mode;
1693                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1694         }
1695
1696         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1697         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1698         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1699
1700         spin_unlock_bh(&bp->phy_lock);
1701 }
1702
1703 static void
1704 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1705         u32 rv2p_proc)
1706 {
1707         int i;
1708         u32 val;
1709
1710
1711         for (i = 0; i < rv2p_code_len; i += 8) {
1712                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1713                 rv2p_code++;
1714                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1715                 rv2p_code++;
1716
1717                 if (rv2p_proc == RV2P_PROC1) {
1718                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1719                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1720                 }
1721                 else {
1722                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1723                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1724                 }
1725         }
1726
1727         /* Reset the processor, un-stall is done later. */
1728         if (rv2p_proc == RV2P_PROC1) {
1729                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1730         }
1731         else {
1732                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1733         }
1734 }
1735
1736 static void
1737 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1738 {
1739         u32 offset;
1740         u32 val;
1741
1742         /* Halt the CPU. */
1743         val = REG_RD_IND(bp, cpu_reg->mode);
1744         val |= cpu_reg->mode_value_halt;
1745         REG_WR_IND(bp, cpu_reg->mode, val);
1746         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1747
1748         /* Load the Text area. */
1749         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1750         if (fw->text) {
1751                 int j;
1752
1753                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1754                         REG_WR_IND(bp, offset, fw->text[j]);
1755                 }
1756         }
1757
1758         /* Load the Data area. */
1759         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1760         if (fw->data) {
1761                 int j;
1762
1763                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1764                         REG_WR_IND(bp, offset, fw->data[j]);
1765                 }
1766         }
1767
1768         /* Load the SBSS area. */
1769         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1770         if (fw->sbss) {
1771                 int j;
1772
1773                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1774                         REG_WR_IND(bp, offset, fw->sbss[j]);
1775                 }
1776         }
1777
1778         /* Load the BSS area. */
1779         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1780         if (fw->bss) {
1781                 int j;
1782
1783                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1784                         REG_WR_IND(bp, offset, fw->bss[j]);
1785                 }
1786         }
1787
1788         /* Load the Read-Only area. */
1789         offset = cpu_reg->spad_base +
1790                 (fw->rodata_addr - cpu_reg->mips_view_base);
1791         if (fw->rodata) {
1792                 int j;
1793
1794                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1795                         REG_WR_IND(bp, offset, fw->rodata[j]);
1796                 }
1797         }
1798
1799         /* Clear the pre-fetch instruction. */
1800         REG_WR_IND(bp, cpu_reg->inst, 0);
1801         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1802
1803         /* Start the CPU. */
1804         val = REG_RD_IND(bp, cpu_reg->mode);
1805         val &= ~cpu_reg->mode_value_halt;
1806         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1807         REG_WR_IND(bp, cpu_reg->mode, val);
1808 }
1809
1810 static void
1811 bnx2_init_cpus(struct bnx2 *bp)
1812 {
1813         struct cpu_reg cpu_reg;
1814         struct fw_info fw;
1815
1816         /* Initialize the RV2P processor. */
1817         load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1818         load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1819
1820         /* Initialize the RX Processor. */
1821         cpu_reg.mode = BNX2_RXP_CPU_MODE;
1822         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
1823         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
1824         cpu_reg.state = BNX2_RXP_CPU_STATE;
1825         cpu_reg.state_value_clear = 0xffffff;
1826         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
1827         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
1828         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
1829         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
1830         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1831         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
1832         cpu_reg.mips_view_base = 0x8000000;
1833
1834         fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
1835         fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
1836         fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
1837         fw.start_addr = bnx2_RXP_b06FwStartAddr;
1838
1839         fw.text_addr = bnx2_RXP_b06FwTextAddr;
1840         fw.text_len = bnx2_RXP_b06FwTextLen;
1841         fw.text_index = 0;
1842         fw.text = bnx2_RXP_b06FwText;
1843
1844         fw.data_addr = bnx2_RXP_b06FwDataAddr;
1845         fw.data_len = bnx2_RXP_b06FwDataLen;
1846         fw.data_index = 0;
1847         fw.data = bnx2_RXP_b06FwData;
1848
1849         fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
1850         fw.sbss_len = bnx2_RXP_b06FwSbssLen;
1851         fw.sbss_index = 0;
1852         fw.sbss = bnx2_RXP_b06FwSbss;
1853
1854         fw.bss_addr = bnx2_RXP_b06FwBssAddr;
1855         fw.bss_len = bnx2_RXP_b06FwBssLen;
1856         fw.bss_index = 0;
1857         fw.bss = bnx2_RXP_b06FwBss;
1858
1859         fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
1860         fw.rodata_len = bnx2_RXP_b06FwRodataLen;
1861         fw.rodata_index = 0;
1862         fw.rodata = bnx2_RXP_b06FwRodata;
1863
1864         load_cpu_fw(bp, &cpu_reg, &fw);
1865
1866         /* Initialize the TX Processor. */
1867         cpu_reg.mode = BNX2_TXP_CPU_MODE;
1868         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
1869         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
1870         cpu_reg.state = BNX2_TXP_CPU_STATE;
1871         cpu_reg.state_value_clear = 0xffffff;
1872         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
1873         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
1874         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
1875         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
1876         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
1877         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
1878         cpu_reg.mips_view_base = 0x8000000;
1879
1880         fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
1881         fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
1882         fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
1883         fw.start_addr = bnx2_TXP_b06FwStartAddr;
1884
1885         fw.text_addr = bnx2_TXP_b06FwTextAddr;
1886         fw.text_len = bnx2_TXP_b06FwTextLen;
1887         fw.text_index = 0;
1888         fw.text = bnx2_TXP_b06FwText;
1889
1890         fw.data_addr = bnx2_TXP_b06FwDataAddr;
1891         fw.data_len = bnx2_TXP_b06FwDataLen;
1892         fw.data_index = 0;
1893         fw.data = bnx2_TXP_b06FwData;
1894
1895         fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
1896         fw.sbss_len = bnx2_TXP_b06FwSbssLen;
1897         fw.sbss_index = 0;
1898         fw.sbss = bnx2_TXP_b06FwSbss;
1899
1900         fw.bss_addr = bnx2_TXP_b06FwBssAddr;
1901         fw.bss_len = bnx2_TXP_b06FwBssLen;
1902         fw.bss_index = 0;
1903         fw.bss = bnx2_TXP_b06FwBss;
1904
1905         fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
1906         fw.rodata_len = bnx2_TXP_b06FwRodataLen;
1907         fw.rodata_index = 0;
1908         fw.rodata = bnx2_TXP_b06FwRodata;
1909
1910         load_cpu_fw(bp, &cpu_reg, &fw);
1911
1912         /* Initialize the TX Patch-up Processor. */
1913         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
1914         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
1915         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
1916         cpu_reg.state = BNX2_TPAT_CPU_STATE;
1917         cpu_reg.state_value_clear = 0xffffff;
1918         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
1919         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
1920         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
1921         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
1922         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
1923         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
1924         cpu_reg.mips_view_base = 0x8000000;
1925
1926         fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
1927         fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
1928         fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
1929         fw.start_addr = bnx2_TPAT_b06FwStartAddr;
1930
1931         fw.text_addr = bnx2_TPAT_b06FwTextAddr;
1932         fw.text_len = bnx2_TPAT_b06FwTextLen;
1933         fw.text_index = 0;
1934         fw.text = bnx2_TPAT_b06FwText;
1935
1936         fw.data_addr = bnx2_TPAT_b06FwDataAddr;
1937         fw.data_len = bnx2_TPAT_b06FwDataLen;
1938         fw.data_index = 0;
1939         fw.data = bnx2_TPAT_b06FwData;
1940
1941         fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
1942         fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
1943         fw.sbss_index = 0;
1944         fw.sbss = bnx2_TPAT_b06FwSbss;
1945
1946         fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
1947         fw.bss_len = bnx2_TPAT_b06FwBssLen;
1948         fw.bss_index = 0;
1949         fw.bss = bnx2_TPAT_b06FwBss;
1950
1951         fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
1952         fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
1953         fw.rodata_index = 0;
1954         fw.rodata = bnx2_TPAT_b06FwRodata;
1955
1956         load_cpu_fw(bp, &cpu_reg, &fw);
1957
1958         /* Initialize the Completion Processor. */
1959         cpu_reg.mode = BNX2_COM_CPU_MODE;
1960         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
1961         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
1962         cpu_reg.state = BNX2_COM_CPU_STATE;
1963         cpu_reg.state_value_clear = 0xffffff;
1964         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
1965         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
1966         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
1967         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
1968         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
1969         cpu_reg.spad_base = BNX2_COM_SCRATCH;
1970         cpu_reg.mips_view_base = 0x8000000;
1971
1972         fw.ver_major = bnx2_COM_b06FwReleaseMajor;
1973         fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
1974         fw.ver_fix = bnx2_COM_b06FwReleaseFix;
1975         fw.start_addr = bnx2_COM_b06FwStartAddr;
1976
1977         fw.text_addr = bnx2_COM_b06FwTextAddr;
1978         fw.text_len = bnx2_COM_b06FwTextLen;
1979         fw.text_index = 0;
1980         fw.text = bnx2_COM_b06FwText;
1981
1982         fw.data_addr = bnx2_COM_b06FwDataAddr;
1983         fw.data_len = bnx2_COM_b06FwDataLen;
1984         fw.data_index = 0;
1985         fw.data = bnx2_COM_b06FwData;
1986
1987         fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
1988         fw.sbss_len = bnx2_COM_b06FwSbssLen;
1989         fw.sbss_index = 0;
1990         fw.sbss = bnx2_COM_b06FwSbss;
1991
1992         fw.bss_addr = bnx2_COM_b06FwBssAddr;
1993         fw.bss_len = bnx2_COM_b06FwBssLen;
1994         fw.bss_index = 0;
1995         fw.bss = bnx2_COM_b06FwBss;
1996
1997         fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
1998         fw.rodata_len = bnx2_COM_b06FwRodataLen;
1999         fw.rodata_index = 0;
2000         fw.rodata = bnx2_COM_b06FwRodata;
2001
2002         load_cpu_fw(bp, &cpu_reg, &fw);
2003
2004 }
2005
2006 static int
2007 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2008 {
2009         u16 pmcsr;
2010
2011         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2012
2013         switch (state) {
2014         case PCI_D0: {
2015                 u32 val;
2016
2017                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2018                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2019                         PCI_PM_CTRL_PME_STATUS);
2020
2021                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2022                         /* delay required during transition out of D3hot */
2023                         msleep(20);
2024
2025                 val = REG_RD(bp, BNX2_EMAC_MODE);
2026                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2027                 val &= ~BNX2_EMAC_MODE_MPKT;
2028                 REG_WR(bp, BNX2_EMAC_MODE, val);
2029
2030                 val = REG_RD(bp, BNX2_RPM_CONFIG);
2031                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2032                 REG_WR(bp, BNX2_RPM_CONFIG, val);
2033                 break;
2034         }
2035         case PCI_D3hot: {
2036                 int i;
2037                 u32 val, wol_msg;
2038
2039                 if (bp->wol) {
2040                         u32 advertising;
2041                         u8 autoneg;
2042
2043                         autoneg = bp->autoneg;
2044                         advertising = bp->advertising;
2045
2046                         bp->autoneg = AUTONEG_SPEED;
2047                         bp->advertising = ADVERTISED_10baseT_Half |
2048                                 ADVERTISED_10baseT_Full |
2049                                 ADVERTISED_100baseT_Half |
2050                                 ADVERTISED_100baseT_Full |
2051                                 ADVERTISED_Autoneg;
2052
2053                         bnx2_setup_copper_phy(bp);
2054
2055                         bp->autoneg = autoneg;
2056                         bp->advertising = advertising;
2057
2058                         bnx2_set_mac_addr(bp);
2059
2060                         val = REG_RD(bp, BNX2_EMAC_MODE);
2061
2062                         /* Enable port mode. */
2063                         val &= ~BNX2_EMAC_MODE_PORT;
2064                         val |= BNX2_EMAC_MODE_PORT_MII |
2065                                BNX2_EMAC_MODE_MPKT_RCVD |
2066                                BNX2_EMAC_MODE_ACPI_RCVD |
2067                                BNX2_EMAC_MODE_FORCE_LINK |
2068                                BNX2_EMAC_MODE_MPKT;
2069
2070                         REG_WR(bp, BNX2_EMAC_MODE, val);
2071
2072                         /* receive all multicast */
2073                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2074                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2075                                        0xffffffff);
2076                         }
2077                         REG_WR(bp, BNX2_EMAC_RX_MODE,
2078                                BNX2_EMAC_RX_MODE_SORT_MODE);
2079
2080                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2081                               BNX2_RPM_SORT_USER0_MC_EN;
2082                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2083                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2084                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2085                                BNX2_RPM_SORT_USER0_ENA);
2086
2087                         /* Need to enable EMAC and RPM for WOL. */
2088                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2089                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2090                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2091                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2092
2093                         val = REG_RD(bp, BNX2_RPM_CONFIG);
2094                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2095                         REG_WR(bp, BNX2_RPM_CONFIG, val);
2096
2097                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2098                 }
2099                 else {
2100                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2101                 }
2102
2103                 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
2104
2105                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2106                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2107                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2108
2109                         if (bp->wol)
2110                                 pmcsr |= 3;
2111                 }
2112                 else {
2113                         pmcsr |= 3;
2114                 }
2115                 if (bp->wol) {
2116                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2117                 }
2118                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2119                                       pmcsr);
2120
2121                 /* No more memory access after this point until
2122                  * device is brought back to D0.
2123                  */
2124                 udelay(50);
2125                 break;
2126         }
2127         default:
2128                 return -EINVAL;
2129         }
2130         return 0;
2131 }
2132
2133 static int
2134 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2135 {
2136         u32 val;
2137         int j;
2138
2139         /* Request access to the flash interface. */
2140         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2141         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2142                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2143                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2144                         break;
2145
2146                 udelay(5);
2147         }
2148
2149         if (j >= NVRAM_TIMEOUT_COUNT)
2150                 return -EBUSY;
2151
2152         return 0;
2153 }
2154
2155 static int
2156 bnx2_release_nvram_lock(struct bnx2 *bp)
2157 {
2158         int j;
2159         u32 val;
2160
2161         /* Relinquish nvram interface. */
2162         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2163
2164         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2165                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2166                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2167                         break;
2168
2169                 udelay(5);
2170         }
2171
2172         if (j >= NVRAM_TIMEOUT_COUNT)
2173                 return -EBUSY;
2174
2175         return 0;
2176 }
2177
2178
2179 static int
2180 bnx2_enable_nvram_write(struct bnx2 *bp)
2181 {
2182         u32 val;
2183
2184         val = REG_RD(bp, BNX2_MISC_CFG);
2185         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2186
2187         if (!bp->flash_info->buffered) {
2188                 int j;
2189
2190                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2191                 REG_WR(bp, BNX2_NVM_COMMAND,
2192                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2193
2194                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2195                         udelay(5);
2196
2197                         val = REG_RD(bp, BNX2_NVM_COMMAND);
2198                         if (val & BNX2_NVM_COMMAND_DONE)
2199                                 break;
2200                 }
2201
2202                 if (j >= NVRAM_TIMEOUT_COUNT)
2203                         return -EBUSY;
2204         }
2205         return 0;
2206 }
2207
2208 static void
2209 bnx2_disable_nvram_write(struct bnx2 *bp)
2210 {
2211         u32 val;
2212
2213         val = REG_RD(bp, BNX2_MISC_CFG);
2214         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2215 }
2216
2217
2218 static void
2219 bnx2_enable_nvram_access(struct bnx2 *bp)
2220 {
2221         u32 val;
2222
2223         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2224         /* Enable both bits, even on read. */
2225         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2226                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2227 }
2228
2229 static void
2230 bnx2_disable_nvram_access(struct bnx2 *bp)
2231 {
2232         u32 val;
2233
2234         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2235         /* Disable both bits, even after read. */
2236         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2237                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2238                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
2239 }
2240
2241 static int
2242 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2243 {
2244         u32 cmd;
2245         int j;
2246
2247         if (bp->flash_info->buffered)
2248                 /* Buffered flash, no erase needed */
2249                 return 0;
2250
2251         /* Build an erase command */
2252         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2253               BNX2_NVM_COMMAND_DOIT;
2254
2255         /* Need to clear DONE bit separately. */
2256         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2257
2258         /* Address of the NVRAM to read from. */
2259         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2260
2261         /* Issue an erase command. */
2262         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2263
2264         /* Wait for completion. */
2265         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2266                 u32 val;
2267
2268                 udelay(5);
2269
2270                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2271                 if (val & BNX2_NVM_COMMAND_DONE)
2272                         break;
2273         }
2274
2275         if (j >= NVRAM_TIMEOUT_COUNT)
2276                 return -EBUSY;
2277
2278         return 0;
2279 }
2280
2281 static int
2282 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2283 {
2284         u32 cmd;
2285         int j;
2286
2287         /* Build the command word. */
2288         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2289
2290         /* Calculate an offset of a buffered flash. */
2291         if (bp->flash_info->buffered) {
2292                 offset = ((offset / bp->flash_info->page_size) <<
2293                            bp->flash_info->page_bits) +
2294                           (offset % bp->flash_info->page_size);
2295         }
2296
2297         /* Need to clear DONE bit separately. */
2298         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2299
2300         /* Address of the NVRAM to read from. */
2301         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2302
2303         /* Issue a read command. */
2304         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2305
2306         /* Wait for completion. */
2307         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2308                 u32 val;
2309
2310                 udelay(5);
2311
2312                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2313                 if (val & BNX2_NVM_COMMAND_DONE) {
2314                         val = REG_RD(bp, BNX2_NVM_READ);
2315
2316                         val = be32_to_cpu(val);
2317                         memcpy(ret_val, &val, 4);
2318                         break;
2319                 }
2320         }
2321         if (j >= NVRAM_TIMEOUT_COUNT)
2322                 return -EBUSY;
2323
2324         return 0;
2325 }
2326
2327
2328 static int
2329 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2330 {
2331         u32 cmd, val32;
2332         int j;
2333
2334         /* Build the command word. */
2335         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2336
2337         /* Calculate an offset of a buffered flash. */
2338         if (bp->flash_info->buffered) {
2339                 offset = ((offset / bp->flash_info->page_size) <<
2340                           bp->flash_info->page_bits) +
2341                          (offset % bp->flash_info->page_size);
2342         }
2343
2344         /* Need to clear DONE bit separately. */
2345         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2346
2347         memcpy(&val32, val, 4);
2348         val32 = cpu_to_be32(val32);
2349
2350         /* Write the data. */
2351         REG_WR(bp, BNX2_NVM_WRITE, val32);
2352
2353         /* Address of the NVRAM to write to. */
2354         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2355
2356         /* Issue the write command. */
2357         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2358
2359         /* Wait for completion. */
2360         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2361                 udelay(5);
2362
2363                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2364                         break;
2365         }
2366         if (j >= NVRAM_TIMEOUT_COUNT)
2367                 return -EBUSY;
2368
2369         return 0;
2370 }
2371
2372 static int
2373 bnx2_init_nvram(struct bnx2 *bp)
2374 {
2375         u32 val;
2376         int j, entry_count, rc;
2377         struct flash_spec *flash;
2378
2379         /* Determine the selected interface. */
2380         val = REG_RD(bp, BNX2_NVM_CFG1);
2381
2382         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2383
2384         rc = 0;
2385         if (val & 0x40000000) {
2386
2387                 /* Flash interface has been reconfigured */
2388                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2389                         j++, flash++) {
2390
2391                         if (val == flash->config1) {
2392                                 bp->flash_info = flash;
2393                                 break;
2394                         }
2395                 }
2396         }
2397         else {
2398                 /* Not yet been reconfigured */
2399
2400                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2401                         j++, flash++) {
2402
2403                         if ((val & FLASH_STRAP_MASK) == flash->strapping) {
2404                                 bp->flash_info = flash;
2405
2406                                 /* Request access to the flash interface. */
2407                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2408                                         return rc;
2409
2410                                 /* Enable access to flash interface */
2411                                 bnx2_enable_nvram_access(bp);
2412
2413                                 /* Reconfigure the flash interface */
2414                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2415                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2416                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2417                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2418
2419                                 /* Disable access to flash interface */
2420                                 bnx2_disable_nvram_access(bp);
2421                                 bnx2_release_nvram_lock(bp);
2422
2423                                 break;
2424                         }
2425                 }
2426         } /* if (val & 0x40000000) */
2427
2428         if (j == entry_count) {
2429                 bp->flash_info = NULL;
2430                 printk(KERN_ALERT "Unknown flash/EEPROM type.\n");
2431                 rc = -ENODEV;
2432         }
2433
2434         return rc;
2435 }
2436
2437 static int
2438 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2439                 int buf_size)
2440 {
2441         int rc = 0;
2442         u32 cmd_flags, offset32, len32, extra;
2443
2444         if (buf_size == 0)
2445                 return 0;
2446
2447         /* Request access to the flash interface. */
2448         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2449                 return rc;
2450
2451         /* Enable access to flash interface */
2452         bnx2_enable_nvram_access(bp);
2453
2454         len32 = buf_size;
2455         offset32 = offset;
2456         extra = 0;
2457
2458         cmd_flags = 0;
2459
2460         if (offset32 & 3) {
2461                 u8 buf[4];
2462                 u32 pre_len;
2463
2464                 offset32 &= ~3;
2465                 pre_len = 4 - (offset & 3);
2466
2467                 if (pre_len >= len32) {
2468                         pre_len = len32;
2469                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2470                                     BNX2_NVM_COMMAND_LAST;
2471                 }
2472                 else {
2473                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2474                 }
2475
2476                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2477
2478                 if (rc)
2479                         return rc;
2480
2481                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2482
2483                 offset32 += 4;
2484                 ret_buf += pre_len;
2485                 len32 -= pre_len;
2486         }
2487         if (len32 & 3) {
2488                 extra = 4 - (len32 & 3);
2489                 len32 = (len32 + 4) & ~3;
2490         }
2491
2492         if (len32 == 4) {
2493                 u8 buf[4];
2494
2495                 if (cmd_flags)
2496                         cmd_flags = BNX2_NVM_COMMAND_LAST;
2497                 else
2498                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2499                                     BNX2_NVM_COMMAND_LAST;
2500
2501                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2502
2503                 memcpy(ret_buf, buf, 4 - extra);
2504         }
2505         else if (len32 > 0) {
2506                 u8 buf[4];
2507
2508                 /* Read the first word. */
2509                 if (cmd_flags)
2510                         cmd_flags = 0;
2511                 else
2512                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2513
2514                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2515
2516                 /* Advance to the next dword. */
2517                 offset32 += 4;
2518                 ret_buf += 4;
2519                 len32 -= 4;
2520
2521                 while (len32 > 4 && rc == 0) {
2522                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2523
2524                         /* Advance to the next dword. */
2525                         offset32 += 4;
2526                         ret_buf += 4;
2527                         len32 -= 4;
2528                 }
2529
2530                 if (rc)
2531                         return rc;
2532
2533                 cmd_flags = BNX2_NVM_COMMAND_LAST;
2534                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2535
2536                 memcpy(ret_buf, buf, 4 - extra);
2537         }
2538
2539         /* Disable access to flash interface */
2540         bnx2_disable_nvram_access(bp);
2541
2542         bnx2_release_nvram_lock(bp);
2543
2544         return rc;
2545 }
2546
2547 static int
2548 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2549                 int buf_size)
2550 {
2551         u32 written, offset32, len32;
2552         u8 *buf, start[4], end[4];
2553         int rc = 0;
2554         int align_start, align_end;
2555
2556         buf = data_buf;
2557         offset32 = offset;
2558         len32 = buf_size;
2559         align_start = align_end = 0;
2560
2561         if ((align_start = (offset32 & 3))) {
2562                 offset32 &= ~3;
2563                 len32 += align_start;
2564                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2565                         return rc;
2566         }
2567
2568         if (len32 & 3) {
2569                 if ((len32 > 4) || !align_start) {
2570                         align_end = 4 - (len32 & 3);
2571                         len32 += align_end;
2572                         if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2573                                 end, 4))) {
2574                                 return rc;
2575                         }
2576                 }
2577         }
2578
2579         if (align_start || align_end) {
2580                 buf = kmalloc(len32, GFP_KERNEL);
2581                 if (buf == 0)
2582                         return -ENOMEM;
2583                 if (align_start) {
2584                         memcpy(buf, start, 4);
2585                 }
2586                 if (align_end) {
2587                         memcpy(buf + len32 - 4, end, 4);
2588                 }
2589                 memcpy(buf + align_start, data_buf, buf_size);
2590         }
2591
2592         written = 0;
2593         while ((written < len32) && (rc == 0)) {
2594                 u32 page_start, page_end, data_start, data_end;
2595                 u32 addr, cmd_flags;
2596                 int i;
2597                 u8 flash_buffer[264];
2598
2599                 /* Find the page_start addr */
2600                 page_start = offset32 + written;
2601                 page_start -= (page_start % bp->flash_info->page_size);
2602                 /* Find the page_end addr */
2603                 page_end = page_start + bp->flash_info->page_size;
2604                 /* Find the data_start addr */
2605                 data_start = (written == 0) ? offset32 : page_start;
2606                 /* Find the data_end addr */
2607                 data_end = (page_end > offset32 + len32) ?
2608                         (offset32 + len32) : page_end;
2609
2610                 /* Request access to the flash interface. */
2611                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2612                         goto nvram_write_end;
2613
2614                 /* Enable access to flash interface */
2615                 bnx2_enable_nvram_access(bp);
2616
2617                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2618                 if (bp->flash_info->buffered == 0) {
2619                         int j;
2620
2621                         /* Read the whole page into the buffer
2622                          * (non-buffer flash only) */
2623                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
2624                                 if (j == (bp->flash_info->page_size - 4)) {
2625                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
2626                                 }
2627                                 rc = bnx2_nvram_read_dword(bp,
2628                                         page_start + j,
2629                                         &flash_buffer[j],
2630                                         cmd_flags);
2631
2632                                 if (rc)
2633                                         goto nvram_write_end;
2634
2635                                 cmd_flags = 0;
2636                         }
2637                 }
2638
2639                 /* Enable writes to flash interface (unlock write-protect) */
2640                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2641                         goto nvram_write_end;
2642
2643                 /* Erase the page */
2644                 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2645                         goto nvram_write_end;
2646
2647                 /* Re-enable the write again for the actual write */
2648                 bnx2_enable_nvram_write(bp);
2649
2650                 /* Loop to write back the buffer data from page_start to
2651                  * data_start */
2652                 i = 0;
2653                 if (bp->flash_info->buffered == 0) {
2654                         for (addr = page_start; addr < data_start;
2655                                 addr += 4, i += 4) {
2656
2657                                 rc = bnx2_nvram_write_dword(bp, addr,
2658                                         &flash_buffer[i], cmd_flags);
2659
2660                                 if (rc != 0)
2661                                         goto nvram_write_end;
2662
2663                                 cmd_flags = 0;
2664                         }
2665                 }
2666
2667                 /* Loop to write the new data from data_start to data_end */
2668                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2669                         if ((addr == page_end - 4) ||
2670                                 ((bp->flash_info->buffered) &&
2671                                  (addr == data_end - 4))) {
2672
2673                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2674                         }
2675                         rc = bnx2_nvram_write_dword(bp, addr, buf,
2676                                 cmd_flags);
2677
2678                         if (rc != 0)
2679                                 goto nvram_write_end;
2680
2681                         cmd_flags = 0;
2682                         buf += 4;
2683                 }
2684
2685                 /* Loop to write back the buffer data from data_end
2686                  * to page_end */
2687                 if (bp->flash_info->buffered == 0) {
2688                         for (addr = data_end; addr < page_end;
2689                                 addr += 4, i += 4) {
2690
2691                                 if (addr == page_end-4) {
2692                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
2693                                 }
2694                                 rc = bnx2_nvram_write_dword(bp, addr,
2695                                         &flash_buffer[i], cmd_flags);
2696
2697                                 if (rc != 0)
2698                                         goto nvram_write_end;
2699
2700                                 cmd_flags = 0;
2701                         }
2702                 }
2703
2704                 /* Disable writes to flash interface (lock write-protect) */
2705                 bnx2_disable_nvram_write(bp);
2706
2707                 /* Disable access to flash interface */
2708                 bnx2_disable_nvram_access(bp);
2709                 bnx2_release_nvram_lock(bp);
2710
2711                 /* Increment written */
2712                 written += data_end - data_start;
2713         }
2714
2715 nvram_write_end:
2716         if (align_start || align_end)
2717                 kfree(buf);
2718         return rc;
2719 }
2720
2721 static int
2722 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
2723 {
2724         u32 val;
2725         int i, rc = 0;
2726
2727         /* Wait for the current PCI transaction to complete before
2728          * issuing a reset. */
2729         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
2730                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2731                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2732                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2733                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2734         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
2735         udelay(5);
2736
2737         /* Deposit a driver reset signature so the firmware knows that
2738          * this is a soft reset. */
2739         REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
2740                    BNX2_DRV_RESET_SIGNATURE_MAGIC);
2741
2742         bp->fw_timed_out = 0;
2743
2744         /* Wait for the firmware to tell us it is ok to issue a reset. */
2745         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
2746
2747         /* Do a dummy read to force the chip to complete all current transaction
2748          * before we issue a reset. */
2749         val = REG_RD(bp, BNX2_MISC_ID);
2750
2751         val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2752               BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2753               BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2754
2755         /* Chip reset. */
2756         REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
2757
2758         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2759             (CHIP_ID(bp) == CHIP_ID_5706_A1))
2760                 msleep(15);
2761
2762         /* Reset takes approximate 30 usec */
2763         for (i = 0; i < 10; i++) {
2764                 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
2765                 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2766                             BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
2767                         break;
2768                 }
2769                 udelay(10);
2770         }
2771
2772         if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2773                    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2774                 printk(KERN_ERR PFX "Chip reset did not complete\n");
2775                 return -EBUSY;
2776         }
2777
2778         /* Make sure byte swapping is properly configured. */
2779         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
2780         if (val != 0x01020304) {
2781                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
2782                 return -ENODEV;
2783         }
2784
2785         bp->fw_timed_out = 0;
2786
2787         /* Wait for the firmware to finish its initialization. */
2788         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
2789
2790         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2791                 /* Adjust the voltage regular to two steps lower.  The default
2792                  * of this register is 0x0000000e. */
2793                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
2794
2795                 /* Remove bad rbuf memory from the free pool. */
2796                 rc = bnx2_alloc_bad_rbuf(bp);
2797         }
2798
2799         return rc;
2800 }
2801
2802 static int
2803 bnx2_init_chip(struct bnx2 *bp)
2804 {
2805         u32 val;
2806
2807         /* Make sure the interrupt is not active. */
2808         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2809
2810         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
2811               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
2812 #ifdef __BIG_ENDIAN
2813               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
2814 #endif
2815               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
2816               DMA_READ_CHANS << 12 |
2817               DMA_WRITE_CHANS << 16;
2818
2819         val |= (0x2 << 20) | (1 << 11);
2820
2821         if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
2822                 val |= (1 << 23);
2823
2824         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
2825             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
2826                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
2827
2828         REG_WR(bp, BNX2_DMA_CONFIG, val);
2829
2830         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2831                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
2832                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
2833                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
2834         }
2835
2836         if (bp->flags & PCIX_FLAG) {
2837                 u16 val16;
2838
2839                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2840                                      &val16);
2841                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2842                                       val16 & ~PCI_X_CMD_ERO);
2843         }
2844
2845         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2846                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
2847                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
2848                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
2849
2850         /* Initialize context mapping and zero out the quick contexts.  The
2851          * context block must have already been enabled. */
2852         bnx2_init_context(bp);
2853
2854         bnx2_init_cpus(bp);
2855         bnx2_init_nvram(bp);
2856
2857         bnx2_set_mac_addr(bp);
2858
2859         val = REG_RD(bp, BNX2_MQ_CONFIG);
2860         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
2861         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
2862         REG_WR(bp, BNX2_MQ_CONFIG, val);
2863
2864         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
2865         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
2866         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
2867
2868         val = (BCM_PAGE_BITS - 8) << 24;
2869         REG_WR(bp, BNX2_RV2P_CONFIG, val);
2870
2871         /* Configure page size. */
2872         val = REG_RD(bp, BNX2_TBDR_CONFIG);
2873         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
2874         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
2875         REG_WR(bp, BNX2_TBDR_CONFIG, val);
2876
2877         val = bp->mac_addr[0] +
2878               (bp->mac_addr[1] << 8) +
2879               (bp->mac_addr[2] << 16) +
2880               bp->mac_addr[3] +
2881               (bp->mac_addr[4] << 8) +
2882               (bp->mac_addr[5] << 16);
2883         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
2884
2885         /* Program the MTU.  Also include 4 bytes for CRC32. */
2886         val = bp->dev->mtu + ETH_HLEN + 4;
2887         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
2888                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
2889         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
2890
2891         bp->last_status_idx = 0;
2892         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
2893
2894         /* Set up how to generate a link change interrupt. */
2895         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2896
2897         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
2898                (u64) bp->status_blk_mapping & 0xffffffff);
2899         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
2900
2901         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
2902                (u64) bp->stats_blk_mapping & 0xffffffff);
2903         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
2904                (u64) bp->stats_blk_mapping >> 32);
2905
2906         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
2907                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
2908
2909         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
2910                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
2911
2912         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
2913                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
2914
2915         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
2916
2917         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
2918
2919         REG_WR(bp, BNX2_HC_COM_TICKS,
2920                (bp->com_ticks_int << 16) | bp->com_ticks);
2921
2922         REG_WR(bp, BNX2_HC_CMD_TICKS,
2923                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
2924
2925         REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
2926         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
2927
2928         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
2929                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
2930         else {
2931                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
2932                        BNX2_HC_CONFIG_TX_TMR_MODE |
2933                        BNX2_HC_CONFIG_COLLECT_STATS);
2934         }
2935
2936         /* Clear internal stats counters. */
2937         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
2938
2939         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
2940
2941         /* Initialize the receive filter. */
2942         bnx2_set_rx_mode(bp->dev);
2943
2944         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
2945
2946         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
2947         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
2948
2949         udelay(20);
2950
2951         return 0;
2952 }
2953
2954
2955 static void
2956 bnx2_init_tx_ring(struct bnx2 *bp)
2957 {
2958         struct tx_bd *txbd;
2959         u32 val;
2960
2961         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
2962
2963         txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
2964         txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
2965
2966         bp->tx_prod = 0;
2967         bp->tx_cons = 0;
2968         bp->tx_prod_bseq = 0;
2969
2970         val = BNX2_L2CTX_TYPE_TYPE_L2;
2971         val |= BNX2_L2CTX_TYPE_SIZE_L2;
2972         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
2973
2974         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
2975         val |= 8 << 16;
2976         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
2977
2978         val = (u64) bp->tx_desc_mapping >> 32;
2979         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
2980
2981         val = (u64) bp->tx_desc_mapping & 0xffffffff;
2982         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
2983 }
2984
2985 static void
2986 bnx2_init_rx_ring(struct bnx2 *bp)
2987 {
2988         struct rx_bd *rxbd;
2989         int i;
2990         u16 prod, ring_prod;
2991         u32 val;
2992
2993         /* 8 for CRC and VLAN */
2994         bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
2995         /* 8 for alignment */
2996         bp->rx_buf_size = bp->rx_buf_use_size + 8;
2997
2998         ring_prod = prod = bp->rx_prod = 0;
2999         bp->rx_cons = 0;
3000         bp->rx_prod_bseq = 0;
3001
3002         rxbd = &bp->rx_desc_ring[0];
3003         for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3004                 rxbd->rx_bd_len = bp->rx_buf_use_size;
3005                 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3006         }
3007
3008         rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3009         rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3010
3011         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3012         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3013         val |= 0x02 << 8;
3014         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3015
3016         val = (u64) bp->rx_desc_mapping >> 32;
3017         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3018
3019         val = (u64) bp->rx_desc_mapping & 0xffffffff;
3020         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3021
3022         for ( ;ring_prod < bp->rx_ring_size; ) {
3023                 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3024                         break;
3025                 }
3026                 prod = NEXT_RX_BD(prod);
3027                 ring_prod = RX_RING_IDX(prod);
3028         }
3029         bp->rx_prod = prod;
3030
3031         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3032
3033         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3034 }
3035
3036 static void
3037 bnx2_free_tx_skbs(struct bnx2 *bp)
3038 {
3039         int i;
3040
3041         if (bp->tx_buf_ring == NULL)
3042                 return;
3043
3044         for (i = 0; i < TX_DESC_CNT; ) {
3045                 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3046                 struct sk_buff *skb = tx_buf->skb;
3047                 int j, last;
3048
3049                 if (skb == NULL) {
3050                         i++;
3051                         continue;
3052                 }
3053
3054                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3055                         skb_headlen(skb), PCI_DMA_TODEVICE);
3056
3057                 tx_buf->skb = NULL;
3058
3059                 last = skb_shinfo(skb)->nr_frags;
3060                 for (j = 0; j < last; j++) {
3061                         tx_buf = &bp->tx_buf_ring[i + j + 1];
3062                         pci_unmap_page(bp->pdev,
3063                                 pci_unmap_addr(tx_buf, mapping),
3064                                 skb_shinfo(skb)->frags[j].size,
3065                                 PCI_DMA_TODEVICE);
3066                 }
3067                 dev_kfree_skb_any(skb);
3068                 i += j + 1;
3069         }
3070
3071 }
3072
3073 static void
3074 bnx2_free_rx_skbs(struct bnx2 *bp)
3075 {
3076         int i;
3077
3078         if (bp->rx_buf_ring == NULL)
3079                 return;
3080
3081         for (i = 0; i < RX_DESC_CNT; i++) {
3082                 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3083                 struct sk_buff *skb = rx_buf->skb;
3084
3085                 if (skb == 0)
3086                         continue;
3087
3088                 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3089                         bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3090
3091                 rx_buf->skb = NULL;
3092
3093                 dev_kfree_skb_any(skb);
3094         }
3095 }
3096
3097 static void
3098 bnx2_free_skbs(struct bnx2 *bp)
3099 {
3100         bnx2_free_tx_skbs(bp);
3101         bnx2_free_rx_skbs(bp);
3102 }
3103
3104 static int
3105 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3106 {
3107         int rc;
3108
3109         rc = bnx2_reset_chip(bp, reset_code);
3110         bnx2_free_skbs(bp);
3111         if (rc)
3112                 return rc;
3113
3114         bnx2_init_chip(bp);
3115         bnx2_init_tx_ring(bp);
3116         bnx2_init_rx_ring(bp);
3117         return 0;
3118 }
3119
3120 static int
3121 bnx2_init_nic(struct bnx2 *bp)
3122 {
3123         int rc;
3124
3125         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3126                 return rc;
3127
3128         bnx2_init_phy(bp);
3129         bnx2_set_link(bp);
3130         return 0;
3131 }
3132
3133 static int
3134 bnx2_test_registers(struct bnx2 *bp)
3135 {
3136         int ret;
3137         int i;
3138         static struct {
3139                 u16   offset;
3140                 u16   flags;
3141                 u32   rw_mask;
3142                 u32   ro_mask;
3143         } reg_tbl[] = {
3144                 { 0x006c, 0, 0x00000000, 0x0000003f },
3145                 { 0x0090, 0, 0xffffffff, 0x00000000 },
3146                 { 0x0094, 0, 0x00000000, 0x00000000 },
3147
3148                 { 0x0404, 0, 0x00003f00, 0x00000000 },
3149                 { 0x0418, 0, 0x00000000, 0xffffffff },
3150                 { 0x041c, 0, 0x00000000, 0xffffffff },
3151                 { 0x0420, 0, 0x00000000, 0x80ffffff },
3152                 { 0x0424, 0, 0x00000000, 0x00000000 },
3153                 { 0x0428, 0, 0x00000000, 0x00000001 },
3154                 { 0x0450, 0, 0x00000000, 0x0000ffff },
3155                 { 0x0454, 0, 0x00000000, 0xffffffff },
3156                 { 0x0458, 0, 0x00000000, 0xffffffff },
3157
3158                 { 0x0808, 0, 0x00000000, 0xffffffff },
3159                 { 0x0854, 0, 0x00000000, 0xffffffff },
3160                 { 0x0868, 0, 0x00000000, 0x77777777 },
3161                 { 0x086c, 0, 0x00000000, 0x77777777 },
3162                 { 0x0870, 0, 0x00000000, 0x77777777 },
3163                 { 0x0874, 0, 0x00000000, 0x77777777 },
3164
3165                 { 0x0c00, 0, 0x00000000, 0x00000001 },
3166                 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3167                 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3168                 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3169                 { 0x0c30, 0, 0x00000000, 0xffffffff },
3170                 { 0x0c34, 0, 0x00000000, 0xffffffff },
3171                 { 0x0c38, 0, 0x00000000, 0xffffffff },
3172                 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3173                 { 0x0c40, 0, 0x00000000, 0xffffffff },
3174                 { 0x0c44, 0, 0x00000000, 0xffffffff },
3175                 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3176                 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3177                 { 0x0c50, 0, 0x00000000, 0xffffffff },
3178                 { 0x0c54, 0, 0x00000000, 0xffffffff },
3179                 { 0x0c58, 0, 0x00000000, 0xffffffff },
3180                 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3181                 { 0x0c60, 0, 0x00000000, 0xffffffff },
3182                 { 0x0c64, 0, 0x00000000, 0xffffffff },
3183                 { 0x0c68, 0, 0x00000000, 0xffffffff },
3184                 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3185                 { 0x0c70, 0, 0x00000000, 0xffffffff },
3186                 { 0x0c74, 0, 0x00000000, 0xffffffff },
3187                 { 0x0c78, 0, 0x00000000, 0xffffffff },
3188                 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3189                 { 0x0c80, 0, 0x00000000, 0xffffffff },
3190                 { 0x0c84, 0, 0x00000000, 0xffffffff },
3191                 { 0x0c88, 0, 0x00000000, 0xffffffff },
3192                 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3193                 { 0x0c90, 0, 0x00000000, 0xffffffff },
3194                 { 0x0c94, 0, 0x00000000, 0xffffffff },
3195                 { 0x0c98, 0, 0x00000000, 0xffffffff },
3196                 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3197                 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3198                 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3199                 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3200                 { 0x0cac, 0, 0x00000000, 0xffffffff },
3201                 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3202                 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3203                 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3204                 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3205                 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3206                 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3207                 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3208                 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3209                 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3210                 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3211                 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3212                 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3213                 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3214                 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3215                 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3216                 { 0x0cec, 0, 0x00000000, 0xffffffff },
3217                 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3218                 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3219                 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3220                 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3221                 { 0x0d00, 0, 0x00000000, 0xffffffff },
3222                 { 0x0d04, 0, 0x00000000, 0xffffffff },
3223
3224                 { 0x1000, 0, 0x00000000, 0x00000001 },
3225                 { 0x1004, 0, 0x00000000, 0x000f0001 },
3226                 { 0x1044, 0, 0x00000000, 0xffc003ff },
3227                 { 0x1080, 0, 0x00000000, 0x0001ffff },
3228                 { 0x1084, 0, 0x00000000, 0xffffffff },
3229                 { 0x1088, 0, 0x00000000, 0xffffffff },
3230                 { 0x108c, 0, 0x00000000, 0xffffffff },
3231                 { 0x1090, 0, 0x00000000, 0xffffffff },
3232                 { 0x1094, 0, 0x00000000, 0xffffffff },
3233                 { 0x1098, 0, 0x00000000, 0xffffffff },
3234                 { 0x109c, 0, 0x00000000, 0xffffffff },
3235                 { 0x10a0, 0, 0x00000000, 0xffffffff },
3236
3237                 { 0x1408, 0, 0x01c00800, 0x00000000 },
3238                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3239                 { 0x14a8, 0, 0x00000000, 0x000001ff },
3240                 { 0x14ac, 0, 0x4fffffff, 0x10000000 },
3241                 { 0x14b0, 0, 0x00000002, 0x00000001 },
3242                 { 0x14b8, 0, 0x00000000, 0x00000000 },
3243                 { 0x14c0, 0, 0x00000000, 0x00000009 },
3244                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3245                 { 0x14cc, 0, 0x00000000, 0x00000001 },
3246                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3247                 { 0x1500, 0, 0x00000000, 0xffffffff },
3248                 { 0x1504, 0, 0x00000000, 0xffffffff },
3249                 { 0x1508, 0, 0x00000000, 0xffffffff },
3250                 { 0x150c, 0, 0x00000000, 0xffffffff },
3251                 { 0x1510, 0, 0x00000000, 0xffffffff },
3252                 { 0x1514, 0, 0x00000000, 0xffffffff },
3253                 { 0x1518, 0, 0x00000000, 0xffffffff },
3254                 { 0x151c, 0, 0x00000000, 0xffffffff },
3255                 { 0x1520, 0, 0x00000000, 0xffffffff },
3256                 { 0x1524, 0, 0x00000000, 0xffffffff },
3257                 { 0x1528, 0, 0x00000000, 0xffffffff },
3258                 { 0x152c, 0, 0x00000000, 0xffffffff },
3259                 { 0x1530, 0, 0x00000000, 0xffffffff },
3260                 { 0x1534, 0, 0x00000000, 0xffffffff },
3261                 { 0x1538, 0, 0x00000000, 0xffffffff },
3262                 { 0x153c, 0, 0x00000000, 0xffffffff },
3263                 { 0x1540, 0, 0x00000000, 0xffffffff },
3264                 { 0x1544, 0, 0x00000000, 0xffffffff },
3265                 { 0x1548, 0, 0x00000000, 0xffffffff },
3266                 { 0x154c, 0, 0x00000000, 0xffffffff },
3267                 { 0x1550, 0, 0x00000000, 0xffffffff },
3268                 { 0x1554, 0, 0x00000000, 0xffffffff },
3269                 { 0x1558, 0, 0x00000000, 0xffffffff },
3270                 { 0x1600, 0, 0x00000000, 0xffffffff },
3271                 { 0x1604, 0, 0x00000000, 0xffffffff },
3272                 { 0x1608, 0, 0x00000000, 0xffffffff },
3273                 { 0x160c, 0, 0x00000000, 0xffffffff },
3274                 { 0x1610, 0, 0x00000000, 0xffffffff },
3275                 { 0x1614, 0, 0x00000000, 0xffffffff },
3276                 { 0x1618, 0, 0x00000000, 0xffffffff },
3277                 { 0x161c, 0, 0x00000000, 0xffffffff },
3278                 { 0x1620, 0, 0x00000000, 0xffffffff },
3279                 { 0x1624, 0, 0x00000000, 0xffffffff },
3280                 { 0x1628, 0, 0x00000000, 0xffffffff },
3281                 { 0x162c, 0, 0x00000000, 0xffffffff },
3282                 { 0x1630, 0, 0x00000000, 0xffffffff },
3283                 { 0x1634, 0, 0x00000000, 0xffffffff },
3284                 { 0x1638, 0, 0x00000000, 0xffffffff },
3285                 { 0x163c, 0, 0x00000000, 0xffffffff },
3286                 { 0x1640, 0, 0x00000000, 0xffffffff },
3287                 { 0x1644, 0, 0x00000000, 0xffffffff },
3288                 { 0x1648, 0, 0x00000000, 0xffffffff },
3289                 { 0x164c, 0, 0x00000000, 0xffffffff },
3290                 { 0x1650, 0, 0x00000000, 0xffffffff },
3291                 { 0x1654, 0, 0x00000000, 0xffffffff },
3292
3293                 { 0x1800, 0, 0x00000000, 0x00000001 },
3294                 { 0x1804, 0, 0x00000000, 0x00000003 },
3295                 { 0x1840, 0, 0x00000000, 0xffffffff },
3296                 { 0x1844, 0, 0x00000000, 0xffffffff },
3297                 { 0x1848, 0, 0x00000000, 0xffffffff },
3298                 { 0x184c, 0, 0x00000000, 0xffffffff },
3299                 { 0x1850, 0, 0x00000000, 0xffffffff },
3300                 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3301                 { 0x1904, 0, 0xffffffff, 0x00000000 },
3302                 { 0x190c, 0, 0xffffffff, 0x00000000 },
3303                 { 0x1914, 0, 0xffffffff, 0x00000000 },
3304                 { 0x191c, 0, 0xffffffff, 0x00000000 },
3305                 { 0x1924, 0, 0xffffffff, 0x00000000 },
3306                 { 0x192c, 0, 0xffffffff, 0x00000000 },
3307                 { 0x1934, 0, 0xffffffff, 0x00000000 },
3308                 { 0x193c, 0, 0xffffffff, 0x00000000 },
3309                 { 0x1944, 0, 0xffffffff, 0x00000000 },
3310                 { 0x194c, 0, 0xffffffff, 0x00000000 },
3311                 { 0x1954, 0, 0xffffffff, 0x00000000 },
3312                 { 0x195c, 0, 0xffffffff, 0x00000000 },
3313                 { 0x1964, 0, 0xffffffff, 0x00000000 },
3314                 { 0x196c, 0, 0xffffffff, 0x00000000 },
3315                 { 0x1974, 0, 0xffffffff, 0x00000000 },
3316                 { 0x197c, 0, 0xffffffff, 0x00000000 },
3317                 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3318
3319                 { 0x1c00, 0, 0x00000000, 0x00000001 },
3320                 { 0x1c04, 0, 0x00000000, 0x00000003 },
3321                 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3322                 { 0x1c40, 0, 0x00000000, 0xffffffff },
3323                 { 0x1c44, 0, 0x00000000, 0xffffffff },
3324                 { 0x1c48, 0, 0x00000000, 0xffffffff },
3325                 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3326                 { 0x1c50, 0, 0x00000000, 0xffffffff },
3327                 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3328                 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3329                 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3330                 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3331                 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3332                 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3333                 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3334                 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3335                 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3336                 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3337                 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3338                 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3339                 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3340                 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3341                 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3342                 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3343                 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3344                 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3345
3346                 { 0x2004, 0, 0x00000000, 0x0337000f },
3347                 { 0x2008, 0, 0xffffffff, 0x00000000 },
3348                 { 0x200c, 0, 0xffffffff, 0x00000000 },
3349                 { 0x2010, 0, 0xffffffff, 0x00000000 },
3350                 { 0x2014, 0, 0x801fff80, 0x00000000 },
3351                 { 0x2018, 0, 0x000003ff, 0x00000000 },
3352
3353                 { 0x2800, 0, 0x00000000, 0x00000001 },
3354                 { 0x2804, 0, 0x00000000, 0x00003f01 },
3355                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3356                 { 0x2810, 0, 0xffff0000, 0x00000000 },
3357                 { 0x2814, 0, 0xffff0000, 0x00000000 },
3358                 { 0x2818, 0, 0xffff0000, 0x00000000 },
3359                 { 0x281c, 0, 0xffff0000, 0x00000000 },
3360                 { 0x2834, 0, 0xffffffff, 0x00000000 },
3361                 { 0x2840, 0, 0x00000000, 0xffffffff },
3362                 { 0x2844, 0, 0x00000000, 0xffffffff },
3363                 { 0x2848, 0, 0xffffffff, 0x00000000 },
3364                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3365
3366                 { 0x2c00, 0, 0x00000000, 0x00000011 },
3367                 { 0x2c04, 0, 0x00000000, 0x00030007 },
3368
3369                 { 0x3000, 0, 0x00000000, 0x00000001 },
3370                 { 0x3004, 0, 0x00000000, 0x007007ff },
3371                 { 0x3008, 0, 0x00000003, 0x00000000 },
3372                 { 0x300c, 0, 0xffffffff, 0x00000000 },
3373                 { 0x3010, 0, 0xffffffff, 0x00000000 },
3374                 { 0x3014, 0, 0xffffffff, 0x00000000 },
3375                 { 0x3034, 0, 0xffffffff, 0x00000000 },
3376                 { 0x3038, 0, 0xffffffff, 0x00000000 },
3377                 { 0x3050, 0, 0x00000001, 0x00000000 },
3378
3379                 { 0x3c00, 0, 0x00000000, 0x00000001 },
3380                 { 0x3c04, 0, 0x00000000, 0x00070000 },
3381                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3382                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3383                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3384                 { 0x3c14, 0, 0x00000000, 0xffffffff },
3385                 { 0x3c18, 0, 0x00000000, 0xffffffff },
3386                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3387                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3388                 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3389                 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3390                 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3391                 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3392                 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3393                 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3394                 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3395                 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3396                 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3397                 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3398                 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3399                 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3400                 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3401                 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3402                 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3403                 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3404                 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3405                 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3406                 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3407                 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3408                 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3409                 { 0x3c78, 0, 0x00000000, 0x00000000 },
3410                 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3411                 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3412                 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3413                 { 0x3c88, 0, 0x00000000, 0xffffffff },
3414                 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3415
3416                 { 0x4000, 0, 0x00000000, 0x00000001 },
3417                 { 0x4004, 0, 0x00000000, 0x00030000 },
3418                 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3419                 { 0x400c, 0, 0xffffffff, 0x00000000 },
3420                 { 0x4088, 0, 0x00000000, 0x00070303 },
3421
3422                 { 0x4400, 0, 0x00000000, 0x00000001 },
3423                 { 0x4404, 0, 0x00000000, 0x00003f01 },
3424                 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3425                 { 0x440c, 0, 0xffffffff, 0x00000000 },
3426                 { 0x4410, 0, 0xffff,     0x0000 },
3427                 { 0x4414, 0, 0xffff,     0x0000 },
3428                 { 0x4418, 0, 0xffff,     0x0000 },
3429                 { 0x441c, 0, 0xffff,     0x0000 },
3430                 { 0x4428, 0, 0xffffffff, 0x00000000 },
3431                 { 0x442c, 0, 0xffffffff, 0x00000000 },
3432                 { 0x4430, 0, 0xffffffff, 0x00000000 },
3433                 { 0x4434, 0, 0xffffffff, 0x00000000 },
3434                 { 0x4438, 0, 0xffffffff, 0x00000000 },
3435                 { 0x443c, 0, 0xffffffff, 0x00000000 },
3436                 { 0x4440, 0, 0xffffffff, 0x00000000 },
3437                 { 0x4444, 0, 0xffffffff, 0x00000000 },
3438
3439                 { 0x4c00, 0, 0x00000000, 0x00000001 },
3440                 { 0x4c04, 0, 0x00000000, 0x0000003f },
3441                 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3442                 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3443                 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3444                 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3445                 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3446                 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3447                 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3448                 { 0x4c50, 0, 0x00000000, 0xffffffff },
3449
3450                 { 0x5004, 0, 0x00000000, 0x0000007f },
3451                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3452                 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3453
3454                 { 0x5400, 0, 0x00000008, 0x00000001 },
3455                 { 0x5404, 0, 0x00000000, 0x0000003f },
3456                 { 0x5408, 0, 0x0000001f, 0x00000000 },
3457                 { 0x540c, 0, 0xffffffff, 0x00000000 },
3458                 { 0x5410, 0, 0xffffffff, 0x00000000 },
3459                 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3460                 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3461                 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3462                 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3463                 { 0x5428, 0, 0x000000ff, 0x00000000 },
3464                 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3465                 { 0x5430, 0, 0x001fff80, 0x00000000 },
3466                 { 0x5438, 0, 0xffffffff, 0x00000000 },
3467                 { 0x543c, 0, 0xffffffff, 0x00000000 },
3468                 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3469
3470                 { 0x5c00, 0, 0x00000000, 0x00000001 },
3471                 { 0x5c04, 0, 0x00000000, 0x0003000f },
3472                 { 0x5c08, 0, 0x00000003, 0x00000000 },
3473                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3474                 { 0x5c10, 0, 0x00000000, 0xffffffff },
3475                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3476                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3477                 { 0x5c88, 0, 0x00000000, 0x00077373 },
3478                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3479
3480                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3481                 { 0x680c, 0, 0xffffffff, 0x00000000 },
3482                 { 0x6810, 0, 0xffffffff, 0x00000000 },
3483                 { 0x6814, 0, 0xffffffff, 0x00000000 },
3484                 { 0x6818, 0, 0xffffffff, 0x00000000 },
3485                 { 0x681c, 0, 0xffffffff, 0x00000000 },
3486                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3487                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3488                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3489                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3490                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3491                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3492                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3493                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3494                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3495                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3496                 { 0x684c, 0, 0xffffffff, 0x00000000 },
3497                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3498                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3499                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3500                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3501                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3502                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3503
3504                 { 0xffff, 0, 0x00000000, 0x00000000 },
3505         };
3506
3507         ret = 0;
3508         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3509                 u32 offset, rw_mask, ro_mask, save_val, val;
3510
3511                 offset = (u32) reg_tbl[i].offset;
3512                 rw_mask = reg_tbl[i].rw_mask;
3513                 ro_mask = reg_tbl[i].ro_mask;
3514
3515                 save_val = readl(bp->regview + offset);
3516
3517                 writel(0, bp->regview + offset);
3518
3519                 val = readl(bp->regview + offset);
3520                 if ((val & rw_mask) != 0) {
3521                         goto reg_test_err;
3522                 }
3523
3524                 if ((val & ro_mask) != (save_val & ro_mask)) {
3525                         goto reg_test_err;
3526                 }
3527
3528                 writel(0xffffffff, bp->regview + offset);
3529
3530                 val = readl(bp->regview + offset);
3531                 if ((val & rw_mask) != rw_mask) {
3532                         goto reg_test_err;
3533                 }
3534
3535                 if ((val & ro_mask) != (save_val & ro_mask)) {
3536                         goto reg_test_err;
3537                 }
3538
3539                 writel(save_val, bp->regview + offset);
3540                 continue;
3541
3542 reg_test_err:
3543                 writel(save_val, bp->regview + offset);
3544                 ret = -ENODEV;
3545                 break;
3546         }
3547         return ret;
3548 }
3549
3550 static int
3551 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3552 {
3553         static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3554                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3555         int i;
3556
3557         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3558                 u32 offset;
3559
3560                 for (offset = 0; offset < size; offset += 4) {
3561
3562                         REG_WR_IND(bp, start + offset, test_pattern[i]);
3563
3564                         if (REG_RD_IND(bp, start + offset) !=
3565                                 test_pattern[i]) {
3566                                 return -ENODEV;
3567                         }
3568                 }
3569         }
3570         return 0;
3571 }
3572
3573 static int
3574 bnx2_test_memory(struct bnx2 *bp)
3575 {
3576         int ret = 0;
3577         int i;
3578         static struct {
3579                 u32   offset;
3580                 u32   len;
3581         } mem_tbl[] = {
3582                 { 0x60000,  0x4000 },
3583                 { 0xa0000,  0x4000 },
3584                 { 0xe0000,  0x4000 },
3585                 { 0x120000, 0x4000 },
3586                 { 0x1a0000, 0x4000 },
3587                 { 0x160000, 0x4000 },
3588                 { 0xffffffff, 0    },
3589         };
3590
3591         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3592                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3593                         mem_tbl[i].len)) != 0) {
3594                         return ret;
3595                 }
3596         }
3597
3598         return ret;
3599 }
3600
3601 static int
3602 bnx2_test_loopback(struct bnx2 *bp)
3603 {
3604         unsigned int pkt_size, num_pkts, i;
3605         struct sk_buff *skb, *rx_skb;
3606         unsigned char *packet;
3607         u16 rx_start_idx, rx_idx, send_idx;
3608         u32 send_bseq, val;
3609         dma_addr_t map;
3610         struct tx_bd *txbd;
3611         struct sw_bd *rx_buf;
3612         struct l2_fhdr *rx_hdr;
3613         int ret = -ENODEV;
3614
3615         if (!netif_running(bp->dev))
3616                 return -ENODEV;
3617
3618         bp->loopback = MAC_LOOPBACK;
3619         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3620         bnx2_set_mac_loopback(bp);
3621
3622         pkt_size = 1514;
3623         skb = dev_alloc_skb(pkt_size);
3624         packet = skb_put(skb, pkt_size);
3625         memcpy(packet, bp->mac_addr, 6);
3626         memset(packet + 6, 0x0, 8);
3627         for (i = 14; i < pkt_size; i++)
3628                 packet[i] = (unsigned char) (i & 0xff);
3629
3630         map = pci_map_single(bp->pdev, skb->data, pkt_size,
3631                 PCI_DMA_TODEVICE);
3632
3633         val = REG_RD(bp, BNX2_HC_COMMAND);
3634         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3635         REG_RD(bp, BNX2_HC_COMMAND);
3636
3637         udelay(5);
3638         rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3639
3640         send_idx = 0;
3641         send_bseq = 0;
3642         num_pkts = 0;
3643
3644         txbd = &bp->tx_desc_ring[send_idx];
3645
3646         txbd->tx_bd_haddr_hi = (u64) map >> 32;
3647         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3648         txbd->tx_bd_mss_nbytes = pkt_size;
3649         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3650
3651         num_pkts++;
3652         send_idx = NEXT_TX_BD(send_idx);
3653
3654         send_bseq += pkt_size;
3655
3656         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3657         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3658
3659
3660         udelay(100);
3661
3662         val = REG_RD(bp, BNX2_HC_COMMAND);
3663         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3664         REG_RD(bp, BNX2_HC_COMMAND);
3665
3666         udelay(5);
3667
3668         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3669         dev_kfree_skb_irq(skb);
3670
3671         if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3672                 goto loopback_test_done;
3673         }
3674
3675         rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3676         if (rx_idx != rx_start_idx + num_pkts) {
3677                 goto loopback_test_done;
3678         }
3679
3680         rx_buf = &bp->rx_buf_ring[rx_start_idx];
3681         rx_skb = rx_buf->skb;
3682
3683         rx_hdr = (struct l2_fhdr *) rx_skb->data;
3684         skb_reserve(rx_skb, bp->rx_offset);
3685
3686         pci_dma_sync_single_for_cpu(bp->pdev,
3687                 pci_unmap_addr(rx_buf, mapping),
3688                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3689
3690         if (rx_hdr->l2_fhdr_errors &
3691                 (L2_FHDR_ERRORS_BAD_CRC |
3692                 L2_FHDR_ERRORS_PHY_DECODE |
3693                 L2_FHDR_ERRORS_ALIGNMENT |
3694                 L2_FHDR_ERRORS_TOO_SHORT |
3695                 L2_FHDR_ERRORS_GIANT_FRAME)) {
3696
3697                 goto loopback_test_done;
3698         }
3699
3700         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3701                 goto loopback_test_done;
3702         }
3703
3704         for (i = 14; i < pkt_size; i++) {
3705                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3706                         goto loopback_test_done;
3707                 }
3708         }
3709
3710         ret = 0;
3711
3712 loopback_test_done:
3713         bp->loopback = 0;
3714         return ret;
3715 }
3716
3717 #define NVRAM_SIZE 0x200
3718 #define CRC32_RESIDUAL 0xdebb20e3
3719
3720 static int
3721 bnx2_test_nvram(struct bnx2 *bp)
3722 {
3723         u32 buf[NVRAM_SIZE / 4];
3724         u8 *data = (u8 *) buf;
3725         int rc = 0;
3726         u32 magic, csum;
3727
3728         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
3729                 goto test_nvram_done;
3730
3731         magic = be32_to_cpu(buf[0]);
3732         if (magic != 0x669955aa) {
3733                 rc = -ENODEV;
3734                 goto test_nvram_done;
3735         }
3736
3737         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
3738                 goto test_nvram_done;
3739
3740         csum = ether_crc_le(0x100, data);
3741         if (csum != CRC32_RESIDUAL) {
3742                 rc = -ENODEV;
3743                 goto test_nvram_done;
3744         }
3745
3746         csum = ether_crc_le(0x100, data + 0x100);
3747         if (csum != CRC32_RESIDUAL) {
3748                 rc = -ENODEV;
3749         }
3750
3751 test_nvram_done:
3752         return rc;
3753 }
3754
3755 static int
3756 bnx2_test_link(struct bnx2 *bp)
3757 {
3758         u32 bmsr;
3759
3760         spin_lock_bh(&bp->phy_lock);
3761         bnx2_read_phy(bp, MII_BMSR, &bmsr);
3762         bnx2_read_phy(bp, MII_BMSR, &bmsr);
3763         spin_unlock_bh(&bp->phy_lock);
3764
3765         if (bmsr & BMSR_LSTATUS) {
3766                 return 0;
3767         }
3768         return -ENODEV;
3769 }
3770
3771 static int
3772 bnx2_test_intr(struct bnx2 *bp)
3773 {
3774         int i;
3775         u32 val;
3776         u16 status_idx;
3777
3778         if (!netif_running(bp->dev))
3779                 return -ENODEV;
3780
3781         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
3782
3783         /* This register is not touched during run-time. */
3784         val = REG_RD(bp, BNX2_HC_COMMAND);
3785         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
3786         REG_RD(bp, BNX2_HC_COMMAND);
3787
3788         for (i = 0; i < 10; i++) {
3789                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
3790                         status_idx) {
3791
3792                         break;
3793                 }
3794
3795                 msleep_interruptible(10);
3796         }
3797         if (i < 10)
3798                 return 0;
3799
3800         return -ENODEV;
3801 }
3802
3803 static void
3804 bnx2_timer(unsigned long data)
3805 {
3806         struct bnx2 *bp = (struct bnx2 *) data;
3807         u32 msg;
3808
3809         if (!netif_running(bp->dev))
3810                 return;
3811
3812         if (atomic_read(&bp->intr_sem) != 0)
3813                 goto bnx2_restart_timer;
3814
3815         msg = (u32) ++bp->fw_drv_pulse_wr_seq;
3816         REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
3817
3818         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
3819             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
3820
3821                 spin_lock(&bp->phy_lock);
3822                 if (bp->serdes_an_pending) {
3823                         bp->serdes_an_pending--;
3824                 }
3825                 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
3826                         u32 bmcr;
3827
3828                         bp->current_interval = bp->timer_interval;
3829
3830                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
3831
3832                         if (bmcr & BMCR_ANENABLE) {
3833                                 u32 phy1, phy2;
3834
3835                                 bnx2_write_phy(bp, 0x1c, 0x7c00);
3836                                 bnx2_read_phy(bp, 0x1c, &phy1);
3837
3838                                 bnx2_write_phy(bp, 0x17, 0x0f01);
3839                                 bnx2_read_phy(bp, 0x15, &phy2);
3840                                 bnx2_write_phy(bp, 0x17, 0x0f01);
3841                                 bnx2_read_phy(bp, 0x15, &phy2);
3842
3843                                 if ((phy1 & 0x10) &&    /* SIGNAL DETECT */
3844                                         !(phy2 & 0x20)) {       /* no CONFIG */
3845
3846                                         bmcr &= ~BMCR_ANENABLE;
3847                                         bmcr |= BMCR_SPEED1000 |
3848                                                 BMCR_FULLDPLX;
3849                                         bnx2_write_phy(bp, MII_BMCR, bmcr);
3850                                         bp->phy_flags |=
3851                                                 PHY_PARALLEL_DETECT_FLAG;
3852                                 }
3853                         }
3854                 }
3855                 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
3856                         (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
3857                         u32 phy2;
3858
3859                         bnx2_write_phy(bp, 0x17, 0x0f01);
3860                         bnx2_read_phy(bp, 0x15, &phy2);
3861                         if (phy2 & 0x20) {
3862                                 u32 bmcr;
3863
3864                                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3865                                 bmcr |= BMCR_ANENABLE;
3866                                 bnx2_write_phy(bp, MII_BMCR, bmcr);
3867
3868                                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
3869
3870                         }
3871                 }
3872                 else
3873                         bp->current_interval = bp->timer_interval;
3874
3875                 spin_unlock(&bp->phy_lock);
3876         }
3877
3878 bnx2_restart_timer:
3879         mod_timer(&bp->timer, jiffies + bp->current_interval);
3880 }
3881
3882 /* Called with rtnl_lock */
3883 static int
3884 bnx2_open(struct net_device *dev)
3885 {
3886         struct bnx2 *bp = dev->priv;
3887         int rc;
3888
3889         bnx2_set_power_state(bp, PCI_D0);
3890         bnx2_disable_int(bp);
3891
3892         rc = bnx2_alloc_mem(bp);
3893         if (rc)
3894                 return rc;
3895
3896         if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
3897                 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
3898                 !disable_msi) {
3899
3900                 if (pci_enable_msi(bp->pdev) == 0) {
3901                         bp->flags |= USING_MSI_FLAG;
3902                         rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
3903                                         dev);
3904                 }
3905                 else {
3906                         rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3907                                         SA_SHIRQ, dev->name, dev);
3908                 }
3909         }
3910         else {
3911                 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
3912                                 dev->name, dev);
3913         }
3914         if (rc) {
3915                 bnx2_free_mem(bp);
3916                 return rc;
3917         }
3918
3919         rc = bnx2_init_nic(bp);
3920
3921         if (rc) {
3922                 free_irq(bp->pdev->irq, dev);
3923                 if (bp->flags & USING_MSI_FLAG) {
3924                         pci_disable_msi(bp->pdev);
3925                         bp->flags &= ~USING_MSI_FLAG;
3926                 }
3927                 bnx2_free_skbs(bp);
3928                 bnx2_free_mem(bp);
3929                 return rc;
3930         }
3931
3932         mod_timer(&bp->timer, jiffies + bp->current_interval);
3933
3934         atomic_set(&bp->intr_sem, 0);
3935
3936         bnx2_enable_int(bp);
3937
3938         if (bp->flags & USING_MSI_FLAG) {
3939                 /* Test MSI to make sure it is working
3940                  * If MSI test fails, go back to INTx mode
3941                  */
3942                 if (bnx2_test_intr(bp) != 0) {
3943                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
3944                                " using MSI, switching to INTx mode. Please"
3945                                " report this failure to the PCI maintainer"
3946                                " and include system chipset information.\n",
3947                                bp->dev->name);
3948
3949                         bnx2_disable_int(bp);
3950                         free_irq(bp->pdev->irq, dev);
3951                         pci_disable_msi(bp->pdev);
3952                         bp->flags &= ~USING_MSI_FLAG;
3953
3954                         rc = bnx2_init_nic(bp);
3955
3956                         if (!rc) {
3957                                 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3958                                         SA_SHIRQ, dev->name, dev);
3959                         }
3960                         if (rc) {
3961                                 bnx2_free_skbs(bp);
3962                                 bnx2_free_mem(bp);
3963                                 del_timer_sync(&bp->timer);
3964                                 return rc;
3965                         }
3966                         bnx2_enable_int(bp);
3967                 }
3968         }
3969         if (bp->flags & USING_MSI_FLAG) {
3970                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
3971         }
3972
3973         netif_start_queue(dev);
3974
3975         return 0;
3976 }
3977
3978 static void
3979 bnx2_reset_task(void *data)
3980 {
3981         struct bnx2 *bp = data;
3982
3983         if (!netif_running(bp->dev))
3984                 return;
3985
3986         bp->in_reset_task = 1;
3987         bnx2_netif_stop(bp);
3988
3989         bnx2_init_nic(bp);
3990
3991         atomic_set(&bp->intr_sem, 1);
3992         bnx2_netif_start(bp);
3993         bp->in_reset_task = 0;
3994 }
3995
3996 static void
3997 bnx2_tx_timeout(struct net_device *dev)
3998 {
3999         struct bnx2 *bp = dev->priv;
4000
4001         /* This allows the netif to be shutdown gracefully before resetting */
4002         schedule_work(&bp->reset_task);
4003 }
4004
4005 #ifdef BCM_VLAN
4006 /* Called with rtnl_lock */
4007 static void
4008 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4009 {
4010         struct bnx2 *bp = dev->priv;
4011
4012         bnx2_netif_stop(bp);
4013
4014         bp->vlgrp = vlgrp;
4015         bnx2_set_rx_mode(dev);
4016
4017         bnx2_netif_start(bp);
4018 }
4019
4020 /* Called with rtnl_lock */
4021 static void
4022 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4023 {
4024         struct bnx2 *bp = dev->priv;
4025
4026         bnx2_netif_stop(bp);
4027
4028         if (bp->vlgrp)
4029                 bp->vlgrp->vlan_devices[vid] = NULL;
4030         bnx2_set_rx_mode(dev);
4031
4032         bnx2_netif_start(bp);
4033 }
4034 #endif
4035
4036 /* Called with dev->xmit_lock.
4037  * hard_start_xmit is pseudo-lockless - a lock is only required when
4038  * the tx queue is full. This way, we get the benefit of lockless
4039  * operations most of the time without the complexities to handle
4040  * netif_stop_queue/wake_queue race conditions.
4041  */
4042 static int
4043 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4044 {
4045         struct bnx2 *bp = dev->priv;
4046         dma_addr_t mapping;
4047         struct tx_bd *txbd;
4048         struct sw_bd *tx_buf;
4049         u32 len, vlan_tag_flags, last_frag, mss;
4050         u16 prod, ring_prod;
4051         int i;
4052
4053         if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4054                 netif_stop_queue(dev);
4055                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4056                         dev->name);
4057
4058                 return NETDEV_TX_BUSY;
4059         }
4060         len = skb_headlen(skb);
4061         prod = bp->tx_prod;
4062         ring_prod = TX_RING_IDX(prod);
4063
4064         vlan_tag_flags = 0;
4065         if (skb->ip_summed == CHECKSUM_HW) {
4066                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4067         }
4068
4069         if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4070                 vlan_tag_flags |=
4071                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4072         }
4073 #ifdef BCM_TSO
4074         if ((mss = skb_shinfo(skb)->tso_size) &&
4075                 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4076                 u32 tcp_opt_len, ip_tcp_len;
4077
4078                 if (skb_header_cloned(skb) &&
4079                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4080                         dev_kfree_skb(skb);
4081                         return NETDEV_TX_OK;
4082                 }
4083
4084                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4085                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4086
4087                 tcp_opt_len = 0;
4088                 if (skb->h.th->doff > 5) {
4089                         tcp_opt_len = (skb->h.th->doff - 5) << 2;
4090                 }
4091                 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4092
4093                 skb->nh.iph->check = 0;
4094                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4095                 skb->h.th->check =
4096                         ~csum_tcpudp_magic(skb->nh.iph->saddr,
4097                                             skb->nh.iph->daddr,
4098                                             0, IPPROTO_TCP, 0);
4099
4100                 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4101                         vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4102                                 (tcp_opt_len >> 2)) << 8;
4103                 }
4104         }
4105         else
4106 #endif
4107         {
4108                 mss = 0;
4109         }
4110
4111         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4112
4113         tx_buf = &bp->tx_buf_ring[ring_prod];
4114         tx_buf->skb = skb;
4115         pci_unmap_addr_set(tx_buf, mapping, mapping);
4116
4117         txbd = &bp->tx_desc_ring[ring_prod];
4118
4119         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4120         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4121         txbd->tx_bd_mss_nbytes = len | (mss << 16);
4122         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4123
4124         last_frag = skb_shinfo(skb)->nr_frags;
4125
4126         for (i = 0; i < last_frag; i++) {
4127                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4128
4129                 prod = NEXT_TX_BD(prod);
4130                 ring_prod = TX_RING_IDX(prod);
4131                 txbd = &bp->tx_desc_ring[ring_prod];
4132
4133                 len = frag->size;
4134                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4135                         len, PCI_DMA_TODEVICE);
4136                 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4137                                 mapping, mapping);
4138
4139                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4140                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4141                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4142                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4143
4144         }
4145         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4146
4147         prod = NEXT_TX_BD(prod);
4148         bp->tx_prod_bseq += skb->len;
4149
4150         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4151         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4152
4153         mmiowb();
4154
4155         bp->tx_prod = prod;
4156         dev->trans_start = jiffies;
4157
4158         if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4159                 spin_lock(&bp->tx_lock);
4160                 netif_stop_queue(dev);
4161
4162                 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4163                         netif_wake_queue(dev);
4164                 spin_unlock(&bp->tx_lock);
4165         }
4166
4167         return NETDEV_TX_OK;
4168 }
4169
4170 /* Called with rtnl_lock */
4171 static int
4172 bnx2_close(struct net_device *dev)
4173 {
4174         struct bnx2 *bp = dev->priv;
4175         u32 reset_code;
4176
4177         /* Calling flush_scheduled_work() may deadlock because
4178          * linkwatch_event() may be on the workqueue and it will try to get
4179          * the rtnl_lock which we are holding.
4180          */
4181         while (bp->in_reset_task)
4182                 msleep(1);
4183
4184         bnx2_netif_stop(bp);
4185         del_timer_sync(&bp->timer);
4186         if (bp->wol)
4187                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4188         else
4189                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4190         bnx2_reset_chip(bp, reset_code);
4191         free_irq(bp->pdev->irq, dev);
4192         if (bp->flags & USING_MSI_FLAG) {
4193                 pci_disable_msi(bp->pdev);
4194                 bp->flags &= ~USING_MSI_FLAG;
4195         }
4196         bnx2_free_skbs(bp);
4197         bnx2_free_mem(bp);
4198         bp->link_up = 0;
4199         netif_carrier_off(bp->dev);
4200         bnx2_set_power_state(bp, PCI_D3hot);
4201         return 0;
4202 }
4203
4204 #define GET_NET_STATS64(ctr)                                    \
4205         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
4206         (unsigned long) (ctr##_lo)
4207
4208 #define GET_NET_STATS32(ctr)            \
4209         (ctr##_lo)
4210
4211 #if (BITS_PER_LONG == 64)
4212 #define GET_NET_STATS   GET_NET_STATS64
4213 #else
4214 #define GET_NET_STATS   GET_NET_STATS32
4215 #endif
4216
4217 static struct net_device_stats *
4218 bnx2_get_stats(struct net_device *dev)
4219 {
4220         struct bnx2 *bp = dev->priv;
4221         struct statistics_block *stats_blk = bp->stats_blk;
4222         struct net_device_stats *net_stats = &bp->net_stats;
4223
4224         if (bp->stats_blk == NULL) {
4225                 return net_stats;
4226         }
4227         net_stats->rx_packets =
4228                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4229                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4230                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4231
4232         net_stats->tx_packets =
4233                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4234                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4235                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4236
4237         net_stats->rx_bytes =
4238                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4239
4240         net_stats->tx_bytes =
4241                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4242
4243         net_stats->multicast =
4244                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4245
4246         net_stats->collisions =
4247                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4248
4249         net_stats->rx_length_errors =
4250                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4251                 stats_blk->stat_EtherStatsOverrsizePkts);
4252
4253         net_stats->rx_over_errors =
4254                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4255
4256         net_stats->rx_frame_errors =
4257                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4258
4259         net_stats->rx_crc_errors =
4260                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4261
4262         net_stats->rx_errors = net_stats->rx_length_errors +
4263                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4264                 net_stats->rx_crc_errors;
4265
4266         net_stats->tx_aborted_errors =
4267                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4268                 stats_blk->stat_Dot3StatsLateCollisions);
4269
4270         if (CHIP_NUM(bp) == CHIP_NUM_5706)
4271                 net_stats->tx_carrier_errors = 0;
4272         else {
4273                 net_stats->tx_carrier_errors =
4274                         (unsigned long)
4275                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
4276         }
4277
4278         net_stats->tx_errors =
4279                 (unsigned long)
4280                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4281                 +
4282                 net_stats->tx_aborted_errors +
4283                 net_stats->tx_carrier_errors;
4284
4285         return net_stats;
4286 }
4287
4288 /* All ethtool functions called with rtnl_lock */
4289
4290 static int
4291 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4292 {
4293         struct bnx2 *bp = dev->priv;
4294
4295         cmd->supported = SUPPORTED_Autoneg;
4296         if (bp->phy_flags & PHY_SERDES_FLAG) {
4297                 cmd->supported |= SUPPORTED_1000baseT_Full |
4298                         SUPPORTED_FIBRE;
4299
4300                 cmd->port = PORT_FIBRE;
4301         }
4302         else {
4303                 cmd->supported |= SUPPORTED_10baseT_Half |
4304                         SUPPORTED_10baseT_Full |
4305                         SUPPORTED_100baseT_Half |
4306                         SUPPORTED_100baseT_Full |
4307                         SUPPORTED_1000baseT_Full |
4308                         SUPPORTED_TP;
4309
4310                 cmd->port = PORT_TP;
4311         }
4312
4313         cmd->advertising = bp->advertising;
4314
4315         if (bp->autoneg & AUTONEG_SPEED) {
4316                 cmd->autoneg = AUTONEG_ENABLE;
4317         }
4318         else {
4319                 cmd->autoneg = AUTONEG_DISABLE;
4320         }
4321
4322         if (netif_carrier_ok(dev)) {
4323                 cmd->speed = bp->line_speed;
4324                 cmd->duplex = bp->duplex;
4325         }
4326         else {
4327                 cmd->speed = -1;
4328                 cmd->duplex = -1;
4329         }
4330
4331         cmd->transceiver = XCVR_INTERNAL;
4332         cmd->phy_address = bp->phy_addr;
4333
4334         return 0;
4335 }
4336
4337 static int
4338 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4339 {
4340         struct bnx2 *bp = dev->priv;
4341         u8 autoneg = bp->autoneg;
4342         u8 req_duplex = bp->req_duplex;
4343         u16 req_line_speed = bp->req_line_speed;
4344         u32 advertising = bp->advertising;
4345
4346         if (cmd->autoneg == AUTONEG_ENABLE) {
4347                 autoneg |= AUTONEG_SPEED;
4348
4349                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4350
4351                 /* allow advertising 1 speed */
4352                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4353                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
4354                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
4355                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
4356
4357                         if (bp->phy_flags & PHY_SERDES_FLAG)
4358                                 return -EINVAL;
4359
4360                         advertising = cmd->advertising;
4361
4362                 }
4363                 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4364                         advertising = cmd->advertising;
4365                 }
4366                 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4367                         return -EINVAL;
4368                 }
4369                 else {
4370                         if (bp->phy_flags & PHY_SERDES_FLAG) {
4371                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4372                         }
4373                         else {
4374                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
4375                         }
4376                 }
4377                 advertising |= ADVERTISED_Autoneg;
4378         }
4379         else {
4380                 if (bp->phy_flags & PHY_SERDES_FLAG) {
4381                         if ((cmd->speed != SPEED_1000) ||
4382                                 (cmd->duplex != DUPLEX_FULL)) {
4383                                 return -EINVAL;
4384                         }
4385                 }
4386                 else if (cmd->speed == SPEED_1000) {
4387                         return -EINVAL;
4388                 }
4389                 autoneg &= ~AUTONEG_SPEED;
4390                 req_line_speed = cmd->speed;
4391                 req_duplex = cmd->duplex;
4392                 advertising = 0;
4393         }
4394
4395         bp->autoneg = autoneg;
4396         bp->advertising = advertising;
4397         bp->req_line_speed = req_line_speed;
4398         bp->req_duplex = req_duplex;
4399
4400         spin_lock_bh(&bp->phy_lock);
4401
4402         bnx2_setup_phy(bp);
4403
4404         spin_unlock_bh(&bp->phy_lock);
4405
4406         return 0;
4407 }
4408
4409 static void
4410 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4411 {
4412         struct bnx2 *bp = dev->priv;
4413
4414         strcpy(info->driver, DRV_MODULE_NAME);
4415         strcpy(info->version, DRV_MODULE_VERSION);
4416         strcpy(info->bus_info, pci_name(bp->pdev));
4417         info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4418         info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4419         info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4420         info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4421         info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4422         info->fw_version[7] = 0;
4423 }
4424
4425 static void
4426 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4427 {
4428         struct bnx2 *bp = dev->priv;
4429
4430         if (bp->flags & NO_WOL_FLAG) {
4431                 wol->supported = 0;
4432                 wol->wolopts = 0;
4433         }
4434         else {
4435                 wol->supported = WAKE_MAGIC;
4436                 if (bp->wol)
4437                         wol->wolopts = WAKE_MAGIC;
4438                 else
4439                         wol->wolopts = 0;
4440         }
4441         memset(&wol->sopass, 0, sizeof(wol->sopass));
4442 }
4443
4444 static int
4445 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4446 {
4447         struct bnx2 *bp = dev->priv;
4448
4449         if (wol->wolopts & ~WAKE_MAGIC)
4450                 return -EINVAL;
4451
4452         if (wol->wolopts & WAKE_MAGIC) {
4453                 if (bp->flags & NO_WOL_FLAG)
4454                         return -EINVAL;
4455
4456                 bp->wol = 1;
4457         }
4458         else {
4459                 bp->wol = 0;
4460         }
4461         return 0;
4462 }
4463
4464 static int
4465 bnx2_nway_reset(struct net_device *dev)
4466 {
4467         struct bnx2 *bp = dev->priv;
4468         u32 bmcr;
4469
4470         if (!(bp->autoneg & AUTONEG_SPEED)) {
4471                 return -EINVAL;
4472         }
4473
4474         spin_lock_bh(&bp->phy_lock);
4475
4476         /* Force a link down visible on the other side */
4477         if (bp->phy_flags & PHY_SERDES_FLAG) {
4478                 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4479                 spin_unlock_bh(&bp->phy_lock);
4480
4481                 msleep(20);
4482
4483                 spin_lock_bh(&bp->phy_lock);
4484                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4485                         bp->current_interval = SERDES_AN_TIMEOUT;
4486                         bp->serdes_an_pending = 1;
4487                         mod_timer(&bp->timer, jiffies + bp->current_interval);
4488                 }
4489         }
4490
4491         bnx2_read_phy(bp, MII_BMCR, &bmcr);
4492         bmcr &= ~BMCR_LOOPBACK;
4493         bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4494
4495         spin_unlock_bh(&bp->phy_lock);
4496
4497         return 0;
4498 }
4499
4500 static int
4501 bnx2_get_eeprom_len(struct net_device *dev)
4502 {
4503         struct bnx2 *bp = dev->priv;
4504
4505         if (bp->flash_info == 0)
4506                 return 0;
4507
4508         return (int) bp->flash_info->total_size;
4509 }
4510
4511 static int
4512 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4513                 u8 *eebuf)
4514 {
4515         struct bnx2 *bp = dev->priv;
4516         int rc;
4517
4518         if (eeprom->offset > bp->flash_info->total_size)
4519                 return -EINVAL;
4520
4521         if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4522                 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4523
4524         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4525
4526         return rc;
4527 }
4528
4529 static int
4530 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4531                 u8 *eebuf)
4532 {
4533         struct bnx2 *bp = dev->priv;
4534         int rc;
4535
4536         if (eeprom->offset > bp->flash_info->total_size)
4537                 return -EINVAL;
4538
4539         if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4540                 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4541
4542         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4543
4544         return rc;
4545 }
4546
4547 static int
4548 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4549 {
4550         struct bnx2 *bp = dev->priv;
4551
4552         memset(coal, 0, sizeof(struct ethtool_coalesce));
4553
4554         coal->rx_coalesce_usecs = bp->rx_ticks;
4555         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4556         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4557         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4558
4559         coal->tx_coalesce_usecs = bp->tx_ticks;
4560         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4561         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4562         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4563
4564         coal->stats_block_coalesce_usecs = bp->stats_ticks;
4565
4566         return 0;
4567 }
4568
4569 static int
4570 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4571 {
4572         struct bnx2 *bp = dev->priv;
4573
4574         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4575         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4576
4577         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4578         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4579
4580         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4581         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4582
4583         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4584         if (bp->rx_quick_cons_trip_int > 0xff)
4585                 bp->rx_quick_cons_trip_int = 0xff;
4586
4587         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4588         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4589
4590         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4591         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4592
4593         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4594         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4595
4596         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4597         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4598                 0xff;
4599
4600         bp->stats_ticks = coal->stats_block_coalesce_usecs;
4601         if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4602         bp->stats_ticks &= 0xffff00;
4603
4604         if (netif_running(bp->dev)) {
4605                 bnx2_netif_stop(bp);
4606                 bnx2_init_nic(bp);
4607                 bnx2_netif_start(bp);
4608         }
4609
4610         return 0;
4611 }
4612
4613 static void
4614 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4615 {
4616         struct bnx2 *bp = dev->priv;
4617
4618         ering->rx_max_pending = MAX_RX_DESC_CNT;
4619         ering->rx_mini_max_pending = 0;
4620         ering->rx_jumbo_max_pending = 0;
4621
4622         ering->rx_pending = bp->rx_ring_size;
4623         ering->rx_mini_pending = 0;
4624         ering->rx_jumbo_pending = 0;
4625
4626         ering->tx_max_pending = MAX_TX_DESC_CNT;
4627         ering->tx_pending = bp->tx_ring_size;
4628 }
4629
4630 static int
4631 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4632 {
4633         struct bnx2 *bp = dev->priv;
4634
4635         if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4636                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4637                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4638
4639                 return -EINVAL;
4640         }
4641         bp->rx_ring_size = ering->rx_pending;
4642         bp->tx_ring_size = ering->tx_pending;
4643
4644         if (netif_running(bp->dev)) {
4645                 bnx2_netif_stop(bp);
4646                 bnx2_init_nic(bp);
4647                 bnx2_netif_start(bp);
4648         }
4649
4650         return 0;
4651 }
4652
4653 static void
4654 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4655 {
4656         struct bnx2 *bp = dev->priv;
4657
4658         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4659         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4660         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4661 }
4662
4663 static int
4664 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4665 {
4666         struct bnx2 *bp = dev->priv;
4667
4668         bp->req_flow_ctrl = 0;
4669         if (epause->rx_pause)
4670                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4671         if (epause->tx_pause)
4672                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4673
4674         if (epause->autoneg) {
4675                 bp->autoneg |= AUTONEG_FLOW_CTRL;
4676         }
4677         else {
4678                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4679         }
4680
4681         spin_lock_bh(&bp->phy_lock);
4682
4683         bnx2_setup_phy(bp);
4684
4685         spin_unlock_bh(&bp->phy_lock);
4686
4687         return 0;
4688 }
4689
4690 static u32
4691 bnx2_get_rx_csum(struct net_device *dev)
4692 {
4693         struct bnx2 *bp = dev->priv;
4694
4695         return bp->rx_csum;
4696 }
4697
4698 static int
4699 bnx2_set_rx_csum(struct net_device *dev, u32 data)
4700 {
4701         struct bnx2 *bp = dev->priv;
4702
4703         bp->rx_csum = data;
4704         return 0;
4705 }
4706
4707 #define BNX2_NUM_STATS 45
4708
4709 static struct {
4710         char string[ETH_GSTRING_LEN];
4711 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4712         { "rx_bytes" },
4713         { "rx_error_bytes" },
4714         { "tx_bytes" },
4715         { "tx_error_bytes" },
4716         { "rx_ucast_packets" },
4717         { "rx_mcast_packets" },
4718         { "rx_bcast_packets" },
4719         { "tx_ucast_packets" },
4720         { "tx_mcast_packets" },
4721         { "tx_bcast_packets" },
4722         { "tx_mac_errors" },
4723         { "tx_carrier_errors" },
4724         { "rx_crc_errors" },
4725         { "rx_align_errors" },
4726         { "tx_single_collisions" },
4727         { "tx_multi_collisions" },
4728         { "tx_deferred" },
4729         { "tx_excess_collisions" },
4730         { "tx_late_collisions" },
4731         { "tx_total_collisions" },
4732         { "rx_fragments" },
4733         { "rx_jabbers" },
4734         { "rx_undersize_packets" },
4735         { "rx_oversize_packets" },
4736         { "rx_64_byte_packets" },
4737         { "rx_65_to_127_byte_packets" },
4738         { "rx_128_to_255_byte_packets" },
4739         { "rx_256_to_511_byte_packets" },
4740         { "rx_512_to_1023_byte_packets" },
4741         { "rx_1024_to_1522_byte_packets" },
4742         { "rx_1523_to_9022_byte_packets" },
4743         { "tx_64_byte_packets" },
4744         { "tx_65_to_127_byte_packets" },
4745         { "tx_128_to_255_byte_packets" },
4746         { "tx_256_to_511_byte_packets" },
4747         { "tx_512_to_1023_byte_packets" },
4748         { "tx_1024_to_1522_byte_packets" },
4749         { "tx_1523_to_9022_byte_packets" },
4750         { "rx_xon_frames" },
4751         { "rx_xoff_frames" },
4752         { "tx_xon_frames" },
4753         { "tx_xoff_frames" },
4754         { "rx_mac_ctrl_frames" },
4755         { "rx_filtered_packets" },
4756         { "rx_discards" },
4757 };
4758
4759 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
4760
4761 static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
4762     STATS_OFFSET32(stat_IfHCInOctets_hi),
4763     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
4764     STATS_OFFSET32(stat_IfHCOutOctets_hi),
4765     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
4766     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
4767     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
4768     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
4769     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
4770     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
4771     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
4772     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
4773     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
4774     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
4775     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
4776     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
4777     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
4778     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
4779     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
4780     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
4781     STATS_OFFSET32(stat_EtherStatsCollisions),
4782     STATS_OFFSET32(stat_EtherStatsFragments),
4783     STATS_OFFSET32(stat_EtherStatsJabbers),
4784     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
4785     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
4786     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
4787     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
4788     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
4789     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
4790     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
4791     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
4792     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
4793     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
4794     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
4795     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
4796     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
4797     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
4798     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
4799     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
4800     STATS_OFFSET32(stat_XonPauseFramesReceived),
4801     STATS_OFFSET32(stat_XoffPauseFramesReceived),
4802     STATS_OFFSET32(stat_OutXonSent),
4803     STATS_OFFSET32(stat_OutXoffSent),
4804     STATS_OFFSET32(stat_MacControlFramesReceived),
4805     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
4806     STATS_OFFSET32(stat_IfInMBUFDiscards),
4807 };
4808
4809 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
4810  * skipped because of errata.
4811  */
4812 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
4813         8,0,8,8,8,8,8,8,8,8,
4814         4,0,4,4,4,4,4,4,4,4,
4815         4,4,4,4,4,4,4,4,4,4,
4816         4,4,4,4,4,4,4,4,4,4,
4817         4,4,4,4,4,
4818 };
4819
4820 #define BNX2_NUM_TESTS 6
4821
4822 static struct {
4823         char string[ETH_GSTRING_LEN];
4824 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
4825         { "register_test (offline)" },
4826         { "memory_test (offline)" },
4827         { "loopback_test (offline)" },
4828         { "nvram_test (online)" },
4829         { "interrupt_test (online)" },
4830         { "link_test (online)" },
4831 };
4832
4833 static int
4834 bnx2_self_test_count(struct net_device *dev)
4835 {
4836         return BNX2_NUM_TESTS;
4837 }
4838
4839 static void
4840 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
4841 {
4842         struct bnx2 *bp = dev->priv;
4843
4844         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
4845         if (etest->flags & ETH_TEST_FL_OFFLINE) {
4846                 bnx2_netif_stop(bp);
4847                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
4848                 bnx2_free_skbs(bp);
4849
4850                 if (bnx2_test_registers(bp) != 0) {
4851                         buf[0] = 1;
4852                         etest->flags |= ETH_TEST_FL_FAILED;
4853                 }
4854                 if (bnx2_test_memory(bp) != 0) {
4855                         buf[1] = 1;
4856                         etest->flags |= ETH_TEST_FL_FAILED;
4857                 }
4858                 if (bnx2_test_loopback(bp) != 0) {
4859                         buf[2] = 1;
4860                         etest->flags |= ETH_TEST_FL_FAILED;
4861                 }
4862
4863                 if (!netif_running(bp->dev)) {
4864                         bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
4865                 }
4866                 else {
4867                         bnx2_init_nic(bp);
4868                         bnx2_netif_start(bp);
4869                 }
4870
4871                 /* wait for link up */
4872                 msleep_interruptible(3000);
4873                 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
4874                         msleep_interruptible(4000);
4875         }
4876
4877         if (bnx2_test_nvram(bp) != 0) {
4878                 buf[3] = 1;
4879                 etest->flags |= ETH_TEST_FL_FAILED;
4880         }
4881         if (bnx2_test_intr(bp) != 0) {
4882                 buf[4] = 1;
4883                 etest->flags |= ETH_TEST_FL_FAILED;
4884         }
4885
4886         if (bnx2_test_link(bp) != 0) {
4887                 buf[5] = 1;
4888                 etest->flags |= ETH_TEST_FL_FAILED;
4889
4890         }
4891 }
4892
4893 static void
4894 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
4895 {
4896         switch (stringset) {
4897         case ETH_SS_STATS:
4898                 memcpy(buf, bnx2_stats_str_arr,
4899                         sizeof(bnx2_stats_str_arr));
4900                 break;
4901         case ETH_SS_TEST:
4902                 memcpy(buf, bnx2_tests_str_arr,
4903                         sizeof(bnx2_tests_str_arr));
4904                 break;
4905         }
4906 }
4907
4908 static int
4909 bnx2_get_stats_count(struct net_device *dev)
4910 {
4911         return BNX2_NUM_STATS;
4912 }
4913
4914 static void
4915 bnx2_get_ethtool_stats(struct net_device *dev,
4916                 struct ethtool_stats *stats, u64 *buf)
4917 {
4918         struct bnx2 *bp = dev->priv;
4919         int i;
4920         u32 *hw_stats = (u32 *) bp->stats_blk;
4921         u8 *stats_len_arr = NULL;
4922
4923         if (hw_stats == NULL) {
4924                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
4925                 return;
4926         }
4927
4928         if (CHIP_NUM(bp) == CHIP_NUM_5706)
4929                 stats_len_arr = bnx2_5706_stats_len_arr;
4930
4931         for (i = 0; i < BNX2_NUM_STATS; i++) {
4932                 if (stats_len_arr[i] == 0) {
4933                         /* skip this counter */
4934                         buf[i] = 0;
4935                         continue;
4936                 }
4937                 if (stats_len_arr[i] == 4) {
4938                         /* 4-byte counter */
4939                         buf[i] = (u64)
4940                                 *(hw_stats + bnx2_stats_offset_arr[i]);
4941                         continue;
4942                 }
4943                 /* 8-byte counter */
4944                 buf[i] = (((u64) *(hw_stats +
4945                                         bnx2_stats_offset_arr[i])) << 32) +
4946                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
4947         }
4948 }
4949
4950 static int
4951 bnx2_phys_id(struct net_device *dev, u32 data)
4952 {
4953         struct bnx2 *bp = dev->priv;
4954         int i;
4955         u32 save;
4956
4957         if (data == 0)
4958                 data = 2;
4959
4960         save = REG_RD(bp, BNX2_MISC_CFG);
4961         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
4962
4963         for (i = 0; i < (data * 2); i++) {
4964                 if ((i % 2) == 0) {
4965                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
4966                 }
4967                 else {
4968                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
4969                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
4970                                 BNX2_EMAC_LED_100MB_OVERRIDE |
4971                                 BNX2_EMAC_LED_10MB_OVERRIDE |
4972                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
4973                                 BNX2_EMAC_LED_TRAFFIC);
4974                 }
4975                 msleep_interruptible(500);
4976                 if (signal_pending(current))
4977                         break;
4978         }
4979         REG_WR(bp, BNX2_EMAC_LED, 0);
4980         REG_WR(bp, BNX2_MISC_CFG, save);
4981         return 0;
4982 }
4983
4984 static struct ethtool_ops bnx2_ethtool_ops = {
4985         .get_settings           = bnx2_get_settings,
4986         .set_settings           = bnx2_set_settings,
4987         .get_drvinfo            = bnx2_get_drvinfo,
4988         .get_wol                = bnx2_get_wol,
4989         .set_wol                = bnx2_set_wol,
4990         .nway_reset             = bnx2_nway_reset,
4991         .get_link               = ethtool_op_get_link,
4992         .get_eeprom_len         = bnx2_get_eeprom_len,
4993         .get_eeprom             = bnx2_get_eeprom,
4994         .set_eeprom             = bnx2_set_eeprom,
4995         .get_coalesce           = bnx2_get_coalesce,
4996         .set_coalesce           = bnx2_set_coalesce,
4997         .get_ringparam          = bnx2_get_ringparam,
4998         .set_ringparam          = bnx2_set_ringparam,
4999         .get_pauseparam         = bnx2_get_pauseparam,
5000         .set_pauseparam         = bnx2_set_pauseparam,
5001         .get_rx_csum            = bnx2_get_rx_csum,
5002         .set_rx_csum            = bnx2_set_rx_csum,
5003         .get_tx_csum            = ethtool_op_get_tx_csum,
5004         .set_tx_csum            = ethtool_op_set_tx_csum,
5005         .get_sg                 = ethtool_op_get_sg,
5006         .set_sg                 = ethtool_op_set_sg,
5007 #ifdef BCM_TSO
5008         .get_tso                = ethtool_op_get_tso,
5009         .set_tso                = ethtool_op_set_tso,
5010 #endif
5011         .self_test_count        = bnx2_self_test_count,
5012         .self_test              = bnx2_self_test,
5013         .get_strings            = bnx2_get_strings,
5014         .phys_id                = bnx2_phys_id,
5015         .get_stats_count        = bnx2_get_stats_count,
5016         .get_ethtool_stats      = bnx2_get_ethtool_stats,
5017 };
5018
5019 /* Called with rtnl_lock */
5020 static int
5021 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5022 {
5023         struct mii_ioctl_data *data = if_mii(ifr);
5024         struct bnx2 *bp = dev->priv;
5025         int err;
5026
5027         switch(cmd) {
5028         case SIOCGMIIPHY:
5029                 data->phy_id = bp->phy_addr;
5030
5031                 /* fallthru */
5032         case SIOCGMIIREG: {
5033                 u32 mii_regval;
5034
5035                 spin_lock_bh(&bp->phy_lock);
5036                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5037                 spin_unlock_bh(&bp->phy_lock);
5038
5039                 data->val_out = mii_regval;
5040
5041                 return err;
5042         }
5043
5044         case SIOCSMIIREG:
5045                 if (!capable(CAP_NET_ADMIN))
5046                         return -EPERM;
5047
5048                 spin_lock_bh(&bp->phy_lock);
5049                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5050                 spin_unlock_bh(&bp->phy_lock);
5051
5052                 return err;
5053
5054         default:
5055                 /* do nothing */
5056                 break;
5057         }
5058         return -EOPNOTSUPP;
5059 }
5060
5061 /* Called with rtnl_lock */
5062 static int
5063 bnx2_change_mac_addr(struct net_device *dev, void *p)
5064 {
5065         struct sockaddr *addr = p;
5066         struct bnx2 *bp = dev->priv;
5067
5068         if (!is_valid_ether_addr(addr->sa_data))
5069                 return -EINVAL;
5070
5071         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5072         if (netif_running(dev))
5073                 bnx2_set_mac_addr(bp);
5074
5075         return 0;
5076 }
5077
5078 /* Called with rtnl_lock */
5079 static int
5080 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5081 {
5082         struct bnx2 *bp = dev->priv;
5083
5084         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5085                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5086                 return -EINVAL;
5087
5088         dev->mtu = new_mtu;
5089         if (netif_running(dev)) {
5090                 bnx2_netif_stop(bp);
5091
5092                 bnx2_init_nic(bp);
5093
5094                 bnx2_netif_start(bp);
5095         }
5096         return 0;
5097 }
5098
5099 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5100 static void
5101 poll_bnx2(struct net_device *dev)
5102 {
5103         struct bnx2 *bp = dev->priv;
5104
5105         disable_irq(bp->pdev->irq);
5106         bnx2_interrupt(bp->pdev->irq, dev, NULL);
5107         enable_irq(bp->pdev->irq);
5108 }
5109 #endif
5110
5111 static int __devinit
5112 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5113 {
5114         struct bnx2 *bp;
5115         unsigned long mem_len;
5116         int rc;
5117         u32 reg;
5118
5119         SET_MODULE_OWNER(dev);
5120         SET_NETDEV_DEV(dev, &pdev->dev);
5121         bp = dev->priv;
5122
5123         bp->flags = 0;
5124         bp->phy_flags = 0;
5125
5126         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5127         rc = pci_enable_device(pdev);
5128         if (rc) {
5129                 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5130                 goto err_out;
5131         }
5132
5133         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5134                 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5135                        "aborting.\n");
5136                 rc = -ENODEV;
5137                 goto err_out_disable;
5138         }
5139
5140         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5141         if (rc) {
5142                 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5143                 goto err_out_disable;
5144         }
5145
5146         pci_set_master(pdev);
5147
5148         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5149         if (bp->pm_cap == 0) {
5150                 printk(KERN_ERR PFX "Cannot find power management capability, "
5151                                "aborting.\n");
5152                 rc = -EIO;
5153                 goto err_out_release;
5154         }
5155
5156         bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5157         if (bp->pcix_cap == 0) {
5158                 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5159                 rc = -EIO;
5160                 goto err_out_release;
5161         }
5162
5163         if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5164                 bp->flags |= USING_DAC_FLAG;
5165                 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5166                         printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5167                                "failed, aborting.\n");
5168                         rc = -EIO;
5169                         goto err_out_release;
5170                 }
5171         }
5172         else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5173                 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5174                 rc = -EIO;
5175                 goto err_out_release;
5176         }
5177
5178         bp->dev = dev;
5179         bp->pdev = pdev;
5180
5181         spin_lock_init(&bp->phy_lock);
5182         spin_lock_init(&bp->tx_lock);
5183         INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5184
5185         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5186         mem_len = MB_GET_CID_ADDR(17);
5187         dev->mem_end = dev->mem_start + mem_len;
5188         dev->irq = pdev->irq;
5189
5190         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5191
5192         if (!bp->regview) {
5193                 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5194                 rc = -ENOMEM;
5195                 goto err_out_release;
5196         }
5197
5198         /* Configure byte swap and enable write to the reg_window registers.
5199          * Rely on CPU to do target byte swapping on big endian systems
5200          * The chip's target access swapping will not swap all accesses
5201          */
5202         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5203                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5204                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5205
5206         bnx2_set_power_state(bp, PCI_D0);
5207
5208         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5209
5210         bp->phy_addr = 1;
5211
5212         /* Get bus information. */
5213         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5214         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5215                 u32 clkreg;
5216
5217                 bp->flags |= PCIX_FLAG;
5218
5219                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5220
5221                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5222                 switch (clkreg) {
5223                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5224                         bp->bus_speed_mhz = 133;
5225                         break;
5226
5227                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5228                         bp->bus_speed_mhz = 100;
5229                         break;
5230
5231                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5232                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5233                         bp->bus_speed_mhz = 66;
5234                         break;
5235
5236                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5237                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5238                         bp->bus_speed_mhz = 50;
5239                         break;
5240
5241                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5242                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5243                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5244                         bp->bus_speed_mhz = 33;
5245                         break;
5246                 }
5247         }
5248         else {
5249                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5250                         bp->bus_speed_mhz = 66;
5251                 else
5252                         bp->bus_speed_mhz = 33;
5253         }
5254
5255         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5256                 bp->flags |= PCI_32BIT_FLAG;
5257
5258         /* 5706A0 may falsely detect SERR and PERR. */
5259         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5260                 reg = REG_RD(bp, PCI_COMMAND);
5261                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5262                 REG_WR(bp, PCI_COMMAND, reg);
5263         }
5264         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5265                 !(bp->flags & PCIX_FLAG)) {
5266
5267                 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5268                        "aborting.\n");
5269                 goto err_out_unmap;
5270         }
5271
5272         bnx2_init_nvram(bp);
5273
5274         /* Get the permanent MAC address.  First we need to make sure the
5275          * firmware is actually running.
5276          */
5277         reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);
5278
5279         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5280             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5281                 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5282                 rc = -ENODEV;
5283                 goto err_out_unmap;
5284         }
5285
5286         bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5287                                 BNX2_DEV_INFO_BC_REV);
5288
5289         reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);
5290         bp->mac_addr[0] = (u8) (reg >> 8);
5291         bp->mac_addr[1] = (u8) reg;
5292
5293         reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);
5294         bp->mac_addr[2] = (u8) (reg >> 24);
5295         bp->mac_addr[3] = (u8) (reg >> 16);
5296         bp->mac_addr[4] = (u8) (reg >> 8);
5297         bp->mac_addr[5] = (u8) reg;
5298
5299         bp->tx_ring_size = MAX_TX_DESC_CNT;
5300         bp->rx_ring_size = 100;
5301
5302         bp->rx_csum = 1;
5303
5304         bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5305
5306         bp->tx_quick_cons_trip_int = 20;
5307         bp->tx_quick_cons_trip = 20;
5308         bp->tx_ticks_int = 80;
5309         bp->tx_ticks = 80;
5310
5311         bp->rx_quick_cons_trip_int = 6;
5312         bp->rx_quick_cons_trip = 6;
5313         bp->rx_ticks_int = 18;
5314         bp->rx_ticks = 18;
5315
5316         bp->stats_ticks = 1000000 & 0xffff00;
5317
5318         bp->timer_interval =  HZ;
5319         bp->current_interval =  HZ;
5320
5321         /* Disable WOL support if we are running on a SERDES chip. */
5322         if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5323                 bp->phy_flags |= PHY_SERDES_FLAG;
5324                 bp->flags |= NO_WOL_FLAG;
5325         }
5326
5327         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5328                 bp->tx_quick_cons_trip_int =
5329                         bp->tx_quick_cons_trip;
5330                 bp->tx_ticks_int = bp->tx_ticks;
5331                 bp->rx_quick_cons_trip_int =
5332                         bp->rx_quick_cons_trip;
5333                 bp->rx_ticks_int = bp->rx_ticks;
5334                 bp->comp_prod_trip_int = bp->comp_prod_trip;
5335                 bp->com_ticks_int = bp->com_ticks;
5336                 bp->cmd_ticks_int = bp->cmd_ticks;
5337         }
5338
5339         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5340         bp->req_line_speed = 0;
5341         if (bp->phy_flags & PHY_SERDES_FLAG) {
5342                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5343
5344                 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5345                                  BNX2_PORT_HW_CFG_CONFIG);
5346                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5347                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5348                         bp->autoneg = 0;
5349                         bp->req_line_speed = bp->line_speed = SPEED_1000;
5350                         bp->req_duplex = DUPLEX_FULL;
5351                 }
5352         }
5353         else {
5354                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5355         }
5356
5357         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5358
5359         init_timer(&bp->timer);
5360         bp->timer.expires = RUN_AT(bp->timer_interval);
5361         bp->timer.data = (unsigned long) bp;
5362         bp->timer.function = bnx2_timer;
5363
5364         return 0;
5365
5366 err_out_unmap:
5367         if (bp->regview) {
5368                 iounmap(bp->regview);
5369                 bp->regview = NULL;
5370         }
5371
5372 err_out_release:
5373         pci_release_regions(pdev);
5374
5375 err_out_disable:
5376         pci_disable_device(pdev);
5377         pci_set_drvdata(pdev, NULL);
5378
5379 err_out:
5380         return rc;
5381 }
5382
5383 static int __devinit
5384 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5385 {
5386         static int version_printed = 0;
5387         struct net_device *dev = NULL;
5388         struct bnx2 *bp;
5389         int rc, i;
5390
5391         if (version_printed++ == 0)
5392                 printk(KERN_INFO "%s", version);
5393
5394         /* dev zeroed in init_etherdev */
5395         dev = alloc_etherdev(sizeof(*bp));
5396
5397         if (!dev)
5398                 return -ENOMEM;
5399
5400         rc = bnx2_init_board(pdev, dev);
5401         if (rc < 0) {
5402                 free_netdev(dev);
5403                 return rc;
5404         }
5405
5406         dev->open = bnx2_open;
5407         dev->hard_start_xmit = bnx2_start_xmit;
5408         dev->stop = bnx2_close;
5409         dev->get_stats = bnx2_get_stats;
5410         dev->set_multicast_list = bnx2_set_rx_mode;
5411         dev->do_ioctl = bnx2_ioctl;
5412         dev->set_mac_address = bnx2_change_mac_addr;
5413         dev->change_mtu = bnx2_change_mtu;
5414         dev->tx_timeout = bnx2_tx_timeout;
5415         dev->watchdog_timeo = TX_TIMEOUT;
5416 #ifdef BCM_VLAN
5417         dev->vlan_rx_register = bnx2_vlan_rx_register;
5418         dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5419 #endif
5420         dev->poll = bnx2_poll;
5421         dev->ethtool_ops = &bnx2_ethtool_ops;
5422         dev->weight = 64;
5423
5424         bp = dev->priv;
5425
5426 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5427         dev->poll_controller = poll_bnx2;
5428 #endif
5429
5430         if ((rc = register_netdev(dev))) {
5431                 printk(KERN_ERR PFX "Cannot register net device\n");
5432                 if (bp->regview)
5433                         iounmap(bp->regview);
5434                 pci_release_regions(pdev);
5435                 pci_disable_device(pdev);
5436                 pci_set_drvdata(pdev, NULL);
5437                 free_netdev(dev);
5438                 return rc;
5439         }
5440
5441         pci_set_drvdata(pdev, dev);
5442
5443         memcpy(dev->dev_addr, bp->mac_addr, 6);
5444         bp->name = board_info[ent->driver_data].name,
5445         printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5446                 "IRQ %d, ",
5447                 dev->name,
5448                 bp->name,
5449                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5450                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5451                 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5452                 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5453                 bp->bus_speed_mhz,
5454                 dev->base_addr,
5455                 bp->pdev->irq);
5456
5457         printk("node addr ");
5458         for (i = 0; i < 6; i++)
5459                 printk("%2.2x", dev->dev_addr[i]);
5460         printk("\n");
5461
5462         dev->features |= NETIF_F_SG;
5463         if (bp->flags & USING_DAC_FLAG)
5464                 dev->features |= NETIF_F_HIGHDMA;
5465         dev->features |= NETIF_F_IP_CSUM;
5466 #ifdef BCM_VLAN
5467         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5468 #endif
5469 #ifdef BCM_TSO
5470         dev->features |= NETIF_F_TSO;
5471 #endif
5472
5473         netif_carrier_off(bp->dev);
5474
5475         return 0;
5476 }
5477
5478 static void __devexit
5479 bnx2_remove_one(struct pci_dev *pdev)
5480 {
5481         struct net_device *dev = pci_get_drvdata(pdev);
5482         struct bnx2 *bp = dev->priv;
5483
5484         flush_scheduled_work();
5485
5486         unregister_netdev(dev);
5487
5488         if (bp->regview)
5489                 iounmap(bp->regview);
5490
5491         free_netdev(dev);
5492         pci_release_regions(pdev);
5493         pci_disable_device(pdev);
5494         pci_set_drvdata(pdev, NULL);
5495 }
5496
5497 static int
5498 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5499 {
5500         struct net_device *dev = pci_get_drvdata(pdev);
5501         struct bnx2 *bp = dev->priv;
5502         u32 reset_code;
5503
5504         if (!netif_running(dev))
5505                 return 0;
5506
5507         bnx2_netif_stop(bp);
5508         netif_device_detach(dev);
5509         del_timer_sync(&bp->timer);
5510         if (bp->wol)
5511                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5512         else
5513                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5514         bnx2_reset_chip(bp, reset_code);
5515         bnx2_free_skbs(bp);
5516         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
5517         return 0;
5518 }
5519
5520 static int
5521 bnx2_resume(struct pci_dev *pdev)
5522 {
5523         struct net_device *dev = pci_get_drvdata(pdev);
5524         struct bnx2 *bp = dev->priv;
5525
5526         if (!netif_running(dev))
5527                 return 0;
5528
5529         bnx2_set_power_state(bp, PCI_D0);
5530         netif_device_attach(dev);
5531         bnx2_init_nic(bp);
5532         bnx2_netif_start(bp);
5533         return 0;
5534 }
5535
5536 static struct pci_driver bnx2_pci_driver = {
5537         .name           = DRV_MODULE_NAME,
5538         .id_table       = bnx2_pci_tbl,
5539         .probe          = bnx2_init_one,
5540         .remove         = __devexit_p(bnx2_remove_one),
5541         .suspend        = bnx2_suspend,
5542         .resume         = bnx2_resume,
5543 };
5544
5545 static int __init bnx2_init(void)
5546 {
5547         return pci_module_init(&bnx2_pci_driver);
5548 }
5549
5550 static void __exit bnx2_cleanup(void)
5551 {
5552         pci_unregister_driver(&bnx2_pci_driver);
5553 }
5554
5555 module_init(bnx2_init);
5556 module_exit(bnx2_cleanup);
5557
5558
5559