git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/string.h>
  39 #include <linux/slab.h>
  40
  41 #include <asm/io.h>
  42
  43 #include <rdma/ib_verbs.h>
  44 #include <rdma/ib_cache.h>
  45 #include <rdma/ib_pack.h>
  46
  47 #include "mthca_dev.h"
  48 #include "mthca_cmd.h"
  49 #include "mthca_memfree.h"
  50 #include "mthca_wqe.h"
  51
  52 enum {
  53         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  54         MTHCA_ACK_REQ_FREQ       = 10,
  55         MTHCA_FLIGHT_LIMIT       = 9,
  56         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  57         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  58         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  59 };
  60
  61 enum {
  62         MTHCA_QP_STATE_RST  = 0,
  63         MTHCA_QP_STATE_INIT = 1,
  64         MTHCA_QP_STATE_RTR  = 2,
  65         MTHCA_QP_STATE_RTS  = 3,
  66         MTHCA_QP_STATE_SQE  = 4,
  67         MTHCA_QP_STATE_SQD  = 5,
  68         MTHCA_QP_STATE_ERR  = 6,
  69         MTHCA_QP_STATE_DRAINING = 7
  70 };
  71
  72 enum {
  73         MTHCA_QP_ST_RC  = 0x0,
  74         MTHCA_QP_ST_UC  = 0x1,
  75         MTHCA_QP_ST_RD  = 0x2,
  76         MTHCA_QP_ST_UD  = 0x3,
  77         MTHCA_QP_ST_MLX = 0x7
  78 };
  79
  80 enum {
  81         MTHCA_QP_PM_MIGRATED = 0x3,
  82         MTHCA_QP_PM_ARMED    = 0x0,
  83         MTHCA_QP_PM_REARM    = 0x1
  84 };
  85
  86 enum {
  87         /* qp_context flags */
  88         MTHCA_QP_BIT_DE  = 1 <<  8,
  89         /* params1 */
  90         MTHCA_QP_BIT_SRE = 1 << 15,
  91         MTHCA_QP_BIT_SWE = 1 << 14,
  92         MTHCA_QP_BIT_SAE = 1 << 13,
  93         MTHCA_QP_BIT_SIC = 1 <<  4,
  94         MTHCA_QP_BIT_SSC = 1 <<  3,
  95         /* params2 */
  96         MTHCA_QP_BIT_RRE = 1 << 15,
  97         MTHCA_QP_BIT_RWE = 1 << 14,
  98         MTHCA_QP_BIT_RAE = 1 << 13,
  99         MTHCA_QP_BIT_RIC = 1 <<  4,
 100         MTHCA_QP_BIT_RSC = 1 <<  3
 101 };
 102
 103 enum {
 104         MTHCA_SEND_DOORBELL_FENCE = 1 << 5
 105 };
 106
 107 struct mthca_qp_path {
 108         __be32 port_pkey;
 109         u8     rnr_retry;
 110         u8     g_mylmc;
 111         __be16 rlid;
 112         u8     ackto;
 113         u8     mgid_index;
 114         u8     static_rate;
 115         u8     hop_limit;
 116         __be32 sl_tclass_flowlabel;
 117         u8     rgid[16];
 118 } __attribute__((packed));
 119
 120 struct mthca_qp_context {
 121         __be32 flags;
 122         __be32 tavor_sched_queue; /* Reserved on Arbel */
 123         u8     mtu_msgmax;
 124         u8     rq_size_stride;  /* Reserved on Tavor */
 125         u8     sq_size_stride;  /* Reserved on Tavor */
 126         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 127         __be32 usr_page;
 128         __be32 local_qpn;
 129         __be32 remote_qpn;
 130         u32    reserved1[2];
 131         struct mthca_qp_path pri_path;
 132         struct mthca_qp_path alt_path;
 133         __be32 rdd;
 134         __be32 pd;
 135         __be32 wqe_base;
 136         __be32 wqe_lkey;
 137         __be32 params1;
 138         __be32 reserved2;
 139         __be32 next_send_psn;
 140         __be32 cqn_snd;
 141         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 142         __be32 snd_db_index;    /* (debugging only entries) */
 143         __be32 last_acked_psn;
 144         __be32 ssn;
 145         __be32 params2;
 146         __be32 rnr_nextrecvpsn;
 147         __be32 ra_buff_indx;
 148         __be32 cqn_rcv;
 149         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 150         __be32 rcv_db_index;    /* (debugging only entries) */
 151         __be32 qkey;
 152         __be32 srqn;
 153         __be32 rmsn;
 154         __be16 rq_wqe_counter;  /* reserved on Tavor */
 155         __be16 sq_wqe_counter;  /* reserved on Tavor */
 156         u32    reserved3[18];
 157 } __attribute__((packed));
 158
 159 struct mthca_qp_param {
 160         __be32 opt_param_mask;
 161         u32    reserved1;
 162         struct mthca_qp_context context;
 163         u32    reserved2[62];
 164 } __attribute__((packed));
 165
 166 enum {
 167         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 168         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 169         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 170         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 171         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 172         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 173         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 174         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 175         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 176         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 177         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 178         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 179         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 180         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 181         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 182         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 183         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 184 };
 185
 186 static const u8 mthca_opcode[] = {
 187         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 188         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 189         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 190         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 191         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 192         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 193         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 194 };
 195
 196 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 197 {
 198         return qp->qpn >= dev->qp_table.sqp_start &&
 199                 qp->qpn <= dev->qp_table.sqp_start + 3;
 200 }
 201
 202 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 203 {
 204         return qp->qpn >= dev->qp_table.sqp_start &&
 205                 qp->qpn <= dev->qp_table.sqp_start + 1;
 206 }
 207
 208 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 209 {
 210         if (qp->is_direct)
 211                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 212         else
 213                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 214                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 215 }
 216
 217 static void *get_send_wqe(struct mthca_qp *qp, int n)
 218 {
 219         if (qp->is_direct)
 220                 return qp->queue.direct.buf + qp->send_wqe_offset +
 221                         (n << qp->sq.wqe_shift);
 222         else
 223                 return qp->queue.page_list[(qp->send_wqe_offset +
 224                                             (n << qp->sq.wqe_shift)) >>
 225                                            PAGE_SHIFT].buf +
 226                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 227                          (PAGE_SIZE - 1));
 228 }
 229
 230 static void mthca_wq_reset(struct mthca_wq *wq)
 231 {
 232         wq->next_ind  = 0;
 233         wq->last_comp = wq->max - 1;
 234         wq->head      = 0;
 235         wq->tail      = 0;
 236 }
 237
 238 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 239                     enum ib_event_type event_type)
 240 {
 241         struct mthca_qp *qp;
 242         struct ib_event event;
 243
 244         spin_lock(&dev->qp_table.lock);
 245         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 246         if (qp)
 247                 ++qp->refcount;
 248         spin_unlock(&dev->qp_table.lock);
 249
 250         if (!qp) {
 251                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 252                 return;
 253         }
 254
 255         if (event_type == IB_EVENT_PATH_MIG)
 256                 qp->port = qp->alt_port;
 257
 258         event.device      = &dev->ib_dev;
 259         event.event       = event_type;
 260         event.element.qp  = &qp->ibqp;
 261         if (qp->ibqp.event_handler)
 262                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 263
 264         spin_lock(&dev->qp_table.lock);
 265         if (!--qp->refcount)
 266                 wake_up(&qp->wait);
 267         spin_unlock(&dev->qp_table.lock);
 268 }
 269
 270 static int to_mthca_state(enum ib_qp_state ib_state)
 271 {
 272         switch (ib_state) {
 273         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 274         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 275         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 276         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 277         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 278         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 279         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 280         default:                return -1;
 281         }
 282 }
 283
 284 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 285
 286 static int to_mthca_st(int transport)
 287 {
 288         switch (transport) {
 289         case RC:  return MTHCA_QP_ST_RC;
 290         case UC:  return MTHCA_QP_ST_UC;
 291         case UD:  return MTHCA_QP_ST_UD;
 292         case RD:  return MTHCA_QP_ST_RD;
 293         case MLX: return MTHCA_QP_ST_MLX;
 294         default:  return -1;
 295         }
 296 }
 297
 298 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 299                         int attr_mask)
 300 {
 301         if (attr_mask & IB_QP_PKEY_INDEX)
 302                 sqp->pkey_index = attr->pkey_index;
 303         if (attr_mask & IB_QP_QKEY)
 304                 sqp->qkey = attr->qkey;
 305         if (attr_mask & IB_QP_SQ_PSN)
 306                 sqp->send_psn = attr->sq_psn;
 307 }
 308
 309 static void init_port(struct mthca_dev *dev, int port)
 310 {
 311         int err;
 312         u8 status;
 313         struct mthca_init_ib_param param;
 314
 315         memset(&param, 0, sizeof param);
 316
 317         param.port_width = dev->limits.port_width_cap;
 318         param.vl_cap     = dev->limits.vl_cap;
 319         param.mtu_cap    = dev->limits.mtu_cap;
 320         param.gid_cap    = dev->limits.gid_table_len;
 321         param.pkey_cap   = dev->limits.pkey_table_len;
 322
 323         err = mthca_INIT_IB(dev, &param, port, &status);
 324         if (err)
 325                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 326         if (status)
 327                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 328 }
 329
 330 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
 331                                   int attr_mask)
 332 {
 333         u8 dest_rd_atomic;
 334         u32 access_flags;
 335         u32 hw_access_flags = 0;
 336
 337         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 338                 dest_rd_atomic = attr->max_dest_rd_atomic;
 339         else
 340                 dest_rd_atomic = qp->resp_depth;
 341
 342         if (attr_mask & IB_QP_ACCESS_FLAGS)
 343                 access_flags = attr->qp_access_flags;
 344         else
 345                 access_flags = qp->atomic_rd_en;
 346
 347         if (!dest_rd_atomic)
 348                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 349
 350         if (access_flags & IB_ACCESS_REMOTE_READ)
 351                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 352         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 353                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 354         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 355                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 356
 357         return cpu_to_be32(hw_access_flags);
 358 }
 359
 360 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
 361 {
 362         switch (mthca_state) {
 363         case MTHCA_QP_STATE_RST:      return IB_QPS_RESET;
 364         case MTHCA_QP_STATE_INIT:     return IB_QPS_INIT;
 365         case MTHCA_QP_STATE_RTR:      return IB_QPS_RTR;
 366         case MTHCA_QP_STATE_RTS:      return IB_QPS_RTS;
 367         case MTHCA_QP_STATE_DRAINING:
 368         case MTHCA_QP_STATE_SQD:      return IB_QPS_SQD;
 369         case MTHCA_QP_STATE_SQE:      return IB_QPS_SQE;
 370         case MTHCA_QP_STATE_ERR:      return IB_QPS_ERR;
 371         default:                      return -1;
 372         }
 373 }
 374
 375 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
 376 {
 377         switch (mthca_mig_state) {
 378         case 0:  return IB_MIG_ARMED;
 379         case 1:  return IB_MIG_REARM;
 380         case 3:  return IB_MIG_MIGRATED;
 381         default: return -1;
 382         }
 383 }
 384
 385 static int to_ib_qp_access_flags(int mthca_flags)
 386 {
 387         int ib_flags = 0;
 388
 389         if (mthca_flags & MTHCA_QP_BIT_RRE)
 390                 ib_flags |= IB_ACCESS_REMOTE_READ;
 391         if (mthca_flags & MTHCA_QP_BIT_RWE)
 392                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
 393         if (mthca_flags & MTHCA_QP_BIT_RAE)
 394                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
 395
 396         return ib_flags;
 397 }
 398
 399 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
 400                                 struct mthca_qp_path *path)
 401 {
 402         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
 403         ib_ah_attr->port_num      = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
 404
 405         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
 406                 return;
 407
 408         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
 409         ib_ah_attr->sl            = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
 410         ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
 411         ib_ah_attr->static_rate   = mthca_rate_to_ib(dev,
 412                                                      path->static_rate & 0xf,
 413                                                      ib_ah_attr->port_num);
 414         ib_ah_attr->ah_flags      = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
 415         if (ib_ah_attr->ah_flags) {
 416                 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
 417                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
 418                 ib_ah_attr->grh.traffic_class =
 419                         (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
 420                 ib_ah_attr->grh.flow_label =
 421                         be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
 422                 memcpy(ib_ah_attr->grh.dgid.raw,
 423                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
 424         }
 425 }
 426
 427 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
 428                    struct ib_qp_init_attr *qp_init_attr)
 429 {
 430         struct mthca_dev *dev = to_mdev(ibqp->device);
 431         struct mthca_qp *qp = to_mqp(ibqp);
 432         int err = 0;
 433         struct mthca_mailbox *mailbox = NULL;
 434         struct mthca_qp_param *qp_param;
 435         struct mthca_qp_context *context;
 436         int mthca_state;
 437         u8 status;
 438
 439         if (qp->state == IB_QPS_RESET) {
 440                 qp_attr->qp_state = IB_QPS_RESET;
 441                 goto done;
 442         }
 443
 444         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 445         if (IS_ERR(mailbox))
 446                 return PTR_ERR(mailbox);
 447
 448         err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
 449         if (err)
 450                 goto out;
 451         if (status) {
 452                 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
 453                 err = -EINVAL;
 454                 goto out;
 455         }
 456
 457         qp_param    = mailbox->buf;
 458         context     = &qp_param->context;
 459         mthca_state = be32_to_cpu(context->flags) >> 28;
 460
 461         qp_attr->qp_state            = to_ib_qp_state(mthca_state);
 462         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
 463         qp_attr->path_mig_state      =
 464                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
 465         qp_attr->qkey                = be32_to_cpu(context->qkey);
 466         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
 467         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
 468         qp_attr->dest_qp_num         = be32_to_cpu(context->remote_qpn) & 0xffffff;
 469         qp_attr->qp_access_flags     =
 470                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
 471
 472         if (qp->transport == RC || qp->transport == UC) {
 473                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
 474                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
 475                 qp_attr->alt_pkey_index =
 476                         be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
 477                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
 478         }
 479
 480         qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
 481         qp_attr->port_num   =
 482                 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
 483
 484         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
 485         qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
 486
 487         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
 488
 489         qp_attr->max_dest_rd_atomic =
 490                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
 491         qp_attr->min_rnr_timer      =
 492                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
 493         qp_attr->timeout            = context->pri_path.ackto >> 3;
 494         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
 495         qp_attr->rnr_retry          = context->pri_path.rnr_retry >> 5;
 496         qp_attr->alt_timeout        = context->alt_path.ackto >> 3;
 497
 498 done:
 499         qp_attr->cur_qp_state        = qp_attr->qp_state;
 500         qp_attr->cap.max_send_wr     = qp->sq.max;
 501         qp_attr->cap.max_recv_wr     = qp->rq.max;
 502         qp_attr->cap.max_send_sge    = qp->sq.max_gs;
 503         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
 504         qp_attr->cap.max_inline_data = qp->max_inline_data;
 505
 506         qp_init_attr->cap            = qp_attr->cap;
 507
 508 out:
 509         mthca_free_mailbox(dev, mailbox);
 510         return err;
 511 }
 512
 513 static int mthca_path_set(struct mthca_dev *dev, struct ib_ah_attr *ah,
 514                           struct mthca_qp_path *path, u8 port)
 515 {
 516         path->g_mylmc     = ah->src_path_bits & 0x7f;
 517         path->rlid        = cpu_to_be16(ah->dlid);
 518         path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
 519
 520         if (ah->ah_flags & IB_AH_GRH) {
 521                 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
 522                         mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
 523                                   ah->grh.sgid_index, dev->limits.gid_table_len-1);
 524                         return -1;
 525                 }
 526
 527                 path->g_mylmc   |= 1 << 7;
 528                 path->mgid_index = ah->grh.sgid_index;
 529                 path->hop_limit  = ah->grh.hop_limit;
 530                 path->sl_tclass_flowlabel =
 531                         cpu_to_be32((ah->sl << 28)                |
 532                                     (ah->grh.traffic_class << 20) |
 533                                     (ah->grh.flow_label));
 534                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 535         } else
 536                 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
 537
 538         return 0;
 539 }
 540
 541 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
 542                     struct ib_udata *udata)
 543 {
 544         struct mthca_dev *dev = to_mdev(ibqp->device);
 545         struct mthca_qp *qp = to_mqp(ibqp);
 546         enum ib_qp_state cur_state, new_state;
 547         struct mthca_mailbox *mailbox;
 548         struct mthca_qp_param *qp_param;
 549         struct mthca_qp_context *qp_context;
 550         u32 sqd_event = 0;
 551         u8 status;
 552         int err = -EINVAL;
 553
 554         mutex_lock(&qp->mutex);
 555
 556         if (attr_mask & IB_QP_CUR_STATE) {
 557                 cur_state = attr->cur_qp_state;
 558         } else {
 559                 spin_lock_irq(&qp->sq.lock);
 560                 spin_lock(&qp->rq.lock);
 561                 cur_state = qp->state;
 562                 spin_unlock(&qp->rq.lock);
 563                 spin_unlock_irq(&qp->sq.lock);
 564         }
 565
 566         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
 567
 568         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
 569                 mthca_dbg(dev, "Bad QP transition (transport %d) "
 570                           "%d->%d with attr 0x%08x\n",
 571                           qp->transport, cur_state, new_state,
 572                           attr_mask);
 573                 goto out;
 574         }
 575
 576         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
 577                 err = 0;
 578                 goto out;
 579         }
 580
 581         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 582              attr->pkey_index >= dev->limits.pkey_table_len) {
 583                 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
 584                           attr->pkey_index, dev->limits.pkey_table_len-1);
 585                 goto out;
 586         }
 587
 588         if ((attr_mask & IB_QP_PORT) &&
 589             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
 590                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
 591                 goto out;
 592         }
 593
 594         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 595             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 596                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 597                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 598                 goto out;
 599         }
 600
 601         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 602             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 603                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 604                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 605                 goto out;
 606         }
 607
 608         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 609         if (IS_ERR(mailbox)) {
 610                 err = PTR_ERR(mailbox);
 611                 goto out;
 612         }
 613         qp_param = mailbox->buf;
 614         qp_context = &qp_param->context;
 615         memset(qp_param, 0, sizeof *qp_param);
 616
 617         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 618                                              (to_mthca_st(qp->transport) << 16));
 619         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 620         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 621                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 622         else {
 623                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 624                 switch (attr->path_mig_state) {
 625                 case IB_MIG_MIGRATED:
 626                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 627                         break;
 628                 case IB_MIG_REARM:
 629                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 630                         break;
 631                 case IB_MIG_ARMED:
 632                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 633                         break;
 634                 }
 635         }
 636
 637         /* leave tavor_sched_queue as 0 */
 638
 639         if (qp->transport == MLX || qp->transport == UD)
 640                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 641         else if (attr_mask & IB_QP_PATH_MTU) {
 642                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
 643                         mthca_dbg(dev, "path MTU (%u) is invalid\n",
 644                                   attr->path_mtu);
 645                         goto out_mailbox;
 646                 }
 647                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 648         }
 649
 650         if (mthca_is_memfree(dev)) {
 651                 if (qp->rq.max)
 652                         qp_context->rq_size_stride = ilog2(qp->rq.max) << 3;
 653                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 654
 655                 if (qp->sq.max)
 656                         qp_context->sq_size_stride = ilog2(qp->sq.max) << 3;
 657                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 658         }
 659
 660         /* leave arbel_sched_queue as 0 */
 661
 662         if (qp->ibqp.uobject)
 663                 qp_context->usr_page =
 664                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 665         else
 666                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 667         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 668         if (attr_mask & IB_QP_DEST_QPN) {
 669                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 670         }
 671
 672         if (qp->transport == MLX)
 673                 qp_context->pri_path.port_pkey |=
 674                         cpu_to_be32(qp->port << 24);
 675         else {
 676                 if (attr_mask & IB_QP_PORT) {
 677                         qp_context->pri_path.port_pkey |=
 678                                 cpu_to_be32(attr->port_num << 24);
 679                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 680                 }
 681         }
 682
 683         if (attr_mask & IB_QP_PKEY_INDEX) {
 684                 qp_context->pri_path.port_pkey |=
 685                         cpu_to_be32(attr->pkey_index);
 686                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 687         }
 688
 689         if (attr_mask & IB_QP_RNR_RETRY) {
 690                 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
 691                         attr->rnr_retry << 5;
 692                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
 693                                                         MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
 694         }
 695
 696         if (attr_mask & IB_QP_AV) {
 697                 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
 698                                    attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 699                         goto out_mailbox;
 700
 701                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 702         }
 703
 704         if (ibqp->qp_type == IB_QPT_RC &&
 705             cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
 706                 u8 sched_queue = ibqp->uobject ? 0x2 : 0x1;
 707
 708                 if (mthca_is_memfree(dev))
 709                         qp_context->rlkey_arbel_sched_queue |= sched_queue;
 710                 else
 711                         qp_context->tavor_sched_queue |= cpu_to_be32(sched_queue);
 712
 713                 qp_param->opt_param_mask |=
 714                         cpu_to_be32(MTHCA_QP_OPTPAR_SCHED_QUEUE);
 715         }
 716
 717         if (attr_mask & IB_QP_TIMEOUT) {
 718                 qp_context->pri_path.ackto = attr->timeout << 3;
 719                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 720         }
 721
 722         if (attr_mask & IB_QP_ALT_PATH) {
 723                 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
 724                         mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
 725                                   attr->alt_pkey_index, dev->limits.pkey_table_len-1);
 726                         goto out_mailbox;
 727                 }
 728
 729                 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
 730                         mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
 731                                 attr->alt_port_num);
 732                         goto out_mailbox;
 733                 }
 734
 735                 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
 736                                    attr->alt_ah_attr.port_num))
 737                         goto out_mailbox;
 738
 739                 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
 740                                                               attr->alt_port_num << 24);
 741                 qp_context->alt_path.ackto = attr->alt_timeout << 3;
 742                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
 743         }
 744
 745         /* leave rdd as 0 */
 746         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 747         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 748         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 749         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 750                                              (MTHCA_FLIGHT_LIMIT << 24) |
 751                                              MTHCA_QP_BIT_SWE);
 752         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 753                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 754         if (attr_mask & IB_QP_RETRY_CNT) {
 755                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 756                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 757         }
 758
 759         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 760                 if (attr->max_rd_atomic) {
 761                         qp_context->params1 |=
 762                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 763                                             MTHCA_QP_BIT_SAE);
 764                         qp_context->params1 |=
 765                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 766                 }
 767                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 768         }
 769
 770         if (attr_mask & IB_QP_SQ_PSN)
 771                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 772         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 773
 774         if (mthca_is_memfree(dev)) {
 775                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 776                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 777         }
 778
 779         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 780                 if (attr->max_dest_rd_atomic)
 781                         qp_context->params2 |=
 782                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 783
 784                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 785         }
 786
 787         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 788                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 789                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 790                                                         MTHCA_QP_OPTPAR_RRE |
 791                                                         MTHCA_QP_OPTPAR_RAE);
 792         }
 793
 794         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 795
 796         if (ibqp->srq)
 797                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 798
 799         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 800                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 801                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 802         }
 803         if (attr_mask & IB_QP_RQ_PSN)
 804                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 805
 806         qp_context->ra_buff_indx =
 807                 cpu_to_be32(dev->qp_table.rdb_base +
 808                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 809                              dev->qp_table.rdb_shift));
 810
 811         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 812
 813         if (mthca_is_memfree(dev))
 814                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 815
 816         if (attr_mask & IB_QP_QKEY) {
 817                 qp_context->qkey = cpu_to_be32(attr->qkey);
 818                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 819         }
 820
 821         if (ibqp->srq)
 822                 qp_context->srqn = cpu_to_be32(1 << 24 |
 823                                                to_msrq(ibqp->srq)->srqn);
 824
 825         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 826             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY               &&
 827             attr->en_sqd_async_notify)
 828                 sqd_event = 1 << 31;
 829
 830         err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
 831                               mailbox, sqd_event, &status);
 832         if (err)
 833                 goto out_mailbox;
 834         if (status) {
 835                 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
 836                            cur_state, new_state, status);
 837                 err = -EINVAL;
 838                 goto out_mailbox;
 839         }
 840
 841         qp->state = new_state;
 842         if (attr_mask & IB_QP_ACCESS_FLAGS)
 843                 qp->atomic_rd_en = attr->qp_access_flags;
 844         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 845                 qp->resp_depth = attr->max_dest_rd_atomic;
 846         if (attr_mask & IB_QP_PORT)
 847                 qp->port = attr->port_num;
 848         if (attr_mask & IB_QP_ALT_PATH)
 849                 qp->alt_port = attr->alt_port_num;
 850
 851         if (is_sqp(dev, qp))
 852                 store_attrs(to_msqp(qp), attr, attr_mask);
 853
 854         /*
 855          * If we moved QP0 to RTR, bring the IB link up; if we moved
 856          * QP0 to RESET or ERROR, bring the link back down.
 857          */
 858         if (is_qp0(dev, qp)) {
 859                 if (cur_state != IB_QPS_RTR &&
 860                     new_state == IB_QPS_RTR)
 861                         init_port(dev, qp->port);
 862
 863                 if (cur_state != IB_QPS_RESET &&
 864                     cur_state != IB_QPS_ERR &&
 865                     (new_state == IB_QPS_RESET ||
 866                      new_state == IB_QPS_ERR))
 867                         mthca_CLOSE_IB(dev, qp->port, &status);
 868         }
 869
 870         /*
 871          * If we moved a kernel QP to RESET, clean up all old CQ
 872          * entries and reinitialize the QP.
 873          */
 874         if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 875                 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
 876                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 877                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 878                         mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
 879
 880                 mthca_wq_reset(&qp->sq);
 881                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 882
 883                 mthca_wq_reset(&qp->rq);
 884                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 885
 886                 if (mthca_is_memfree(dev)) {
 887                         *qp->sq.db = 0;
 888                         *qp->rq.db = 0;
 889                 }
 890         }
 891
 892 out_mailbox:
 893         mthca_free_mailbox(dev, mailbox);
 894
 895 out:
 896         mutex_unlock(&qp->mutex);
 897         return err;
 898 }
 899
 900 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
 901 {
 902         /*
 903          * Calculate the maximum size of WQE s/g segments, excluding
 904          * the next segment and other non-data segments.
 905          */
 906         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
 907
 908         switch (qp->transport) {
 909         case MLX:
 910                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 911                 break;
 912
 913         case UD:
 914                 if (mthca_is_memfree(dev))
 915                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 916                 else
 917                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 918                 break;
 919
 920         default:
 921                 max_data_size -= sizeof (struct mthca_raddr_seg);
 922                 break;
 923         }
 924
 925         return max_data_size;
 926 }
 927
 928 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
 929 {
 930         /* We don't support inline data for kernel QPs (yet). */
 931         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
 932 }
 933
 934 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 935                                  struct mthca_pd *pd,
 936                                  struct mthca_qp *qp)
 937 {
 938         int max_data_size = mthca_max_data_size(dev, qp,
 939                                                 min(dev->limits.max_desc_sz,
 940                                                     1 << qp->sq.wqe_shift));
 941
 942         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
 943
 944         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 945                               max_data_size / sizeof (struct mthca_data_seg));
 946         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 947                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 948                                 sizeof (struct mthca_next_seg)) /
 949                                sizeof (struct mthca_data_seg));
 950 }
 951
 952 /*
 953  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 954  * rq.max_gs and sq.max_gs must all be assigned.
 955  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 956  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 957  * queue)
 958  */
 959 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 960                                struct mthca_pd *pd,
 961                                struct mthca_qp *qp)
 962 {
 963         int size;
 964         int err = -ENOMEM;
 965
 966         size = sizeof (struct mthca_next_seg) +
 967                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 968
 969         if (size > dev->limits.max_desc_sz)
 970                 return -EINVAL;
 971
 972         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 973              qp->rq.wqe_shift++)
 974                 ; /* nothing */
 975
 976         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 977         switch (qp->transport) {
 978         case MLX:
 979                 size += 2 * sizeof (struct mthca_data_seg);
 980                 break;
 981
 982         case UD:
 983                 size += mthca_is_memfree(dev) ?
 984                         sizeof (struct mthca_arbel_ud_seg) :
 985                         sizeof (struct mthca_tavor_ud_seg);
 986                 break;
 987
 988         case UC:
 989                 size += sizeof (struct mthca_raddr_seg);
 990                 break;
 991
 992         case RC:
 993                 size += sizeof (struct mthca_raddr_seg);
 994                 /*
 995                  * An atomic op will require an atomic segment, a
 996                  * remote address segment and one scatter entry.
 997                  */
 998                 size = max_t(int, size,
 999                              sizeof (struct mthca_atomic_seg) +
1000                              sizeof (struct mthca_raddr_seg) +
1001                              sizeof (struct mthca_data_seg));
1002                 break;
1003
1004         default:
1005                 break;
1006         }
1007
1008         /* Make sure that we have enough space for a bind request */
1009         size = max_t(int, size, sizeof (struct mthca_bind_seg));
1010
1011         size += sizeof (struct mthca_next_seg);
1012
1013         if (size > dev->limits.max_desc_sz)
1014                 return -EINVAL;
1015
1016         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1017              qp->sq.wqe_shift++)
1018                 ; /* nothing */
1019
1020         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1021                                     1 << qp->sq.wqe_shift);
1022
1023         /*
1024          * If this is a userspace QP, we don't actually have to
1025          * allocate anything.  All we need is to calculate the WQE
1026          * sizes and the send_wqe_offset, so we're done now.
1027          */
1028         if (pd->ibpd.uobject)
1029                 return 0;
1030
1031         size = PAGE_ALIGN(qp->send_wqe_offset +
1032                           (qp->sq.max << qp->sq.wqe_shift));
1033
1034         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1035                            GFP_KERNEL);
1036         if (!qp->wrid)
1037                 goto err_out;
1038
1039         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1040                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1041         if (err)
1042                 goto err_out;
1043
1044         return 0;
1045
1046 err_out:
1047         kfree(qp->wrid);
1048         return err;
1049 }
1050
1051 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1052                                struct mthca_qp *qp)
1053 {
1054         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1055                                        (qp->sq.max << qp->sq.wqe_shift)),
1056                        &qp->queue, qp->is_direct, &qp->mr);
1057         kfree(qp->wrid);
1058 }
1059
1060 static int mthca_map_memfree(struct mthca_dev *dev,
1061                              struct mthca_qp *qp)
1062 {
1063         int ret;
1064
1065         if (mthca_is_memfree(dev)) {
1066                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1067                 if (ret)
1068                         return ret;
1069
1070                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1071                 if (ret)
1072                         goto err_qpc;
1073
1074                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1075                                       qp->qpn << dev->qp_table.rdb_shift);
1076                 if (ret)
1077                         goto err_eqpc;
1078
1079         }
1080
1081         return 0;
1082
1083 err_eqpc:
1084         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1085
1086 err_qpc:
1087         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1088
1089         return ret;
1090 }
1091
1092 static void mthca_unmap_memfree(struct mthca_dev *dev,
1093                                 struct mthca_qp *qp)
1094 {
1095         mthca_table_put(dev, dev->qp_table.rdb_table,
1096                         qp->qpn << dev->qp_table.rdb_shift);
1097         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1098         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1099 }
1100
1101 static int mthca_alloc_memfree(struct mthca_dev *dev,
1102                                struct mthca_qp *qp)
1103 {
1104         if (mthca_is_memfree(dev)) {
1105                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1106                                                  qp->qpn, &qp->rq.db);
1107                 if (qp->rq.db_index < 0)
1108                         return -ENOMEM;
1109
1110                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1111                                                  qp->qpn, &qp->sq.db);
1112                 if (qp->sq.db_index < 0) {
1113                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1114                         return -ENOMEM;
1115                 }
1116         }
1117
1118         return 0;
1119 }
1120
1121 static void mthca_free_memfree(struct mthca_dev *dev,
1122                                struct mthca_qp *qp)
1123 {
1124         if (mthca_is_memfree(dev)) {
1125                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1126                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1127         }
1128 }
1129
1130 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1131                                  struct mthca_pd *pd,
1132                                  struct mthca_cq *send_cq,
1133                                  struct mthca_cq *recv_cq,
1134                                  enum ib_sig_type send_policy,
1135                                  struct mthca_qp *qp)
1136 {
1137         int ret;
1138         int i;
1139
1140         qp->refcount = 1;
1141         init_waitqueue_head(&qp->wait);
1142         mutex_init(&qp->mutex);
1143         qp->state        = IB_QPS_RESET;
1144         qp->atomic_rd_en = 0;
1145         qp->resp_depth   = 0;
1146         qp->sq_policy    = send_policy;
1147         mthca_wq_reset(&qp->sq);
1148         mthca_wq_reset(&qp->rq);
1149
1150         spin_lock_init(&qp->sq.lock);
1151         spin_lock_init(&qp->rq.lock);
1152
1153         ret = mthca_map_memfree(dev, qp);
1154         if (ret)
1155                 return ret;
1156
1157         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1158         if (ret) {
1159                 mthca_unmap_memfree(dev, qp);
1160                 return ret;
1161         }
1162
1163         mthca_adjust_qp_caps(dev, pd, qp);
1164
1165         /*
1166          * If this is a userspace QP, we're done now.  The doorbells
1167          * will be allocated and buffers will be initialized in
1168          * userspace.
1169          */
1170         if (pd->ibpd.uobject)
1171                 return 0;
1172
1173         ret = mthca_alloc_memfree(dev, qp);
1174         if (ret) {
1175                 mthca_free_wqe_buf(dev, qp);
1176                 mthca_unmap_memfree(dev, qp);
1177                 return ret;
1178         }
1179
1180         if (mthca_is_memfree(dev)) {
1181                 struct mthca_next_seg *next;
1182                 struct mthca_data_seg *scatter;
1183                 int size = (sizeof (struct mthca_next_seg) +
1184                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1185
1186                 for (i = 0; i < qp->rq.max; ++i) {
1187                         next = get_recv_wqe(qp, i);
1188                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1189                                                    qp->rq.wqe_shift);
1190                         next->ee_nds = cpu_to_be32(size);
1191
1192                         for (scatter = (void *) (next + 1);
1193                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1194                              ++scatter)
1195                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1196                 }
1197
1198                 for (i = 0; i < qp->sq.max; ++i) {
1199                         next = get_send_wqe(qp, i);
1200                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1201                                                     qp->sq.wqe_shift) +
1202                                                    qp->send_wqe_offset);
1203                 }
1204         }
1205
1206         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1207         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1208
1209         return 0;
1210 }
1211
1212 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1213                              struct mthca_pd *pd, struct mthca_qp *qp)
1214 {
1215         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1216
1217         /* Sanity check QP size before proceeding */
1218         if (cap->max_send_wr     > dev->limits.max_wqes ||
1219             cap->max_recv_wr     > dev->limits.max_wqes ||
1220             cap->max_send_sge    > dev->limits.max_sg   ||
1221             cap->max_recv_sge    > dev->limits.max_sg   ||
1222             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1223                 return -EINVAL;
1224
1225         /*
1226          * For MLX transport we need 2 extra S/G entries:
1227          * one for the header and one for the checksum at the end
1228          */
1229         if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1230                 return -EINVAL;
1231
1232         if (mthca_is_memfree(dev)) {
1233                 qp->rq.max = cap->max_recv_wr ?
1234                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1235                 qp->sq.max = cap->max_send_wr ?
1236                         roundup_pow_of_two(cap->max_send_wr) : 0;
1237         } else {
1238                 qp->rq.max = cap->max_recv_wr;
1239                 qp->sq.max = cap->max_send_wr;
1240         }
1241
1242         qp->rq.max_gs = cap->max_recv_sge;
1243         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1244                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1245                                     MTHCA_INLINE_CHUNK_SIZE) /
1246                               sizeof (struct mthca_data_seg));
1247
1248         return 0;
1249 }
1250
1251 int mthca_alloc_qp(struct mthca_dev *dev,
1252                    struct mthca_pd *pd,
1253                    struct mthca_cq *send_cq,
1254                    struct mthca_cq *recv_cq,
1255                    enum ib_qp_type type,
1256                    enum ib_sig_type send_policy,
1257                    struct ib_qp_cap *cap,
1258                    struct mthca_qp *qp)
1259 {
1260         int err;
1261
1262         switch (type) {
1263         case IB_QPT_RC: qp->transport = RC; break;
1264         case IB_QPT_UC: qp->transport = UC; break;
1265         case IB_QPT_UD: qp->transport = UD; break;
1266         default: return -EINVAL;
1267         }
1268
1269         err = mthca_set_qp_size(dev, cap, pd, qp);
1270         if (err)
1271                 return err;
1272
1273         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1274         if (qp->qpn == -1)
1275                 return -ENOMEM;
1276
1277         /* initialize port to zero for error-catching. */
1278         qp->port = 0;
1279
1280         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1281                                     send_policy, qp);
1282         if (err) {
1283                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1284                 return err;
1285         }
1286
1287         spin_lock_irq(&dev->qp_table.lock);
1288         mthca_array_set(&dev->qp_table.qp,
1289                         qp->qpn & (dev->limits.num_qps - 1), qp);
1290         spin_unlock_irq(&dev->qp_table.lock);
1291
1292         return 0;
1293 }
1294
1295 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1296 {
1297         if (send_cq == recv_cq)
1298                 spin_lock_irq(&send_cq->lock);
1299         else if (send_cq->cqn < recv_cq->cqn) {
1300                 spin_lock_irq(&send_cq->lock);
1301                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1302         } else {
1303                 spin_lock_irq(&recv_cq->lock);
1304                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1305         }
1306 }
1307
1308 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1309 {
1310         if (send_cq == recv_cq)
1311                 spin_unlock_irq(&send_cq->lock);
1312         else if (send_cq->cqn < recv_cq->cqn) {
1313                 spin_unlock(&recv_cq->lock);
1314                 spin_unlock_irq(&send_cq->lock);
1315         } else {
1316                 spin_unlock(&send_cq->lock);
1317                 spin_unlock_irq(&recv_cq->lock);
1318         }
1319 }
1320
1321 int mthca_alloc_sqp(struct mthca_dev *dev,
1322                     struct mthca_pd *pd,
1323                     struct mthca_cq *send_cq,
1324                     struct mthca_cq *recv_cq,
1325                     enum ib_sig_type send_policy,
1326                     struct ib_qp_cap *cap,
1327                     int qpn,
1328                     int port,
1329                     struct mthca_sqp *sqp)
1330 {
1331         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1332         int err;
1333
1334         sqp->qp.transport = MLX;
1335         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1336         if (err)
1337                 return err;
1338
1339         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1340         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1341                                              &sqp->header_dma, GFP_KERNEL);
1342         if (!sqp->header_buf)
1343                 return -ENOMEM;
1344
1345         spin_lock_irq(&dev->qp_table.lock);
1346         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1347                 err = -EBUSY;
1348         else
1349                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1350         spin_unlock_irq(&dev->qp_table.lock);
1351
1352         if (err)
1353                 goto err_out;
1354
1355         sqp->qp.port      = port;
1356         sqp->qp.qpn       = mqpn;
1357         sqp->qp.transport = MLX;
1358
1359         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1360                                     send_policy, &sqp->qp);
1361         if (err)
1362                 goto err_out_free;
1363
1364         atomic_inc(&pd->sqp_count);
1365
1366         return 0;
1367
1368  err_out_free:
1369         /*
1370          * Lock CQs here, so that CQ polling code can do QP lookup
1371          * without taking a lock.
1372          */
1373         mthca_lock_cqs(send_cq, recv_cq);
1374
1375         spin_lock(&dev->qp_table.lock);
1376         mthca_array_clear(&dev->qp_table.qp, mqpn);
1377         spin_unlock(&dev->qp_table.lock);
1378
1379         mthca_unlock_cqs(send_cq, recv_cq);
1380
1381  err_out:
1382         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1383                           sqp->header_buf, sqp->header_dma);
1384
1385         return err;
1386 }
1387
1388 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1389 {
1390         int c;
1391
1392         spin_lock_irq(&dev->qp_table.lock);
1393         c = qp->refcount;
1394         spin_unlock_irq(&dev->qp_table.lock);
1395
1396         return c;
1397 }
1398
1399 void mthca_free_qp(struct mthca_dev *dev,
1400                    struct mthca_qp *qp)
1401 {
1402         u8 status;
1403         struct mthca_cq *send_cq;
1404         struct mthca_cq *recv_cq;
1405
1406         send_cq = to_mcq(qp->ibqp.send_cq);
1407         recv_cq = to_mcq(qp->ibqp.recv_cq);
1408
1409         /*
1410          * Lock CQs here, so that CQ polling code can do QP lookup
1411          * without taking a lock.
1412          */
1413         mthca_lock_cqs(send_cq, recv_cq);
1414
1415         spin_lock(&dev->qp_table.lock);
1416         mthca_array_clear(&dev->qp_table.qp,
1417                           qp->qpn & (dev->limits.num_qps - 1));
1418         --qp->refcount;
1419         spin_unlock(&dev->qp_table.lock);
1420
1421         mthca_unlock_cqs(send_cq, recv_cq);
1422
1423         wait_event(qp->wait, !get_qp_refcount(dev, qp));
1424
1425         if (qp->state != IB_QPS_RESET)
1426                 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1427                                 NULL, 0, &status);
1428
1429         /*
1430          * If this is a userspace QP, the buffers, MR, CQs and so on
1431          * will be cleaned up in userspace, so all we have to do is
1432          * unref the mem-free tables and free the QPN in our table.
1433          */
1434         if (!qp->ibqp.uobject) {
1435                 mthca_cq_clean(dev, recv_cq, qp->qpn,
1436                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1437                 if (send_cq != recv_cq)
1438                         mthca_cq_clean(dev, send_cq, qp->qpn, NULL);
1439
1440                 mthca_free_memfree(dev, qp);
1441                 mthca_free_wqe_buf(dev, qp);
1442         }
1443
1444         mthca_unmap_memfree(dev, qp);
1445
1446         if (is_sqp(dev, qp)) {
1447                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1448                 dma_free_coherent(&dev->pdev->dev,
1449                                   to_msqp(qp)->header_buf_size,
1450                                   to_msqp(qp)->header_buf,
1451                                   to_msqp(qp)->header_dma);
1452         } else
1453                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1454 }
1455
1456 /* Create UD header for an MLX send and build a data segment for it */
1457 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1458                             int ind, struct ib_send_wr *wr,
1459                             struct mthca_mlx_seg *mlx,
1460                             struct mthca_data_seg *data)
1461 {
1462         int header_size;
1463         int err;
1464         u16 pkey;
1465
1466         ib_ud_header_init(256, /* assume a MAD */
1467                           mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1468                           &sqp->ud_header);
1469
1470         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1471         if (err)
1472                 return err;
1473         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1474         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1475                                   (sqp->ud_header.lrh.destination_lid ==
1476                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1477                                   (sqp->ud_header.lrh.service_level << 8));
1478         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1479         mlx->vcrc = 0;
1480
1481         switch (wr->opcode) {
1482         case IB_WR_SEND:
1483                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1484                 sqp->ud_header.immediate_present = 0;
1485                 break;
1486         case IB_WR_SEND_WITH_IMM:
1487                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1488                 sqp->ud_header.immediate_present = 1;
1489                 sqp->ud_header.immediate_data = wr->imm_data;
1490                 break;
1491         default:
1492                 return -EINVAL;
1493         }
1494
1495         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1496         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1497                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1498         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1499         if (!sqp->qp.ibqp.qp_num)
1500                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1501                                    sqp->pkey_index, &pkey);
1502         else
1503                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1504                                    wr->wr.ud.pkey_index, &pkey);
1505         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1506         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1507         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1508         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1509                                                sqp->qkey : wr->wr.ud.remote_qkey);
1510         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1511
1512         header_size = ib_ud_header_pack(&sqp->ud_header,
1513                                         sqp->header_buf +
1514                                         ind * MTHCA_UD_HEADER_SIZE);
1515
1516         data->byte_count = cpu_to_be32(header_size);
1517         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1518         data->addr       = cpu_to_be64(sqp->header_dma +
1519                                        ind * MTHCA_UD_HEADER_SIZE);
1520
1521         return 0;
1522 }
1523
1524 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1525                                     struct ib_cq *ib_cq)
1526 {
1527         unsigned cur;
1528         struct mthca_cq *cq;
1529
1530         cur = wq->head - wq->tail;
1531         if (likely(cur + nreq < wq->max))
1532                 return 0;
1533
1534         cq = to_mcq(ib_cq);
1535         spin_lock(&cq->lock);
1536         cur = wq->head - wq->tail;
1537         spin_unlock(&cq->lock);
1538
1539         return cur + nreq >= wq->max;
1540 }
1541
1542 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1543                           struct ib_send_wr **bad_wr)
1544 {
1545         struct mthca_dev *dev = to_mdev(ibqp->device);
1546         struct mthca_qp *qp = to_mqp(ibqp);
1547         void *wqe;
1548         void *prev_wqe;
1549         unsigned long flags;
1550         int err = 0;
1551         int nreq;
1552         int i;
1553         int size;
1554         int size0 = 0;
1555         u32 f0;
1556         int ind;
1557         u8 op0 = 0;
1558
1559         spin_lock_irqsave(&qp->sq.lock, flags);
1560
1561         /* XXX check that state is OK to post send */
1562
1563         ind = qp->sq.next_ind;
1564
1565         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1566                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1567                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1568                                         " %d max, %d nreq)\n", qp->qpn,
1569                                         qp->sq.head, qp->sq.tail,
1570                                         qp->sq.max, nreq);
1571                         err = -ENOMEM;
1572                         *bad_wr = wr;
1573                         goto out;
1574                 }
1575
1576                 wqe = get_send_wqe(qp, ind);
1577                 prev_wqe = qp->sq.last;
1578                 qp->sq.last = wqe;
1579
1580                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1581                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1582                 ((struct mthca_next_seg *) wqe)->flags =
1583                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1584                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1585                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1586                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1587                         cpu_to_be32(1);
1588                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1589                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1590                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1591
1592                 wqe += sizeof (struct mthca_next_seg);
1593                 size = sizeof (struct mthca_next_seg) / 16;
1594
1595                 switch (qp->transport) {
1596                 case RC:
1597                         switch (wr->opcode) {
1598                         case IB_WR_ATOMIC_CMP_AND_SWP:
1599                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1600                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1601                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1602                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1603                                         cpu_to_be32(wr->wr.atomic.rkey);
1604                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1605
1606                                 wqe += sizeof (struct mthca_raddr_seg);
1607
1608                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1609                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1610                                                 cpu_to_be64(wr->wr.atomic.swap);
1611                                         ((struct mthca_atomic_seg *) wqe)->compare =
1612                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1613                                 } else {
1614                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1615                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1616                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1617                                 }
1618
1619                                 wqe += sizeof (struct mthca_atomic_seg);
1620                                 size += (sizeof (struct mthca_raddr_seg) +
1621                                          sizeof (struct mthca_atomic_seg)) / 16;
1622                                 break;
1623
1624                         case IB_WR_RDMA_WRITE:
1625                         case IB_WR_RDMA_WRITE_WITH_IMM:
1626                         case IB_WR_RDMA_READ:
1627                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1628                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1629                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1630                                         cpu_to_be32(wr->wr.rdma.rkey);
1631                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1632                                 wqe += sizeof (struct mthca_raddr_seg);
1633                                 size += sizeof (struct mthca_raddr_seg) / 16;
1634                                 break;
1635
1636                         default:
1637                                 /* No extra segments required for sends */
1638                                 break;
1639                         }
1640
1641                         break;
1642
1643                 case UC:
1644                         switch (wr->opcode) {
1645                         case IB_WR_RDMA_WRITE:
1646                         case IB_WR_RDMA_WRITE_WITH_IMM:
1647                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1648                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1649                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1650                                         cpu_to_be32(wr->wr.rdma.rkey);
1651                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1652                                 wqe += sizeof (struct mthca_raddr_seg);
1653                                 size += sizeof (struct mthca_raddr_seg) / 16;
1654                                 break;
1655
1656                         default:
1657                                 /* No extra segments required for sends */
1658                                 break;
1659                         }
1660
1661                         break;
1662
1663                 case UD:
1664                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1665                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1666                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1667                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1668                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1669                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1670                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1671                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1672
1673                         wqe += sizeof (struct mthca_tavor_ud_seg);
1674                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1675                         break;
1676
1677                 case MLX:
1678                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1679                                                wqe - sizeof (struct mthca_next_seg),
1680                                                wqe);
1681                         if (err) {
1682                                 *bad_wr = wr;
1683                                 goto out;
1684                         }
1685                         wqe += sizeof (struct mthca_data_seg);
1686                         size += sizeof (struct mthca_data_seg) / 16;
1687                         break;
1688                 }
1689
1690                 if (wr->num_sge > qp->sq.max_gs) {
1691                         mthca_err(dev, "too many gathers\n");
1692                         err = -EINVAL;
1693                         *bad_wr = wr;
1694                         goto out;
1695                 }
1696
1697                 for (i = 0; i < wr->num_sge; ++i) {
1698                         ((struct mthca_data_seg *) wqe)->byte_count =
1699                                 cpu_to_be32(wr->sg_list[i].length);
1700                         ((struct mthca_data_seg *) wqe)->lkey =
1701                                 cpu_to_be32(wr->sg_list[i].lkey);
1702                         ((struct mthca_data_seg *) wqe)->addr =
1703                                 cpu_to_be64(wr->sg_list[i].addr);
1704                         wqe += sizeof (struct mthca_data_seg);
1705                         size += sizeof (struct mthca_data_seg) / 16;
1706                 }
1707
1708                 /* Add one more inline data segment for ICRC */
1709                 if (qp->transport == MLX) {
1710                         ((struct mthca_data_seg *) wqe)->byte_count =
1711                                 cpu_to_be32((1 << 31) | 4);
1712                         ((u32 *) wqe)[1] = 0;
1713                         wqe += sizeof (struct mthca_data_seg);
1714                         size += sizeof (struct mthca_data_seg) / 16;
1715                 }
1716
1717                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1718
1719                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1720                         mthca_err(dev, "opcode invalid\n");
1721                         err = -EINVAL;
1722                         *bad_wr = wr;
1723                         goto out;
1724                 }
1725
1726                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1727                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1728                                      qp->send_wqe_offset) |
1729                                     mthca_opcode[wr->opcode]);
1730                 wmb();
1731                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1732                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1733                                     ((wr->send_flags & IB_SEND_FENCE) ?
1734                                     MTHCA_NEXT_FENCE : 0));
1735
1736                 if (!size0) {
1737                         size0 = size;
1738                         op0   = mthca_opcode[wr->opcode];
1739                         f0    = wr->send_flags & IB_SEND_FENCE ?
1740                                 MTHCA_SEND_DOORBELL_FENCE : 0;
1741                 }
1742
1743                 ++ind;
1744                 if (unlikely(ind >= qp->sq.max))
1745                         ind -= qp->sq.max;
1746         }
1747
1748 out:
1749         if (likely(nreq)) {
1750                 __be32 doorbell[2];
1751
1752                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1753                                            qp->send_wqe_offset) | f0 | op0);
1754                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1755
1756                 wmb();
1757
1758                 mthca_write64(doorbell,
1759                               dev->kar + MTHCA_SEND_DOORBELL,
1760                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1761                 /*
1762                  * Make sure doorbells don't leak out of SQ spinlock
1763                  * and reach the HCA out of order:
1764                  */
1765                 mmiowb();
1766         }
1767
1768         qp->sq.next_ind = ind;
1769         qp->sq.head    += nreq;
1770
1771         spin_unlock_irqrestore(&qp->sq.lock, flags);
1772         return err;
1773 }
1774
1775 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1776                              struct ib_recv_wr **bad_wr)
1777 {
1778         struct mthca_dev *dev = to_mdev(ibqp->device);
1779         struct mthca_qp *qp = to_mqp(ibqp);
1780         __be32 doorbell[2];
1781         unsigned long flags;
1782         int err = 0;
1783         int nreq;
1784         int i;
1785         int size;
1786         int size0 = 0;
1787         int ind;
1788         void *wqe;
1789         void *prev_wqe;
1790
1791         spin_lock_irqsave(&qp->rq.lock, flags);
1792
1793         /* XXX check that state is OK to post receive */
1794
1795         ind = qp->rq.next_ind;
1796
1797         for (nreq = 0; wr; wr = wr->next) {
1798                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1799                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1800                                         " %d max, %d nreq)\n", qp->qpn,
1801                                         qp->rq.head, qp->rq.tail,
1802                                         qp->rq.max, nreq);
1803                         err = -ENOMEM;
1804                         *bad_wr = wr;
1805                         goto out;
1806                 }
1807
1808                 wqe = get_recv_wqe(qp, ind);
1809                 prev_wqe = qp->rq.last;
1810                 qp->rq.last = wqe;
1811
1812                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1813                 ((struct mthca_next_seg *) wqe)->ee_nds =
1814                         cpu_to_be32(MTHCA_NEXT_DBD);
1815                 ((struct mthca_next_seg *) wqe)->flags = 0;
1816
1817                 wqe += sizeof (struct mthca_next_seg);
1818                 size = sizeof (struct mthca_next_seg) / 16;
1819
1820                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1821                         err = -EINVAL;
1822                         *bad_wr = wr;
1823                         goto out;
1824                 }
1825
1826                 for (i = 0; i < wr->num_sge; ++i) {
1827                         ((struct mthca_data_seg *) wqe)->byte_count =
1828                                 cpu_to_be32(wr->sg_list[i].length);
1829                         ((struct mthca_data_seg *) wqe)->lkey =
1830                                 cpu_to_be32(wr->sg_list[i].lkey);
1831                         ((struct mthca_data_seg *) wqe)->addr =
1832                                 cpu_to_be64(wr->sg_list[i].addr);
1833                         wqe += sizeof (struct mthca_data_seg);
1834                         size += sizeof (struct mthca_data_seg) / 16;
1835                 }
1836
1837                 qp->wrid[ind] = wr->wr_id;
1838
1839                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1840                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1841                 wmb();
1842                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1843                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1844
1845                 if (!size0)
1846                         size0 = size;
1847
1848                 ++ind;
1849                 if (unlikely(ind >= qp->rq.max))
1850                         ind -= qp->rq.max;
1851
1852                 ++nreq;
1853                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1854                         nreq = 0;
1855
1856                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1857                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1858
1859                         wmb();
1860
1861                         mthca_write64(doorbell,
1862                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1863                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1864
1865                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1866                         size0 = 0;
1867                 }
1868         }
1869
1870 out:
1871         if (likely(nreq)) {
1872                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1873                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1874
1875                 wmb();
1876
1877                 mthca_write64(doorbell,
1878                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1879                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1880         }
1881
1882         qp->rq.next_ind = ind;
1883         qp->rq.head    += nreq;
1884
1885         /*
1886          * Make sure doorbells don't leak out of RQ spinlock and reach
1887          * the HCA out of order:
1888          */
1889         mmiowb();
1890
1891         spin_unlock_irqrestore(&qp->rq.lock, flags);
1892         return err;
1893 }
1894
1895 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1896                           struct ib_send_wr **bad_wr)
1897 {
1898         struct mthca_dev *dev = to_mdev(ibqp->device);
1899         struct mthca_qp *qp = to_mqp(ibqp);
1900         __be32 doorbell[2];
1901         void *wqe;
1902         void *prev_wqe;
1903         unsigned long flags;
1904         int err = 0;
1905         int nreq;
1906         int i;
1907         int size;
1908         int size0 = 0;
1909         u32 f0;
1910         int ind;
1911         u8 op0 = 0;
1912
1913         spin_lock_irqsave(&qp->sq.lock, flags);
1914
1915         /* XXX check that state is OK to post send */
1916
1917         ind = qp->sq.head & (qp->sq.max - 1);
1918
1919         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1920                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1921                         nreq = 0;
1922
1923                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1924                                                   ((qp->sq.head & 0xffff) << 8) |
1925                                                   f0 | op0);
1926                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1927
1928                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1929                         size0 = 0;
1930
1931                         /*
1932                          * Make sure that descriptors are written before
1933                          * doorbell record.
1934                          */
1935                         wmb();
1936                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1937
1938                         /*
1939                          * Make sure doorbell record is written before we
1940                          * write MMIO send doorbell.
1941                          */
1942                         wmb();
1943                         mthca_write64(doorbell,
1944                                       dev->kar + MTHCA_SEND_DOORBELL,
1945                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1946                 }
1947
1948                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1949                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1950                                         " %d max, %d nreq)\n", qp->qpn,
1951                                         qp->sq.head, qp->sq.tail,
1952                                         qp->sq.max, nreq);
1953                         err = -ENOMEM;
1954                         *bad_wr = wr;
1955                         goto out;
1956                 }
1957
1958                 wqe = get_send_wqe(qp, ind);
1959                 prev_wqe = qp->sq.last;
1960                 qp->sq.last = wqe;
1961
1962                 ((struct mthca_next_seg *) wqe)->flags =
1963                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1964                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1965                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1966                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1967                         cpu_to_be32(1);
1968                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1969                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1970                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1971
1972                 wqe += sizeof (struct mthca_next_seg);
1973                 size = sizeof (struct mthca_next_seg) / 16;
1974
1975                 switch (qp->transport) {
1976                 case RC:
1977                         switch (wr->opcode) {
1978                         case IB_WR_ATOMIC_CMP_AND_SWP:
1979                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1980                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1981                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1982                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1983                                         cpu_to_be32(wr->wr.atomic.rkey);
1984                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1985
1986                                 wqe += sizeof (struct mthca_raddr_seg);
1987
1988                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1989                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1990                                                 cpu_to_be64(wr->wr.atomic.swap);
1991                                         ((struct mthca_atomic_seg *) wqe)->compare =
1992                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1993                                 } else {
1994                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1995                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1996                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1997                                 }
1998
1999                                 wqe += sizeof (struct mthca_atomic_seg);
2000                                 size += (sizeof (struct mthca_raddr_seg) +
2001                                          sizeof (struct mthca_atomic_seg)) / 16;
2002                                 break;
2003
2004                         case IB_WR_RDMA_READ:
2005                         case IB_WR_RDMA_WRITE:
2006                         case IB_WR_RDMA_WRITE_WITH_IMM:
2007                                 ((struct mthca_raddr_seg *) wqe)->raddr =
2008                                         cpu_to_be64(wr->wr.rdma.remote_addr);
2009                                 ((struct mthca_raddr_seg *) wqe)->rkey =
2010                                         cpu_to_be32(wr->wr.rdma.rkey);
2011                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
2012                                 wqe += sizeof (struct mthca_raddr_seg);
2013                                 size += sizeof (struct mthca_raddr_seg) / 16;
2014                                 break;
2015
2016                         default:
2017                                 /* No extra segments required for sends */
2018                                 break;
2019                         }
2020
2021                         break;
2022
2023                 case UC:
2024                         switch (wr->opcode) {
2025                         case IB_WR_RDMA_WRITE:
2026                         case IB_WR_RDMA_WRITE_WITH_IMM:
2027                                 ((struct mthca_raddr_seg *) wqe)->raddr =
2028                                         cpu_to_be64(wr->wr.rdma.remote_addr);
2029                                 ((struct mthca_raddr_seg *) wqe)->rkey =
2030                                         cpu_to_be32(wr->wr.rdma.rkey);
2031                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
2032                                 wqe += sizeof (struct mthca_raddr_seg);
2033                                 size += sizeof (struct mthca_raddr_seg) / 16;
2034                                 break;
2035
2036                         default:
2037                                 /* No extra segments required for sends */
2038                                 break;
2039                         }
2040
2041                         break;
2042
2043                 case UD:
2044                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
2045                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
2046                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
2047                                 cpu_to_be32(wr->wr.ud.remote_qpn);
2048                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
2049                                 cpu_to_be32(wr->wr.ud.remote_qkey);
2050
2051                         wqe += sizeof (struct mthca_arbel_ud_seg);
2052                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
2053                         break;
2054
2055                 case MLX:
2056                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
2057                                                wqe - sizeof (struct mthca_next_seg),
2058                                                wqe);
2059                         if (err) {
2060                                 *bad_wr = wr;
2061                                 goto out;
2062                         }
2063                         wqe += sizeof (struct mthca_data_seg);
2064                         size += sizeof (struct mthca_data_seg) / 16;
2065                         break;
2066                 }
2067
2068                 if (wr->num_sge > qp->sq.max_gs) {
2069                         mthca_err(dev, "too many gathers\n");
2070                         err = -EINVAL;
2071                         *bad_wr = wr;
2072                         goto out;
2073                 }
2074
2075                 for (i = 0; i < wr->num_sge; ++i) {
2076                         ((struct mthca_data_seg *) wqe)->byte_count =
2077                                 cpu_to_be32(wr->sg_list[i].length);
2078                         ((struct mthca_data_seg *) wqe)->lkey =
2079                                 cpu_to_be32(wr->sg_list[i].lkey);
2080                         ((struct mthca_data_seg *) wqe)->addr =
2081                                 cpu_to_be64(wr->sg_list[i].addr);
2082                         wqe += sizeof (struct mthca_data_seg);
2083                         size += sizeof (struct mthca_data_seg) / 16;
2084                 }
2085
2086                 /* Add one more inline data segment for ICRC */
2087                 if (qp->transport == MLX) {
2088                         ((struct mthca_data_seg *) wqe)->byte_count =
2089                                 cpu_to_be32((1 << 31) | 4);
2090                         ((u32 *) wqe)[1] = 0;
2091                         wqe += sizeof (struct mthca_data_seg);
2092                         size += sizeof (struct mthca_data_seg) / 16;
2093                 }
2094
2095                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2096
2097                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2098                         mthca_err(dev, "opcode invalid\n");
2099                         err = -EINVAL;
2100                         *bad_wr = wr;
2101                         goto out;
2102                 }
2103
2104                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2105                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2106                                      qp->send_wqe_offset) |
2107                                     mthca_opcode[wr->opcode]);
2108                 wmb();
2109                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2110                         cpu_to_be32(MTHCA_NEXT_DBD | size |
2111                                     ((wr->send_flags & IB_SEND_FENCE) ?
2112                                      MTHCA_NEXT_FENCE : 0));
2113
2114                 if (!size0) {
2115                         size0 = size;
2116                         op0   = mthca_opcode[wr->opcode];
2117                         f0    = wr->send_flags & IB_SEND_FENCE ?
2118                                 MTHCA_SEND_DOORBELL_FENCE : 0;
2119                 }
2120
2121                 ++ind;
2122                 if (unlikely(ind >= qp->sq.max))
2123                         ind -= qp->sq.max;
2124         }
2125
2126 out:
2127         if (likely(nreq)) {
2128                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2129                                           ((qp->sq.head & 0xffff) << 8) |
2130                                           f0 | op0);
2131                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2132
2133                 qp->sq.head += nreq;
2134
2135                 /*
2136                  * Make sure that descriptors are written before
2137                  * doorbell record.
2138                  */
2139                 wmb();
2140                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2141
2142                 /*
2143                  * Make sure doorbell record is written before we
2144                  * write MMIO send doorbell.
2145                  */
2146                 wmb();
2147                 mthca_write64(doorbell,
2148                               dev->kar + MTHCA_SEND_DOORBELL,
2149                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2150         }
2151
2152         /*
2153          * Make sure doorbells don't leak out of SQ spinlock and reach
2154          * the HCA out of order:
2155          */
2156         mmiowb();
2157
2158         spin_unlock_irqrestore(&qp->sq.lock, flags);
2159         return err;
2160 }
2161
2162 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2163                              struct ib_recv_wr **bad_wr)
2164 {
2165         struct mthca_dev *dev = to_mdev(ibqp->device);
2166         struct mthca_qp *qp = to_mqp(ibqp);
2167         unsigned long flags;
2168         int err = 0;
2169         int nreq;
2170         int ind;
2171         int i;
2172         void *wqe;
2173
2174         spin_lock_irqsave(&qp->rq.lock, flags);
2175
2176         /* XXX check that state is OK to post receive */
2177
2178         ind = qp->rq.head & (qp->rq.max - 1);
2179
2180         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2181                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2182                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2183                                         " %d max, %d nreq)\n", qp->qpn,
2184                                         qp->rq.head, qp->rq.tail,
2185                                         qp->rq.max, nreq);
2186                         err = -ENOMEM;
2187                         *bad_wr = wr;
2188                         goto out;
2189                 }
2190
2191                 wqe = get_recv_wqe(qp, ind);
2192
2193                 ((struct mthca_next_seg *) wqe)->flags = 0;
2194
2195                 wqe += sizeof (struct mthca_next_seg);
2196
2197                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2198                         err = -EINVAL;
2199                         *bad_wr = wr;
2200                         goto out;
2201                 }
2202
2203                 for (i = 0; i < wr->num_sge; ++i) {
2204                         ((struct mthca_data_seg *) wqe)->byte_count =
2205                                 cpu_to_be32(wr->sg_list[i].length);
2206                         ((struct mthca_data_seg *) wqe)->lkey =
2207                                 cpu_to_be32(wr->sg_list[i].lkey);
2208                         ((struct mthca_data_seg *) wqe)->addr =
2209                                 cpu_to_be64(wr->sg_list[i].addr);
2210                         wqe += sizeof (struct mthca_data_seg);
2211                 }
2212
2213                 if (i < qp->rq.max_gs) {
2214                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2215                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2216                         ((struct mthca_data_seg *) wqe)->addr = 0;
2217                 }
2218
2219                 qp->wrid[ind] = wr->wr_id;
2220
2221                 ++ind;
2222                 if (unlikely(ind >= qp->rq.max))
2223                         ind -= qp->rq.max;
2224         }
2225 out:
2226         if (likely(nreq)) {
2227                 qp->rq.head += nreq;
2228
2229                 /*
2230                  * Make sure that descriptors are written before
2231                  * doorbell record.
2232                  */
2233                 wmb();
2234                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2235         }
2236
2237         spin_unlock_irqrestore(&qp->rq.lock, flags);
2238         return err;
2239 }
2240
2241 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2242                         int index, int *dbd, __be32 *new_wqe)
2243 {
2244         struct mthca_next_seg *next;
2245
2246         /*
2247          * For SRQs, all WQEs generate a CQE, so we're always at the
2248          * end of the doorbell chain.
2249          */
2250         if (qp->ibqp.srq) {
2251                 *new_wqe = 0;
2252                 return;
2253         }
2254
2255         if (is_send)
2256                 next = get_send_wqe(qp, index);
2257         else
2258                 next = get_recv_wqe(qp, index);
2259
2260         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2261         if (next->ee_nds & cpu_to_be32(0x3f))
2262                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2263                         (next->ee_nds & cpu_to_be32(0x3f));
2264         else
2265                 *new_wqe = 0;
2266 }
2267
2268 int mthca_init_qp_table(struct mthca_dev *dev)
2269 {
2270         int err;
2271         u8 status;
2272         int i;
2273
2274         spin_lock_init(&dev->qp_table.lock);
2275
2276         /*
2277          * We reserve 2 extra QPs per port for the special QPs.  The
2278          * special QP for port 1 has to be even, so round up.
2279          */
2280         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2281         err = mthca_alloc_init(&dev->qp_table.alloc,
2282                                dev->limits.num_qps,
2283                                (1 << 24) - 1,
2284                                dev->qp_table.sqp_start +
2285                                MTHCA_MAX_PORTS * 2);
2286         if (err)
2287                 return err;
2288
2289         err = mthca_array_init(&dev->qp_table.qp,
2290                                dev->limits.num_qps);
2291         if (err) {
2292                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2293                 return err;
2294         }
2295
2296         for (i = 0; i < 2; ++i) {
2297                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2298                                             dev->qp_table.sqp_start + i * 2,
2299                                             &status);
2300                 if (err)
2301                         goto err_out;
2302                 if (status) {
2303                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2304                                    "status %02x, aborting.\n",
2305                                    status);
2306                         err = -EINVAL;
2307                         goto err_out;
2308                 }
2309         }
2310         return 0;
2311
2312  err_out:
2313         for (i = 0; i < 2; ++i)
2314                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2315
2316         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2317         mthca_alloc_cleanup(&dev->qp_table.alloc);
2318
2319         return err;
2320 }
2321
2322 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2323 {
2324         int i;
2325         u8 status;
2326
2327         for (i = 0; i < 2; ++i)
2328                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2329
2330         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2331         mthca_alloc_cleanup(&dev->qp_table.alloc);
2332 }