2 * Freescale DMA ALSA SoC PCM driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed
7 * under the terms of the GNU General Public License version 2. This
8 * program is licensed "as is" without any warranty of any kind, whether
11 * This driver implements ASoC support for the Elo DMA controller, which is
12 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
13 * the PCM driver is what handles the DMA buffer.
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
33 * The formats that the DMA controller supports, which is anything
34 * that is 8, 16, or 32 bits.
36 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
37 SNDRV_PCM_FMTBIT_U8 | \
38 SNDRV_PCM_FMTBIT_S16_LE | \
39 SNDRV_PCM_FMTBIT_S16_BE | \
40 SNDRV_PCM_FMTBIT_U16_LE | \
41 SNDRV_PCM_FMTBIT_U16_BE | \
42 SNDRV_PCM_FMTBIT_S24_LE | \
43 SNDRV_PCM_FMTBIT_S24_BE | \
44 SNDRV_PCM_FMTBIT_U24_LE | \
45 SNDRV_PCM_FMTBIT_U24_BE | \
46 SNDRV_PCM_FMTBIT_S32_LE | \
47 SNDRV_PCM_FMTBIT_S32_BE | \
48 SNDRV_PCM_FMTBIT_U32_LE | \
49 SNDRV_PCM_FMTBIT_U32_BE)
51 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
52 SNDRV_PCM_RATE_CONTINUOUS)
54 /* DMA global data. This structure is used by fsl_dma_open() to determine
55 * which DMA channels to assign to a substream. Unfortunately, ASoC V1 does
56 * not allow the machine driver to provide this information to the PCM
57 * driver in advance, and there's no way to differentiate between the two
58 * DMA controllers. So for now, this driver only supports one SSI device
59 * using two DMA channels. We cannot support multiple DMA devices.
61 * ssi_stx_phys: bus address of SSI STX register
62 * ssi_srx_phys: bus address of SSI SRX register
63 * dma_channel: pointer to the DMA channel's registers
64 * irq: IRQ for this DMA channel
65 * assigned: set to 1 if that DMA channel is assigned to a substream
68 dma_addr_t ssi_stx_phys;
69 dma_addr_t ssi_srx_phys;
70 struct ccsr_dma_channel __iomem *dma_channel[2];
72 unsigned int assigned[2];
76 * The number of DMA links to use. Two is the bare minimum, but if you
77 * have really small links you might need more.
79 #define NUM_DMA_LINKS 2
81 /** fsl_dma_private: p-substream DMA data
83 * Each substream has a 1-to-1 association with a DMA channel.
85 * The link[] array is first because it needs to be aligned on a 32-byte
86 * boundary, so putting it first will ensure alignment without padding the
89 * @link[]: array of link descriptors
90 * @controller_id: which DMA controller (0, 1, ...)
91 * @channel_id: which DMA channel on the controller (0, 1, 2, ...)
92 * @dma_channel: pointer to the DMA channel's registers
93 * @irq: IRQ for this DMA channel
94 * @substream: pointer to the substream object, needed by the ISR
95 * @ssi_sxx_phys: bus address of the STX or SRX register to use
96 * @ld_buf_phys: physical address of the LD buffer
97 * @current_link: index into link[] of the link currently being processed
98 * @dma_buf_phys: physical address of the DMA buffer
99 * @dma_buf_next: physical address of the next period to process
100 * @dma_buf_end: physical address of the byte after the end of the DMA
101 * @buffer period_size: the size of a single period
102 * @num_periods: the number of periods in the DMA buffer
104 struct fsl_dma_private {
105 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
106 unsigned int controller_id;
107 unsigned int channel_id;
108 struct ccsr_dma_channel __iomem *dma_channel;
110 struct snd_pcm_substream *substream;
111 dma_addr_t ssi_sxx_phys;
112 dma_addr_t ld_buf_phys;
113 unsigned int current_link;
114 dma_addr_t dma_buf_phys;
115 dma_addr_t dma_buf_next;
116 dma_addr_t dma_buf_end;
118 unsigned int num_periods;
122 * fsl_dma_hardare: define characteristics of the PCM hardware.
124 * The PCM hardware is the Freescale DMA controller. This structure defines
125 * the capabilities of that hardware.
127 * Since the sampling rate and data format are not controlled by the DMA
128 * controller, we specify no limits for those values. The only exception is
129 * period_bytes_min, which is set to a reasonably low value to prevent the
130 * DMA controller from generating too many interrupts per second.
132 * Since each link descriptor has a 32-bit byte count field, we set
133 * period_bytes_max to the largest 32-bit number. We also have no maximum
136 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a
137 * limitation in the SSI driver requires the sample rates for playback and
138 * capture to be the same.
140 static const struct snd_pcm_hardware fsl_dma_hardware = {
142 .info = SNDRV_PCM_INFO_INTERLEAVED |
143 SNDRV_PCM_INFO_MMAP |
144 SNDRV_PCM_INFO_MMAP_VALID |
145 SNDRV_PCM_INFO_JOINT_DUPLEX,
146 .formats = FSLDMA_PCM_FORMATS,
147 .rates = FSLDMA_PCM_RATES,
150 .period_bytes_min = 512, /* A reasonable limit */
151 .period_bytes_max = (u32) -1,
152 .periods_min = NUM_DMA_LINKS,
153 .periods_max = (unsigned int) -1,
154 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */
158 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
160 * This function should be called by the ISR whenever the DMA controller
161 * halts data transfer.
163 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
167 snd_pcm_stream_lock_irqsave(substream, flags);
169 if (snd_pcm_running(substream))
170 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
172 snd_pcm_stream_unlock_irqrestore(substream, flags);
176 * fsl_dma_update_pointers - update LD pointers to point to the next period
178 * As each period is completed, this function changes the the link
179 * descriptor pointers for that period to point to the next period.
181 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
183 struct fsl_dma_link_descriptor *link =
184 &dma_private->link[dma_private->current_link];
186 /* Update our link descriptors to point to the next period */
187 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
189 cpu_to_be32(dma_private->dma_buf_next);
192 cpu_to_be32(dma_private->dma_buf_next);
194 /* Update our variables for next time */
195 dma_private->dma_buf_next += dma_private->period_size;
197 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
198 dma_private->dma_buf_next = dma_private->dma_buf_phys;
200 if (++dma_private->current_link >= NUM_DMA_LINKS)
201 dma_private->current_link = 0;
205 * fsl_dma_isr: interrupt handler for the DMA controller
207 * @irq: IRQ of the DMA channel
208 * @dev_id: pointer to the dma_private structure for this DMA channel
210 static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
212 struct fsl_dma_private *dma_private = dev_id;
213 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
214 irqreturn_t ret = IRQ_NONE;
217 /* We got an interrupt, so read the status register to see what we
218 were interrupted for.
220 sr = in_be32(&dma_channel->sr);
222 if (sr & CCSR_DMA_SR_TE) {
223 dev_err(dma_private->substream->pcm->card->dev,
224 "DMA transmit error (controller=%u channel=%u irq=%u\n",
225 dma_private->controller_id,
226 dma_private->channel_id, irq);
227 fsl_dma_abort_stream(dma_private->substream);
228 sr2 |= CCSR_DMA_SR_TE;
232 if (sr & CCSR_DMA_SR_CH)
235 if (sr & CCSR_DMA_SR_PE) {
236 dev_err(dma_private->substream->pcm->card->dev,
237 "DMA%u programming error (channel=%u irq=%u)\n",
238 dma_private->controller_id,
239 dma_private->channel_id, irq);
240 fsl_dma_abort_stream(dma_private->substream);
241 sr2 |= CCSR_DMA_SR_PE;
245 if (sr & CCSR_DMA_SR_EOLNI) {
246 sr2 |= CCSR_DMA_SR_EOLNI;
250 if (sr & CCSR_DMA_SR_CB)
253 if (sr & CCSR_DMA_SR_EOSI) {
254 struct snd_pcm_substream *substream = dma_private->substream;
256 /* Tell ALSA we completed a period. */
257 snd_pcm_period_elapsed(substream);
260 * Update our link descriptors to point to the next period. We
261 * only need to do this if the number of periods is not equal to
262 * the number of links.
264 if (dma_private->num_periods != NUM_DMA_LINKS)
265 fsl_dma_update_pointers(dma_private);
267 sr2 |= CCSR_DMA_SR_EOSI;
271 if (sr & CCSR_DMA_SR_EOLSI) {
272 sr2 |= CCSR_DMA_SR_EOLSI;
276 /* Clear the bits that we set */
278 out_be32(&dma_channel->sr, sr2);
284 * fsl_dma_new: initialize this PCM driver.
286 * This function is called when the codec driver calls snd_soc_new_pcms(),
287 * once for each .dai_link in the machine driver's snd_soc_card
290 static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai,
293 static u64 fsl_dma_dmamask = DMA_BIT_MASK(32);
296 if (!card->dev->dma_mask)
297 card->dev->dma_mask = &fsl_dma_dmamask;
299 if (!card->dev->coherent_dma_mask)
300 card->dev->coherent_dma_mask = fsl_dma_dmamask;
302 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev,
303 fsl_dma_hardware.buffer_bytes_max,
304 &pcm->streams[0].substream->dma_buffer);
307 "Can't allocate playback DMA buffer (size=%u)\n",
308 fsl_dma_hardware.buffer_bytes_max);
312 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev,
313 fsl_dma_hardware.buffer_bytes_max,
314 &pcm->streams[1].substream->dma_buffer);
316 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer);
318 "Can't allocate capture DMA buffer (size=%u)\n",
319 fsl_dma_hardware.buffer_bytes_max);
327 * fsl_dma_open: open a new substream.
329 * Each substream has its own DMA buffer.
331 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
332 * descriptors that ping-pong from one period to the next. For example, if
333 * there are six periods and two link descriptors, this is how they look
334 * before playback starts:
336 * The last link descriptor
337 * ____________ points back to the first
346 * _________________________________________
347 * | | | | | | | The DMA buffer is
348 * | | | | | | | divided into 6 parts
349 * |______|______|______|______|______|______|
351 * and here's how they look after the first period is finished playing:
363 * _________________________________________
366 * |______|______|______|______|______|______|
368 * The first link descriptor now points to the third period. The DMA
369 * controller is currently playing the second period. When it finishes, it
370 * will jump back to the first descriptor and play the third period.
372 * There are four reasons we do this:
374 * 1. The only way to get the DMA controller to automatically restart the
375 * transfer when it gets to the end of the buffer is to use chaining
376 * mode. Basic direct mode doesn't offer that feature.
377 * 2. We need to receive an interrupt at the end of every period. The DMA
378 * controller can generate an interrupt at the end of every link transfer
379 * (aka segment). Making each period into a DMA segment will give us the
380 * interrupts we need.
381 * 3. By creating only two link descriptors, regardless of the number of
382 * periods, we do not need to reallocate the link descriptors if the
383 * number of periods changes.
384 * 4. All of the audio data is still stored in a single, contiguous DMA
385 * buffer, which is what ALSA expects. We're just dividing it into
386 * contiguous parts, and creating a link descriptor for each one.
388 static int fsl_dma_open(struct snd_pcm_substream *substream)
390 struct snd_pcm_runtime *runtime = substream->runtime;
391 struct fsl_dma_private *dma_private;
392 struct ccsr_dma_channel __iomem *dma_channel;
393 dma_addr_t ld_buf_phys;
394 u64 temp_link; /* Pointer to next link descriptor */
396 unsigned int channel;
401 * Reject any DMA buffer whose size is not a multiple of the period
402 * size. We need to make sure that the DMA buffer can be evenly divided
405 ret = snd_pcm_hw_constraint_integer(runtime,
406 SNDRV_PCM_HW_PARAM_PERIODS);
408 dev_err(substream->pcm->card->dev, "invalid buffer size\n");
412 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
414 if (dma_global_data.assigned[channel]) {
415 dev_err(substream->pcm->card->dev,
416 "DMA channel already assigned\n");
420 dma_private = dma_alloc_coherent(substream->pcm->dev,
421 sizeof(struct fsl_dma_private), &ld_buf_phys, GFP_KERNEL);
423 dev_err(substream->pcm->card->dev,
424 "can't allocate DMA private data\n");
427 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
428 dma_private->ssi_sxx_phys = dma_global_data.ssi_stx_phys;
430 dma_private->ssi_sxx_phys = dma_global_data.ssi_srx_phys;
432 dma_private->dma_channel = dma_global_data.dma_channel[channel];
433 dma_private->irq = dma_global_data.irq[channel];
434 dma_private->substream = substream;
435 dma_private->ld_buf_phys = ld_buf_phys;
436 dma_private->dma_buf_phys = substream->dma_buffer.addr;
438 /* We only support one DMA controller for now */
439 dma_private->controller_id = 0;
440 dma_private->channel_id = channel;
442 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private);
444 dev_err(substream->pcm->card->dev,
445 "can't register ISR for IRQ %u (ret=%i)\n",
446 dma_private->irq, ret);
447 dma_free_coherent(substream->pcm->dev,
448 sizeof(struct fsl_dma_private),
449 dma_private, dma_private->ld_buf_phys);
453 dma_global_data.assigned[channel] = 1;
455 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
456 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
457 runtime->private_data = dma_private;
459 /* Program the fixed DMA controller parameters */
461 dma_channel = dma_private->dma_channel;
463 temp_link = dma_private->ld_buf_phys +
464 sizeof(struct fsl_dma_link_descriptor);
466 for (i = 0; i < NUM_DMA_LINKS; i++) {
467 struct fsl_dma_link_descriptor *link = &dma_private->link[i];
469 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
470 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
471 link->next = cpu_to_be64(temp_link);
473 temp_link += sizeof(struct fsl_dma_link_descriptor);
475 /* The last link descriptor points to the first */
476 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
478 /* Tell the DMA controller where the first link descriptor is */
479 out_be32(&dma_channel->clndar,
480 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
481 out_be32(&dma_channel->eclndar,
482 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
484 /* The manual says the BCR must be clear before enabling EMP */
485 out_be32(&dma_channel->bcr, 0);
488 * Program the mode register for interrupts, external master control,
489 * and source/destination hold. Also clear the Channel Abort bit.
491 mr = in_be32(&dma_channel->mr) &
492 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
495 * We want External Master Start and External Master Pause enabled,
496 * because the SSI is controlling the DMA controller. We want the DMA
497 * controller to be set up in advance, and then we signal only the SSI
498 * to start transferring.
500 * We want End-Of-Segment Interrupts enabled, because this will generate
501 * an interrupt at the end of each segment (each link descriptor
502 * represents one segment). Each DMA segment is the same thing as an
503 * ALSA period, so this is how we get an interrupt at the end of every
506 * We want Error Interrupt enabled, so that we can get an error if
507 * the DMA controller is mis-programmed somehow.
509 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
512 /* For playback, we want the destination address to be held. For
513 capture, set the source address to be held. */
514 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
515 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
517 out_be32(&dma_channel->mr, mr);
523 * fsl_dma_hw_params: continue initializing the DMA links
525 * This function obtains hardware parameters about the opened stream and
526 * programs the DMA controller accordingly.
528 * Note that due to a quirk of the SSI's STX register, the target address
529 * for the DMA operations depends on the sample size. So we don't program
530 * the dest_addr (for playback -- source_addr for capture) fields in the
531 * link descriptors here. We do that in fsl_dma_prepare()
533 static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
534 struct snd_pcm_hw_params *hw_params)
536 struct snd_pcm_runtime *runtime = substream->runtime;
537 struct fsl_dma_private *dma_private = runtime->private_data;
539 dma_addr_t temp_addr; /* Pointer to next period */
543 /* Get all the parameters we need */
544 size_t buffer_size = params_buffer_bytes(hw_params);
545 size_t period_size = params_period_bytes(hw_params);
547 /* Initialize our DMA tracking variables */
548 dma_private->period_size = period_size;
549 dma_private->num_periods = params_periods(hw_params);
550 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
551 dma_private->dma_buf_next = dma_private->dma_buf_phys +
552 (NUM_DMA_LINKS * period_size);
553 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
554 dma_private->dma_buf_next = dma_private->dma_buf_phys;
557 * The actual address in STX0 (destination for playback, source for
558 * capture) is based on the sample size, but we don't know the sample
559 * size in this function, so we'll have to adjust that later. See
560 * comments in fsl_dma_prepare().
562 * The DMA controller does not have a cache, so the CPU does not
563 * need to tell it to flush its cache. However, the DMA
564 * controller does need to tell the CPU to flush its cache.
565 * That's what the SNOOP bit does.
567 * Also, even though the DMA controller supports 36-bit addressing, for
568 * simplicity we currently support only 32-bit addresses for the audio
571 temp_addr = substream->dma_buffer.addr;
573 for (i = 0; i < NUM_DMA_LINKS; i++) {
574 struct fsl_dma_link_descriptor *link = &dma_private->link[i];
576 link->count = cpu_to_be32(period_size);
578 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
579 link->source_addr = cpu_to_be32(temp_addr);
581 link->dest_addr = cpu_to_be32(temp_addr);
583 temp_addr += period_size;
590 * fsl_dma_prepare - prepare the DMA registers for playback.
592 * This function is called after the specifics of the audio data are known,
593 * i.e. snd_pcm_runtime is initialized.
595 * In this function, we finish programming the registers of the DMA
596 * controller that are dependent on the sample size.
598 * One of the drawbacks with big-endian is that when copying integers of
599 * different sizes to a fixed-sized register, the address to which the
600 * integer must be copied is dependent on the size of the integer.
602 * For example, if P is the address of a 32-bit register, and X is a 32-bit
603 * integer, then X should be copied to address P. However, if X is a 16-bit
604 * integer, then it should be copied to P+2. If X is an 8-bit register,
605 * then it should be copied to P+3.
607 * So for playback of 8-bit samples, the DMA controller must transfer single
608 * bytes from the DMA buffer to the last byte of the STX0 register, i.e.
609 * offset by 3 bytes. For 16-bit samples, the offset is two bytes.
611 * For 24-bit samples, the offset is 1 byte. However, the DMA controller
612 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
613 * and 8 bytes at a time). So we do not support packed 24-bit samples.
614 * 24-bit data must be padded to 32 bits.
616 static int fsl_dma_prepare(struct snd_pcm_substream *substream)
618 struct snd_pcm_runtime *runtime = substream->runtime;
619 struct fsl_dma_private *dma_private = runtime->private_data;
620 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
623 dma_addr_t ssi_sxx_phys; /* Bus address of SSI STX register */
624 unsigned int frame_size; /* Number of bytes per frame */
626 ssi_sxx_phys = dma_private->ssi_sxx_phys;
628 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
629 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
631 switch (runtime->sample_bits) {
633 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
637 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
641 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
644 dev_err(substream->pcm->card->dev,
645 "unsupported sample size %u\n", runtime->sample_bits);
649 frame_size = runtime->frame_bits / 8;
651 * BWC should always be a multiple of the frame size. BWC determines
652 * how many bytes are sent/received before the DMA controller checks the
653 * SSI to see if it needs to stop. For playback, the transmit FIFO can
654 * hold three frames, so we want to send two frames at a time. For
655 * capture, the receive FIFO is triggered when it contains one frame, so
656 * we want to receive one frame at a time.
659 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
660 mr |= CCSR_DMA_MR_BWC(2 * frame_size);
662 mr |= CCSR_DMA_MR_BWC(frame_size);
664 out_be32(&dma_channel->mr, mr);
667 * Program the address of the DMA transfer to/from the SSI.
669 for (i = 0; i < NUM_DMA_LINKS; i++) {
670 struct fsl_dma_link_descriptor *link = &dma_private->link[i];
672 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
673 link->dest_addr = cpu_to_be32(ssi_sxx_phys);
675 link->source_addr = cpu_to_be32(ssi_sxx_phys);
682 * fsl_dma_pointer: determine the current position of the DMA transfer
684 * This function is called by ALSA when ALSA wants to know where in the
685 * stream buffer the hardware currently is.
687 * For playback, the SAR register contains the physical address of the most
688 * recent DMA transfer. For capture, the value is in the DAR register.
690 * The base address of the buffer is stored in the source_addr field of the
691 * first link descriptor.
693 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream)
695 struct snd_pcm_runtime *runtime = substream->runtime;
696 struct fsl_dma_private *dma_private = runtime->private_data;
697 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
699 snd_pcm_uframes_t frames;
701 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
702 position = in_be32(&dma_channel->sar);
704 position = in_be32(&dma_channel->dar);
706 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
709 * If the current address is just past the end of the buffer, wrap it
712 if (frames == runtime->buffer_size)
719 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
721 * Release the resources allocated in fsl_dma_hw_params() and de-program the
724 * This function can be called multiple times.
726 static int fsl_dma_hw_free(struct snd_pcm_substream *substream)
728 struct snd_pcm_runtime *runtime = substream->runtime;
729 struct fsl_dma_private *dma_private = runtime->private_data;
732 struct ccsr_dma_channel __iomem *dma_channel;
734 dma_channel = dma_private->dma_channel;
737 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
738 out_be32(&dma_channel->mr, 0);
740 /* Reset all the other registers */
741 out_be32(&dma_channel->sr, -1);
742 out_be32(&dma_channel->clndar, 0);
743 out_be32(&dma_channel->eclndar, 0);
744 out_be32(&dma_channel->satr, 0);
745 out_be32(&dma_channel->sar, 0);
746 out_be32(&dma_channel->datr, 0);
747 out_be32(&dma_channel->dar, 0);
748 out_be32(&dma_channel->bcr, 0);
749 out_be32(&dma_channel->nlndar, 0);
750 out_be32(&dma_channel->enlndar, 0);
757 * fsl_dma_close: close the stream.
759 static int fsl_dma_close(struct snd_pcm_substream *substream)
761 struct snd_pcm_runtime *runtime = substream->runtime;
762 struct fsl_dma_private *dma_private = runtime->private_data;
763 int dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
766 if (dma_private->irq)
767 free_irq(dma_private->irq, dma_private);
769 if (dma_private->ld_buf_phys) {
770 dma_unmap_single(substream->pcm->dev,
771 dma_private->ld_buf_phys,
772 sizeof(dma_private->link), DMA_TO_DEVICE);
775 /* Deallocate the fsl_dma_private structure */
776 dma_free_coherent(substream->pcm->dev,
777 sizeof(struct fsl_dma_private),
778 dma_private, dma_private->ld_buf_phys);
779 substream->runtime->private_data = NULL;
782 dma_global_data.assigned[dir] = 0;
788 * Remove this PCM driver.
790 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm)
792 struct snd_pcm_substream *substream;
795 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
796 substream = pcm->streams[i].substream;
798 snd_dma_free_pages(&substream->dma_buffer);
799 substream->dma_buffer.area = NULL;
800 substream->dma_buffer.addr = 0;
805 static struct snd_pcm_ops fsl_dma_ops = {
806 .open = fsl_dma_open,
807 .close = fsl_dma_close,
808 .ioctl = snd_pcm_lib_ioctl,
809 .hw_params = fsl_dma_hw_params,
810 .hw_free = fsl_dma_hw_free,
811 .prepare = fsl_dma_prepare,
812 .pointer = fsl_dma_pointer,
815 struct snd_soc_platform fsl_soc_platform = {
817 .pcm_ops = &fsl_dma_ops,
818 .pcm_new = fsl_dma_new,
819 .pcm_free = fsl_dma_free_dma_buffers,
821 EXPORT_SYMBOL_GPL(fsl_soc_platform);
824 * fsl_dma_configure: store the DMA parameters from the fabric driver.
826 * This function is called by the ASoC fabric driver to give us the DMA and
827 * SSI channel information.
829 * Unfortunately, ASoC V1 does make it possible to determine the DMA/SSI
830 * data when a substream is created, so for now we need to store this data
831 * into a global variable. This means that we can only support one DMA
832 * controller, and hence only one SSI.
834 int fsl_dma_configure(struct fsl_dma_info *dma_info)
836 static int initialized;
838 /* We only support one DMA controller for now */
842 dma_global_data.ssi_stx_phys = dma_info->ssi_stx_phys;
843 dma_global_data.ssi_srx_phys = dma_info->ssi_srx_phys;
844 dma_global_data.dma_channel[0] = dma_info->dma_channel[0];
845 dma_global_data.dma_channel[1] = dma_info->dma_channel[1];
846 dma_global_data.irq[0] = dma_info->dma_irq[0];
847 dma_global_data.irq[1] = dma_info->dma_irq[1];
848 dma_global_data.assigned[0] = 0;
849 dma_global_data.assigned[1] = 0;
854 EXPORT_SYMBOL_GPL(fsl_dma_configure);
856 static int __init fsl_soc_platform_init(void)
858 return snd_soc_register_platform(&fsl_soc_platform);
860 module_init(fsl_soc_platform_init);
862 static void __exit fsl_soc_platform_exit(void)
864 snd_soc_unregister_platform(&fsl_soc_platform);
866 module_exit(fsl_soc_platform_exit);
868 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
869 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM module");
870 MODULE_LICENSE("GPL");