Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/driver-2.6
[linux-2.6] / arch / powerpc / platforms / pasemi / setup.c
1 /*
2  * Copyright (C) 2006-2007 PA Semi, Inc
3  *
4  * Authors: Kip Walker, PA Semi
5  *          Olof Johansson, PA Semi
6  *
7  * Maintained by: Olof Johansson <olof@lixom.net>
8  *
9  * Based on arch/powerpc/platforms/maple/setup.c
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  */
24
25 #include <linux/errno.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/console.h>
29 #include <linux/pci.h>
30
31 #include <asm/prom.h>
32 #include <asm/system.h>
33 #include <asm/iommu.h>
34 #include <asm/machdep.h>
35 #include <asm/mpic.h>
36 #include <asm/smp.h>
37 #include <asm/time.h>
38 #include <asm/of_platform.h>
39
40 #include "pasemi.h"
41
42 /* SDC reset register, must be pre-mapped at reset time */
43 static void __iomem *reset_reg;
44
45 /* Various error status registers, must be pre-mapped at MCE time */
46
47 #define MAX_MCE_REGS    32
48 struct mce_regs {
49         char *name;
50         void __iomem *addr;
51 };
52
53 static struct mce_regs mce_regs[MAX_MCE_REGS];
54 static int num_mce_regs;
55
56
57 static void pas_restart(char *cmd)
58 {
59         printk("Restarting...\n");
60         while (1)
61                 out_le32(reset_reg, 0x6000000);
62 }
63
64 #ifdef CONFIG_SMP
65 static DEFINE_SPINLOCK(timebase_lock);
66 static unsigned long timebase;
67
68 static void __devinit pas_give_timebase(void)
69 {
70         spin_lock(&timebase_lock);
71         mtspr(SPRN_TBCTL, TBCTL_FREEZE);
72         isync();
73         timebase = get_tb();
74         spin_unlock(&timebase_lock);
75
76         while (timebase)
77                 barrier();
78         mtspr(SPRN_TBCTL, TBCTL_RESTART);
79 }
80
81 static void __devinit pas_take_timebase(void)
82 {
83         while (!timebase)
84                 smp_rmb();
85
86         spin_lock(&timebase_lock);
87         set_tb(timebase >> 32, timebase & 0xffffffff);
88         timebase = 0;
89         spin_unlock(&timebase_lock);
90 }
91
92 struct smp_ops_t pas_smp_ops = {
93         .probe          = smp_mpic_probe,
94         .message_pass   = smp_mpic_message_pass,
95         .kick_cpu       = smp_generic_kick_cpu,
96         .setup_cpu      = smp_mpic_setup_cpu,
97         .give_timebase  = pas_give_timebase,
98         .take_timebase  = pas_take_timebase,
99 };
100 #endif /* CONFIG_SMP */
101
102 void __init pas_setup_arch(void)
103 {
104 #ifdef CONFIG_SMP
105         /* Setup SMP callback */
106         smp_ops = &pas_smp_ops;
107 #endif
108         /* Lookup PCI hosts */
109         pas_pci_init();
110
111 #ifdef CONFIG_DUMMY_CONSOLE
112         conswitchp = &dummy_con;
113 #endif
114
115         /* Remap SDC register for doing reset */
116         /* XXXOJN This should maybe come out of the device tree */
117         reset_reg = ioremap(0xfc101100, 4);
118 }
119
120 static int __init pas_setup_mce_regs(void)
121 {
122         struct pci_dev *dev;
123         int reg;
124
125         if (!machine_is(pasemi))
126                 return -ENODEV;
127
128         /* Remap various SoC status registers for use by the MCE handler */
129
130         reg = 0;
131
132         dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
133         while (dev && reg < MAX_MCE_REGS) {
134                 mce_regs[reg].name = kasprintf(GFP_KERNEL,
135                                                 "mc%d_mcdebug_errsta", reg);
136                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
137                 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
138                 reg++;
139         }
140
141         dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
142         if (dev && reg+4 < MAX_MCE_REGS) {
143                 mce_regs[reg].name = "iobdbg_IntStatus1";
144                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
145                 reg++;
146                 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
147                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
148                 reg++;
149                 mce_regs[reg].name = "iobiom_IntStatus";
150                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
151                 reg++;
152                 mce_regs[reg].name = "iobiom_IntDbgReg";
153                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
154                 reg++;
155         }
156
157         dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
158         if (dev && reg+2 < MAX_MCE_REGS) {
159                 mce_regs[reg].name = "l2csts_IntStatus";
160                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
161                 reg++;
162                 mce_regs[reg].name = "l2csts_Cnt";
163                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
164                 reg++;
165         }
166
167         num_mce_regs = reg;
168
169         return 0;
170 }
171 device_initcall(pas_setup_mce_regs);
172
173 static __init void pas_init_IRQ(void)
174 {
175         struct device_node *np;
176         struct device_node *root, *mpic_node;
177         unsigned long openpic_addr;
178         const unsigned int *opprop;
179         int naddr, opplen;
180         struct mpic *mpic;
181
182         mpic_node = NULL;
183
184         for_each_node_by_type(np, "interrupt-controller")
185                 if (of_device_is_compatible(np, "open-pic")) {
186                         mpic_node = np;
187                         break;
188                 }
189         if (!mpic_node)
190                 for_each_node_by_type(np, "open-pic") {
191                         mpic_node = np;
192                         break;
193                 }
194         if (!mpic_node) {
195                 printk(KERN_ERR
196                         "Failed to locate the MPIC interrupt controller\n");
197                 return;
198         }
199
200         /* Find address list in /platform-open-pic */
201         root = of_find_node_by_path("/");
202         naddr = of_n_addr_cells(root);
203         opprop = of_get_property(root, "platform-open-pic", &opplen);
204         if (!opprop) {
205                 printk(KERN_ERR "No platform-open-pic property.\n");
206                 of_node_put(root);
207                 return;
208         }
209         openpic_addr = of_read_number(opprop, naddr);
210         printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
211
212         mpic = mpic_alloc(mpic_node, openpic_addr,
213                           MPIC_PRIMARY|MPIC_LARGE_VECTORS|MPIC_WANTS_RESET,
214                           0, 0, " PAS-OPIC  ");
215         BUG_ON(!mpic);
216
217         mpic_assign_isu(mpic, 0, openpic_addr + 0x10000);
218         mpic_init(mpic);
219         of_node_put(mpic_node);
220         of_node_put(root);
221 }
222
223 static void __init pas_progress(char *s, unsigned short hex)
224 {
225         printk("[%04x] : %s\n", hex, s ? s : "");
226 }
227
228
229 static int pas_machine_check_handler(struct pt_regs *regs)
230 {
231         int cpu = smp_processor_id();
232         unsigned long srr0, srr1, dsisr;
233         int dump_slb = 0;
234         int i;
235
236         srr0 = regs->nip;
237         srr1 = regs->msr;
238         dsisr = mfspr(SPRN_DSISR);
239         printk(KERN_ERR "Machine Check on CPU %d\n", cpu);
240         printk(KERN_ERR "SRR0  0x%016lx SRR1 0x%016lx\n", srr0, srr1);
241         printk(KERN_ERR "DSISR 0x%016lx DAR  0x%016lx\n", dsisr, regs->dar);
242         printk(KERN_ERR "BER   0x%016lx MER  0x%016lx\n", mfspr(SPRN_PA6T_BER),
243                 mfspr(SPRN_PA6T_MER));
244         printk(KERN_ERR "IER   0x%016lx DER  0x%016lx\n", mfspr(SPRN_PA6T_IER),
245                 mfspr(SPRN_PA6T_DER));
246         printk(KERN_ERR "Cause:\n");
247
248         if (srr1 & 0x200000)
249                 printk(KERN_ERR "Signalled by SDC\n");
250
251         if (srr1 & 0x100000) {
252                 printk(KERN_ERR "Load/Store detected error:\n");
253                 if (dsisr & 0x8000)
254                         printk(KERN_ERR "D-cache ECC double-bit error or bus error\n");
255                 if (dsisr & 0x4000)
256                         printk(KERN_ERR "LSU snoop response error\n");
257                 if (dsisr & 0x2000) {
258                         printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n");
259                         dump_slb = 1;
260                 }
261                 if (dsisr & 0x1000)
262                         printk(KERN_ERR "Recoverable Duptags\n");
263                 if (dsisr & 0x800)
264                         printk(KERN_ERR "Recoverable D-cache parity error count overflow\n");
265                 if (dsisr & 0x400)
266                         printk(KERN_ERR "TLB parity error count overflow\n");
267         }
268
269         if (srr1 & 0x80000)
270                 printk(KERN_ERR "Bus Error\n");
271
272         if (srr1 & 0x40000) {
273                 printk(KERN_ERR "I-side SLB multiple hit\n");
274                 dump_slb = 1;
275         }
276
277         if (srr1 & 0x20000)
278                 printk(KERN_ERR "I-cache parity error hit\n");
279
280         if (num_mce_regs == 0)
281                 printk(KERN_ERR "No MCE registers mapped yet, can't dump\n");
282         else
283                 printk(KERN_ERR "SoC debug registers:\n");
284
285         for (i = 0; i < num_mce_regs; i++)
286                 printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name,
287                         in_le32(mce_regs[i].addr));
288
289         if (dump_slb) {
290                 unsigned long e, v;
291                 int i;
292
293                 printk(KERN_ERR "slb contents:\n");
294                 for (i = 0; i < SLB_NUM_ENTRIES; i++) {
295                         asm volatile("slbmfee  %0,%1" : "=r" (e) : "r" (i));
296                         asm volatile("slbmfev  %0,%1" : "=r" (v) : "r" (i));
297                         printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v);
298                 }
299         }
300
301
302         /* SRR1[62] is from MSR[62] if recoverable, so pass that back */
303         return !!(srr1 & 0x2);
304 }
305
306 static void __init pas_init_early(void)
307 {
308         iommu_init_early_pasemi();
309 }
310
311 static struct of_device_id pasemi_bus_ids[] = {
312         { .type = "sdc", },
313         {},
314 };
315
316 static int __init pasemi_publish_devices(void)
317 {
318         if (!machine_is(pasemi))
319                 return 0;
320
321         /* Publish OF platform devices for SDC and other non-PCI devices */
322         of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);
323
324         return 0;
325 }
326 device_initcall(pasemi_publish_devices);
327
328
329 /*
330  * Called very early, MMU is off, device-tree isn't unflattened
331  */
332 static int __init pas_probe(void)
333 {
334         unsigned long root = of_get_flat_dt_root();
335
336         if (!of_flat_dt_is_compatible(root, "PA6T-1682M"))
337                 return 0;
338
339         hpte_init_native();
340
341         alloc_iobmap_l2();
342
343         return 1;
344 }
345
346 define_machine(pasemi) {
347         .name                   = "PA Semi PA6T-1682M",
348         .probe                  = pas_probe,
349         .setup_arch             = pas_setup_arch,
350         .init_early             = pas_init_early,
351         .init_IRQ               = pas_init_IRQ,
352         .get_irq                = mpic_get_irq,
353         .restart                = pas_restart,
354         .get_boot_time          = pas_get_boot_time,
355         .calibrate_decr         = generic_calibrate_decr,
356         .progress               = pas_progress,
357         .machine_check_exception = pas_machine_check_handler,
358 };