2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
8 * Copyright (C) 2001 Florian Lohoff (flo@rfc822.org)
9 * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
11 * (In all truth, Jed Schimmel wrote all this code.)
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/types.h>
17 #include <linux/blkdev.h>
18 #include <linux/delay.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/spinlock.h>
23 #include <asm/pgtable.h>
24 #include <asm/sgialib.h>
25 #include <asm/sgi/sgi.h>
26 #include <asm/sgi/mc.h>
27 #include <asm/sgi/hpc3.h>
28 #include <asm/sgi/ip22.h>
33 #include <scsi/scsi_host.h>
36 #include <linux/stat.h>
39 #define DPRINTK(args...) printk(args)
41 #define DPRINTK(args...)
44 #define HDATA(ptr) ((struct ip22_hostdata *)((ptr)->hostdata))
46 struct ip22_hostdata {
47 struct WD33C93_hostdata wh;
55 struct hpc_dma_desc desc;
56 u32 _padding; /* align to quadword boundary */
59 struct Scsi_Host *sgiwd93_host;
60 struct Scsi_Host *sgiwd93_host1;
62 /* Wuff wuff, wuff, wd33c93.c, wuff wuff, object oriented, bow wow. */
63 static inline void write_wd33c93_count(const wd33c93_regs regs,
66 *regs.SASR = WD_TRANSFER_COUNT_MSB;
68 *regs.SCMD = ((value >> 16) & 0xff);
69 *regs.SCMD = ((value >> 8) & 0xff);
70 *regs.SCMD = ((value >> 0) & 0xff);
74 static inline unsigned long read_wd33c93_count(const wd33c93_regs regs)
78 *regs.SASR = WD_TRANSFER_COUNT_MSB;
80 value = ((*regs.SCMD & 0xff) << 16);
81 value |= ((*regs.SCMD & 0xff) << 8);
82 value |= ((*regs.SCMD & 0xff) << 0);
87 static irqreturn_t sgiwd93_intr(int irq, void *dev_id)
89 struct Scsi_Host * host = (struct Scsi_Host *) dev_id;
92 spin_lock_irqsave(host->host_lock, flags);
94 spin_unlock_irqrestore(host->host_lock, flags);
100 void fill_hpc_entries(struct hpc_chunk *hcp, struct scsi_cmnd *cmd, int datainp)
102 unsigned long len = cmd->SCp.this_residual;
103 void *addr = cmd->SCp.ptr;
107 physaddr = dma_map_single(NULL, addr, len, cmd->sc_data_direction);
108 cmd->SCp.dma_handle = physaddr;
112 * even cntinfo could be up to 16383, without
113 * magic only 8192 works correctly
115 count = len > 8192 ? 8192 : len;
116 hcp->desc.pbuf = physaddr;
117 hcp->desc.cntinfo = count;
124 * To make sure, if we trip an HPC bug, that we transfer every single
125 * byte, we tag on an extra zero length dma descriptor at the end of
129 hcp->desc.cntinfo = HPCDMA_EOX;
132 static int dma_setup(struct scsi_cmnd *cmd, int datainp)
134 struct ip22_hostdata *hdata = HDATA(cmd->device->host);
135 struct hpc3_scsiregs *hregs =
136 (struct hpc3_scsiregs *) cmd->device->host->base;
137 struct hpc_chunk *hcp = (struct hpc_chunk *) hdata->hd.cpu;
139 DPRINTK("dma_setup: datainp<%d> hcp<%p> ", datainp, hcp);
141 hdata->wh.dma_dir = datainp;
144 * wd33c93 shouldn't pass us bogus dma_setups, but it does:-( The
145 * other wd33c93 drivers deal with it the same way (which isn't that
146 * obvious). IMHO a better fix would be, not to do these dma setups
147 * in the first place.
149 if (cmd->SCp.ptr == NULL || cmd->SCp.this_residual == 0)
152 fill_hpc_entries(hcp, cmd, datainp);
156 /* Start up the HPC. */
157 hregs->ndptr = hdata->hd.dma;
159 hregs->ctrl = HPC3_SCTRL_ACTIVE;
161 hregs->ctrl = HPC3_SCTRL_ACTIVE | HPC3_SCTRL_DIR;
166 static void dma_stop(struct Scsi_Host *instance, struct scsi_cmnd *SCpnt,
169 struct ip22_hostdata *hdata = HDATA(instance);
170 struct hpc3_scsiregs *hregs;
175 hregs = (struct hpc3_scsiregs *) SCpnt->device->host->base;
177 DPRINTK("dma_stop: status<%d> ", status);
179 /* First stop the HPC and flush it's FIFO. */
180 if (hdata->wh.dma_dir) {
181 hregs->ctrl |= HPC3_SCTRL_FLUSH;
182 while (hregs->ctrl & HPC3_SCTRL_ACTIVE)
186 dma_unmap_single(NULL, SCpnt->SCp.dma_handle, SCpnt->SCp.this_residual,
187 SCpnt->sc_data_direction);
192 void sgiwd93_reset(unsigned long base)
194 struct hpc3_scsiregs *hregs = (struct hpc3_scsiregs *) base;
196 hregs->ctrl = HPC3_SCTRL_CRESET;
201 static inline void init_hpc_chain(struct hpc_data *hd)
203 struct hpc_chunk *hcp = (struct hpc_chunk *) hd->cpu;
204 struct hpc_chunk *dma = (struct hpc_chunk *) hd->dma;
205 unsigned long start, end;
207 start = (unsigned long) hcp;
208 end = start + PAGE_SIZE;
209 while (start < end) {
210 hcp->desc.pnext = (u32) (dma + 1);
211 hcp->desc.cntinfo = HPCDMA_EOX;
213 start += sizeof(struct hpc_chunk);
216 hcp->desc.pnext = hd->dma;
219 static struct Scsi_Host * __init sgiwd93_setup_scsi(
220 struct scsi_host_template *SGIblows, int unit, int irq,
221 struct hpc3_scsiregs *hregs, unsigned char *wdregs)
223 struct ip22_hostdata *hdata;
224 struct Scsi_Host *host;
227 host = scsi_register(SGIblows, sizeof(struct ip22_hostdata));
231 host->base = (unsigned long) hregs;
235 hdata->hd.cpu = dma_alloc_coherent(NULL, PAGE_SIZE, &hdata->hd.dma,
237 if (!hdata->hd.cpu) {
238 printk(KERN_WARNING "sgiwd93: Could not allocate memory for "
239 "host %d buffer.\n", unit);
242 init_hpc_chain(&hdata->hd);
244 regs.SASR = wdregs + 3;
245 regs.SCMD = wdregs + 7;
247 wd33c93_init(host, regs, dma_setup, dma_stop, WD33C93_FS_MHZ(20));
249 if (hdata->wh.no_sync == 0xff)
250 hdata->wh.no_sync = 0;
252 if (request_irq(irq, sgiwd93_intr, 0, "SGI WD93", (void *) host)) {
253 printk(KERN_WARNING "sgiwd93: Could not register irq %d "
254 "for host %d.\n", irq, unit);
260 dma_free_coherent(NULL, PAGE_SIZE, hdata->hd.cpu, hdata->hd.dma);
264 scsi_unregister(host);
269 static int __init sgiwd93_detect(struct scsi_host_template *SGIblows)
273 SGIblows->proc_name = "SGIWD93";
274 sgiwd93_host = sgiwd93_setup_scsi(SGIblows, 0, SGI_WD93_0_IRQ,
276 (unsigned char *)hpc3c0->scsi0_ext);
280 /* Set up second controller on the Indigo2 */
281 if (ip22_is_fullhouse()) {
282 sgiwd93_host1 = sgiwd93_setup_scsi(SGIblows, 1, SGI_WD93_1_IRQ,
284 (unsigned char *)hpc3c0->scsi1_ext);
292 static int sgiwd93_release(struct Scsi_Host *instance)
294 struct ip22_hostdata *hdata = HDATA(instance);
297 if (sgiwd93_host && sgiwd93_host == instance)
298 irq = SGI_WD93_0_IRQ;
299 else if (sgiwd93_host1 && sgiwd93_host1 == instance)
300 irq = SGI_WD93_1_IRQ;
302 free_irq(irq, sgiwd93_intr);
303 dma_free_coherent(NULL, PAGE_SIZE, hdata->hd.cpu, hdata->hd.dma);
309 static int sgiwd93_bus_reset(struct scsi_cmnd *cmd)
311 /* FIXME perform bus-specific reset */
313 /* FIXME 2: kill this function, and let midlayer fallback
314 to the same result, calling wd33c93_host_reset() */
316 spin_lock_irq(cmd->device->host->host_lock);
317 wd33c93_host_reset(cmd);
318 spin_unlock_irq(cmd->device->host->host_lock);
324 * Kludge alert - the SCSI code calls the abort and reset method with int
325 * arguments not with pointers. So this is going to blow up beautyfully
326 * on 64-bit systems with memory outside the compat address spaces.
328 static struct scsi_host_template driver_template = {
329 .proc_name = "SGIWD93",
331 .detect = sgiwd93_detect,
332 .release = sgiwd93_release,
333 .queuecommand = wd33c93_queuecommand,
334 .eh_abort_handler = wd33c93_abort,
335 .eh_bus_reset_handler = sgiwd93_bus_reset,
336 .eh_host_reset_handler = wd33c93_host_reset,
339 .sg_tablesize = SG_ALL,
341 .use_clustering = DISABLE_CLUSTERING,
343 #include "scsi_module.c"