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   1 /* smp.c: Sparc64 SMP support.
   2  *
   3  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/sched.h>
   9 #include <linux/mm.h>
  10 #include <linux/pagemap.h>
  11 #include <linux/threads.h>
  12 #include <linux/smp.h>
  13 #include <linux/smp_lock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/fs.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/cache.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/profile.h>
  24 #include <linux/bootmem.h>
  25
  26 #include <asm/head.h>
  27 #include <asm/ptrace.h>
  28 #include <asm/atomic.h>
  29 #include <asm/tlbflush.h>
  30 #include <asm/mmu_context.h>
  31 #include <asm/cpudata.h>
  32
  33 #include <asm/irq.h>
  34 #include <asm/page.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/oplib.h>
  37 #include <asm/uaccess.h>
  38 #include <asm/timer.h>
  39 #include <asm/starfire.h>
  40 #include <asm/tlb.h>
  41 #include <asm/sections.h>
  42
  43 extern void calibrate_delay(void);
  44
  45 /* Please don't make this stuff initdata!!!  --DaveM */
  46 static unsigned char boot_cpu_id;
  47
  48 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
  49 cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
  50 static cpumask_t smp_commenced_mask;
  51 static cpumask_t cpu_callout_map;
  52
  53 void smp_info(struct seq_file *m)
  54 {
  55         int i;
  56
  57         seq_printf(m, "State:\n");
  58         for (i = 0; i < NR_CPUS; i++) {
  59                 if (cpu_online(i))
  60                         seq_printf(m,
  61                                    "CPU%d:\t\tonline\n", i);
  62         }
  63 }
  64
  65 void smp_bogo(struct seq_file *m)
  66 {
  67         int i;
  68
  69         for (i = 0; i < NR_CPUS; i++)
  70                 if (cpu_online(i))
  71                         seq_printf(m,
  72                                    "Cpu%dBogo\t: %lu.%02lu\n"
  73                                    "Cpu%dClkTck\t: %016lx\n",
  74                                    i, cpu_data(i).udelay_val / (500000/HZ),
  75                                    (cpu_data(i).udelay_val / (5000/HZ)) % 100,
  76                                    i, cpu_data(i).clock_tick);
  77 }
  78
  79 void __init smp_store_cpu_info(int id)
  80 {
  81         int cpu_node, def;
  82
  83         /* multiplier and counter set by
  84            smp_setup_percpu_timer()  */
  85         cpu_data(id).udelay_val                 = loops_per_jiffy;
  86
  87         cpu_find_by_mid(id, &cpu_node);
  88         cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
  89                                                      "clock-frequency", 0);
  90
  91         cpu_data(id).idle_volume                = 1;
  92
  93         def = ((tlb_type == hypervisor) ? (8 * 1024) : (16 * 1024));
  94         cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
  95                                                       def);
  96
  97         def = 32;
  98         cpu_data(id).dcache_line_size =
  99                 prom_getintdefault(cpu_node, "dcache-line-size", def);
 100
 101         def = 16 * 1024;
 102         cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
 103                                                       def);
 104
 105         def = 32;
 106         cpu_data(id).icache_line_size =
 107                 prom_getintdefault(cpu_node, "icache-line-size", def);
 108
 109         def = ((tlb_type == hypervisor) ?
 110                (3 * 1024 * 1024) :
 111                (4 * 1024 * 1024));
 112         cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
 113                                                       def);
 114
 115         def = 64;
 116         cpu_data(id).ecache_line_size =
 117                 prom_getintdefault(cpu_node, "ecache-line-size", def);
 118
 119         printk("CPU[%d]: Caches "
 120                "D[sz(%d):line_sz(%d)] "
 121                "I[sz(%d):line_sz(%d)] "
 122                "E[sz(%d):line_sz(%d)]\n",
 123                id,
 124                cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
 125                cpu_data(id).icache_size, cpu_data(id).icache_line_size,
 126                cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
 127 }
 128
 129 static void smp_setup_percpu_timer(void);
 130
 131 static volatile unsigned long callin_flag = 0;
 132
 133 void __init smp_callin(void)
 134 {
 135         int cpuid = hard_smp_processor_id();
 136
 137         __local_per_cpu_offset = __per_cpu_offset(cpuid);
 138
 139         if (tlb_type == hypervisor)
 140                 sun4v_ktsb_register();
 141
 142         __flush_tlb_all();
 143
 144         smp_setup_percpu_timer();
 145
 146         if (cheetah_pcache_forced_on)
 147                 cheetah_enable_pcache();
 148
 149         local_irq_enable();
 150
 151         calibrate_delay();
 152         smp_store_cpu_info(cpuid);
 153         callin_flag = 1;
 154         __asm__ __volatile__("membar #Sync\n\t"
 155                              "flush  %%g6" : : : "memory");
 156
 157         /* Clear this or we will die instantly when we
 158          * schedule back to this idler...
 159          */
 160         current_thread_info()->new_child = 0;
 161
 162         /* Attach to the address space of init_task. */
 163         atomic_inc(&init_mm.mm_count);
 164         current->active_mm = &init_mm;
 165
 166         while (!cpu_isset(cpuid, smp_commenced_mask))
 167                 rmb();
 168
 169         cpu_set(cpuid, cpu_online_map);
 170
 171         /* idle thread is expected to have preempt disabled */
 172         preempt_disable();
 173 }
 174
 175 void cpu_panic(void)
 176 {
 177         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
 178         panic("SMP bolixed\n");
 179 }
 180
 181 static unsigned long current_tick_offset __read_mostly;
 182
 183 /* This tick register synchronization scheme is taken entirely from
 184  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
 185  *
 186  * The only change I've made is to rework it so that the master
 187  * initiates the synchonization instead of the slave. -DaveM
 188  */
 189
 190 #define MASTER  0
 191 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
 192
 193 #define NUM_ROUNDS      64      /* magic value */
 194 #define NUM_ITERS       5       /* likewise */
 195
 196 static DEFINE_SPINLOCK(itc_sync_lock);
 197 static unsigned long go[SLAVE + 1];
 198
 199 #define DEBUG_TICK_SYNC 0
 200
 201 static inline long get_delta (long *rt, long *master)
 202 {
 203         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
 204         unsigned long tcenter, t0, t1, tm;
 205         unsigned long i;
 206
 207         for (i = 0; i < NUM_ITERS; i++) {
 208                 t0 = tick_ops->get_tick();
 209                 go[MASTER] = 1;
 210                 membar_storeload();
 211                 while (!(tm = go[SLAVE]))
 212                         rmb();
 213                 go[SLAVE] = 0;
 214                 wmb();
 215                 t1 = tick_ops->get_tick();
 216
 217                 if (t1 - t0 < best_t1 - best_t0)
 218                         best_t0 = t0, best_t1 = t1, best_tm = tm;
 219         }
 220
 221         *rt = best_t1 - best_t0;
 222         *master = best_tm - best_t0;
 223
 224         /* average best_t0 and best_t1 without overflow: */
 225         tcenter = (best_t0/2 + best_t1/2);
 226         if (best_t0 % 2 + best_t1 % 2 == 2)
 227                 tcenter++;
 228         return tcenter - best_tm;
 229 }
 230
 231 void smp_synchronize_tick_client(void)
 232 {
 233         long i, delta, adj, adjust_latency = 0, done = 0;
 234         unsigned long flags, rt, master_time_stamp, bound;
 235 #if DEBUG_TICK_SYNC
 236         struct {
 237                 long rt;        /* roundtrip time */
 238                 long master;    /* master's timestamp */
 239                 long diff;      /* difference between midpoint and master's timestamp */
 240                 long lat;       /* estimate of itc adjustment latency */
 241         } t[NUM_ROUNDS];
 242 #endif
 243
 244         go[MASTER] = 1;
 245
 246         while (go[MASTER])
 247                 rmb();
 248
 249         local_irq_save(flags);
 250         {
 251                 for (i = 0; i < NUM_ROUNDS; i++) {
 252                         delta = get_delta(&rt, &master_time_stamp);
 253                         if (delta == 0) {
 254                                 done = 1;       /* let's lock on to this... */
 255                                 bound = rt;
 256                         }
 257
 258                         if (!done) {
 259                                 if (i > 0) {
 260                                         adjust_latency += -delta;
 261                                         adj = -delta + adjust_latency/4;
 262                                 } else
 263                                         adj = -delta;
 264
 265                                 tick_ops->add_tick(adj, current_tick_offset);
 266                         }
 267 #if DEBUG_TICK_SYNC
 268                         t[i].rt = rt;
 269                         t[i].master = master_time_stamp;
 270                         t[i].diff = delta;
 271                         t[i].lat = adjust_latency/4;
 272 #endif
 273                 }
 274         }
 275         local_irq_restore(flags);
 276
 277 #if DEBUG_TICK_SYNC
 278         for (i = 0; i < NUM_ROUNDS; i++)
 279                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
 280                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
 281 #endif
 282
 283         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
 284                "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
 285 }
 286
 287 static void smp_start_sync_tick_client(int cpu);
 288
 289 static void smp_synchronize_one_tick(int cpu)
 290 {
 291         unsigned long flags, i;
 292
 293         go[MASTER] = 0;
 294
 295         smp_start_sync_tick_client(cpu);
 296
 297         /* wait for client to be ready */
 298         while (!go[MASTER])
 299                 rmb();
 300
 301         /* now let the client proceed into his loop */
 302         go[MASTER] = 0;
 303         membar_storeload();
 304
 305         spin_lock_irqsave(&itc_sync_lock, flags);
 306         {
 307                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
 308                         while (!go[MASTER])
 309                                 rmb();
 310                         go[MASTER] = 0;
 311                         wmb();
 312                         go[SLAVE] = tick_ops->get_tick();
 313                         membar_storeload();
 314                 }
 315         }
 316         spin_unlock_irqrestore(&itc_sync_lock, flags);
 317 }
 318
 319 extern unsigned long sparc64_cpu_startup;
 320
 321 /* The OBP cpu startup callback truncates the 3rd arg cookie to
 322  * 32-bits (I think) so to be safe we have it read the pointer
 323  * contained here so we work on >4GB machines. -DaveM
 324  */
 325 static struct thread_info *cpu_new_thread = NULL;
 326
 327 static int __devinit smp_boot_one_cpu(unsigned int cpu)
 328 {
 329         unsigned long entry =
 330                 (unsigned long)(&sparc64_cpu_startup);
 331         unsigned long cookie =
 332                 (unsigned long)(&cpu_new_thread);
 333         struct task_struct *p;
 334         int timeout, ret, cpu_node;
 335
 336         p = fork_idle(cpu);
 337         callin_flag = 0;
 338         cpu_new_thread = task_thread_info(p);
 339         cpu_set(cpu, cpu_callout_map);
 340
 341         cpu_find_by_mid(cpu, &cpu_node);
 342         prom_startcpu(cpu_node, entry, cookie);
 343
 344         for (timeout = 0; timeout < 5000000; timeout++) {
 345                 if (callin_flag)
 346                         break;
 347                 udelay(100);
 348         }
 349         if (callin_flag) {
 350                 ret = 0;
 351         } else {
 352                 printk("Processor %d is stuck.\n", cpu);
 353                 cpu_clear(cpu, cpu_callout_map);
 354                 ret = -ENODEV;
 355         }
 356         cpu_new_thread = NULL;
 357
 358         return ret;
 359 }
 360
 361 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
 362 {
 363         u64 result, target;
 364         int stuck, tmp;
 365
 366         if (this_is_starfire) {
 367                 /* map to real upaid */
 368                 cpu = (((cpu & 0x3c) << 1) |
 369                         ((cpu & 0x40) >> 4) |
 370                         (cpu & 0x3));
 371         }
 372
 373         target = (cpu << 14) | 0x70;
 374 again:
 375         /* Ok, this is the real Spitfire Errata #54.
 376          * One must read back from a UDB internal register
 377          * after writes to the UDB interrupt dispatch, but
 378          * before the membar Sync for that write.
 379          * So we use the high UDB control register (ASI 0x7f,
 380          * ADDR 0x20) for the dummy read. -DaveM
 381          */
 382         tmp = 0x40;
 383         __asm__ __volatile__(
 384         "wrpr   %1, %2, %%pstate\n\t"
 385         "stxa   %4, [%0] %3\n\t"
 386         "stxa   %5, [%0+%8] %3\n\t"
 387         "add    %0, %8, %0\n\t"
 388         "stxa   %6, [%0+%8] %3\n\t"
 389         "membar #Sync\n\t"
 390         "stxa   %%g0, [%7] %3\n\t"
 391         "membar #Sync\n\t"
 392         "mov    0x20, %%g1\n\t"
 393         "ldxa   [%%g1] 0x7f, %%g0\n\t"
 394         "membar #Sync"
 395         : "=r" (tmp)
 396         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
 397           "r" (data0), "r" (data1), "r" (data2), "r" (target),
 398           "r" (0x10), "0" (tmp)
 399         : "g1");
 400
 401         /* NOTE: PSTATE_IE is still clear. */
 402         stuck = 100000;
 403         do {
 404                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 405                         : "=r" (result)
 406                         : "i" (ASI_INTR_DISPATCH_STAT));
 407                 if (result == 0) {
 408                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 409                                              : : "r" (pstate));
 410                         return;
 411                 }
 412                 stuck -= 1;
 413                 if (stuck == 0)
 414                         break;
 415         } while (result & 0x1);
 416         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 417                              : : "r" (pstate));
 418         if (stuck == 0) {
 419                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 420                        smp_processor_id(), result);
 421         } else {
 422                 udelay(2);
 423                 goto again;
 424         }
 425 }
 426
 427 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 428 {
 429         u64 pstate;
 430         int i;
 431
 432         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 433         for_each_cpu_mask(i, mask)
 434                 spitfire_xcall_helper(data0, data1, data2, pstate, i);
 435 }
 436
 437 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
 438  * packet, but we have no use for that.  However we do take advantage of
 439  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
 440  */
 441 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 442 {
 443         u64 pstate, ver;
 444         int nack_busy_id, is_jbus;
 445
 446         if (cpus_empty(mask))
 447                 return;
 448
 449         /* Unfortunately, someone at Sun had the brilliant idea to make the
 450          * busy/nack fields hard-coded by ITID number for this Ultra-III
 451          * derivative processor.
 452          */
 453         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 454         is_jbus = ((ver >> 32) == __JALAPENO_ID ||
 455                    (ver >> 32) == __SERRANO_ID);
 456
 457         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 458
 459 retry:
 460         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
 461                              : : "r" (pstate), "i" (PSTATE_IE));
 462
 463         /* Setup the dispatch data registers. */
 464         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
 465                              "stxa      %1, [%4] %6\n\t"
 466                              "stxa      %2, [%5] %6\n\t"
 467                              "membar    #Sync\n\t"
 468                              : /* no outputs */
 469                              : "r" (data0), "r" (data1), "r" (data2),
 470                                "r" (0x40), "r" (0x50), "r" (0x60),
 471                                "i" (ASI_INTR_W));
 472
 473         nack_busy_id = 0;
 474         {
 475                 int i;
 476
 477                 for_each_cpu_mask(i, mask) {
 478                         u64 target = (i << 14) | 0x70;
 479
 480                         if (!is_jbus)
 481                                 target |= (nack_busy_id << 24);
 482                         __asm__ __volatile__(
 483                                 "stxa   %%g0, [%0] %1\n\t"
 484                                 "membar #Sync\n\t"
 485                                 : /* no outputs */
 486                                 : "r" (target), "i" (ASI_INTR_W));
 487                         nack_busy_id++;
 488                 }
 489         }
 490
 491         /* Now, poll for completion. */
 492         {
 493                 u64 dispatch_stat;
 494                 long stuck;
 495
 496                 stuck = 100000 * nack_busy_id;
 497                 do {
 498                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
 499                                              : "=r" (dispatch_stat)
 500                                              : "i" (ASI_INTR_DISPATCH_STAT));
 501                         if (dispatch_stat == 0UL) {
 502                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 503                                                      : : "r" (pstate));
 504                                 return;
 505                         }
 506                         if (!--stuck)
 507                                 break;
 508                 } while (dispatch_stat & 0x5555555555555555UL);
 509
 510                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 511                                      : : "r" (pstate));
 512
 513                 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
 514                         /* Busy bits will not clear, continue instead
 515                          * of freezing up on this cpu.
 516                          */
 517                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 518                                smp_processor_id(), dispatch_stat);
 519                 } else {
 520                         int i, this_busy_nack = 0;
 521
 522                         /* Delay some random time with interrupts enabled
 523                          * to prevent deadlock.
 524                          */
 525                         udelay(2 * nack_busy_id);
 526
 527                         /* Clear out the mask bits for cpus which did not
 528                          * NACK us.
 529                          */
 530                         for_each_cpu_mask(i, mask) {
 531                                 u64 check_mask;
 532
 533                                 if (is_jbus)
 534                                         check_mask = (0x2UL << (2*i));
 535                                 else
 536                                         check_mask = (0x2UL <<
 537                                                       this_busy_nack);
 538                                 if ((dispatch_stat & check_mask) == 0)
 539                                         cpu_clear(i, mask);
 540                                 this_busy_nack += 2;
 541                         }
 542
 543                         goto retry;
 544                 }
 545         }
 546 }
 547
 548 #if 0
 549 /* Multi-cpu list version.  */
 550 static int init_cpu_list(u16 *list, cpumask_t mask)
 551 {
 552         int i, cnt;
 553
 554         cnt = 0;
 555         for_each_cpu_mask(i, mask)
 556                 list[cnt++] = i;
 557
 558         return cnt;
 559 }
 560
 561 static int update_cpu_list(u16 *list, int orig_cnt, cpumask_t mask)
 562 {
 563         int i;
 564
 565         for (i = 0; i < orig_cnt; i++) {
 566                 if (list[i] == 0xffff)
 567                         cpu_clear(i, mask);
 568         }
 569
 570         return init_cpu_list(list, mask);
 571 }
 572
 573 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 574 {
 575         int this_cpu = get_cpu();
 576         struct trap_per_cpu *tb = &trap_block[this_cpu];
 577         u64 *mondo = __va(tb->cpu_mondo_block_pa);
 578         u16 *cpu_list = __va(tb->cpu_list_pa);
 579         int cnt, retries;
 580
 581         mondo[0] = data0;
 582         mondo[1] = data1;
 583         mondo[2] = data2;
 584         wmb();
 585
 586         retries = 0;
 587         cnt = init_cpu_list(cpu_list, mask);
 588         do {
 589                 register unsigned long func __asm__("%o5");
 590                 register unsigned long arg0 __asm__("%o0");
 591                 register unsigned long arg1 __asm__("%o1");
 592                 register unsigned long arg2 __asm__("%o2");
 593
 594                 func = HV_FAST_CPU_MONDO_SEND;
 595                 arg0 = cnt;
 596                 arg1 = tb->cpu_list_pa;
 597                 arg2 = tb->cpu_mondo_block_pa;
 598
 599                 __asm__ __volatile__("ta        %8"
 600                                      : "=&r" (func), "=&r" (arg0),
 601                                        "=&r" (arg1), "=&r" (arg2)
 602                                      : "0" (func), "1" (arg0),
 603                                        "2" (arg1), "3" (arg2),
 604                                        "i" (HV_FAST_TRAP)
 605                                      : "memory");
 606                 if (likely(arg0 == HV_EOK))
 607                         break;
 608
 609                 if (unlikely(++retries > 100)) {
 610                         printk("CPU[%d]: sun4v mondo error %lu\n",
 611                                this_cpu, func);
 612                         break;
 613                 }
 614
 615                 cnt = update_cpu_list(cpu_list, cnt, mask);
 616
 617                 udelay(2 * cnt);
 618         } while (1);
 619
 620         put_cpu();
 621 }
 622 #else
 623 /* Single-cpu list version.  */
 624 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 625 {
 626         int this_cpu = get_cpu();
 627         struct trap_per_cpu *tb = &trap_block[this_cpu];
 628         u64 *mondo = __va(tb->cpu_mondo_block_pa);
 629         u16 *cpu_list = __va(tb->cpu_list_pa);
 630         int i;
 631
 632         mondo[0] = data0;
 633         mondo[1] = data1;
 634         mondo[2] = data2;
 635         wmb();
 636
 637         for_each_cpu_mask(i, mask) {
 638                 int retries = 0;
 639
 640                 do {
 641                         register unsigned long func __asm__("%o5");
 642                         register unsigned long arg0 __asm__("%o0");
 643                         register unsigned long arg1 __asm__("%o1");
 644                         register unsigned long arg2 __asm__("%o2");
 645
 646                         cpu_list[0] = i;
 647                         func = HV_FAST_CPU_MONDO_SEND;
 648                         arg0 = 1;
 649                         arg1 = tb->cpu_list_pa;
 650                         arg2 = tb->cpu_mondo_block_pa;
 651
 652                         __asm__ __volatile__("ta        %8"
 653                                              : "=&r" (func), "=&r" (arg0),
 654                                                "=&r" (arg1), "=&r" (arg2)
 655                                              : "0" (func), "1" (arg0),
 656                                                "2" (arg1), "3" (arg2),
 657                                                "i" (HV_FAST_TRAP)
 658                                              : "memory");
 659                         if (likely(arg0 == HV_EOK))
 660                                 break;
 661
 662                         if (unlikely(++retries > 100)) {
 663                                 printk("CPU[%d]: sun4v mondo error %lu\n",
 664                                        this_cpu, func);
 665                                 break;
 666                         }
 667
 668                         udelay(2 * i);
 669                 } while (1);
 670         }
 671
 672         put_cpu();
 673 }
 674 #endif
 675
 676 /* Send cross call to all processors mentioned in MASK
 677  * except self.
 678  */
 679 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
 680 {
 681         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
 682         int this_cpu = get_cpu();
 683
 684         cpus_and(mask, mask, cpu_online_map);
 685         cpu_clear(this_cpu, mask);
 686
 687         if (tlb_type == spitfire)
 688                 spitfire_xcall_deliver(data0, data1, data2, mask);
 689         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 690                 cheetah_xcall_deliver(data0, data1, data2, mask);
 691         else
 692                 hypervisor_xcall_deliver(data0, data1, data2, mask);
 693         /* NOTE: Caller runs local copy on master. */
 694
 695         put_cpu();
 696 }
 697
 698 extern unsigned long xcall_sync_tick;
 699
 700 static void smp_start_sync_tick_client(int cpu)
 701 {
 702         cpumask_t mask = cpumask_of_cpu(cpu);
 703
 704         smp_cross_call_masked(&xcall_sync_tick,
 705                               0, 0, 0, mask);
 706 }
 707
 708 /* Send cross call to all processors except self. */
 709 #define smp_cross_call(func, ctx, data1, data2) \
 710         smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
 711
 712 struct call_data_struct {
 713         void (*func) (void *info);
 714         void *info;
 715         atomic_t finished;
 716         int wait;
 717 };
 718
 719 static DEFINE_SPINLOCK(call_lock);
 720 static struct call_data_struct *call_data;
 721
 722 extern unsigned long xcall_call_function;
 723
 724 /*
 725  * You must not call this function with disabled interrupts or from a
 726  * hardware interrupt handler or from a bottom half handler.
 727  */
 728 static int smp_call_function_mask(void (*func)(void *info), void *info,
 729                                   int nonatomic, int wait, cpumask_t mask)
 730 {
 731         struct call_data_struct data;
 732         int cpus = cpus_weight(mask) - 1;
 733         long timeout;
 734
 735         if (!cpus)
 736                 return 0;
 737
 738         /* Can deadlock when called with interrupts disabled */
 739         WARN_ON(irqs_disabled());
 740
 741         data.func = func;
 742         data.info = info;
 743         atomic_set(&data.finished, 0);
 744         data.wait = wait;
 745
 746         spin_lock(&call_lock);
 747
 748         call_data = &data;
 749
 750         smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
 751
 752         /*
 753          * Wait for other cpus to complete function or at
 754          * least snap the call data.
 755          */
 756         timeout = 1000000;
 757         while (atomic_read(&data.finished) != cpus) {
 758                 if (--timeout <= 0)
 759                         goto out_timeout;
 760                 barrier();
 761                 udelay(1);
 762         }
 763
 764         spin_unlock(&call_lock);
 765
 766         return 0;
 767
 768 out_timeout:
 769         spin_unlock(&call_lock);
 770         printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n",
 771                (long) num_online_cpus() - 1L,
 772                (long) atomic_read(&data.finished));
 773         return 0;
 774 }
 775
 776 int smp_call_function(void (*func)(void *info), void *info,
 777                       int nonatomic, int wait)
 778 {
 779         return smp_call_function_mask(func, info, nonatomic, wait,
 780                                       cpu_online_map);
 781 }
 782
 783 void smp_call_function_client(int irq, struct pt_regs *regs)
 784 {
 785         void (*func) (void *info) = call_data->func;
 786         void *info = call_data->info;
 787
 788         clear_softint(1 << irq);
 789         if (call_data->wait) {
 790                 /* let initiator proceed only after completion */
 791                 func(info);
 792                 atomic_inc(&call_data->finished);
 793         } else {
 794                 /* let initiator proceed after getting data */
 795                 atomic_inc(&call_data->finished);
 796                 func(info);
 797         }
 798 }
 799
 800 static void tsb_sync(void *info)
 801 {
 802         struct mm_struct *mm = info;
 803
 804         if (current->active_mm == mm)
 805                 tsb_context_switch(mm);
 806 }
 807
 808 void smp_tsb_sync(struct mm_struct *mm)
 809 {
 810         smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
 811 }
 812
 813 extern unsigned long xcall_flush_tlb_mm;
 814 extern unsigned long xcall_flush_tlb_pending;
 815 extern unsigned long xcall_flush_tlb_kernel_range;
 816 extern unsigned long xcall_report_regs;
 817 extern unsigned long xcall_receive_signal;
 818
 819 #ifdef DCACHE_ALIASING_POSSIBLE
 820 extern unsigned long xcall_flush_dcache_page_cheetah;
 821 #endif
 822 extern unsigned long xcall_flush_dcache_page_spitfire;
 823
 824 #ifdef CONFIG_DEBUG_DCFLUSH
 825 extern atomic_t dcpage_flushes;
 826 extern atomic_t dcpage_flushes_xcall;
 827 #endif
 828
 829 static __inline__ void __local_flush_dcache_page(struct page *page)
 830 {
 831 #ifdef DCACHE_ALIASING_POSSIBLE
 832         __flush_dcache_page(page_address(page),
 833                             ((tlb_type == spitfire) &&
 834                              page_mapping(page) != NULL));
 835 #else
 836         if (page_mapping(page) != NULL &&
 837             tlb_type == spitfire)
 838                 __flush_icache_page(__pa(page_address(page)));
 839 #endif
 840 }
 841
 842 void smp_flush_dcache_page_impl(struct page *page, int cpu)
 843 {
 844         cpumask_t mask = cpumask_of_cpu(cpu);
 845         int this_cpu;
 846
 847         if (tlb_type == hypervisor)
 848                 return;
 849
 850 #ifdef CONFIG_DEBUG_DCFLUSH
 851         atomic_inc(&dcpage_flushes);
 852 #endif
 853
 854         this_cpu = get_cpu();
 855
 856         if (cpu == this_cpu) {
 857                 __local_flush_dcache_page(page);
 858         } else if (cpu_online(cpu)) {
 859                 void *pg_addr = page_address(page);
 860                 u64 data0;
 861
 862                 if (tlb_type == spitfire) {
 863                         data0 =
 864                                 ((u64)&xcall_flush_dcache_page_spitfire);
 865                         if (page_mapping(page) != NULL)
 866                                 data0 |= ((u64)1 << 32);
 867                         spitfire_xcall_deliver(data0,
 868                                                __pa(pg_addr),
 869                                                (u64) pg_addr,
 870                                                mask);
 871                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 872 #ifdef DCACHE_ALIASING_POSSIBLE
 873                         data0 =
 874                                 ((u64)&xcall_flush_dcache_page_cheetah);
 875                         cheetah_xcall_deliver(data0,
 876                                               __pa(pg_addr),
 877                                               0, mask);
 878 #endif
 879                 }
 880 #ifdef CONFIG_DEBUG_DCFLUSH
 881                 atomic_inc(&dcpage_flushes_xcall);
 882 #endif
 883         }
 884
 885         put_cpu();
 886 }
 887
 888 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
 889 {
 890         void *pg_addr = page_address(page);
 891         cpumask_t mask = cpu_online_map;
 892         u64 data0;
 893         int this_cpu;
 894
 895         if (tlb_type == hypervisor)
 896                 return;
 897
 898         this_cpu = get_cpu();
 899
 900         cpu_clear(this_cpu, mask);
 901
 902 #ifdef CONFIG_DEBUG_DCFLUSH
 903         atomic_inc(&dcpage_flushes);
 904 #endif
 905         if (cpus_empty(mask))
 906                 goto flush_self;
 907         if (tlb_type == spitfire) {
 908                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 909                 if (page_mapping(page) != NULL)
 910                         data0 |= ((u64)1 << 32);
 911                 spitfire_xcall_deliver(data0,
 912                                        __pa(pg_addr),
 913                                        (u64) pg_addr,
 914                                        mask);
 915         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 916 #ifdef DCACHE_ALIASING_POSSIBLE
 917                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 918                 cheetah_xcall_deliver(data0,
 919                                       __pa(pg_addr),
 920                                       0, mask);
 921 #endif
 922         }
 923 #ifdef CONFIG_DEBUG_DCFLUSH
 924         atomic_inc(&dcpage_flushes_xcall);
 925 #endif
 926  flush_self:
 927         __local_flush_dcache_page(page);
 928
 929         put_cpu();
 930 }
 931
 932 void smp_receive_signal(int cpu)
 933 {
 934         cpumask_t mask = cpumask_of_cpu(cpu);
 935
 936         if (cpu_online(cpu)) {
 937                 u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff);
 938
 939                 if (tlb_type == spitfire)
 940                         spitfire_xcall_deliver(data0, 0, 0, mask);
 941                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 942                         cheetah_xcall_deliver(data0, 0, 0, mask);
 943                 else if (tlb_type == hypervisor)
 944                         hypervisor_xcall_deliver(data0, 0, 0, mask);
 945         }
 946 }
 947
 948 void smp_receive_signal_client(int irq, struct pt_regs *regs)
 949 {
 950         /* Just return, rtrap takes care of the rest. */
 951         clear_softint(1 << irq);
 952 }
 953
 954 void smp_report_regs(void)
 955 {
 956         smp_cross_call(&xcall_report_regs, 0, 0, 0);
 957 }
 958
 959 /* We know that the window frames of the user have been flushed
 960  * to the stack before we get here because all callers of us
 961  * are flush_tlb_*() routines, and these run after flush_cache_*()
 962  * which performs the flushw.
 963  *
 964  * The SMP TLB coherency scheme we use works as follows:
 965  *
 966  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
 967  *    space has (potentially) executed on, this is the heuristic
 968  *    we use to avoid doing cross calls.
 969  *
 970  *    Also, for flushing from kswapd and also for clones, we
 971  *    use cpu_vm_mask as the list of cpus to make run the TLB.
 972  *
 973  * 2) TLB context numbers are shared globally across all processors
 974  *    in the system, this allows us to play several games to avoid
 975  *    cross calls.
 976  *
 977  *    One invariant is that when a cpu switches to a process, and
 978  *    that processes tsk->active_mm->cpu_vm_mask does not have the
 979  *    current cpu's bit set, that tlb context is flushed locally.
 980  *
 981  *    If the address space is non-shared (ie. mm->count == 1) we avoid
 982  *    cross calls when we want to flush the currently running process's
 983  *    tlb state.  This is done by clearing all cpu bits except the current
 984  *    processor's in current->active_mm->cpu_vm_mask and performing the
 985  *    flush locally only.  This will force any subsequent cpus which run
 986  *    this task to flush the context from the local tlb if the process
 987  *    migrates to another cpu (again).
 988  *
 989  * 3) For shared address spaces (threads) and swapping we bite the
 990  *    bullet for most cases and perform the cross call (but only to
 991  *    the cpus listed in cpu_vm_mask).
 992  *
 993  *    The performance gain from "optimizing" away the cross call for threads is
 994  *    questionable (in theory the big win for threads is the massive sharing of
 995  *    address space state across processors).
 996  */
 997
 998 /* This currently is only used by the hugetlb arch pre-fault
 999  * hook on UltraSPARC-III+ and later when changing the pagesize
1000  * bits of the context register for an address space.
1001  */
1002 void smp_flush_tlb_mm(struct mm_struct *mm)
1003 {
1004         u32 ctx = CTX_HWBITS(mm->context);
1005         int cpu = get_cpu();
1006
1007         if (atomic_read(&mm->mm_users) == 1) {
1008                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1009                 goto local_flush_and_out;
1010         }
1011
1012         smp_cross_call_masked(&xcall_flush_tlb_mm,
1013                               ctx, 0, 0,
1014                               mm->cpu_vm_mask);
1015
1016 local_flush_and_out:
1017         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1018
1019         put_cpu();
1020 }
1021
1022 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1023 {
1024         u32 ctx = CTX_HWBITS(mm->context);
1025         int cpu = get_cpu();
1026
1027         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1028                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1029         else
1030                 smp_cross_call_masked(&xcall_flush_tlb_pending,
1031                                       ctx, nr, (unsigned long) vaddrs,
1032                                       mm->cpu_vm_mask);
1033
1034         __flush_tlb_pending(ctx, nr, vaddrs);
1035
1036         put_cpu();
1037 }
1038
1039 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1040 {
1041         start &= PAGE_MASK;
1042         end    = PAGE_ALIGN(end);
1043         if (start != end) {
1044                 smp_cross_call(&xcall_flush_tlb_kernel_range,
1045                                0, start, end);
1046
1047                 __flush_tlb_kernel_range(start, end);
1048         }
1049 }
1050
1051 /* CPU capture. */
1052 /* #define CAPTURE_DEBUG */
1053 extern unsigned long xcall_capture;
1054
1055 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1056 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1057 static unsigned long penguins_are_doing_time;
1058
1059 void smp_capture(void)
1060 {
1061         int result = atomic_add_ret(1, &smp_capture_depth);
1062
1063         if (result == 1) {
1064                 int ncpus = num_online_cpus();
1065
1066 #ifdef CAPTURE_DEBUG
1067                 printk("CPU[%d]: Sending penguins to jail...",
1068                        smp_processor_id());
1069 #endif
1070                 penguins_are_doing_time = 1;
1071                 membar_storestore_loadstore();
1072                 atomic_inc(&smp_capture_registry);
1073                 smp_cross_call(&xcall_capture, 0, 0, 0);
1074                 while (atomic_read(&smp_capture_registry) != ncpus)
1075                         rmb();
1076 #ifdef CAPTURE_DEBUG
1077                 printk("done\n");
1078 #endif
1079         }
1080 }
1081
1082 void smp_release(void)
1083 {
1084         if (atomic_dec_and_test(&smp_capture_depth)) {
1085 #ifdef CAPTURE_DEBUG
1086                 printk("CPU[%d]: Giving pardon to "
1087                        "imprisoned penguins\n",
1088                        smp_processor_id());
1089 #endif
1090                 penguins_are_doing_time = 0;
1091                 membar_storeload_storestore();
1092                 atomic_dec(&smp_capture_registry);
1093         }
1094 }
1095
1096 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1097  * can service tlb flush xcalls...
1098  */
1099 extern void prom_world(int);
1100
1101 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1102 {
1103         clear_softint(1 << irq);
1104
1105         preempt_disable();
1106
1107         __asm__ __volatile__("flushw");
1108         prom_world(1);
1109         atomic_inc(&smp_capture_registry);
1110         membar_storeload_storestore();
1111         while (penguins_are_doing_time)
1112                 rmb();
1113         atomic_dec(&smp_capture_registry);
1114         prom_world(0);
1115
1116         preempt_enable();
1117 }
1118
1119 #define prof_multiplier(__cpu)          cpu_data(__cpu).multiplier
1120 #define prof_counter(__cpu)             cpu_data(__cpu).counter
1121
1122 void smp_percpu_timer_interrupt(struct pt_regs *regs)
1123 {
1124         unsigned long compare, tick, pstate;
1125         int cpu = smp_processor_id();
1126         int user = user_mode(regs);
1127
1128         /*
1129          * Check for level 14 softint.
1130          */
1131         {
1132                 unsigned long tick_mask = tick_ops->softint_mask;
1133
1134                 if (!(get_softint() & tick_mask)) {
1135                         extern void handler_irq(int, struct pt_regs *);
1136
1137                         handler_irq(14, regs);
1138                         return;
1139                 }
1140                 clear_softint(tick_mask);
1141         }
1142
1143         do {
1144                 profile_tick(CPU_PROFILING, regs);
1145                 if (!--prof_counter(cpu)) {
1146                         irq_enter();
1147
1148                         if (cpu == boot_cpu_id) {
1149                                 kstat_this_cpu.irqs[0]++;
1150                                 timer_tick_interrupt(regs);
1151                         }
1152
1153                         update_process_times(user);
1154
1155                         irq_exit();
1156
1157                         prof_counter(cpu) = prof_multiplier(cpu);
1158                 }
1159
1160                 /* Guarantee that the following sequences execute
1161                  * uninterrupted.
1162                  */
1163                 __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1164                                      "wrpr      %0, %1, %%pstate"
1165                                      : "=r" (pstate)
1166                                      : "i" (PSTATE_IE));
1167
1168                 compare = tick_ops->add_compare(current_tick_offset);
1169                 tick = tick_ops->get_tick();
1170
1171                 /* Restore PSTATE_IE. */
1172                 __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1173                                      : /* no outputs */
1174                                      : "r" (pstate));
1175         } while (time_after_eq(tick, compare));
1176 }
1177
1178 static void __init smp_setup_percpu_timer(void)
1179 {
1180         int cpu = smp_processor_id();
1181         unsigned long pstate;
1182
1183         prof_counter(cpu) = prof_multiplier(cpu) = 1;
1184
1185         /* Guarantee that the following sequences execute
1186          * uninterrupted.
1187          */
1188         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1189                              "wrpr      %0, %1, %%pstate"
1190                              : "=r" (pstate)
1191                              : "i" (PSTATE_IE));
1192
1193         tick_ops->init_tick(current_tick_offset);
1194
1195         /* Restore PSTATE_IE. */
1196         __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1197                              : /* no outputs */
1198                              : "r" (pstate));
1199 }
1200
1201 void __init smp_tick_init(void)
1202 {
1203         boot_cpu_id = hard_smp_processor_id();
1204         current_tick_offset = timer_tick_offset;
1205
1206         cpu_set(boot_cpu_id, cpu_online_map);
1207         prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
1208 }
1209
1210 /* /proc/profile writes can call this, don't __init it please. */
1211 static DEFINE_SPINLOCK(prof_setup_lock);
1212
1213 int setup_profiling_timer(unsigned int multiplier)
1214 {
1215         unsigned long flags;
1216         int i;
1217
1218         if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
1219                 return -EINVAL;
1220
1221         spin_lock_irqsave(&prof_setup_lock, flags);
1222         for (i = 0; i < NR_CPUS; i++)
1223                 prof_multiplier(i) = multiplier;
1224         current_tick_offset = (timer_tick_offset / multiplier);
1225         spin_unlock_irqrestore(&prof_setup_lock, flags);
1226
1227         return 0;
1228 }
1229
1230 /* Constrain the number of cpus to max_cpus.  */
1231 void __init smp_prepare_cpus(unsigned int max_cpus)
1232 {
1233         if (num_possible_cpus() > max_cpus) {
1234                 int instance, mid;
1235
1236                 instance = 0;
1237                 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1238                         if (mid != boot_cpu_id) {
1239                                 cpu_clear(mid, phys_cpu_present_map);
1240                                 if (num_possible_cpus() <= max_cpus)
1241                                         break;
1242                         }
1243                         instance++;
1244                 }
1245         }
1246
1247         smp_store_cpu_info(boot_cpu_id);
1248 }
1249
1250 /* Set this up early so that things like the scheduler can init
1251  * properly.  We use the same cpu mask for both the present and
1252  * possible cpu map.
1253  */
1254 void __init smp_setup_cpu_possible_map(void)
1255 {
1256         int instance, mid;
1257
1258         instance = 0;
1259         while (!cpu_find_by_instance(instance, NULL, &mid)) {
1260                 if (mid < NR_CPUS)
1261                         cpu_set(mid, phys_cpu_present_map);
1262                 instance++;
1263         }
1264 }
1265
1266 void __devinit smp_prepare_boot_cpu(void)
1267 {
1268         int cpu = hard_smp_processor_id();
1269
1270         if (cpu >= NR_CPUS) {
1271                 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1272                 prom_halt();
1273         }
1274
1275         current_thread_info()->cpu = cpu;
1276         __local_per_cpu_offset = __per_cpu_offset(cpu);
1277
1278         cpu_set(smp_processor_id(), cpu_online_map);
1279         cpu_set(smp_processor_id(), phys_cpu_present_map);
1280 }
1281
1282 int __devinit __cpu_up(unsigned int cpu)
1283 {
1284         int ret = smp_boot_one_cpu(cpu);
1285
1286         if (!ret) {
1287                 cpu_set(cpu, smp_commenced_mask);
1288                 while (!cpu_isset(cpu, cpu_online_map))
1289                         mb();
1290                 if (!cpu_isset(cpu, cpu_online_map)) {
1291                         ret = -ENODEV;
1292                 } else {
1293                         /* On SUN4V, writes to %tick and %stick are
1294                          * not allowed.
1295                          */
1296                         if (tlb_type != hypervisor)
1297                                 smp_synchronize_one_tick(cpu);
1298                 }
1299         }
1300         return ret;
1301 }
1302
1303 void __init smp_cpus_done(unsigned int max_cpus)
1304 {
1305         unsigned long bogosum = 0;
1306         int i;
1307
1308         for (i = 0; i < NR_CPUS; i++) {
1309                 if (cpu_online(i))
1310                         bogosum += cpu_data(i).udelay_val;
1311         }
1312         printk("Total of %ld processors activated "
1313                "(%lu.%02lu BogoMIPS).\n",
1314                (long) num_online_cpus(),
1315                bogosum/(500000/HZ),
1316                (bogosum/(5000/HZ))%100);
1317 }
1318
1319 void smp_send_reschedule(int cpu)
1320 {
1321         smp_receive_signal(cpu);
1322 }
1323
1324 /* This is a nop because we capture all other cpus
1325  * anyways when making the PROM active.
1326  */
1327 void smp_send_stop(void)
1328 {
1329 }
1330
1331 unsigned long __per_cpu_base __read_mostly;
1332 unsigned long __per_cpu_shift __read_mostly;
1333
1334 EXPORT_SYMBOL(__per_cpu_base);
1335 EXPORT_SYMBOL(__per_cpu_shift);
1336
1337 void __init setup_per_cpu_areas(void)
1338 {
1339         unsigned long goal, size, i;
1340         char *ptr;
1341
1342         /* Copy section for each CPU (we discard the original) */
1343         goal = ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES);
1344 #ifdef CONFIG_MODULES
1345         if (goal < PERCPU_ENOUGH_ROOM)
1346                 goal = PERCPU_ENOUGH_ROOM;
1347 #endif
1348         __per_cpu_shift = 0;
1349         for (size = 1UL; size < goal; size <<= 1UL)
1350                 __per_cpu_shift++;
1351
1352         ptr = alloc_bootmem(size * NR_CPUS);
1353
1354         __per_cpu_base = ptr - __per_cpu_start;
1355
1356         for (i = 0; i < NR_CPUS; i++, ptr += size)
1357                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1358 }