2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/config.h>
6 #include <linux/kernel.h>
8 #include <linux/delay.h>
9 #include <linux/string.h>
10 #include <linux/init.h>
11 #include <linux/capability.h>
12 #include <linux/sched.h>
13 #include <linux/errno.h>
14 #include <linux/bootmem.h>
16 #include <asm/processor.h>
19 #include <asm/sections.h>
20 #include <asm/pci-bridge.h>
21 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
28 #define DBG(x...) printk(x)
33 unsigned long isa_io_base = 0;
34 unsigned long isa_mem_base = 0;
35 unsigned long pci_dram_offset = 0;
36 int pcibios_assign_bus_offset = 1;
38 void pcibios_make_OF_bus_map(void);
40 static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
41 static int probe_resource(struct pci_bus *parent, struct resource *pr,
42 struct resource *res, struct resource **conflict);
43 static void update_bridge_base(struct pci_bus *bus, int i);
44 static void pcibios_fixup_resources(struct pci_dev* dev);
45 static void fixup_broken_pcnet32(struct pci_dev* dev);
46 static int reparent_resources(struct resource *parent, struct resource *res);
47 static void fixup_rev1_53c810(struct pci_dev* dev);
48 static void fixup_cpc710_pci64(struct pci_dev* dev);
50 static u8* pci_to_OF_bus_map;
53 /* By default, we don't re-assign bus numbers. We do this only on
56 int pci_assign_all_busses;
58 struct pci_controller* hose_head;
59 struct pci_controller** hose_tail = &hose_head;
61 static int pci_bus_count;
64 fixup_rev1_53c810(struct pci_dev* dev)
66 /* rev 1 ncr53c810 chips don't set the class at all which means
67 * they don't get their resources remapped. Fix that here.
70 if ((dev->class == PCI_CLASS_NOT_DEFINED)) {
71 printk("NCR 53c810 rev 1 detected, setting PCI class.\n");
72 dev->class = PCI_CLASS_STORAGE_SCSI;
75 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
78 fixup_broken_pcnet32(struct pci_dev* dev)
80 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
81 dev->vendor = PCI_VENDOR_ID_AMD;
82 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
85 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
88 fixup_cpc710_pci64(struct pci_dev* dev)
90 /* Hide the PCI64 BARs from the kernel as their content doesn't
91 * fit well in the resource management
93 dev->resource[0].start = dev->resource[0].end = 0;
94 dev->resource[0].flags = 0;
95 dev->resource[1].start = dev->resource[1].end = 0;
96 dev->resource[1].flags = 0;
98 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
101 pcibios_fixup_resources(struct pci_dev *dev)
103 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
105 unsigned long offset;
108 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
111 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
112 struct resource *res = dev->resource + i;
115 if (res->end == 0xffffffff) {
116 DBG("PCI:%s Resource %d [%08lx-%08lx] is unassigned\n",
117 pci_name(dev), i, res->start, res->end);
118 res->end -= res->start;
120 res->flags |= IORESOURCE_UNSET;
124 if (res->flags & IORESOURCE_MEM) {
125 offset = hose->pci_mem_offset;
126 } else if (res->flags & IORESOURCE_IO) {
127 offset = (unsigned long) hose->io_base_virt
131 res->start += offset;
134 printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n",
135 i, res->flags, pci_name(dev),
136 res->start - offset, res->start);
141 /* Call machine specific resource fixup */
142 if (ppc_md.pcibios_fixup_resources)
143 ppc_md.pcibios_fixup_resources(dev);
145 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
147 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
148 struct resource *res)
150 unsigned long offset = 0;
151 struct pci_controller *hose = dev->sysdata;
153 if (hose && res->flags & IORESOURCE_IO)
154 offset = (unsigned long)hose->io_base_virt - isa_io_base;
155 else if (hose && res->flags & IORESOURCE_MEM)
156 offset = hose->pci_mem_offset;
157 region->start = res->start - offset;
158 region->end = res->end - offset;
160 EXPORT_SYMBOL(pcibios_resource_to_bus);
162 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
163 struct pci_bus_region *region)
165 unsigned long offset = 0;
166 struct pci_controller *hose = dev->sysdata;
168 if (hose && res->flags & IORESOURCE_IO)
169 offset = (unsigned long)hose->io_base_virt - isa_io_base;
170 else if (hose && res->flags & IORESOURCE_MEM)
171 offset = hose->pci_mem_offset;
172 res->start = region->start + offset;
173 res->end = region->end + offset;
175 EXPORT_SYMBOL(pcibios_bus_to_resource);
178 * We need to avoid collisions with `mirrored' VGA ports
179 * and other strange ISA hardware, so we always want the
180 * addresses to be allocated in the 0x000-0x0ff region
183 * Why? Because some silly external IO cards only decode
184 * the low 10 bits of the IO address. The 0x00-0xff region
185 * is reserved for motherboard devices that decode all 16
186 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
187 * but we want to try to avoid allocating at 0x2900-0x2bff
188 * which might have be mirrored at 0x0100-0x03ff..
190 void pcibios_align_resource(void *data, struct resource *res, unsigned long size,
193 struct pci_dev *dev = data;
195 if (res->flags & IORESOURCE_IO) {
196 unsigned long start = res->start;
199 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
200 " (%ld bytes)\n", pci_name(dev),
201 dev->resource - res, size);
205 start = (start + 0x3ff) & ~0x3ff;
210 EXPORT_SYMBOL(pcibios_align_resource);
213 * Handle resources of PCI devices. If the world were perfect, we could
214 * just allocate all the resource regions and do nothing more. It isn't.
215 * On the other hand, we cannot just re-allocate all devices, as it would
216 * require us to know lots of host bridge internals. So we attempt to
217 * keep as much of the original configuration as possible, but tweak it
218 * when it's found to be wrong.
220 * Known BIOS problems we have to work around:
221 * - I/O or memory regions not configured
222 * - regions configured, but not enabled in the command register
223 * - bogus I/O addresses above 64K used
224 * - expansion ROMs left enabled (this may sound harmless, but given
225 * the fact the PCI specs explicitly allow address decoders to be
226 * shared between expansion ROMs and other resource regions, it's
227 * at least dangerous)
230 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
231 * This gives us fixed barriers on where we can allocate.
232 * (2) Allocate resources for all enabled devices. If there is
233 * a collision, just mark the resource as unallocated. Also
234 * disable expansion ROMs during this step.
235 * (3) Try to allocate resources for disabled devices. If the
236 * resources were assigned correctly, everything goes well,
237 * if they weren't, they won't disturb allocation of other
239 * (4) Assign new addresses to resources which were either
240 * not configured at all or misconfigured. If explicitly
241 * requested by the user, configure expansion ROM address
246 pcibios_allocate_bus_resources(struct list_head *bus_list)
250 struct resource *res, *pr;
252 /* Depth-First Search on bus tree */
253 list_for_each_entry(bus, bus_list, node) {
254 for (i = 0; i < 4; ++i) {
255 if ((res = bus->resource[i]) == NULL || !res->flags
256 || res->start > res->end)
258 if (bus->parent == NULL)
259 pr = (res->flags & IORESOURCE_IO)?
260 &ioport_resource: &iomem_resource;
262 pr = pci_find_parent_resource(bus->self, res);
264 /* this happens when the generic PCI
265 * code (wrongly) decides that this
266 * bridge is transparent -- paulus
272 DBG("PCI: bridge rsrc %lx..%lx (%lx), parent %p\n",
273 res->start, res->end, res->flags, pr);
275 if (request_resource(pr, res) == 0)
278 * Must be a conflict with an existing entry.
279 * Move that entry (or entries) under the
280 * bridge resource and try again.
282 if (reparent_resources(pr, res) == 0)
285 printk(KERN_ERR "PCI: Cannot allocate resource region "
286 "%d of PCI bridge %d\n", i, bus->number);
287 if (pci_relocate_bridge_resource(bus, i))
288 bus->resource[i] = NULL;
290 pcibios_allocate_bus_resources(&bus->children);
295 * Reparent resource children of pr that conflict with res
296 * under res, and make res replace those children.
299 reparent_resources(struct resource *parent, struct resource *res)
301 struct resource *p, **pp;
302 struct resource **firstpp = NULL;
304 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
305 if (p->end < res->start)
307 if (res->end < p->start)
309 if (p->start < res->start || p->end > res->end)
310 return -1; /* not completely contained */
315 return -1; /* didn't find any conflicting entries? */
316 res->parent = parent;
317 res->child = *firstpp;
321 for (p = res->child; p != NULL; p = p->sibling) {
323 DBG(KERN_INFO "PCI: reparented %s [%lx..%lx] under %s\n",
324 p->name, p->start, p->end, res->name);
330 * A bridge has been allocated a range which is outside the range
331 * of its parent bridge, so it needs to be moved.
334 pci_relocate_bridge_resource(struct pci_bus *bus, int i)
336 struct resource *res, *pr, *conflict;
337 unsigned long try, size;
339 struct pci_bus *parent = bus->parent;
341 if (parent == NULL) {
342 /* shouldn't ever happen */
343 printk(KERN_ERR "PCI: can't move host bridge resource\n");
346 res = bus->resource[i];
350 for (j = 0; j < 4; j++) {
351 struct resource *r = parent->resource[j];
354 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
356 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
360 if (res->flags & IORESOURCE_PREFETCH)
365 size = res->end - res->start;
366 if (pr->start > pr->end || size > pr->end - pr->start)
370 res->start = try - size;
372 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
374 if (conflict->start <= pr->start + size)
376 try = conflict->start - 1;
378 if (request_resource(pr, res)) {
379 DBG(KERN_ERR "PCI: huh? couldn't move to %lx..%lx\n",
380 res->start, res->end);
381 return -1; /* "can't happen" */
383 update_bridge_base(bus, i);
384 printk(KERN_INFO "PCI: bridge %d resource %d moved to %lx..%lx\n",
385 bus->number, i, res->start, res->end);
390 probe_resource(struct pci_bus *parent, struct resource *pr,
391 struct resource *res, struct resource **conflict)
398 for (r = pr->child; r != NULL; r = r->sibling) {
399 if (r->end >= res->start && res->end >= r->start) {
404 list_for_each_entry(bus, &parent->children, node) {
405 for (i = 0; i < 4; ++i) {
406 if ((r = bus->resource[i]) == NULL)
408 if (!r->flags || r->start > r->end || r == res)
410 if (pci_find_parent_resource(bus->self, r) != pr)
412 if (r->end >= res->start && res->end >= r->start) {
418 list_for_each_entry(dev, &parent->devices, bus_list) {
419 for (i = 0; i < 6; ++i) {
420 r = &dev->resource[i];
421 if (!r->flags || (r->flags & IORESOURCE_UNSET))
423 if (pci_find_parent_resource(dev, r) != pr)
425 if (r->end >= res->start && res->end >= r->start) {
435 update_bridge_base(struct pci_bus *bus, int i)
437 struct resource *res = bus->resource[i];
438 u8 io_base_lo, io_limit_lo;
439 u16 mem_base, mem_limit;
441 unsigned long start, end, off;
442 struct pci_dev *dev = bus->self;
443 struct pci_controller *hose = dev->sysdata;
446 printk("update_bridge_base: no hose?\n");
449 pci_read_config_word(dev, PCI_COMMAND, &cmd);
450 pci_write_config_word(dev, PCI_COMMAND,
451 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
452 if (res->flags & IORESOURCE_IO) {
453 off = (unsigned long) hose->io_base_virt - isa_io_base;
454 start = res->start - off;
455 end = res->end - off;
456 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
457 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
459 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
461 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
463 io_base_lo |= PCI_IO_RANGE_TYPE_32;
465 io_base_lo |= PCI_IO_RANGE_TYPE_16;
466 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
467 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
469 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
471 off = hose->pci_mem_offset;
472 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
473 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
474 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
475 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
477 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
478 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
479 off = hose->pci_mem_offset;
480 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
481 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
482 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
483 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
486 DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n",
487 pci_name(dev), i, res->flags);
489 pci_write_config_word(dev, PCI_COMMAND, cmd);
492 static inline void alloc_resource(struct pci_dev *dev, int idx)
494 struct resource *pr, *r = &dev->resource[idx];
496 DBG("PCI:%s: Resource %d: %08lx-%08lx (f=%lx)\n",
497 pci_name(dev), idx, r->start, r->end, r->flags);
498 pr = pci_find_parent_resource(dev, r);
499 if (!pr || request_resource(pr, r) < 0) {
500 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
501 " of device %s\n", idx, pci_name(dev));
503 DBG("PCI: parent is %p: %08lx-%08lx (f=%lx)\n",
504 pr, pr->start, pr->end, pr->flags);
505 /* We'll assign a new address later */
506 r->flags |= IORESOURCE_UNSET;
513 pcibios_allocate_resources(int pass)
515 struct pci_dev *dev = NULL;
520 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
521 pci_read_config_word(dev, PCI_COMMAND, &command);
522 for (idx = 0; idx < 6; idx++) {
523 r = &dev->resource[idx];
524 if (r->parent) /* Already allocated */
526 if (!r->flags || (r->flags & IORESOURCE_UNSET))
527 continue; /* Not assigned at all */
528 if (r->flags & IORESOURCE_IO)
529 disabled = !(command & PCI_COMMAND_IO);
531 disabled = !(command & PCI_COMMAND_MEMORY);
532 if (pass == disabled)
533 alloc_resource(dev, idx);
537 r = &dev->resource[PCI_ROM_RESOURCE];
538 if (r->flags & IORESOURCE_ROM_ENABLE) {
539 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
541 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
542 r->flags &= ~IORESOURCE_ROM_ENABLE;
543 pci_read_config_dword(dev, dev->rom_base_reg, ®);
544 pci_write_config_dword(dev, dev->rom_base_reg,
545 reg & ~PCI_ROM_ADDRESS_ENABLE);
551 pcibios_assign_resources(void)
553 struct pci_dev *dev = NULL;
557 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
558 int class = dev->class >> 8;
560 /* Don't touch classless devices and host bridges */
561 if (!class || class == PCI_CLASS_BRIDGE_HOST)
564 for (idx = 0; idx < 6; idx++) {
565 r = &dev->resource[idx];
568 * We shall assign a new address to this resource,
569 * either because the BIOS (sic) forgot to do so
570 * or because we have decided the old address was
571 * unusable for some reason.
573 if ((r->flags & IORESOURCE_UNSET) && r->end &&
574 (!ppc_md.pcibios_enable_device_hook ||
575 !ppc_md.pcibios_enable_device_hook(dev, 1))) {
576 r->flags &= ~IORESOURCE_UNSET;
577 pci_assign_resource(dev, idx);
581 #if 0 /* don't assign ROMs */
582 r = &dev->resource[PCI_ROM_RESOURCE];
586 pci_assign_resource(dev, PCI_ROM_RESOURCE);
593 pcibios_enable_resources(struct pci_dev *dev, int mask)
599 pci_read_config_word(dev, PCI_COMMAND, &cmd);
601 for (idx=0; idx<6; idx++) {
602 /* Only set up the requested stuff */
603 if (!(mask & (1<<idx)))
606 r = &dev->resource[idx];
607 if (r->flags & IORESOURCE_UNSET) {
608 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
611 if (r->flags & IORESOURCE_IO)
612 cmd |= PCI_COMMAND_IO;
613 if (r->flags & IORESOURCE_MEM)
614 cmd |= PCI_COMMAND_MEMORY;
616 if (dev->resource[PCI_ROM_RESOURCE].start)
617 cmd |= PCI_COMMAND_MEMORY;
618 if (cmd != old_cmd) {
619 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
620 pci_write_config_word(dev, PCI_COMMAND, cmd);
625 static int next_controller_index;
627 struct pci_controller * __init
628 pcibios_alloc_controller(void)
630 struct pci_controller *hose;
632 hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
633 memset(hose, 0, sizeof(struct pci_controller));
636 hose_tail = &hose->next;
638 hose->index = next_controller_index++;
645 * Functions below are used on OpenFirmware machines.
647 static void __openfirmware
648 make_one_node_map(struct device_node* node, u8 pci_bus)
653 if (pci_bus >= pci_bus_count)
655 bus_range = (int *) get_property(node, "bus-range", &len);
656 if (bus_range == NULL || len < 2 * sizeof(int)) {
657 printk(KERN_WARNING "Can't get bus-range for %s, "
658 "assuming it starts at 0\n", node->full_name);
659 pci_to_OF_bus_map[pci_bus] = 0;
661 pci_to_OF_bus_map[pci_bus] = bus_range[0];
663 for (node=node->child; node != 0;node = node->sibling) {
665 unsigned int *class_code, *reg;
667 class_code = (unsigned int *) get_property(node, "class-code", NULL);
668 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
669 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
671 reg = (unsigned int *)get_property(node, "reg", NULL);
674 dev = pci_find_slot(pci_bus, ((reg[0] >> 8) & 0xff));
675 if (!dev || !dev->subordinate)
677 make_one_node_map(node, dev->subordinate->number);
682 pcibios_make_OF_bus_map(void)
685 struct pci_controller* hose;
688 pci_to_OF_bus_map = (u8*)kmalloc(pci_bus_count, GFP_KERNEL);
689 if (!pci_to_OF_bus_map) {
690 printk(KERN_ERR "Can't allocate OF bus map !\n");
694 /* We fill the bus map with invalid values, that helps
697 for (i=0; i<pci_bus_count; i++)
698 pci_to_OF_bus_map[i] = 0xff;
700 /* For each hose, we begin searching bridges */
701 for(hose=hose_head; hose; hose=hose->next) {
702 struct device_node* node;
703 node = (struct device_node *)hose->arch_data;
706 make_one_node_map(node, hose->first_busno);
708 of_prop_map = get_property(find_path_device("/"), "pci-OF-bus-map", NULL);
710 memcpy(of_prop_map, pci_to_OF_bus_map, pci_bus_count);
712 printk("PCI->OF bus map:\n");
713 for (i=0; i<pci_bus_count; i++) {
714 if (pci_to_OF_bus_map[i] == 0xff)
716 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
721 typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
723 static struct device_node* __openfirmware
724 scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
726 struct device_node* sub_node;
728 for (; node != 0;node = node->sibling) {
729 unsigned int *class_code;
731 if (filter(node, data))
734 /* For PCI<->PCI bridges or CardBus bridges, we go down
735 * Note: some OFs create a parent node "multifunc-device" as
736 * a fake root for all functions of a multi-function device,
737 * we go down them as well.
739 class_code = (unsigned int *) get_property(node, "class-code", NULL);
740 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
741 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
742 strcmp(node->name, "multifunc-device"))
744 sub_node = scan_OF_pci_childs(node->child, filter, data);
752 scan_OF_pci_childs_iterator(struct device_node* node, void* data)
755 u8* fdata = (u8*)data;
757 reg = (unsigned int *) get_property(node, "reg", NULL);
758 if (reg && ((reg[0] >> 8) & 0xff) == fdata[1]
759 && ((reg[0] >> 16) & 0xff) == fdata[0])
764 static struct device_node* __openfirmware
765 scan_OF_childs_for_device(struct device_node* node, u8 bus, u8 dev_fn)
767 u8 filter_data[2] = {bus, dev_fn};
769 return scan_OF_pci_childs(node, scan_OF_pci_childs_iterator, filter_data);
773 * Scans the OF tree for a device node matching a PCI device
776 pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
778 struct pci_controller *hose;
779 struct device_node *node;
785 /* Lookup the hose */
787 hose = pci_bus_to_hose(busnr);
791 /* Check it has an OF node associated */
792 node = (struct device_node *) hose->arch_data;
796 /* Fixup bus number according to what OF think it is. */
797 #ifdef CONFIG_PPC_PMAC
798 /* The G5 need a special case here. Basically, we don't remap all
799 * busses on it so we don't create the pci-OF-map. However, we do
800 * remap the AGP bus and so have to deal with it. A future better
801 * fix has to be done by making the remapping per-host and always
802 * filling the pci_to_OF map. --BenH
804 if (_machine == _MACH_Pmac && busnr >= 0xf0)
808 if (pci_to_OF_bus_map)
809 busnr = pci_to_OF_bus_map[busnr];
813 /* Now, lookup childs of the hose */
814 return scan_OF_childs_for_device(node->child, busnr, devfn);
818 pci_device_to_OF_node(struct pci_dev *dev)
820 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
823 /* This routine is meant to be used early during boot, when the
824 * PCI bus numbers have not yet been assigned, and you need to
825 * issue PCI config cycles to an OF device.
826 * It could also be used to "fix" RTAS config cycles if you want
827 * to set pci_assign_all_busses to 1 and still use RTAS for PCI
830 struct pci_controller*
831 pci_find_hose_for_OF_device(struct device_node* node)
836 struct pci_controller* hose;
837 for (hose=hose_head;hose;hose=hose->next)
838 if (hose->arch_data == node)
845 static int __openfirmware
846 find_OF_pci_device_filter(struct device_node* node, void* data)
848 return ((void *)node == data);
852 * Returns the PCI device matching a given OF node
855 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
858 struct pci_controller* hose;
859 struct pci_dev* dev = NULL;
863 /* Make sure it's really a PCI device */
864 hose = pci_find_hose_for_OF_device(node);
865 if (!hose || !hose->arch_data)
867 if (!scan_OF_pci_childs(((struct device_node*)hose->arch_data)->child,
868 find_OF_pci_device_filter, (void *)node))
870 reg = (unsigned int *) get_property(node, "reg", NULL);
873 *bus = (reg[0] >> 16) & 0xff;
874 *devfn = ((reg[0] >> 8) & 0xff);
876 /* Ok, here we need some tweak. If we have already renumbered
877 * all busses, we can't rely on the OF bus number any more.
878 * the pci_to_OF_bus_map is not enough as several PCI busses
879 * may match the same OF bus number.
881 if (!pci_to_OF_bus_map)
883 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
884 if (pci_to_OF_bus_map[dev->bus->number] != *bus)
886 if (dev->devfn != *devfn)
888 *bus = dev->bus->number;
895 pci_process_bridge_OF_ranges(struct pci_controller *hose,
896 struct device_node *dev, int primary)
898 static unsigned int static_lc_ranges[256] __initdata;
899 unsigned int *dt_ranges, *lc_ranges, *ranges, *prev;
901 int rlen = 0, orig_rlen;
903 struct resource *res;
904 int np, na = prom_n_addr_cells(dev);
907 /* First we try to merge ranges to fix a problem with some pmacs
908 * that can have more than 3 ranges, fortunately using contiguous
911 dt_ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
914 /* Sanity check, though hopefully that never happens */
915 if (rlen > sizeof(static_lc_ranges)) {
916 printk(KERN_WARNING "OF ranges property too large !\n");
917 rlen = sizeof(static_lc_ranges);
919 lc_ranges = static_lc_ranges;
920 memcpy(lc_ranges, dt_ranges, rlen);
923 /* Let's work on a copy of the "ranges" property instead of damaging
924 * the device-tree image in memory
928 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
930 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
931 (prev[2] + prev[na+4]) == ranges[2] &&
932 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
933 prev[na+4] += ranges[na+4];
944 * The ranges property is laid out as an array of elements,
945 * each of which comprises:
946 * cells 0 - 2: a PCI address
947 * cells 3 or 3+4: a CPU physical address
948 * (size depending on dev->n_addr_cells)
949 * cells 4+5 or 5+6: the size of the range
953 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
956 switch (ranges[0] >> 24) {
957 case 1: /* I/O space */
960 hose->io_base_phys = ranges[na+2];
961 /* limit I/O space to 16MB */
962 if (size > 0x01000000)
964 hose->io_base_virt = ioremap(ranges[na+2], size);
966 isa_io_base = (unsigned long) hose->io_base_virt;
967 res = &hose->io_resource;
968 res->flags = IORESOURCE_IO;
969 res->start = ranges[2];
971 case 2: /* memory space */
973 if (ranges[1] == 0 && ranges[2] == 0
974 && ranges[na+4] <= (16 << 20)) {
975 /* 1st 16MB, i.e. ISA memory area */
977 isa_mem_base = ranges[na+2];
980 while (memno < 3 && hose->mem_resources[memno].flags)
983 hose->pci_mem_offset = ranges[na+2] - ranges[2];
985 res = &hose->mem_resources[memno];
986 res->flags = IORESOURCE_MEM;
987 res->start = ranges[na+2];
992 res->name = dev->full_name;
993 res->end = res->start + size - 1;
1002 /* We create the "pci-OF-bus-map" property now so it appears in the
1006 pci_create_OF_bus_map(void)
1008 struct property* of_prop;
1010 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
1011 if (of_prop && find_path_device("/")) {
1012 memset(of_prop, -1, sizeof(struct property) + 256);
1013 of_prop->name = "pci-OF-bus-map";
1014 of_prop->length = 256;
1015 of_prop->value = (unsigned char *)&of_prop[1];
1016 prom_add_property(find_path_device("/"), of_prop);
1020 static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
1022 struct pci_dev *pdev;
1023 struct device_node *np;
1025 pdev = to_pci_dev (dev);
1026 np = pci_device_to_OF_node(pdev);
1027 if (np == NULL || np->full_name == NULL)
1029 return sprintf(buf, "%s", np->full_name);
1031 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
1033 #endif /* CONFIG_PPC_OF */
1035 /* Add sysfs properties */
1036 void pcibios_add_platform_entries(struct pci_dev *pdev)
1038 #ifdef CONFIG_PPC_OF
1039 device_create_file(&pdev->dev, &dev_attr_devspec);
1040 #endif /* CONFIG_PPC_OF */
1044 #ifdef CONFIG_PPC_PMAC
1046 * This set of routines checks for PCI<->PCI bridges that have closed
1047 * IO resources and have child devices. It tries to re-open an IO
1050 * This is a _temporary_ fix to workaround a problem with Apple's OF
1051 * closing IO windows on P2P bridges when the OF drivers of cards
1052 * below this bridge don't claim any IO range (typically ATI or
1055 * A more complete fix would be to use drivers/pci/setup-bus.c, which
1056 * involves a working pcibios_fixup_pbus_ranges(), some more care about
1057 * ordering when creating the host bus resources, and maybe a few more
1061 /* Initialize bridges with base/limit values we have collected */
1063 do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga)
1065 struct pci_dev *bridge = bus->self;
1066 struct pci_controller* hose = (struct pci_controller *)bridge->sysdata;
1069 struct resource res;
1071 if (bus->resource[0] == NULL)
1073 res = *(bus->resource[0]);
1075 DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge));
1076 res.start -= ((unsigned long) hose->io_base_virt - isa_io_base);
1077 res.end -= ((unsigned long) hose->io_base_virt - isa_io_base);
1078 DBG(" IO window: %08lx-%08lx\n", res.start, res.end);
1080 /* Set up the top and bottom of the PCI I/O segment for this bus. */
1081 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
1083 l |= (res.start >> 8) & 0x00f0;
1084 l |= res.end & 0xf000;
1085 pci_write_config_dword(bridge, PCI_IO_BASE, l);
1087 if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
1088 l = (res.start >> 16) | (res.end & 0xffff0000);
1089 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l);
1092 pci_read_config_word(bridge, PCI_COMMAND, &w);
1093 w |= PCI_COMMAND_IO;
1094 pci_write_config_word(bridge, PCI_COMMAND, w);
1096 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1098 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w);
1099 w |= PCI_BRIDGE_CTL_VGA;
1100 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w);
1105 /* This function is pretty basic and actually quite broken for the
1106 * general case, it's enough for us right now though. It's supposed
1107 * to tell us if we need to open an IO range at all or not and what
1111 check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga)
1113 struct pci_dev *dev;
1117 #define push_end(res, size) do { unsigned long __sz = (size) ; \
1118 res->end = ((res->end + __sz) / (__sz + 1)) * (__sz + 1) + __sz; \
1121 list_for_each_entry(dev, &bus->devices, bus_list) {
1122 u16 class = dev->class >> 8;
1124 if (class == PCI_CLASS_DISPLAY_VGA ||
1125 class == PCI_CLASS_NOT_DEFINED_VGA)
1127 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate)
1128 rc |= check_for_io_childs(dev->subordinate, res, found_vga);
1129 if (class == PCI_CLASS_BRIDGE_CARDBUS)
1130 push_end(res, 0xfff);
1132 for (i=0; i<PCI_NUM_RESOURCES; i++) {
1134 unsigned long r_size;
1136 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI
1137 && i >= PCI_BRIDGE_RESOURCES)
1139 r = &dev->resource[i];
1140 r_size = r->end - r->start;
1143 if (r->flags & IORESOURCE_IO && (r_size) != 0) {
1145 push_end(res, r_size);
1153 /* Here we scan all P2P bridges of a given level that have a closed
1154 * IO window. Note that the test for the presence of a VGA card should
1155 * be improved to take into account already configured P2P bridges,
1156 * currently, we don't see them and might end up configuring 2 bridges
1157 * with VGA pass through enabled
1160 do_fixup_p2p_level(struct pci_bus *bus)
1166 for (parent_io=0; parent_io<4; parent_io++)
1167 if (bus->resource[parent_io]
1168 && bus->resource[parent_io]->flags & IORESOURCE_IO)
1173 list_for_each_entry(b, &bus->children, node) {
1174 struct pci_dev *d = b->self;
1175 struct pci_controller* hose = (struct pci_controller *)d->sysdata;
1176 struct resource *res = b->resource[0];
1177 struct resource tmp_res;
1181 memset(&tmp_res, 0, sizeof(tmp_res));
1182 tmp_res.start = bus->resource[parent_io]->start;
1184 /* We don't let low addresses go through that closed P2P bridge, well,
1185 * that may not be necessary but I feel safer that way
1187 if (tmp_res.start == 0)
1188 tmp_res.start = 0x1000;
1190 if (!list_empty(&b->devices) && res && res->flags == 0 &&
1191 res != bus->resource[parent_io] &&
1192 (d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1193 check_for_io_childs(b, &tmp_res, &found_vga)) {
1196 printk(KERN_INFO "Fixing up IO bus %s\n", b->name);
1200 printk(KERN_WARNING "Skipping VGA, already active"
1201 " on bus segment\n");
1206 pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo);
1208 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32)
1209 max = ((unsigned long) hose->io_base_virt
1210 - isa_io_base) + 0xffffffff;
1212 max = ((unsigned long) hose->io_base_virt
1213 - isa_io_base) + 0xffff;
1216 res->flags = IORESOURCE_IO;
1217 res->name = b->name;
1219 /* Find a resource in the parent where we can allocate */
1220 for (i = 0 ; i < 4; i++) {
1221 struct resource *r = bus->resource[i];
1224 if ((r->flags & IORESOURCE_IO) == 0)
1226 DBG("Trying to allocate from %08lx, size %08lx from parent"
1227 " res %d: %08lx -> %08lx\n",
1228 res->start, res->end, i, r->start, r->end);
1230 if (allocate_resource(r, res, res->end + 1, res->start, max,
1231 res->end + 1, NULL, NULL) < 0) {
1235 do_update_p2p_io_resource(b, found_vga);
1239 do_fixup_p2p_level(b);
1244 pcibios_fixup_p2p_bridges(void)
1248 list_for_each_entry(b, &pci_root_buses, node)
1249 do_fixup_p2p_level(b);
1252 #endif /* CONFIG_PPC_PMAC */
1257 struct pci_controller *hose;
1258 struct pci_bus *bus;
1261 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1263 /* Scan all of the recorded PCI controllers. */
1264 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
1265 if (pci_assign_all_busses)
1266 hose->first_busno = next_busno;
1267 hose->last_busno = 0xff;
1268 bus = pci_scan_bus(hose->first_busno, hose->ops, hose);
1269 hose->last_busno = bus->subordinate;
1270 if (pci_assign_all_busses || next_busno <= hose->last_busno)
1271 next_busno = hose->last_busno + pcibios_assign_bus_offset;
1273 pci_bus_count = next_busno;
1275 /* OpenFirmware based machines need a map of OF bus
1276 * numbers vs. kernel bus numbers since we may have to
1279 if (pci_assign_all_busses && have_of)
1280 pcibios_make_OF_bus_map();
1282 /* Do machine dependent PCI interrupt routing */
1283 if (ppc_md.pci_swizzle && ppc_md.pci_map_irq)
1284 pci_fixup_irqs(ppc_md.pci_swizzle, ppc_md.pci_map_irq);
1286 /* Call machine dependent fixup */
1287 if (ppc_md.pcibios_fixup)
1288 ppc_md.pcibios_fixup();
1290 /* Allocate and assign resources */
1291 pcibios_allocate_bus_resources(&pci_root_buses);
1292 pcibios_allocate_resources(0);
1293 pcibios_allocate_resources(1);
1294 #ifdef CONFIG_PPC_PMAC
1295 pcibios_fixup_p2p_bridges();
1296 #endif /* CONFIG_PPC_PMAC */
1297 pcibios_assign_resources();
1299 /* Call machine dependent post-init code */
1300 if (ppc_md.pcibios_after_init)
1301 ppc_md.pcibios_after_init();
1306 subsys_initcall(pcibios_init);
1308 unsigned char __init
1309 common_swizzle(struct pci_dev *dev, unsigned char *pinp)
1311 struct pci_controller *hose = dev->sysdata;
1313 if (dev->bus->number != hose->first_busno) {
1316 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
1317 /* Move up the chain of bridges. */
1318 dev = dev->bus->self;
1319 } while (dev->bus->self);
1322 /* The slot is the idsel of the last bridge. */
1324 return PCI_SLOT(dev->devfn);
1327 unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
1328 unsigned long start, unsigned long size)
1333 void __init pcibios_fixup_bus(struct pci_bus *bus)
1335 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1336 unsigned long io_offset;
1337 struct resource *res;
1340 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1341 if (bus->parent == NULL) {
1342 /* This is a host bridge - fill in its resources */
1345 bus->resource[0] = res = &hose->io_resource;
1348 printk(KERN_ERR "I/O resource not set for host"
1349 " bridge %d\n", hose->index);
1351 res->end = IO_SPACE_LIMIT;
1352 res->flags = IORESOURCE_IO;
1354 res->start += io_offset;
1355 res->end += io_offset;
1357 for (i = 0; i < 3; ++i) {
1358 res = &hose->mem_resources[i];
1362 printk(KERN_ERR "Memory resource not set for "
1363 "host bridge %d\n", hose->index);
1364 res->start = hose->pci_mem_offset;
1366 res->flags = IORESOURCE_MEM;
1368 bus->resource[i+1] = res;
1371 /* This is a subordinate bridge */
1372 pci_read_bridge_bases(bus);
1374 for (i = 0; i < 4; ++i) {
1375 if ((res = bus->resource[i]) == NULL)
1379 if (io_offset && (res->flags & IORESOURCE_IO)) {
1380 res->start += io_offset;
1381 res->end += io_offset;
1382 } else if (hose->pci_mem_offset
1383 && (res->flags & IORESOURCE_MEM)) {
1384 res->start += hose->pci_mem_offset;
1385 res->end += hose->pci_mem_offset;
1390 if (ppc_md.pcibios_fixup_bus)
1391 ppc_md.pcibios_fixup_bus(bus);
1394 char __init *pcibios_setup(char *str)
1399 /* the next one is stolen from the alpha port... */
1401 pcibios_update_irq(struct pci_dev *dev, int irq)
1403 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
1404 /* XXX FIXME - update OF device tree node interrupt property */
1407 int pcibios_enable_device(struct pci_dev *dev, int mask)
1413 if (ppc_md.pcibios_enable_device_hook)
1414 if (ppc_md.pcibios_enable_device_hook(dev, 0))
1417 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1419 for (idx=0; idx<6; idx++) {
1420 r = &dev->resource[idx];
1421 if (r->flags & IORESOURCE_UNSET) {
1422 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
1425 if (r->flags & IORESOURCE_IO)
1426 cmd |= PCI_COMMAND_IO;
1427 if (r->flags & IORESOURCE_MEM)
1428 cmd |= PCI_COMMAND_MEMORY;
1430 if (cmd != old_cmd) {
1431 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1432 pci_name(dev), old_cmd, cmd);
1433 pci_write_config_word(dev, PCI_COMMAND, cmd);
1438 struct pci_controller*
1439 pci_bus_to_hose(int bus)
1441 struct pci_controller* hose = hose_head;
1443 for (; hose; hose = hose->next)
1444 if (bus >= hose->first_busno && bus <= hose->last_busno)
1450 pci_bus_io_base(unsigned int bus)
1452 struct pci_controller *hose;
1454 hose = pci_bus_to_hose(bus);
1457 return hose->io_base_virt;
1461 pci_bus_io_base_phys(unsigned int bus)
1463 struct pci_controller *hose;
1465 hose = pci_bus_to_hose(bus);
1468 return hose->io_base_phys;
1472 pci_bus_mem_base_phys(unsigned int bus)
1474 struct pci_controller *hose;
1476 hose = pci_bus_to_hose(bus);
1479 return hose->pci_mem_offset;
1483 pci_resource_to_bus(struct pci_dev *pdev, struct resource *res)
1485 /* Hack alert again ! See comments in chrp_pci.c
1487 struct pci_controller* hose =
1488 (struct pci_controller *)pdev->sysdata;
1489 if (hose && res->flags & IORESOURCE_MEM)
1490 return res->start - hose->pci_mem_offset;
1491 /* We may want to do something with IOs here... */
1496 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
1497 unsigned long *offset,
1498 enum pci_mmap_state mmap_state)
1500 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1501 unsigned long io_offset = 0;
1505 return NULL; /* should never happen */
1507 /* If memory, add on the PCI bridge address offset */
1508 if (mmap_state == pci_mmap_mem) {
1509 *offset += hose->pci_mem_offset;
1510 res_bit = IORESOURCE_MEM;
1512 io_offset = hose->io_base_virt - ___IO_BASE;
1513 *offset += io_offset;
1514 res_bit = IORESOURCE_IO;
1518 * Check that the offset requested corresponds to one of the
1519 * resources of the device.
1521 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1522 struct resource *rp = &dev->resource[i];
1523 int flags = rp->flags;
1525 /* treat ROM as memory (should be already) */
1526 if (i == PCI_ROM_RESOURCE)
1527 flags |= IORESOURCE_MEM;
1529 /* Active and same type? */
1530 if ((flags & res_bit) == 0)
1533 /* In the range of this resource? */
1534 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
1537 /* found it! construct the final physical address */
1538 if (mmap_state == pci_mmap_io)
1539 *offset += hose->io_base_phys - io_offset;
1547 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1550 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
1551 pgprot_t protection,
1552 enum pci_mmap_state mmap_state,
1555 unsigned long prot = pgprot_val(protection);
1557 /* Write combine is always 0 on non-memory space mappings. On
1558 * memory space, if the user didn't pass 1, we check for a
1559 * "prefetchable" resource. This is a bit hackish, but we use
1560 * this to workaround the inability of /sysfs to provide a write
1563 if (mmap_state != pci_mmap_mem)
1565 else if (write_combine == 0) {
1566 if (rp->flags & IORESOURCE_PREFETCH)
1570 /* XXX would be nice to have a way to ask for write-through */
1571 prot |= _PAGE_NO_CACHE;
1573 prot &= ~_PAGE_GUARDED;
1575 prot |= _PAGE_GUARDED;
1577 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
1580 return __pgprot(prot);
1584 * This one is used by /dev/mem and fbdev who have no clue about the
1585 * PCI device, it tries to find the PCI device first and calls the
1588 pgprot_t pci_phys_mem_access_prot(struct file *file,
1589 unsigned long offset,
1591 pgprot_t protection)
1593 struct pci_dev *pdev = NULL;
1594 struct resource *found = NULL;
1595 unsigned long prot = pgprot_val(protection);
1598 if (page_is_ram(offset >> PAGE_SHIFT))
1601 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
1603 for_each_pci_dev(pdev) {
1604 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1605 struct resource *rp = &pdev->resource[i];
1606 int flags = rp->flags;
1608 /* Active and same type? */
1609 if ((flags & IORESOURCE_MEM) == 0)
1611 /* In the range of this resource? */
1612 if (offset < (rp->start & PAGE_MASK) ||
1622 if (found->flags & IORESOURCE_PREFETCH)
1623 prot &= ~_PAGE_GUARDED;
1627 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
1629 return __pgprot(prot);
1634 * Perform the actual remap of the pages for a PCI device mapping, as
1635 * appropriate for this architecture. The region in the process to map
1636 * is described by vm_start and vm_end members of VMA, the base physical
1637 * address is found in vm_pgoff.
1638 * The pci device structure is provided so that architectures may make mapping
1639 * decisions on a per-device or per-bus basis.
1641 * Returns a negative error code on failure, zero on success.
1643 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1644 enum pci_mmap_state mmap_state,
1647 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1648 struct resource *rp;
1651 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
1655 vma->vm_pgoff = offset >> PAGE_SHIFT;
1656 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
1657 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
1659 mmap_state, write_combine);
1661 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
1662 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1667 /* Obsolete functions. Should be removed once the symbios driver
1671 phys_to_bus(unsigned long pa)
1673 struct pci_controller *hose;
1676 for (hose = hose_head; hose; hose = hose->next) {
1677 for (i = 0; i < 3; ++i) {
1678 if (pa >= hose->mem_resources[i].start
1679 && pa <= hose->mem_resources[i].end) {
1681 * XXX the hose->pci_mem_offset really
1682 * only applies to mem_resources[0].
1683 * We need a way to store an offset for
1684 * the others. -- paulus
1687 pa -= hose->pci_mem_offset;
1692 /* hmmm, didn't find it */
1697 pci_phys_to_bus(unsigned long pa, int busnr)
1699 struct pci_controller* hose = pci_bus_to_hose(busnr);
1702 return pa - hose->pci_mem_offset;
1706 pci_bus_to_phys(unsigned int ba, int busnr)
1708 struct pci_controller* hose = pci_bus_to_hose(busnr);
1711 return ba + hose->pci_mem_offset;
1714 /* Provide information on locations of various I/O regions in physical
1715 * memory. Do this on a per-card basis so that we choose the right
1717 * Note that the returned IO or memory base is a physical address
1720 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1722 struct pci_controller* hose;
1723 long result = -EOPNOTSUPP;
1725 /* Argh ! Please forgive me for that hack, but that's the
1726 * simplest way to get existing XFree to not lockup on some
1727 * G5 machines... So when something asks for bus 0 io base
1728 * (bus 0 is HT root), we return the AGP one instead.
1730 #ifdef CONFIG_PPC_PMAC
1731 if (_machine == _MACH_Pmac && machine_is_compatible("MacRISC4"))
1734 #endif /* CONFIG_PPC_PMAC */
1736 hose = pci_bus_to_hose(bus);
1741 case IOBASE_BRIDGE_NUMBER:
1742 return (long)hose->first_busno;
1744 return (long)hose->pci_mem_offset;
1746 return (long)hose->io_base_phys;
1748 return (long)isa_io_base;
1749 case IOBASE_ISA_MEM:
1750 return (long)isa_mem_base;
1756 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1757 const struct resource *rsrc,
1758 u64 *start, u64 *end)
1760 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1761 unsigned long offset = 0;
1766 if (rsrc->flags & IORESOURCE_IO)
1767 offset = ___IO_BASE - hose->io_base_virt + hose->io_base_phys;
1769 *start = rsrc->start + offset;
1770 *end = rsrc->end + offset;
1774 pci_init_resource(struct resource *res, unsigned long start, unsigned long end,
1775 int flags, char *name)
1782 res->sibling = NULL;
1786 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
1788 unsigned long start = pci_resource_start(dev, bar);
1789 unsigned long len = pci_resource_len(dev, bar);
1790 unsigned long flags = pci_resource_flags(dev, bar);
1794 if (max && len > max)
1796 if (flags & IORESOURCE_IO)
1797 return ioport_map(start, len);
1798 if (flags & IORESOURCE_MEM)
1799 /* Not checking IORESOURCE_CACHEABLE because PPC does
1800 * not currently distinguish between ioremap and
1803 return ioremap(start, len);
1808 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
1812 EXPORT_SYMBOL(pci_iomap);
1813 EXPORT_SYMBOL(pci_iounmap);
1817 * Null PCI config access functions, for the case when we can't
1820 #define NULL_PCI_OP(rw, size, type) \
1822 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1824 return PCIBIOS_DEVICE_NOT_FOUND; \
1828 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1831 return PCIBIOS_DEVICE_NOT_FOUND;
1835 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1838 return PCIBIOS_DEVICE_NOT_FOUND;
1841 static struct pci_ops null_pci_ops =
1848 * These functions are used early on before PCI scanning is done
1849 * and all of the pci_dev and pci_bus structures have been created.
1851 static struct pci_bus *
1852 fake_pci_bus(struct pci_controller *hose, int busnr)
1854 static struct pci_bus bus;
1857 hose = pci_bus_to_hose(busnr);
1859 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1863 bus.ops = hose? hose->ops: &null_pci_ops;
1867 #define EARLY_PCI_OP(rw, size, type) \
1868 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1869 int devfn, int offset, type value) \
1871 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1872 devfn, offset, value); \
1875 EARLY_PCI_OP(read, byte, u8 *)
1876 EARLY_PCI_OP(read, word, u16 *)
1877 EARLY_PCI_OP(read, dword, u32 *)
1878 EARLY_PCI_OP(write, byte, u8)
1879 EARLY_PCI_OP(write, word, u16)
1880 EARLY_PCI_OP(write, dword, u32)