Merge with rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
[linux-2.6] / drivers / mtd / nand / s3c2410.c
1 /* linux/drivers/mtd/nand/s3c2410.c
2  *
3  * Copyright (c) 2004 Simtec Electronics
4  *      http://www.simtec.co.uk/products/SWLINUX/
5  *      Ben Dooks <ben@simtec.co.uk>
6  *
7  * Samsung S3C2410 NAND driver
8  *
9  * Changelog:
10  *      21-Sep-2004  BJD  Initial version
11  *      23-Sep-2004  BJD  Mulitple device support
12  *      28-Sep-2004  BJD  Fixed ECC placement for Hardware mode
13  *      12-Oct-2004  BJD  Fixed errors in use of platform data
14  *      18-Feb-2005  BJD  Fix sparse errors
15  *      14-Mar-2005  BJD  Applied tglx's code reduction patch
16  *
17  * $Id: s3c2410.c,v 1.12 2005/03/17 11:31:26 bjd Exp $
18  *
19  * This program is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License as published by
21  * the Free Software Foundation; either version 2 of the License, or
22  * (at your option) any later version.
23  *
24  * This program is distributed in the hope that it will be useful,
25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
27  * GNU General Public License for more details.
28  *
29  * You should have received a copy of the GNU General Public License
30  * along with this program; if not, write to the Free Software
31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
32 */
33
34 #include <config/mtd/nand/s3c2410/hwecc.h>
35 #include <config/mtd/nand/s3c2410/debug.h>
36
37 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
38 #define DEBUG
39 #endif
40
41 #include <linux/module.h>
42 #include <linux/types.h>
43 #include <linux/init.h>
44 #include <linux/kernel.h>
45 #include <linux/string.h>
46 #include <linux/ioport.h>
47 #include <linux/device.h>
48 #include <linux/delay.h>
49 #include <linux/err.h>
50
51 #include <linux/mtd/mtd.h>
52 #include <linux/mtd/nand.h>
53 #include <linux/mtd/nand_ecc.h>
54 #include <linux/mtd/partitions.h>
55
56 #include <asm/io.h>
57 #include <asm/mach-types.h>
58 #include <asm/hardware/clock.h>
59
60 #include <asm/arch/regs-nand.h>
61 #include <asm/arch/nand.h>
62
63 #define PFX "s3c2410-nand: "
64
65 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
66 static int hardware_ecc = 1;
67 #else
68 static int hardware_ecc = 0;
69 #endif
70
71 /* new oob placement block for use with hardware ecc generation
72  */
73
74 static struct nand_oobinfo nand_hw_eccoob = {
75         .useecc         = MTD_NANDECC_AUTOPLACE,
76         .eccbytes       = 3,
77         .eccpos         = {0, 1, 2 },
78         .oobfree        = { {8, 8} }
79 };
80
81 /* controller and mtd information */
82
83 struct s3c2410_nand_info;
84
85 struct s3c2410_nand_mtd {
86         struct mtd_info                 mtd;
87         struct nand_chip                chip;
88         struct s3c2410_nand_set         *set;
89         struct s3c2410_nand_info        *info;
90         int                             scan_res;
91 };
92
93 /* overview of the s3c2410 nand state */
94
95 struct s3c2410_nand_info {
96         /* mtd info */
97         struct nand_hw_control          controller;
98         struct s3c2410_nand_mtd         *mtds;
99         struct s3c2410_platform_nand    *platform;
100
101         /* device info */
102         struct device                   *device;
103         struct resource                 *area;
104         struct clk                      *clk;
105         void __iomem                    *regs;
106         int                             mtd_count;
107 };
108
109 /* conversion functions */
110
111 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
112 {
113         return container_of(mtd, struct s3c2410_nand_mtd, mtd);
114 }
115
116 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
117 {
118         return s3c2410_nand_mtd_toours(mtd)->info;
119 }
120
121 static struct s3c2410_nand_info *to_nand_info(struct device *dev)
122 {
123         return dev_get_drvdata(dev);
124 }
125
126 static struct s3c2410_platform_nand *to_nand_plat(struct device *dev)
127 {
128         return dev->platform_data;
129 }
130
131 /* timing calculations */
132
133 #define NS_IN_KHZ 10000000
134
135 static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max)
136 {
137         int result;
138
139         result = (wanted * NS_IN_KHZ) / clk;
140         result++;
141
142         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
143
144         if (result > max) {
145                 printk("%d ns is too big for current clock rate %ld\n",
146                        wanted, clk);
147                 return -1;
148         }
149
150         if (result < 1)
151                 result = 1;
152
153         return result;
154 }
155
156 #define to_ns(ticks,clk) (((clk) * (ticks)) / NS_IN_KHZ)
157
158 /* controller setup */
159
160 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, 
161                                struct device *dev)
162 {
163         struct s3c2410_platform_nand *plat = to_nand_plat(dev);
164         unsigned int tacls, twrph0, twrph1;
165         unsigned long clkrate = clk_get_rate(info->clk);
166         unsigned long cfg;
167
168         /* calculate the timing information for the controller */
169
170         if (plat != NULL) {
171                 tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 8);
172                 twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8);
173                 twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8);
174         } else {
175                 /* default timings */
176                 tacls = 8;
177                 twrph0 = 8;
178                 twrph1 = 8;
179         }
180         
181         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
182                 printk(KERN_ERR PFX "cannot get timings suitable for board\n");
183                 return -EINVAL;
184         }
185
186         printk(KERN_INFO PFX "timing: Tacls %ldns, Twrph0 %ldns, Twrph1 %ldns\n",
187                to_ns(tacls, clkrate),
188                to_ns(twrph0, clkrate),
189                to_ns(twrph1, clkrate));
190
191         cfg  = S3C2410_NFCONF_EN;
192         cfg |= S3C2410_NFCONF_TACLS(tacls-1);
193         cfg |= S3C2410_NFCONF_TWRPH0(twrph0-1);
194         cfg |= S3C2410_NFCONF_TWRPH1(twrph1-1);
195
196         pr_debug(PFX "NF_CONF is 0x%lx\n", cfg);
197
198         writel(cfg, info->regs + S3C2410_NFCONF);
199         return 0;
200 }
201
202 /* select chip */
203
204 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
205 {
206         struct s3c2410_nand_info *info;
207         struct s3c2410_nand_mtd *nmtd; 
208         struct nand_chip *this = mtd->priv;
209         unsigned long cur;
210
211         nmtd = this->priv;
212         info = nmtd->info;
213
214         cur = readl(info->regs + S3C2410_NFCONF);
215
216         if (chip == -1) {
217                 cur |= S3C2410_NFCONF_nFCE;
218         } else {
219                 if (chip > nmtd->set->nr_chips) {
220                         printk(KERN_ERR PFX "chip %d out of range\n", chip);
221                         return;
222                 }
223
224                 if (info->platform != NULL) {
225                         if (info->platform->select_chip != NULL)
226                                 (info->platform->select_chip)(nmtd->set, chip);
227                 }
228
229                 cur &= ~S3C2410_NFCONF_nFCE;
230         }
231
232         writel(cur, info->regs + S3C2410_NFCONF);
233 }
234
235 /* command and control functions */
236
237 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd)
238 {
239         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
240         struct nand_chip *chip = mtd->priv;
241         unsigned long cur;
242
243         switch (cmd) {
244         case NAND_CTL_SETNCE:
245                 cur = readl(info->regs + S3C2410_NFCONF);
246                 cur &= ~S3C2410_NFCONF_nFCE;
247                 writel(cur, info->regs + S3C2410_NFCONF);
248                 break;
249
250         case NAND_CTL_CLRNCE:
251                 cur = readl(info->regs + S3C2410_NFCONF);
252                 cur |= S3C2410_NFCONF_nFCE;
253                 writel(cur, info->regs + S3C2410_NFCONF);
254                 break;
255
256         case NAND_CTL_SETCLE:
257                 chip->IO_ADDR_W    = info->regs + S3C2410_NFCMD;
258                 break;
259
260         case NAND_CTL_SETALE:
261                 chip->IO_ADDR_W    = info->regs + S3C2410_NFADDR;
262                 break;
263
264                 /* NAND_CTL_CLRCLE: */
265                 /* NAND_CTL_CLRALE: */
266         default:
267                 chip->IO_ADDR_W    = info->regs + S3C2410_NFDATA;
268                 break;
269         }
270 }
271
272 /* s3c2410_nand_devready()
273  *
274  * returns 0 if the nand is busy, 1 if it is ready
275 */
276
277 static int s3c2410_nand_devready(struct mtd_info *mtd)
278 {
279         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
280         
281         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
282 }
283
284 /* ECC handling functions */
285
286 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
287                                      u_char *read_ecc, u_char *calc_ecc)
288 {
289         pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n",
290                  mtd, dat, read_ecc, calc_ecc);
291
292         pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n",
293                  read_ecc[0], read_ecc[1], read_ecc[2],
294                  calc_ecc[0], calc_ecc[1], calc_ecc[2]);
295
296         if (read_ecc[0] == calc_ecc[0] &&
297             read_ecc[1] == calc_ecc[1] &&
298             read_ecc[2] == calc_ecc[2]) 
299                 return 0;
300
301         /* we curently have no method for correcting the error */
302
303         return -1;
304 }
305
306 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
307 {
308         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
309         unsigned long ctrl;
310
311         ctrl = readl(info->regs + S3C2410_NFCONF);
312         ctrl |= S3C2410_NFCONF_INITECC;
313         writel(ctrl, info->regs + S3C2410_NFCONF);
314 }
315
316 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd,
317                                       const u_char *dat, u_char *ecc_code)
318 {
319         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
320
321         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
322         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
323         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
324
325         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n",
326                  ecc_code[0], ecc_code[1], ecc_code[2]);
327
328         return 0;
329 }
330
331
332 /* over-ride the standard functions for a little more speed? */
333
334 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
335 {
336         struct nand_chip *this = mtd->priv;
337         readsb(this->IO_ADDR_R, buf, len);
338 }
339
340 static void s3c2410_nand_write_buf(struct mtd_info *mtd,
341                                    const u_char *buf, int len)
342 {
343         struct nand_chip *this = mtd->priv;
344         writesb(this->IO_ADDR_W, buf, len);
345 }
346
347 /* device management functions */
348
349 static int s3c2410_nand_remove(struct device *dev)
350 {
351         struct s3c2410_nand_info *info = to_nand_info(dev);
352
353         dev_set_drvdata(dev, NULL);
354
355         if (info == NULL) 
356                 return 0;
357
358         /* first thing we need to do is release all our mtds
359          * and their partitions, then go through freeing the
360          * resources used 
361          */
362         
363         if (info->mtds != NULL) {
364                 struct s3c2410_nand_mtd *ptr = info->mtds;
365                 int mtdno;
366
367                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
368                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
369                         nand_release(&ptr->mtd);
370                 }
371
372                 kfree(info->mtds);
373         }
374
375         /* free the common resources */
376
377         if (info->clk != NULL && !IS_ERR(info->clk)) {
378                 clk_disable(info->clk);
379                 clk_unuse(info->clk);
380                 clk_put(info->clk);
381         }
382
383         if (info->regs != NULL) {
384                 iounmap(info->regs);
385                 info->regs = NULL;
386         }
387
388         if (info->area != NULL) {
389                 release_resource(info->area);
390                 kfree(info->area);
391                 info->area = NULL;
392         }
393
394         kfree(info);
395
396         return 0;
397 }
398
399 #ifdef CONFIG_MTD_PARTITIONS
400 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
401                                       struct s3c2410_nand_mtd *mtd,
402                                       struct s3c2410_nand_set *set)
403 {
404         if (set == NULL)
405                 return add_mtd_device(&mtd->mtd);
406
407         if (set->nr_partitions > 0 && set->partitions != NULL) {
408                 return add_mtd_partitions(&mtd->mtd,
409                                           set->partitions,
410                                           set->nr_partitions);
411         }
412
413         return add_mtd_device(&mtd->mtd);
414 }
415 #else
416 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
417                                       struct s3c2410_nand_mtd *mtd,
418                                       struct s3c2410_nand_set *set)
419 {
420         return add_mtd_device(&mtd->mtd);
421 }
422 #endif
423
424 /* s3c2410_nand_init_chip
425  *
426  * init a single instance of an chip 
427 */
428
429 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
430                                    struct s3c2410_nand_mtd *nmtd,
431                                    struct s3c2410_nand_set *set)
432 {
433         struct nand_chip *chip = &nmtd->chip;
434
435         chip->IO_ADDR_R    = info->regs + S3C2410_NFDATA;
436         chip->IO_ADDR_W    = info->regs + S3C2410_NFDATA;
437         chip->hwcontrol    = s3c2410_nand_hwcontrol;
438         chip->dev_ready    = s3c2410_nand_devready;
439         chip->write_buf    = s3c2410_nand_write_buf;
440         chip->read_buf     = s3c2410_nand_read_buf;
441         chip->select_chip  = s3c2410_nand_select_chip;
442         chip->chip_delay   = 50;
443         chip->priv         = nmtd;
444         chip->options      = 0;
445         chip->controller   = &info->controller;
446
447         nmtd->info         = info;
448         nmtd->mtd.priv     = chip;
449         nmtd->set          = set;
450
451         if (hardware_ecc) {
452                 chip->correct_data  = s3c2410_nand_correct_data;
453                 chip->enable_hwecc  = s3c2410_nand_enable_hwecc;
454                 chip->calculate_ecc = s3c2410_nand_calculate_ecc;
455                 chip->eccmode       = NAND_ECC_HW3_512;
456                 chip->autooob       = &nand_hw_eccoob;
457         } else {
458                 chip->eccmode       = NAND_ECC_SOFT;
459         }
460 }
461
462 /* s3c2410_nand_probe
463  *
464  * called by device layer when it finds a device matching
465  * one our driver can handled. This code checks to see if
466  * it can allocate all necessary resources then calls the
467  * nand layer to look for devices
468 */
469
470 static int s3c2410_nand_probe(struct device *dev)
471 {
472         struct platform_device *pdev = to_platform_device(dev);
473         struct s3c2410_platform_nand *plat = to_nand_plat(dev);
474         struct s3c2410_nand_info *info;
475         struct s3c2410_nand_mtd *nmtd;
476         struct s3c2410_nand_set *sets;
477         struct resource *res;
478         int err = 0;
479         int size;
480         int nr_sets;
481         int setno;
482
483         pr_debug("s3c2410_nand_probe(%p)\n", dev);
484
485         info = kmalloc(sizeof(*info), GFP_KERNEL);
486         if (info == NULL) {
487                 printk(KERN_ERR PFX "no memory for flash info\n");
488                 err = -ENOMEM;
489                 goto exit_error;
490         }
491
492         memzero(info, sizeof(*info));
493         dev_set_drvdata(dev, info);
494
495         spin_lock_init(&info->controller.lock);
496
497         /* get the clock source and enable it */
498
499         info->clk = clk_get(dev, "nand");
500         if (IS_ERR(info->clk)) {
501                 printk(KERN_ERR PFX "failed to get clock");
502                 err = -ENOENT;
503                 goto exit_error;
504         }
505
506         clk_use(info->clk);
507         clk_enable(info->clk);
508
509         /* allocate and map the resource */
510
511         res = pdev->resource;  /* assume that the flash has one resource */
512         size = res->end - res->start + 1;
513
514         info->area = request_mem_region(res->start, size, pdev->name);
515
516         if (info->area == NULL) {
517                 printk(KERN_ERR PFX "cannot reserve register region\n");
518                 err = -ENOENT;
519                 goto exit_error;
520         }
521
522         info->device = dev;
523         info->platform = plat;
524         info->regs = ioremap(res->start, size);
525
526         if (info->regs == NULL) {
527                 printk(KERN_ERR PFX "cannot reserve register region\n");
528                 err = -EIO;
529                 goto exit_error;
530         }               
531
532         printk(KERN_INFO PFX "mapped registers at %p\n", info->regs);
533
534         /* initialise the hardware */
535
536         err = s3c2410_nand_inithw(info, dev);
537         if (err != 0)
538                 goto exit_error;
539
540         sets = (plat != NULL) ? plat->sets : NULL;
541         nr_sets = (plat != NULL) ? plat->nr_sets : 1;
542
543         info->mtd_count = nr_sets;
544
545         /* allocate our information */
546
547         size = nr_sets * sizeof(*info->mtds);
548         info->mtds = kmalloc(size, GFP_KERNEL);
549         if (info->mtds == NULL) {
550                 printk(KERN_ERR PFX "failed to allocate mtd storage\n");
551                 err = -ENOMEM;
552                 goto exit_error;
553         }
554
555         memzero(info->mtds, size);
556
557         /* initialise all possible chips */
558
559         nmtd = info->mtds;
560
561         for (setno = 0; setno < nr_sets; setno++, nmtd++) {
562                 pr_debug("initialising set %d (%p, info %p)\n",
563                          setno, nmtd, info);
564                 
565                 s3c2410_nand_init_chip(info, nmtd, sets);
566
567                 nmtd->scan_res = nand_scan(&nmtd->mtd,
568                                            (sets) ? sets->nr_chips : 1);
569
570                 if (nmtd->scan_res == 0) {
571                         s3c2410_nand_add_partition(info, nmtd, sets);
572                 }
573
574                 if (sets != NULL)
575                         sets++;
576         }
577         
578         pr_debug("initialised ok\n");
579         return 0;
580
581  exit_error:
582         s3c2410_nand_remove(dev);
583
584         if (err == 0)
585                 err = -EINVAL;
586         return err;
587 }
588
589 static struct device_driver s3c2410_nand_driver = {
590         .name           = "s3c2410-nand",
591         .bus            = &platform_bus_type,
592         .probe          = s3c2410_nand_probe,
593         .remove         = s3c2410_nand_remove,
594 };
595
596 static int __init s3c2410_nand_init(void)
597 {
598         printk("S3C2410 NAND Driver, (c) 2004 Simtec Electronics\n");
599         return driver_register(&s3c2410_nand_driver);
600 }
601
602 static void __exit s3c2410_nand_exit(void)
603 {
604         driver_unregister(&s3c2410_nand_driver);
605 }
606
607 module_init(s3c2410_nand_init);
608 module_exit(s3c2410_nand_exit);
609
610 MODULE_LICENSE("GPL");
611 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
612 MODULE_DESCRIPTION("S3C2410 MTD NAND driver");