git.oblomov.eu Git - linux-2.6/blob - arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/config.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #ifdef CONFIG_ACPI
  34 #include <acpi/acpi_bus.h>
  35 #endif
  36
  37 #include <asm/io.h>
  38 #include <asm/smp.h>
  39 #include <asm/desc.h>
  40 #include <asm/proto.h>
  41 #include <asm/mach_apic.h>
  42 #include <asm/acpi.h>
  43 #include <asm/dma.h>
  44
  45 #define __apicdebuginit  __init
  46
  47 int sis_apic_bug; /* not actually supported, dummy for compile */
  48
  49 static int no_timer_check;
  50
  51 int disable_timer_pin_1 __initdata;
  52
  53 int timer_over_8254 __initdata = 0;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59
  60 /*
  61  * # of IRQ routing registers
  62  */
  63 int nr_ioapic_registers[MAX_IO_APICS];
  64
  65 /*
  66  * Rough estimation of how many shared IRQs there are, can
  67  * be changed anytime.
  68  */
  69 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  70 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  71
  72 /*
  73  * This is performance-critical, we want to do it O(1)
  74  *
  75  * the indexing order of this array favors 1:1 mappings
  76  * between pins and IRQs.
  77  */
  78
  79 static struct irq_pin_list {
  80         short apic, pin, next;
  81 } irq_2_pin[PIN_MAP_SIZE];
  82
  83 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  84 #ifdef CONFIG_PCI_MSI
  85 #define vector_to_irq(vector)   \
  86         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  87 #else
  88 #define vector_to_irq(vector)   (vector)
  89 #endif
  90
  91 #define __DO_ACTION(R, ACTION, FINAL)                                   \
  92                                                                         \
  93 {                                                                       \
  94         int pin;                                                        \
  95         struct irq_pin_list *entry = irq_2_pin + irq;                   \
  96                                                                         \
  97         BUG_ON(irq >= NR_IRQS);                                         \
  98         for (;;) {                                                      \
  99                 unsigned int reg;                                       \
 100                 pin = entry->pin;                                       \
 101                 if (pin == -1)                                          \
 102                         break;                                          \
 103                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 104                 reg ACTION;                                             \
 105                 io_apic_modify(entry->apic, reg);                       \
 106                 if (!entry->next)                                       \
 107                         break;                                          \
 108                 entry = irq_2_pin + entry->next;                        \
 109         }                                                               \
 110         FINAL;                                                          \
 111 }
 112
 113 #ifdef CONFIG_SMP
 114 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 115 {
 116         unsigned long flags;
 117         unsigned int dest;
 118         cpumask_t tmp;
 119
 120         cpus_and(tmp, mask, cpu_online_map);
 121         if (cpus_empty(tmp))
 122                 tmp = TARGET_CPUS;
 123
 124         cpus_and(mask, tmp, CPU_MASK_ALL);
 125
 126         dest = cpu_mask_to_apicid(mask);
 127
 128         /*
 129          * Only the high 8 bits are valid.
 130          */
 131         dest = SET_APIC_LOGICAL_ID(dest);
 132
 133         spin_lock_irqsave(&ioapic_lock, flags);
 134         __DO_ACTION(1, = dest, )
 135         set_irq_info(irq, mask);
 136         spin_unlock_irqrestore(&ioapic_lock, flags);
 137 }
 138 #endif
 139
 140 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
 141
 142 /*
 143  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 144  * shared ISA-space IRQs, so we have to support them. We are super
 145  * fast in the common case, and fast for shared ISA-space IRQs.
 146  */
 147 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 148 {
 149         static int first_free_entry = NR_IRQS;
 150         struct irq_pin_list *entry = irq_2_pin + irq;
 151
 152         BUG_ON(irq >= NR_IRQS);
 153         while (entry->next)
 154                 entry = irq_2_pin + entry->next;
 155
 156         if (entry->pin != -1) {
 157                 entry->next = first_free_entry;
 158                 entry = irq_2_pin + entry->next;
 159                 if (++first_free_entry >= PIN_MAP_SIZE)
 160                         panic("io_apic.c: ran out of irq_2_pin entries!");
 161         }
 162         entry->apic = apic;
 163         entry->pin = pin;
 164 }
 165
 166
 167 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 168                                                                         \
 169         static void name##_IO_APIC_irq (unsigned int irq)               \
 170         __DO_ACTION(R, ACTION, FINAL)
 171
 172 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 173                                                 /* mask = 1 */
 174 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 175                                                 /* mask = 0 */
 176
 177 static void mask_IO_APIC_irq (unsigned int irq)
 178 {
 179         unsigned long flags;
 180
 181         spin_lock_irqsave(&ioapic_lock, flags);
 182         __mask_IO_APIC_irq(irq);
 183         spin_unlock_irqrestore(&ioapic_lock, flags);
 184 }
 185
 186 static void unmask_IO_APIC_irq (unsigned int irq)
 187 {
 188         unsigned long flags;
 189
 190         spin_lock_irqsave(&ioapic_lock, flags);
 191         __unmask_IO_APIC_irq(irq);
 192         spin_unlock_irqrestore(&ioapic_lock, flags);
 193 }
 194
 195 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 196 {
 197         struct IO_APIC_route_entry entry;
 198         unsigned long flags;
 199
 200         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 201         spin_lock_irqsave(&ioapic_lock, flags);
 202         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 203         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 204         spin_unlock_irqrestore(&ioapic_lock, flags);
 205         if (entry.delivery_mode == dest_SMI)
 206                 return;
 207         /*
 208          * Disable it in the IO-APIC irq-routing table:
 209          */
 210         memset(&entry, 0, sizeof(entry));
 211         entry.mask = 1;
 212         spin_lock_irqsave(&ioapic_lock, flags);
 213         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 214         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 215         spin_unlock_irqrestore(&ioapic_lock, flags);
 216 }
 217
 218 static void clear_IO_APIC (void)
 219 {
 220         int apic, pin;
 221
 222         for (apic = 0; apic < nr_ioapics; apic++)
 223                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 224                         clear_IO_APIC_pin(apic, pin);
 225 }
 226
 227 /*
 228  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 229  * specific CPU-side IRQs.
 230  */
 231
 232 #define MAX_PIRQS 8
 233 static int pirq_entries [MAX_PIRQS];
 234 static int pirqs_enabled;
 235 int skip_ioapic_setup;
 236 int ioapic_force;
 237
 238 /* dummy parsing: see setup.c */
 239
 240 static int __init disable_ioapic_setup(char *str)
 241 {
 242         skip_ioapic_setup = 1;
 243         return 1;
 244 }
 245
 246 static int __init enable_ioapic_setup(char *str)
 247 {
 248         ioapic_force = 1;
 249         skip_ioapic_setup = 0;
 250         return 1;
 251 }
 252
 253 __setup("noapic", disable_ioapic_setup);
 254 __setup("apic", enable_ioapic_setup);
 255
 256 static int __init setup_disable_8254_timer(char *s)
 257 {
 258         timer_over_8254 = -1;
 259         return 1;
 260 }
 261 static int __init setup_enable_8254_timer(char *s)
 262 {
 263         timer_over_8254 = 2;
 264         return 1;
 265 }
 266
 267 __setup("disable_8254_timer", setup_disable_8254_timer);
 268 __setup("enable_8254_timer", setup_enable_8254_timer);
 269
 270 #include <asm/pci-direct.h>
 271 #include <linux/pci_ids.h>
 272 #include <linux/pci.h>
 273
 274
 275 #ifdef CONFIG_ACPI
 276
 277 static int nvidia_hpet_detected __initdata;
 278
 279 static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
 280 {
 281         nvidia_hpet_detected = 1;
 282         return 0;
 283 }
 284 #endif
 285
 286 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 287    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 288    Use pci direct infrastructure because this runs before the PCI subsystem.
 289
 290    Can be overwritten with "apic"
 291
 292    And another hack to disable the IOMMU on VIA chipsets.
 293
 294    ... and others. Really should move this somewhere else.
 295
 296    Kludge-O-Rama. */
 297 void __init check_ioapic(void)
 298 {
 299         int num,slot,func;
 300         /* Poor man's PCI discovery */
 301         for (num = 0; num < 32; num++) {
 302                 for (slot = 0; slot < 32; slot++) {
 303                         for (func = 0; func < 8; func++) {
 304                                 u32 class;
 305                                 u32 vendor;
 306                                 u8 type;
 307                                 class = read_pci_config(num,slot,func,
 308                                                         PCI_CLASS_REVISION);
 309                                 if (class == 0xffffffff)
 310                                         break;
 311
 312                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 313                                         continue;
 314
 315                                 vendor = read_pci_config(num, slot, func,
 316                                                          PCI_VENDOR_ID);
 317                                 vendor &= 0xffff;
 318                                 switch (vendor) {
 319                                 case PCI_VENDOR_ID_VIA:
 320 #ifdef CONFIG_GART_IOMMU
 321                                         if ((end_pfn > MAX_DMA32_PFN ||
 322                                              force_iommu) &&
 323                                             !iommu_aperture_allowed) {
 324                                                 printk(KERN_INFO
 325     "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
 326                                                 iommu_aperture_disabled = 1;
 327                                         }
 328 #endif
 329                                         return;
 330                                 case PCI_VENDOR_ID_NVIDIA:
 331 #ifdef CONFIG_ACPI
 332                                         /*
 333                                          * All timer overrides on Nvidia are
 334                                          * wrong unless HPET is enabled.
 335                                          */
 336                                         nvidia_hpet_detected = 0;
 337                                         acpi_table_parse(ACPI_HPET,
 338                                                         nvidia_hpet_check);
 339                                         if (nvidia_hpet_detected == 0) {
 340                                                 acpi_skip_timer_override = 1;
 341                                                 printk(KERN_INFO "Nvidia board "
 342                                                     "detected. Ignoring ACPI "
 343                                                     "timer override.\n");
 344                                         }
 345 #endif
 346                                         /* RED-PEN skip them on mptables too? */
 347                                         return;
 348
 349                                 /* This should be actually default, but
 350                                    for 2.6.16 let's do it for ATI only where
 351                                    it's really needed. */
 352                                 case PCI_VENDOR_ID_ATI:
 353                                         if (timer_over_8254 == 1) {
 354                                                 timer_over_8254 = 0;
 355                                         printk(KERN_INFO
 356                 "ATI board detected. Disabling timer routing over 8254.\n");
 357                                         }
 358                                         return;
 359                                 }
 360
 361
 362                                 /* No multi-function device? */
 363                                 type = read_pci_config_byte(num,slot,func,
 364                                                             PCI_HEADER_TYPE);
 365                                 if (!(type & 0x80))
 366                                         break;
 367                         }
 368                 }
 369         }
 370 }
 371
 372 static int __init ioapic_pirq_setup(char *str)
 373 {
 374         int i, max;
 375         int ints[MAX_PIRQS+1];
 376
 377         get_options(str, ARRAY_SIZE(ints), ints);
 378
 379         for (i = 0; i < MAX_PIRQS; i++)
 380                 pirq_entries[i] = -1;
 381
 382         pirqs_enabled = 1;
 383         apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
 384         max = MAX_PIRQS;
 385         if (ints[0] < MAX_PIRQS)
 386                 max = ints[0];
 387
 388         for (i = 0; i < max; i++) {
 389                 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 390                 /*
 391                  * PIRQs are mapped upside down, usually.
 392                  */
 393                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 394         }
 395         return 1;
 396 }
 397
 398 __setup("pirq=", ioapic_pirq_setup);
 399
 400 /*
 401  * Find the IRQ entry number of a certain pin.
 402  */
 403 static int find_irq_entry(int apic, int pin, int type)
 404 {
 405         int i;
 406
 407         for (i = 0; i < mp_irq_entries; i++)
 408                 if (mp_irqs[i].mpc_irqtype == type &&
 409                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 410                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 411                     mp_irqs[i].mpc_dstirq == pin)
 412                         return i;
 413
 414         return -1;
 415 }
 416
 417 /*
 418  * Find the pin to which IRQ[irq] (ISA) is connected
 419  */
 420 static int __init find_isa_irq_pin(int irq, int type)
 421 {
 422         int i;
 423
 424         for (i = 0; i < mp_irq_entries; i++) {
 425                 int lbus = mp_irqs[i].mpc_srcbus;
 426
 427                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 428                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 429                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 430                     (mp_irqs[i].mpc_irqtype == type) &&
 431                     (mp_irqs[i].mpc_srcbusirq == irq))
 432
 433                         return mp_irqs[i].mpc_dstirq;
 434         }
 435         return -1;
 436 }
 437
 438 static int __init find_isa_irq_apic(int irq, int type)
 439 {
 440         int i;
 441
 442         for (i = 0; i < mp_irq_entries; i++) {
 443                 int lbus = mp_irqs[i].mpc_srcbus;
 444
 445                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 446                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 447                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 448                     (mp_irqs[i].mpc_irqtype == type) &&
 449                     (mp_irqs[i].mpc_srcbusirq == irq))
 450                         break;
 451         }
 452         if (i < mp_irq_entries) {
 453                 int apic;
 454                 for(apic = 0; apic < nr_ioapics; apic++) {
 455                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 456                                 return apic;
 457                 }
 458         }
 459
 460         return -1;
 461 }
 462
 463 /*
 464  * Find a specific PCI IRQ entry.
 465  * Not an __init, possibly needed by modules
 466  */
 467 static int pin_2_irq(int idx, int apic, int pin);
 468
 469 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 470 {
 471         int apic, i, best_guess = -1;
 472
 473         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 474                 bus, slot, pin);
 475         if (mp_bus_id_to_pci_bus[bus] == -1) {
 476                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 477                 return -1;
 478         }
 479         for (i = 0; i < mp_irq_entries; i++) {
 480                 int lbus = mp_irqs[i].mpc_srcbus;
 481
 482                 for (apic = 0; apic < nr_ioapics; apic++)
 483                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 484                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 485                                 break;
 486
 487                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 488                     !mp_irqs[i].mpc_irqtype &&
 489                     (bus == lbus) &&
 490                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 491                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 492
 493                         if (!(apic || IO_APIC_IRQ(irq)))
 494                                 continue;
 495
 496                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 497                                 return irq;
 498                         /*
 499                          * Use the first all-but-pin matching entry as a
 500                          * best-guess fuzzy result for broken mptables.
 501                          */
 502                         if (best_guess < 0)
 503                                 best_guess = irq;
 504                 }
 505         }
 506         BUG_ON(best_guess >= NR_IRQS);
 507         return best_guess;
 508 }
 509
 510 /*
 511  * EISA Edge/Level control register, ELCR
 512  */
 513 static int EISA_ELCR(unsigned int irq)
 514 {
 515         if (irq < 16) {
 516                 unsigned int port = 0x4d0 + (irq >> 3);
 517                 return (inb(port) >> (irq & 7)) & 1;
 518         }
 519         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 520         return 0;
 521 }
 522
 523 /* EISA interrupts are always polarity zero and can be edge or level
 524  * trigger depending on the ELCR value.  If an interrupt is listed as
 525  * EISA conforming in the MP table, that means its trigger type must
 526  * be read in from the ELCR */
 527
 528 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 529 #define default_EISA_polarity(idx)      (0)
 530
 531 /* ISA interrupts are always polarity zero edge triggered,
 532  * when listed as conforming in the MP table. */
 533
 534 #define default_ISA_trigger(idx)        (0)
 535 #define default_ISA_polarity(idx)       (0)
 536
 537 /* PCI interrupts are always polarity one level triggered,
 538  * when listed as conforming in the MP table. */
 539
 540 #define default_PCI_trigger(idx)        (1)
 541 #define default_PCI_polarity(idx)       (1)
 542
 543 /* MCA interrupts are always polarity zero level triggered,
 544  * when listed as conforming in the MP table. */
 545
 546 #define default_MCA_trigger(idx)        (1)
 547 #define default_MCA_polarity(idx)       (0)
 548
 549 static int __init MPBIOS_polarity(int idx)
 550 {
 551         int bus = mp_irqs[idx].mpc_srcbus;
 552         int polarity;
 553
 554         /*
 555          * Determine IRQ line polarity (high active or low active):
 556          */
 557         switch (mp_irqs[idx].mpc_irqflag & 3)
 558         {
 559                 case 0: /* conforms, ie. bus-type dependent polarity */
 560                 {
 561                         switch (mp_bus_id_to_type[bus])
 562                         {
 563                                 case MP_BUS_ISA: /* ISA pin */
 564                                 {
 565                                         polarity = default_ISA_polarity(idx);
 566                                         break;
 567                                 }
 568                                 case MP_BUS_EISA: /* EISA pin */
 569                                 {
 570                                         polarity = default_EISA_polarity(idx);
 571                                         break;
 572                                 }
 573                                 case MP_BUS_PCI: /* PCI pin */
 574                                 {
 575                                         polarity = default_PCI_polarity(idx);
 576                                         break;
 577                                 }
 578                                 case MP_BUS_MCA: /* MCA pin */
 579                                 {
 580                                         polarity = default_MCA_polarity(idx);
 581                                         break;
 582                                 }
 583                                 default:
 584                                 {
 585                                         printk(KERN_WARNING "broken BIOS!!\n");
 586                                         polarity = 1;
 587                                         break;
 588                                 }
 589                         }
 590                         break;
 591                 }
 592                 case 1: /* high active */
 593                 {
 594                         polarity = 0;
 595                         break;
 596                 }
 597                 case 2: /* reserved */
 598                 {
 599                         printk(KERN_WARNING "broken BIOS!!\n");
 600                         polarity = 1;
 601                         break;
 602                 }
 603                 case 3: /* low active */
 604                 {
 605                         polarity = 1;
 606                         break;
 607                 }
 608                 default: /* invalid */
 609                 {
 610                         printk(KERN_WARNING "broken BIOS!!\n");
 611                         polarity = 1;
 612                         break;
 613                 }
 614         }
 615         return polarity;
 616 }
 617
 618 static int MPBIOS_trigger(int idx)
 619 {
 620         int bus = mp_irqs[idx].mpc_srcbus;
 621         int trigger;
 622
 623         /*
 624          * Determine IRQ trigger mode (edge or level sensitive):
 625          */
 626         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 627         {
 628                 case 0: /* conforms, ie. bus-type dependent */
 629                 {
 630                         switch (mp_bus_id_to_type[bus])
 631                         {
 632                                 case MP_BUS_ISA: /* ISA pin */
 633                                 {
 634                                         trigger = default_ISA_trigger(idx);
 635                                         break;
 636                                 }
 637                                 case MP_BUS_EISA: /* EISA pin */
 638                                 {
 639                                         trigger = default_EISA_trigger(idx);
 640                                         break;
 641                                 }
 642                                 case MP_BUS_PCI: /* PCI pin */
 643                                 {
 644                                         trigger = default_PCI_trigger(idx);
 645                                         break;
 646                                 }
 647                                 case MP_BUS_MCA: /* MCA pin */
 648                                 {
 649                                         trigger = default_MCA_trigger(idx);
 650                                         break;
 651                                 }
 652                                 default:
 653                                 {
 654                                         printk(KERN_WARNING "broken BIOS!!\n");
 655                                         trigger = 1;
 656                                         break;
 657                                 }
 658                         }
 659                         break;
 660                 }
 661                 case 1: /* edge */
 662                 {
 663                         trigger = 0;
 664                         break;
 665                 }
 666                 case 2: /* reserved */
 667                 {
 668                         printk(KERN_WARNING "broken BIOS!!\n");
 669                         trigger = 1;
 670                         break;
 671                 }
 672                 case 3: /* level */
 673                 {
 674                         trigger = 1;
 675                         break;
 676                 }
 677                 default: /* invalid */
 678                 {
 679                         printk(KERN_WARNING "broken BIOS!!\n");
 680                         trigger = 0;
 681                         break;
 682                 }
 683         }
 684         return trigger;
 685 }
 686
 687 static inline int irq_polarity(int idx)
 688 {
 689         return MPBIOS_polarity(idx);
 690 }
 691
 692 static inline int irq_trigger(int idx)
 693 {
 694         return MPBIOS_trigger(idx);
 695 }
 696
 697 static int next_irq = 16;
 698
 699 /*
 700  * gsi_irq_sharing -- Name overload!  "irq" can be either a legacy IRQ
 701  * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
 702  * from ACPI, which can reach 800 in large boxen.
 703  *
 704  * Compact the sparse GSI space into a sequential IRQ series and reuse
 705  * vectors if possible.
 706  */
 707 int gsi_irq_sharing(int gsi)
 708 {
 709         int i, tries, vector;
 710
 711         BUG_ON(gsi >= NR_IRQ_VECTORS);
 712
 713         if (platform_legacy_irq(gsi))
 714                 return gsi;
 715
 716         if (gsi_2_irq[gsi] != 0xFF)
 717                 return (int)gsi_2_irq[gsi];
 718
 719         tries = NR_IRQS;
 720   try_again:
 721         vector = assign_irq_vector(gsi);
 722
 723         /*
 724          * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
 725          * use of vector and if found, return that IRQ.  However, we never want
 726          * to share legacy IRQs, which usually have a different trigger mode
 727          * than PCI.
 728          */
 729         for (i = 0; i < NR_IRQS; i++)
 730                 if (IO_APIC_VECTOR(i) == vector)
 731                         break;
 732         if (platform_legacy_irq(i)) {
 733                 if (--tries >= 0) {
 734                         IO_APIC_VECTOR(i) = 0;
 735                         goto try_again;
 736                 }
 737                 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
 738         }
 739         if (i < NR_IRQS) {
 740                 gsi_2_irq[gsi] = i;
 741                 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
 742                                 gsi, vector, i);
 743                 return i;
 744         }
 745
 746         i = next_irq++;
 747         BUG_ON(i >= NR_IRQS);
 748         gsi_2_irq[gsi] = i;
 749         IO_APIC_VECTOR(i) = vector;
 750         printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
 751                         gsi, vector, i);
 752         return i;
 753 }
 754
 755 static int pin_2_irq(int idx, int apic, int pin)
 756 {
 757         int irq, i;
 758         int bus = mp_irqs[idx].mpc_srcbus;
 759
 760         /*
 761          * Debugging check, we are in big trouble if this message pops up!
 762          */
 763         if (mp_irqs[idx].mpc_dstirq != pin)
 764                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 765
 766         switch (mp_bus_id_to_type[bus])
 767         {
 768                 case MP_BUS_ISA: /* ISA pin */
 769                 case MP_BUS_EISA:
 770                 case MP_BUS_MCA:
 771                 {
 772                         irq = mp_irqs[idx].mpc_srcbusirq;
 773                         break;
 774                 }
 775                 case MP_BUS_PCI: /* PCI pin */
 776                 {
 777                         /*
 778                          * PCI IRQs are mapped in order
 779                          */
 780                         i = irq = 0;
 781                         while (i < apic)
 782                                 irq += nr_ioapic_registers[i++];
 783                         irq += pin;
 784                         irq = gsi_irq_sharing(irq);
 785                         break;
 786                 }
 787                 default:
 788                 {
 789                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 790                         irq = 0;
 791                         break;
 792                 }
 793         }
 794         BUG_ON(irq >= NR_IRQS);
 795
 796         /*
 797          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 798          */
 799         if ((pin >= 16) && (pin <= 23)) {
 800                 if (pirq_entries[pin-16] != -1) {
 801                         if (!pirq_entries[pin-16]) {
 802                                 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
 803                         } else {
 804                                 irq = pirq_entries[pin-16];
 805                                 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
 806                                                 pin-16, irq);
 807                         }
 808                 }
 809         }
 810         BUG_ON(irq >= NR_IRQS);
 811         return irq;
 812 }
 813
 814 static inline int IO_APIC_irq_trigger(int irq)
 815 {
 816         int apic, idx, pin;
 817
 818         for (apic = 0; apic < nr_ioapics; apic++) {
 819                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 820                         idx = find_irq_entry(apic,pin,mp_INT);
 821                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 822                                 return irq_trigger(idx);
 823                 }
 824         }
 825         /*
 826          * nonexistent IRQs are edge default
 827          */
 828         return 0;
 829 }
 830
 831 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 832 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
 833
 834 int assign_irq_vector(int irq)
 835 {
 836         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 837
 838         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
 839         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
 840                 return IO_APIC_VECTOR(irq);
 841 next:
 842         current_vector += 8;
 843         if (current_vector == IA32_SYSCALL_VECTOR)
 844                 goto next;
 845
 846         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 847                 /* If we run out of vectors on large boxen, must share them. */
 848                 offset = (offset + 1) % 8;
 849                 current_vector = FIRST_DEVICE_VECTOR + offset;
 850         }
 851
 852         vector_irq[current_vector] = irq;
 853         if (irq != AUTO_ASSIGN)
 854                 IO_APIC_VECTOR(irq) = current_vector;
 855
 856         return current_vector;
 857 }
 858
 859 extern void (*interrupt[NR_IRQS])(void);
 860 static struct hw_interrupt_type ioapic_level_type;
 861 static struct hw_interrupt_type ioapic_edge_type;
 862
 863 #define IOAPIC_AUTO     -1
 864 #define IOAPIC_EDGE     0
 865 #define IOAPIC_LEVEL    1
 866
 867 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 868 {
 869         if (use_pci_vector() && !platform_legacy_irq(irq)) {
 870                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 871                                 trigger == IOAPIC_LEVEL)
 872                         irq_desc[vector].handler = &ioapic_level_type;
 873                 else
 874                         irq_desc[vector].handler = &ioapic_edge_type;
 875                 set_intr_gate(vector, interrupt[vector]);
 876         } else  {
 877                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 878                                 trigger == IOAPIC_LEVEL)
 879                         irq_desc[irq].handler = &ioapic_level_type;
 880                 else
 881                         irq_desc[irq].handler = &ioapic_edge_type;
 882                 set_intr_gate(vector, interrupt[irq]);
 883         }
 884 }
 885
 886 static void __init setup_IO_APIC_irqs(void)
 887 {
 888         struct IO_APIC_route_entry entry;
 889         int apic, pin, idx, irq, first_notcon = 1, vector;
 890         unsigned long flags;
 891
 892         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 893
 894         for (apic = 0; apic < nr_ioapics; apic++) {
 895         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 896
 897                 /*
 898                  * add it to the IO-APIC irq-routing table:
 899                  */
 900                 memset(&entry,0,sizeof(entry));
 901
 902                 entry.delivery_mode = INT_DELIVERY_MODE;
 903                 entry.dest_mode = INT_DEST_MODE;
 904                 entry.mask = 0;                         /* enable IRQ */
 905                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 906
 907                 idx = find_irq_entry(apic,pin,mp_INT);
 908                 if (idx == -1) {
 909                         if (first_notcon) {
 910                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 911                                 first_notcon = 0;
 912                         } else
 913                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 914                         continue;
 915                 }
 916
 917                 entry.trigger = irq_trigger(idx);
 918                 entry.polarity = irq_polarity(idx);
 919
 920                 if (irq_trigger(idx)) {
 921                         entry.trigger = 1;
 922                         entry.mask = 1;
 923                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 924                 }
 925
 926                 irq = pin_2_irq(idx, apic, pin);
 927                 add_pin_to_irq(irq, apic, pin);
 928
 929                 if (!apic && !IO_APIC_IRQ(irq))
 930                         continue;
 931
 932                 if (IO_APIC_IRQ(irq)) {
 933                         vector = assign_irq_vector(irq);
 934                         entry.vector = vector;
 935
 936                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 937                         if (!apic && (irq < 16))
 938                                 disable_8259A_irq(irq);
 939                 }
 940                 spin_lock_irqsave(&ioapic_lock, flags);
 941                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 942                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 943                 set_native_irq_info(irq, TARGET_CPUS);
 944                 spin_unlock_irqrestore(&ioapic_lock, flags);
 945         }
 946         }
 947
 948         if (!first_notcon)
 949                 apic_printk(APIC_VERBOSE," not connected.\n");
 950 }
 951
 952 /*
 953  * Set up the 8259A-master output pin as broadcast to all
 954  * CPUs.
 955  */
 956 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 957 {
 958         struct IO_APIC_route_entry entry;
 959         unsigned long flags;
 960
 961         memset(&entry,0,sizeof(entry));
 962
 963         disable_8259A_irq(0);
 964
 965         /* mask LVT0 */
 966         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 967
 968         /*
 969          * We use logical delivery to get the timer IRQ
 970          * to the first CPU.
 971          */
 972         entry.dest_mode = INT_DEST_MODE;
 973         entry.mask = 0;                                 /* unmask IRQ now */
 974         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 975         entry.delivery_mode = INT_DELIVERY_MODE;
 976         entry.polarity = 0;
 977         entry.trigger = 0;
 978         entry.vector = vector;
 979
 980         /*
 981          * The timer IRQ doesn't have to know that behind the
 982          * scene we have a 8259A-master in AEOI mode ...
 983          */
 984         irq_desc[0].handler = &ioapic_edge_type;
 985
 986         /*
 987          * Add it to the IO-APIC irq-routing table:
 988          */
 989         spin_lock_irqsave(&ioapic_lock, flags);
 990         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 991         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 992         spin_unlock_irqrestore(&ioapic_lock, flags);
 993
 994         enable_8259A_irq(0);
 995 }
 996
 997 void __init UNEXPECTED_IO_APIC(void)
 998 {
 999 }
1000
1001 void __apicdebuginit print_IO_APIC(void)
1002 {
1003         int apic, i;
1004         union IO_APIC_reg_00 reg_00;
1005         union IO_APIC_reg_01 reg_01;
1006         union IO_APIC_reg_02 reg_02;
1007         unsigned long flags;
1008
1009         if (apic_verbosity == APIC_QUIET)
1010                 return;
1011
1012         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1013         for (i = 0; i < nr_ioapics; i++)
1014                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1015                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1016
1017         /*
1018          * We are a bit conservative about what we expect.  We have to
1019          * know about every hardware change ASAP.
1020          */
1021         printk(KERN_INFO "testing the IO APIC.......................\n");
1022
1023         for (apic = 0; apic < nr_ioapics; apic++) {
1024
1025         spin_lock_irqsave(&ioapic_lock, flags);
1026         reg_00.raw = io_apic_read(apic, 0);
1027         reg_01.raw = io_apic_read(apic, 1);
1028         if (reg_01.bits.version >= 0x10)
1029                 reg_02.raw = io_apic_read(apic, 2);
1030         spin_unlock_irqrestore(&ioapic_lock, flags);
1031
1032         printk("\n");
1033         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1034         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1035         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1036         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1037                 UNEXPECTED_IO_APIC();
1038
1039         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1040         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1041         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1042                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1043                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1044                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1045                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1046                 (reg_01.bits.entries != 0x2E) &&
1047                 (reg_01.bits.entries != 0x3F) &&
1048                 (reg_01.bits.entries != 0x03)
1049         )
1050                 UNEXPECTED_IO_APIC();
1051
1052         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1053         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1054         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1055                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1056                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1057                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1058                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1059                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1060         )
1061                 UNEXPECTED_IO_APIC();
1062         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1063                 UNEXPECTED_IO_APIC();
1064
1065         if (reg_01.bits.version >= 0x10) {
1066                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1067                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1068                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1069                         UNEXPECTED_IO_APIC();
1070         }
1071
1072         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1073
1074         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1075                           " Stat Dest Deli Vect:   \n");
1076
1077         for (i = 0; i <= reg_01.bits.entries; i++) {
1078                 struct IO_APIC_route_entry entry;
1079
1080                 spin_lock_irqsave(&ioapic_lock, flags);
1081                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1082                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1083                 spin_unlock_irqrestore(&ioapic_lock, flags);
1084
1085                 printk(KERN_DEBUG " %02x %03X %02X  ",
1086                         i,
1087                         entry.dest.logical.logical_dest,
1088                         entry.dest.physical.physical_dest
1089                 );
1090
1091                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1092                         entry.mask,
1093                         entry.trigger,
1094                         entry.irr,
1095                         entry.polarity,
1096                         entry.delivery_status,
1097                         entry.dest_mode,
1098                         entry.delivery_mode,
1099                         entry.vector
1100                 );
1101         }
1102         }
1103         if (use_pci_vector())
1104                 printk(KERN_INFO "Using vector-based indexing\n");
1105         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1106         for (i = 0; i < NR_IRQS; i++) {
1107                 struct irq_pin_list *entry = irq_2_pin + i;
1108                 if (entry->pin < 0)
1109                         continue;
1110                 if (use_pci_vector() && !platform_legacy_irq(i))
1111                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1112                 else
1113                         printk(KERN_DEBUG "IRQ%d ", i);
1114                 for (;;) {
1115                         printk("-> %d:%d", entry->apic, entry->pin);
1116                         if (!entry->next)
1117                                 break;
1118                         entry = irq_2_pin + entry->next;
1119                 }
1120                 printk("\n");
1121         }
1122
1123         printk(KERN_INFO ".................................... done.\n");
1124
1125         return;
1126 }
1127
1128 #if 0
1129
1130 static __apicdebuginit void print_APIC_bitfield (int base)
1131 {
1132         unsigned int v;
1133         int i, j;
1134
1135         if (apic_verbosity == APIC_QUIET)
1136                 return;
1137
1138         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1139         for (i = 0; i < 8; i++) {
1140                 v = apic_read(base + i*0x10);
1141                 for (j = 0; j < 32; j++) {
1142                         if (v & (1<<j))
1143                                 printk("1");
1144                         else
1145                                 printk("0");
1146                 }
1147                 printk("\n");
1148         }
1149 }
1150
1151 void __apicdebuginit print_local_APIC(void * dummy)
1152 {
1153         unsigned int v, ver, maxlvt;
1154
1155         if (apic_verbosity == APIC_QUIET)
1156                 return;
1157
1158         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1159                 smp_processor_id(), hard_smp_processor_id());
1160         v = apic_read(APIC_ID);
1161         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1162         v = apic_read(APIC_LVR);
1163         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1164         ver = GET_APIC_VERSION(v);
1165         maxlvt = get_maxlvt();
1166
1167         v = apic_read(APIC_TASKPRI);
1168         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1169
1170         v = apic_read(APIC_ARBPRI);
1171         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1172                 v & APIC_ARBPRI_MASK);
1173         v = apic_read(APIC_PROCPRI);
1174         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1175
1176         v = apic_read(APIC_EOI);
1177         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1178         v = apic_read(APIC_RRR);
1179         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1180         v = apic_read(APIC_LDR);
1181         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1182         v = apic_read(APIC_DFR);
1183         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1184         v = apic_read(APIC_SPIV);
1185         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1186
1187         printk(KERN_DEBUG "... APIC ISR field:\n");
1188         print_APIC_bitfield(APIC_ISR);
1189         printk(KERN_DEBUG "... APIC TMR field:\n");
1190         print_APIC_bitfield(APIC_TMR);
1191         printk(KERN_DEBUG "... APIC IRR field:\n");
1192         print_APIC_bitfield(APIC_IRR);
1193
1194         v = apic_read(APIC_ESR);
1195         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1196
1197         v = apic_read(APIC_ICR);
1198         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1199         v = apic_read(APIC_ICR2);
1200         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1201
1202         v = apic_read(APIC_LVTT);
1203         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1204
1205         if (maxlvt > 3) {                       /* PC is LVT#4. */
1206                 v = apic_read(APIC_LVTPC);
1207                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1208         }
1209         v = apic_read(APIC_LVT0);
1210         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1211         v = apic_read(APIC_LVT1);
1212         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1213
1214         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1215                 v = apic_read(APIC_LVTERR);
1216                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1217         }
1218
1219         v = apic_read(APIC_TMICT);
1220         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1221         v = apic_read(APIC_TMCCT);
1222         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1223         v = apic_read(APIC_TDCR);
1224         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1225         printk("\n");
1226 }
1227
1228 void print_all_local_APICs (void)
1229 {
1230         on_each_cpu(print_local_APIC, NULL, 1, 1);
1231 }
1232
1233 void __apicdebuginit print_PIC(void)
1234 {
1235         unsigned int v;
1236         unsigned long flags;
1237
1238         if (apic_verbosity == APIC_QUIET)
1239                 return;
1240
1241         printk(KERN_DEBUG "\nprinting PIC contents\n");
1242
1243         spin_lock_irqsave(&i8259A_lock, flags);
1244
1245         v = inb(0xa1) << 8 | inb(0x21);
1246         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1247
1248         v = inb(0xa0) << 8 | inb(0x20);
1249         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1250
1251         outb(0x0b,0xa0);
1252         outb(0x0b,0x20);
1253         v = inb(0xa0) << 8 | inb(0x20);
1254         outb(0x0a,0xa0);
1255         outb(0x0a,0x20);
1256
1257         spin_unlock_irqrestore(&i8259A_lock, flags);
1258
1259         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1260
1261         v = inb(0x4d1) << 8 | inb(0x4d0);
1262         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1263 }
1264
1265 #endif  /*  0  */
1266
1267 static void __init enable_IO_APIC(void)
1268 {
1269         union IO_APIC_reg_01 reg_01;
1270         int i8259_apic, i8259_pin;
1271         int i, apic;
1272         unsigned long flags;
1273
1274         for (i = 0; i < PIN_MAP_SIZE; i++) {
1275                 irq_2_pin[i].pin = -1;
1276                 irq_2_pin[i].next = 0;
1277         }
1278         if (!pirqs_enabled)
1279                 for (i = 0; i < MAX_PIRQS; i++)
1280                         pirq_entries[i] = -1;
1281
1282         /*
1283          * The number of IO-APIC IRQ registers (== #pins):
1284          */
1285         for (apic = 0; apic < nr_ioapics; apic++) {
1286                 spin_lock_irqsave(&ioapic_lock, flags);
1287                 reg_01.raw = io_apic_read(apic, 1);
1288                 spin_unlock_irqrestore(&ioapic_lock, flags);
1289                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1290         }
1291         for(apic = 0; apic < nr_ioapics; apic++) {
1292                 int pin;
1293                 /* See if any of the pins is in ExtINT mode */
1294                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1295                         struct IO_APIC_route_entry entry;
1296                         spin_lock_irqsave(&ioapic_lock, flags);
1297                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1298                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1299                         spin_unlock_irqrestore(&ioapic_lock, flags);
1300
1301
1302                         /* If the interrupt line is enabled and in ExtInt mode
1303                          * I have found the pin where the i8259 is connected.
1304                          */
1305                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1306                                 ioapic_i8259.apic = apic;
1307                                 ioapic_i8259.pin  = pin;
1308                                 goto found_i8259;
1309                         }
1310                 }
1311         }
1312  found_i8259:
1313         /* Look to see what if the MP table has reported the ExtINT */
1314         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1315         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1316         /* Trust the MP table if nothing is setup in the hardware */
1317         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1318                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1319                 ioapic_i8259.pin  = i8259_pin;
1320                 ioapic_i8259.apic = i8259_apic;
1321         }
1322         /* Complain if the MP table and the hardware disagree */
1323         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1324                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1325         {
1326                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1327         }
1328
1329         /*
1330          * Do not trust the IO-APIC being empty at bootup
1331          */
1332         clear_IO_APIC();
1333 }
1334
1335 /*
1336  * Not an __init, needed by the reboot code
1337  */
1338 void disable_IO_APIC(void)
1339 {
1340         /*
1341          * Clear the IO-APIC before rebooting:
1342          */
1343         clear_IO_APIC();
1344
1345         /*
1346          * If the i8259 is routed through an IOAPIC
1347          * Put that IOAPIC in virtual wire mode
1348          * so legacy interrupts can be delivered.
1349          */
1350         if (ioapic_i8259.pin != -1) {
1351                 struct IO_APIC_route_entry entry;
1352                 unsigned long flags;
1353
1354                 memset(&entry, 0, sizeof(entry));
1355                 entry.mask            = 0; /* Enabled */
1356                 entry.trigger         = 0; /* Edge */
1357                 entry.irr             = 0;
1358                 entry.polarity        = 0; /* High */
1359                 entry.delivery_status = 0;
1360                 entry.dest_mode       = 0; /* Physical */
1361                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1362                 entry.vector          = 0;
1363                 entry.dest.physical.physical_dest =
1364                                         GET_APIC_ID(apic_read(APIC_ID));
1365
1366                 /*
1367                  * Add it to the IO-APIC irq-routing table:
1368                  */
1369                 spin_lock_irqsave(&ioapic_lock, flags);
1370                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1371                         *(((int *)&entry)+1));
1372                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1373                         *(((int *)&entry)+0));
1374                 spin_unlock_irqrestore(&ioapic_lock, flags);
1375         }
1376
1377         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1378 }
1379
1380 /*
1381  * function to set the IO-APIC physical IDs based on the
1382  * values stored in the MPC table.
1383  *
1384  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1385  */
1386
1387 static void __init setup_ioapic_ids_from_mpc (void)
1388 {
1389         union IO_APIC_reg_00 reg_00;
1390         int apic;
1391         int i;
1392         unsigned char old_id;
1393         unsigned long flags;
1394
1395         /*
1396          * Set the IOAPIC ID to the value stored in the MPC table.
1397          */
1398         for (apic = 0; apic < nr_ioapics; apic++) {
1399
1400                 /* Read the register 0 value */
1401                 spin_lock_irqsave(&ioapic_lock, flags);
1402                 reg_00.raw = io_apic_read(apic, 0);
1403                 spin_unlock_irqrestore(&ioapic_lock, flags);
1404
1405                 old_id = mp_ioapics[apic].mpc_apicid;
1406
1407
1408                 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1409
1410
1411                 /*
1412                  * We need to adjust the IRQ routing table
1413                  * if the ID changed.
1414                  */
1415                 if (old_id != mp_ioapics[apic].mpc_apicid)
1416                         for (i = 0; i < mp_irq_entries; i++)
1417                                 if (mp_irqs[i].mpc_dstapic == old_id)
1418                                         mp_irqs[i].mpc_dstapic
1419                                                 = mp_ioapics[apic].mpc_apicid;
1420
1421                 /*
1422                  * Read the right value from the MPC table and
1423                  * write it into the ID register.
1424                  */
1425                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1426                                 mp_ioapics[apic].mpc_apicid);
1427
1428                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1429                 spin_lock_irqsave(&ioapic_lock, flags);
1430                 io_apic_write(apic, 0, reg_00.raw);
1431                 spin_unlock_irqrestore(&ioapic_lock, flags);
1432
1433                 /*
1434                  * Sanity check
1435                  */
1436                 spin_lock_irqsave(&ioapic_lock, flags);
1437                 reg_00.raw = io_apic_read(apic, 0);
1438                 spin_unlock_irqrestore(&ioapic_lock, flags);
1439                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1440                         printk("could not set ID!\n");
1441                 else
1442                         apic_printk(APIC_VERBOSE," ok.\n");
1443         }
1444 }
1445
1446 /*
1447  * There is a nasty bug in some older SMP boards, their mptable lies
1448  * about the timer IRQ. We do the following to work around the situation:
1449  *
1450  *      - timer IRQ defaults to IO-APIC IRQ
1451  *      - if this function detects that timer IRQs are defunct, then we fall
1452  *        back to ISA timer IRQs
1453  */
1454 static int __init timer_irq_works(void)
1455 {
1456         unsigned long t1 = jiffies;
1457
1458         local_irq_enable();
1459         /* Let ten ticks pass... */
1460         mdelay((10 * 1000) / HZ);
1461
1462         /*
1463          * Expect a few ticks at least, to be sure some possible
1464          * glue logic does not lock up after one or two first
1465          * ticks in a non-ExtINT mode.  Also the local APIC
1466          * might have cached one ExtINT interrupt.  Finally, at
1467          * least one tick may be lost due to delays.
1468          */
1469
1470         /* jiffies wrap? */
1471         if (jiffies - t1 > 4)
1472                 return 1;
1473         return 0;
1474 }
1475
1476 /*
1477  * In the SMP+IOAPIC case it might happen that there are an unspecified
1478  * number of pending IRQ events unhandled. These cases are very rare,
1479  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1480  * better to do it this way as thus we do not have to be aware of
1481  * 'pending' interrupts in the IRQ path, except at this point.
1482  */
1483 /*
1484  * Edge triggered needs to resend any interrupt
1485  * that was delayed but this is now handled in the device
1486  * independent code.
1487  */
1488
1489 /*
1490  * Starting up a edge-triggered IO-APIC interrupt is
1491  * nasty - we need to make sure that we get the edge.
1492  * If it is already asserted for some reason, we need
1493  * return 1 to indicate that is was pending.
1494  *
1495  * This is not complete - we should be able to fake
1496  * an edge even if it isn't on the 8259A...
1497  */
1498
1499 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1500 {
1501         int was_pending = 0;
1502         unsigned long flags;
1503
1504         spin_lock_irqsave(&ioapic_lock, flags);
1505         if (irq < 16) {
1506                 disable_8259A_irq(irq);
1507                 if (i8259A_irq_pending(irq))
1508                         was_pending = 1;
1509         }
1510         __unmask_IO_APIC_irq(irq);
1511         spin_unlock_irqrestore(&ioapic_lock, flags);
1512
1513         return was_pending;
1514 }
1515
1516 /*
1517  * Once we have recorded IRQ_PENDING already, we can mask the
1518  * interrupt for real. This prevents IRQ storms from unhandled
1519  * devices.
1520  */
1521 static void ack_edge_ioapic_irq(unsigned int irq)
1522 {
1523         move_irq(irq);
1524         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1525                                         == (IRQ_PENDING | IRQ_DISABLED))
1526                 mask_IO_APIC_irq(irq);
1527         ack_APIC_irq();
1528 }
1529
1530 /*
1531  * Level triggered interrupts can just be masked,
1532  * and shutting down and starting up the interrupt
1533  * is the same as enabling and disabling them -- except
1534  * with a startup need to return a "was pending" value.
1535  *
1536  * Level triggered interrupts are special because we
1537  * do not touch any IO-APIC register while handling
1538  * them. We ack the APIC in the end-IRQ handler, not
1539  * in the start-IRQ-handler. Protection against reentrance
1540  * from the same interrupt is still provided, both by the
1541  * generic IRQ layer and by the fact that an unacked local
1542  * APIC does not accept IRQs.
1543  */
1544 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1545 {
1546         unmask_IO_APIC_irq(irq);
1547
1548         return 0; /* don't check for pending */
1549 }
1550
1551 static void end_level_ioapic_irq (unsigned int irq)
1552 {
1553         move_irq(irq);
1554         ack_APIC_irq();
1555 }
1556
1557 #ifdef CONFIG_PCI_MSI
1558 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1559 {
1560         int irq = vector_to_irq(vector);
1561
1562         return startup_edge_ioapic_irq(irq);
1563 }
1564
1565 static void ack_edge_ioapic_vector(unsigned int vector)
1566 {
1567         int irq = vector_to_irq(vector);
1568
1569         move_native_irq(vector);
1570         ack_edge_ioapic_irq(irq);
1571 }
1572
1573 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1574 {
1575         int irq = vector_to_irq(vector);
1576
1577         return startup_level_ioapic_irq (irq);
1578 }
1579
1580 static void end_level_ioapic_vector (unsigned int vector)
1581 {
1582         int irq = vector_to_irq(vector);
1583
1584         move_native_irq(vector);
1585         end_level_ioapic_irq(irq);
1586 }
1587
1588 static void mask_IO_APIC_vector (unsigned int vector)
1589 {
1590         int irq = vector_to_irq(vector);
1591
1592         mask_IO_APIC_irq(irq);
1593 }
1594
1595 static void unmask_IO_APIC_vector (unsigned int vector)
1596 {
1597         int irq = vector_to_irq(vector);
1598
1599         unmask_IO_APIC_irq(irq);
1600 }
1601
1602 #ifdef CONFIG_SMP
1603 static void set_ioapic_affinity_vector (unsigned int vector,
1604                                         cpumask_t cpu_mask)
1605 {
1606         int irq = vector_to_irq(vector);
1607
1608         set_native_irq_info(vector, cpu_mask);
1609         set_ioapic_affinity_irq(irq, cpu_mask);
1610 }
1611 #endif // CONFIG_SMP
1612 #endif // CONFIG_PCI_MSI
1613
1614 /*
1615  * Level and edge triggered IO-APIC interrupts need different handling,
1616  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1617  * handled with the level-triggered descriptor, but that one has slightly
1618  * more overhead. Level-triggered interrupts cannot be handled with the
1619  * edge-triggered handler, without risking IRQ storms and other ugly
1620  * races.
1621  */
1622
1623 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1624         .typename = "IO-APIC-edge",
1625         .startup        = startup_edge_ioapic,
1626         .shutdown       = shutdown_edge_ioapic,
1627         .enable         = enable_edge_ioapic,
1628         .disable        = disable_edge_ioapic,
1629         .ack            = ack_edge_ioapic,
1630         .end            = end_edge_ioapic,
1631 #ifdef CONFIG_SMP
1632         .set_affinity = set_ioapic_affinity,
1633 #endif
1634 };
1635
1636 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1637         .typename = "IO-APIC-level",
1638         .startup        = startup_level_ioapic,
1639         .shutdown       = shutdown_level_ioapic,
1640         .enable         = enable_level_ioapic,
1641         .disable        = disable_level_ioapic,
1642         .ack            = mask_and_ack_level_ioapic,
1643         .end            = end_level_ioapic,
1644 #ifdef CONFIG_SMP
1645         .set_affinity = set_ioapic_affinity,
1646 #endif
1647 };
1648
1649 static inline void init_IO_APIC_traps(void)
1650 {
1651         int irq;
1652
1653         /*
1654          * NOTE! The local APIC isn't very good at handling
1655          * multiple interrupts at the same interrupt level.
1656          * As the interrupt level is determined by taking the
1657          * vector number and shifting that right by 4, we
1658          * want to spread these out a bit so that they don't
1659          * all fall in the same interrupt level.
1660          *
1661          * Also, we've got to be careful not to trash gate
1662          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1663          */
1664         for (irq = 0; irq < NR_IRQS ; irq++) {
1665                 int tmp = irq;
1666                 if (use_pci_vector()) {
1667                         if (!platform_legacy_irq(tmp))
1668                                 if ((tmp = vector_to_irq(tmp)) == -1)
1669                                         continue;
1670                 }
1671                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1672                         /*
1673                          * Hmm.. We don't have an entry for this,
1674                          * so default to an old-fashioned 8259
1675                          * interrupt if we can..
1676                          */
1677                         if (irq < 16)
1678                                 make_8259A_irq(irq);
1679                         else
1680                                 /* Strange. Oh, well.. */
1681                                 irq_desc[irq].handler = &no_irq_type;
1682                 }
1683         }
1684 }
1685
1686 static void enable_lapic_irq (unsigned int irq)
1687 {
1688         unsigned long v;
1689
1690         v = apic_read(APIC_LVT0);
1691         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1692 }
1693
1694 static void disable_lapic_irq (unsigned int irq)
1695 {
1696         unsigned long v;
1697
1698         v = apic_read(APIC_LVT0);
1699         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1700 }
1701
1702 static void ack_lapic_irq (unsigned int irq)
1703 {
1704         ack_APIC_irq();
1705 }
1706
1707 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1708
1709 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1710         .typename = "local-APIC-edge",
1711         .startup = NULL, /* startup_irq() not used for IRQ0 */
1712         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1713         .enable = enable_lapic_irq,
1714         .disable = disable_lapic_irq,
1715         .ack = ack_lapic_irq,
1716         .end = end_lapic_irq,
1717 };
1718
1719 static void setup_nmi (void)
1720 {
1721         /*
1722          * Dirty trick to enable the NMI watchdog ...
1723          * We put the 8259A master into AEOI mode and
1724          * unmask on all local APICs LVT0 as NMI.
1725          *
1726          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1727          * is from Maciej W. Rozycki - so we do not have to EOI from
1728          * the NMI handler or the timer interrupt.
1729          */
1730         printk(KERN_INFO "activating NMI Watchdog ...");
1731
1732         enable_NMI_through_LVT0(NULL);
1733
1734         printk(" done.\n");
1735 }
1736
1737 /*
1738  * This looks a bit hackish but it's about the only one way of sending
1739  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1740  * not support the ExtINT mode, unfortunately.  We need to send these
1741  * cycles as some i82489DX-based boards have glue logic that keeps the
1742  * 8259A interrupt line asserted until INTA.  --macro
1743  */
1744 static inline void unlock_ExtINT_logic(void)
1745 {
1746         int apic, pin, i;
1747         struct IO_APIC_route_entry entry0, entry1;
1748         unsigned char save_control, save_freq_select;
1749         unsigned long flags;
1750
1751         pin  = find_isa_irq_pin(8, mp_INT);
1752         apic = find_isa_irq_apic(8, mp_INT);
1753         if (pin == -1)
1754                 return;
1755
1756         spin_lock_irqsave(&ioapic_lock, flags);
1757         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1758         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1759         spin_unlock_irqrestore(&ioapic_lock, flags);
1760         clear_IO_APIC_pin(apic, pin);
1761
1762         memset(&entry1, 0, sizeof(entry1));
1763
1764         entry1.dest_mode = 0;                   /* physical delivery */
1765         entry1.mask = 0;                        /* unmask IRQ now */
1766         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1767         entry1.delivery_mode = dest_ExtINT;
1768         entry1.polarity = entry0.polarity;
1769         entry1.trigger = 0;
1770         entry1.vector = 0;
1771
1772         spin_lock_irqsave(&ioapic_lock, flags);
1773         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1774         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1775         spin_unlock_irqrestore(&ioapic_lock, flags);
1776
1777         save_control = CMOS_READ(RTC_CONTROL);
1778         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1779         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1780                    RTC_FREQ_SELECT);
1781         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1782
1783         i = 100;
1784         while (i-- > 0) {
1785                 mdelay(10);
1786                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1787                         i -= 10;
1788         }
1789
1790         CMOS_WRITE(save_control, RTC_CONTROL);
1791         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1792         clear_IO_APIC_pin(apic, pin);
1793
1794         spin_lock_irqsave(&ioapic_lock, flags);
1795         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1796         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1797         spin_unlock_irqrestore(&ioapic_lock, flags);
1798 }
1799
1800 int timer_uses_ioapic_pin_0;
1801
1802 /*
1803  * This code may look a bit paranoid, but it's supposed to cooperate with
1804  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1805  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1806  * fanatically on his truly buggy board.
1807  *
1808  * FIXME: really need to revamp this for modern platforms only.
1809  */
1810 static inline void check_timer(void)
1811 {
1812         int apic1, pin1, apic2, pin2;
1813         int vector;
1814
1815         /*
1816          * get/set the timer IRQ vector:
1817          */
1818         disable_8259A_irq(0);
1819         vector = assign_irq_vector(0);
1820         set_intr_gate(vector, interrupt[0]);
1821
1822         /*
1823          * Subtle, code in do_timer_interrupt() expects an AEOI
1824          * mode for the 8259A whenever interrupts are routed
1825          * through I/O APICs.  Also IRQ0 has to be enabled in
1826          * the 8259A which implies the virtual wire has to be
1827          * disabled in the local APIC.
1828          */
1829         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1830         init_8259A(1);
1831         if (timer_over_8254 > 0)
1832                 enable_8259A_irq(0);
1833
1834         pin1  = find_isa_irq_pin(0, mp_INT);
1835         apic1 = find_isa_irq_apic(0, mp_INT);
1836         pin2  = ioapic_i8259.pin;
1837         apic2 = ioapic_i8259.apic;
1838
1839         if (pin1 == 0)
1840                 timer_uses_ioapic_pin_0 = 1;
1841
1842         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1843                 vector, apic1, pin1, apic2, pin2);
1844
1845         if (pin1 != -1) {
1846                 /*
1847                  * Ok, does IRQ0 through the IOAPIC work?
1848                  */
1849                 unmask_IO_APIC_irq(0);
1850                 if (!no_timer_check && timer_irq_works()) {
1851                         nmi_watchdog_default();
1852                         if (nmi_watchdog == NMI_IO_APIC) {
1853                                 disable_8259A_irq(0);
1854                                 setup_nmi();
1855                                 enable_8259A_irq(0);
1856                         }
1857                         if (disable_timer_pin_1 > 0)
1858                                 clear_IO_APIC_pin(0, pin1);
1859                         return;
1860                 }
1861                 clear_IO_APIC_pin(apic1, pin1);
1862                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1863                                 "connected to IO-APIC\n");
1864         }
1865
1866         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1867                                 "through the 8259A ... ");
1868         if (pin2 != -1) {
1869                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1870                         apic2, pin2);
1871                 /*
1872                  * legacy devices should be connected to IO APIC #0
1873                  */
1874                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1875                 if (timer_irq_works()) {
1876                         apic_printk(APIC_VERBOSE," works.\n");
1877                         nmi_watchdog_default();
1878                         if (nmi_watchdog == NMI_IO_APIC) {
1879                                 setup_nmi();
1880                         }
1881                         return;
1882                 }
1883                 /*
1884                  * Cleanup, just in case ...
1885                  */
1886                 clear_IO_APIC_pin(apic2, pin2);
1887         }
1888         apic_printk(APIC_VERBOSE," failed.\n");
1889
1890         if (nmi_watchdog == NMI_IO_APIC) {
1891                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1892                 nmi_watchdog = 0;
1893         }
1894
1895         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1896
1897         disable_8259A_irq(0);
1898         irq_desc[0].handler = &lapic_irq_type;
1899         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1900         enable_8259A_irq(0);
1901
1902         if (timer_irq_works()) {
1903                 apic_printk(APIC_VERBOSE," works.\n");
1904                 return;
1905         }
1906         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1907         apic_printk(APIC_VERBOSE," failed.\n");
1908
1909         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1910
1911         init_8259A(0);
1912         make_8259A_irq(0);
1913         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1914
1915         unlock_ExtINT_logic();
1916
1917         if (timer_irq_works()) {
1918                 apic_printk(APIC_VERBOSE," works.\n");
1919                 return;
1920         }
1921         apic_printk(APIC_VERBOSE," failed :(.\n");
1922         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1923 }
1924
1925 static int __init notimercheck(char *s)
1926 {
1927         no_timer_check = 1;
1928         return 1;
1929 }
1930 __setup("no_timer_check", notimercheck);
1931
1932 /*
1933  *
1934  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1935  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1936  *   Linux doesn't really care, as it's not actually used
1937  *   for any interrupt handling anyway.
1938  */
1939 #define PIC_IRQS        (1<<2)
1940
1941 void __init setup_IO_APIC(void)
1942 {
1943         enable_IO_APIC();
1944
1945         if (acpi_ioapic)
1946                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1947         else
1948                 io_apic_irqs = ~PIC_IRQS;
1949
1950         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1951
1952         /*
1953          * Set up the IO-APIC IRQ routing table.
1954          */
1955         if (!acpi_ioapic)
1956                 setup_ioapic_ids_from_mpc();
1957         sync_Arb_IDs();
1958         setup_IO_APIC_irqs();
1959         init_IO_APIC_traps();
1960         check_timer();
1961         if (!acpi_ioapic)
1962                 print_IO_APIC();
1963 }
1964
1965 struct sysfs_ioapic_data {
1966         struct sys_device dev;
1967         struct IO_APIC_route_entry entry[0];
1968 };
1969 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1970
1971 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1972 {
1973         struct IO_APIC_route_entry *entry;
1974         struct sysfs_ioapic_data *data;
1975         unsigned long flags;
1976         int i;
1977
1978         data = container_of(dev, struct sysfs_ioapic_data, dev);
1979         entry = data->entry;
1980         spin_lock_irqsave(&ioapic_lock, flags);
1981         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1982                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1983                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1984         }
1985         spin_unlock_irqrestore(&ioapic_lock, flags);
1986
1987         return 0;
1988 }
1989
1990 static int ioapic_resume(struct sys_device *dev)
1991 {
1992         struct IO_APIC_route_entry *entry;
1993         struct sysfs_ioapic_data *data;
1994         unsigned long flags;
1995         union IO_APIC_reg_00 reg_00;
1996         int i;
1997
1998         data = container_of(dev, struct sysfs_ioapic_data, dev);
1999         entry = data->entry;
2000
2001         spin_lock_irqsave(&ioapic_lock, flags);
2002         reg_00.raw = io_apic_read(dev->id, 0);
2003         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2004                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2005                 io_apic_write(dev->id, 0, reg_00.raw);
2006         }
2007         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2008                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2009                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2010         }
2011         spin_unlock_irqrestore(&ioapic_lock, flags);
2012
2013         return 0;
2014 }
2015
2016 static struct sysdev_class ioapic_sysdev_class = {
2017         set_kset_name("ioapic"),
2018         .suspend = ioapic_suspend,
2019         .resume = ioapic_resume,
2020 };
2021
2022 static int __init ioapic_init_sysfs(void)
2023 {
2024         struct sys_device * dev;
2025         int i, size, error = 0;
2026
2027         error = sysdev_class_register(&ioapic_sysdev_class);
2028         if (error)
2029                 return error;
2030
2031         for (i = 0; i < nr_ioapics; i++ ) {
2032                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2033                         * sizeof(struct IO_APIC_route_entry);
2034                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2035                 if (!mp_ioapic_data[i]) {
2036                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2037                         continue;
2038                 }
2039                 memset(mp_ioapic_data[i], 0, size);
2040                 dev = &mp_ioapic_data[i]->dev;
2041                 dev->id = i;
2042                 dev->cls = &ioapic_sysdev_class;
2043                 error = sysdev_register(dev);
2044                 if (error) {
2045                         kfree(mp_ioapic_data[i]);
2046                         mp_ioapic_data[i] = NULL;
2047                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2048                         continue;
2049                 }
2050         }
2051
2052         return 0;
2053 }
2054
2055 device_initcall(ioapic_init_sysfs);
2056
2057 /* --------------------------------------------------------------------------
2058                           ACPI-based IOAPIC Configuration
2059    -------------------------------------------------------------------------- */
2060
2061 #ifdef CONFIG_ACPI
2062
2063 #define IO_APIC_MAX_ID          0xFE
2064
2065 int __init io_apic_get_version (int ioapic)
2066 {
2067         union IO_APIC_reg_01    reg_01;
2068         unsigned long flags;
2069
2070         spin_lock_irqsave(&ioapic_lock, flags);
2071         reg_01.raw = io_apic_read(ioapic, 1);
2072         spin_unlock_irqrestore(&ioapic_lock, flags);
2073
2074         return reg_01.bits.version;
2075 }
2076
2077
2078 int __init io_apic_get_redir_entries (int ioapic)
2079 {
2080         union IO_APIC_reg_01    reg_01;
2081         unsigned long flags;
2082
2083         spin_lock_irqsave(&ioapic_lock, flags);
2084         reg_01.raw = io_apic_read(ioapic, 1);
2085         spin_unlock_irqrestore(&ioapic_lock, flags);
2086
2087         return reg_01.bits.entries;
2088 }
2089
2090
2091 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2092 {
2093         struct IO_APIC_route_entry entry;
2094         unsigned long flags;
2095
2096         if (!IO_APIC_IRQ(irq)) {
2097                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2098                         ioapic);
2099                 return -EINVAL;
2100         }
2101
2102         /*
2103          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2104          * Note that we mask (disable) IRQs now -- these get enabled when the
2105          * corresponding device driver registers for this IRQ.
2106          */
2107
2108         memset(&entry,0,sizeof(entry));
2109
2110         entry.delivery_mode = INT_DELIVERY_MODE;
2111         entry.dest_mode = INT_DEST_MODE;
2112         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2113         entry.trigger = triggering;
2114         entry.polarity = polarity;
2115         entry.mask = 1;                                  /* Disabled (masked) */
2116
2117         irq = gsi_irq_sharing(irq);
2118         /*
2119          * IRQs < 16 are already in the irq_2_pin[] map
2120          */
2121         if (irq >= 16)
2122                 add_pin_to_irq(irq, ioapic, pin);
2123
2124         entry.vector = assign_irq_vector(irq);
2125
2126         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2127                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2128                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2129                triggering, polarity);
2130
2131         ioapic_register_intr(irq, entry.vector, triggering);
2132
2133         if (!ioapic && (irq < 16))
2134                 disable_8259A_irq(irq);
2135
2136         spin_lock_irqsave(&ioapic_lock, flags);
2137         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2138         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2139         set_native_irq_info(use_pci_vector() ?  entry.vector : irq, TARGET_CPUS);
2140         spin_unlock_irqrestore(&ioapic_lock, flags);
2141
2142         return 0;
2143 }
2144
2145 #endif /* CONFIG_ACPI */
2146
2147
2148 /*
2149  * This function currently is only a helper for the i386 smp boot process where
2150  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2151  * so mask in all cases should simply be TARGET_CPUS
2152  */
2153 #ifdef CONFIG_SMP
2154 void __init setup_ioapic_dest(void)
2155 {
2156         int pin, ioapic, irq, irq_entry;
2157
2158         if (skip_ioapic_setup == 1)
2159                 return;
2160
2161         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2162                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2163                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2164                         if (irq_entry == -1)
2165                                 continue;
2166                         irq = pin_2_irq(irq_entry, ioapic, pin);
2167                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2168                 }
2169
2170         }
2171 }
2172 #endif