git.oblomov.eu Git - linux-2.6/blob - drivers/spi/pxa2xx_spi.c

   1 /*
   2  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21 #include <linux/device.h>
  22 #include <linux/ioport.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/spi/spi.h>
  28 #include <linux/workqueue.h>
  29 #include <linux/errno.h>
  30 #include <linux/delay.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34 #include <asm/hardware.h>
  35 #include <asm/delay.h>
  36 #include <asm/dma.h>
  37
  38 #include <asm/arch/hardware.h>
  39 #include <asm/arch/pxa-regs.h>
  40 #include <asm/arch/pxa2xx_spi.h>
  41
  42 MODULE_AUTHOR("Stephen Street");
  43 MODULE_DESCRIPTION("PXA2xx SSP SPI Contoller");
  44 MODULE_LICENSE("GPL");
  45
  46 #define MAX_BUSES 3
  47
  48 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
  49 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
  50 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
  51
  52 #define DEFINE_SSP_REG(reg, off) \
  53 static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \
  54 static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }
  55
  56 DEFINE_SSP_REG(SSCR0, 0x00)
  57 DEFINE_SSP_REG(SSCR1, 0x04)
  58 DEFINE_SSP_REG(SSSR, 0x08)
  59 DEFINE_SSP_REG(SSITR, 0x0c)
  60 DEFINE_SSP_REG(SSDR, 0x10)
  61 DEFINE_SSP_REG(SSTO, 0x28)
  62 DEFINE_SSP_REG(SSPSP, 0x2c)
  63
  64 #define START_STATE ((void*)0)
  65 #define RUNNING_STATE ((void*)1)
  66 #define DONE_STATE ((void*)2)
  67 #define ERROR_STATE ((void*)-1)
  68
  69 #define QUEUE_RUNNING 0
  70 #define QUEUE_STOPPED 1
  71
  72 struct driver_data {
  73         /* Driver model hookup */
  74         struct platform_device *pdev;
  75
  76         /* SPI framework hookup */
  77         enum pxa_ssp_type ssp_type;
  78         struct spi_master *master;
  79
  80         /* PXA hookup */
  81         struct pxa2xx_spi_master *master_info;
  82
  83         /* DMA setup stuff */
  84         int rx_channel;
  85         int tx_channel;
  86         u32 *null_dma_buf;
  87
  88         /* SSP register addresses */
  89         void *ioaddr;
  90         u32 ssdr_physical;
  91
  92         /* SSP masks*/
  93         u32 dma_cr1;
  94         u32 int_cr1;
  95         u32 clear_sr;
  96         u32 mask_sr;
  97
  98         /* Driver message queue */
  99         struct workqueue_struct *workqueue;
 100         struct work_struct pump_messages;
 101         spinlock_t lock;
 102         struct list_head queue;
 103         int busy;
 104         int run;
 105
 106         /* Message Transfer pump */
 107         struct tasklet_struct pump_transfers;
 108
 109         /* Current message transfer state info */
 110         struct spi_message* cur_msg;
 111         struct spi_transfer* cur_transfer;
 112         struct chip_data *cur_chip;
 113         size_t len;
 114         void *tx;
 115         void *tx_end;
 116         void *rx;
 117         void *rx_end;
 118         int dma_mapped;
 119         dma_addr_t rx_dma;
 120         dma_addr_t tx_dma;
 121         size_t rx_map_len;
 122         size_t tx_map_len;
 123         u8 n_bytes;
 124         u32 dma_width;
 125         int cs_change;
 126         void (*write)(struct driver_data *drv_data);
 127         void (*read)(struct driver_data *drv_data);
 128         irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
 129         void (*cs_control)(u32 command);
 130 };
 131
 132 struct chip_data {
 133         u32 cr0;
 134         u32 cr1;
 135         u32 to;
 136         u32 psp;
 137         u32 timeout;
 138         u8 n_bytes;
 139         u32 dma_width;
 140         u32 dma_burst_size;
 141         u32 threshold;
 142         u32 dma_threshold;
 143         u8 enable_dma;
 144         u8 bits_per_word;
 145         u32 speed_hz;
 146         void (*write)(struct driver_data *drv_data);
 147         void (*read)(struct driver_data *drv_data);
 148         void (*cs_control)(u32 command);
 149 };
 150
 151 static void pump_messages(void *data);
 152
 153 static int flush(struct driver_data *drv_data)
 154 {
 155         unsigned long limit = loops_per_jiffy << 1;
 156
 157         void *reg = drv_data->ioaddr;
 158
 159         do {
 160                 while (read_SSSR(reg) & SSSR_RNE) {
 161                         read_SSDR(reg);
 162                 }
 163         } while ((read_SSSR(reg) & SSSR_BSY) && limit--);
 164         write_SSSR(SSSR_ROR, reg);
 165
 166         return limit;
 167 }
 168
 169 static void restore_state(struct driver_data *drv_data)
 170 {
 171         void *reg = drv_data->ioaddr;
 172
 173         /* Clear status and disable clock */
 174         write_SSSR(drv_data->clear_sr, reg);
 175         write_SSCR0(drv_data->cur_chip->cr0 & ~SSCR0_SSE, reg);
 176
 177         /* Load the registers */
 178         write_SSCR1(drv_data->cur_chip->cr1, reg);
 179         write_SSCR0(drv_data->cur_chip->cr0, reg);
 180         if (drv_data->ssp_type != PXA25x_SSP) {
 181                 write_SSTO(0, reg);
 182                 write_SSPSP(drv_data->cur_chip->psp, reg);
 183         }
 184 }
 185
 186 static void null_cs_control(u32 command)
 187 {
 188 }
 189
 190 static void null_writer(struct driver_data *drv_data)
 191 {
 192         void *reg = drv_data->ioaddr;
 193         u8 n_bytes = drv_data->n_bytes;
 194
 195         while ((read_SSSR(reg) & SSSR_TNF)
 196                         && (drv_data->tx < drv_data->tx_end)) {
 197                 write_SSDR(0, reg);
 198                 drv_data->tx += n_bytes;
 199         }
 200 }
 201
 202 static void null_reader(struct driver_data *drv_data)
 203 {
 204         void *reg = drv_data->ioaddr;
 205         u8 n_bytes = drv_data->n_bytes;
 206
 207         while ((read_SSSR(reg) & SSSR_RNE)
 208                         && (drv_data->rx < drv_data->rx_end)) {
 209                 read_SSDR(reg);
 210                 drv_data->rx += n_bytes;
 211         }
 212 }
 213
 214 static void u8_writer(struct driver_data *drv_data)
 215 {
 216         void *reg = drv_data->ioaddr;
 217
 218         while ((read_SSSR(reg) & SSSR_TNF)
 219                         && (drv_data->tx < drv_data->tx_end)) {
 220                 write_SSDR(*(u8 *)(drv_data->tx), reg);
 221                 ++drv_data->tx;
 222         }
 223 }
 224
 225 static void u8_reader(struct driver_data *drv_data)
 226 {
 227         void *reg = drv_data->ioaddr;
 228
 229         while ((read_SSSR(reg) & SSSR_RNE)
 230                         && (drv_data->rx < drv_data->rx_end)) {
 231                 *(u8 *)(drv_data->rx) = read_SSDR(reg);
 232                 ++drv_data->rx;
 233         }
 234 }
 235
 236 static void u16_writer(struct driver_data *drv_data)
 237 {
 238         void *reg = drv_data->ioaddr;
 239
 240         while ((read_SSSR(reg) & SSSR_TNF)
 241                         && (drv_data->tx < drv_data->tx_end)) {
 242                 write_SSDR(*(u16 *)(drv_data->tx), reg);
 243                 drv_data->tx += 2;
 244         }
 245 }
 246
 247 static void u16_reader(struct driver_data *drv_data)
 248 {
 249         void *reg = drv_data->ioaddr;
 250
 251         while ((read_SSSR(reg) & SSSR_RNE)
 252                         && (drv_data->rx < drv_data->rx_end)) {
 253                 *(u16 *)(drv_data->rx) = read_SSDR(reg);
 254                 drv_data->rx += 2;
 255         }
 256 }
 257 static void u32_writer(struct driver_data *drv_data)
 258 {
 259         void *reg = drv_data->ioaddr;
 260
 261         while ((read_SSSR(reg) & SSSR_TNF)
 262                         && (drv_data->tx < drv_data->tx_end)) {
 263                 write_SSDR(*(u32 *)(drv_data->tx), reg);
 264                 drv_data->tx += 4;
 265         }
 266 }
 267
 268 static void u32_reader(struct driver_data *drv_data)
 269 {
 270         void *reg = drv_data->ioaddr;
 271
 272         while ((read_SSSR(reg) & SSSR_RNE)
 273                         && (drv_data->rx < drv_data->rx_end)) {
 274                 *(u32 *)(drv_data->rx) = read_SSDR(reg);
 275                 drv_data->rx += 4;
 276         }
 277 }
 278
 279 static void *next_transfer(struct driver_data *drv_data)
 280 {
 281         struct spi_message *msg = drv_data->cur_msg;
 282         struct spi_transfer *trans = drv_data->cur_transfer;
 283
 284         /* Move to next transfer */
 285         if (trans->transfer_list.next != &msg->transfers) {
 286                 drv_data->cur_transfer =
 287                         list_entry(trans->transfer_list.next,
 288                                         struct spi_transfer,
 289                                         transfer_list);
 290                 return RUNNING_STATE;
 291         } else
 292                 return DONE_STATE;
 293 }
 294
 295 static int map_dma_buffers(struct driver_data *drv_data)
 296 {
 297         struct spi_message *msg = drv_data->cur_msg;
 298         struct device *dev = &msg->spi->dev;
 299
 300         if (!drv_data->cur_chip->enable_dma)
 301                 return 0;
 302
 303         if (msg->is_dma_mapped)
 304                 return  drv_data->rx_dma && drv_data->tx_dma;
 305
 306         if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
 307                 return 0;
 308
 309         /* Modify setup if rx buffer is null */
 310         if (drv_data->rx == NULL) {
 311                 *drv_data->null_dma_buf = 0;
 312                 drv_data->rx = drv_data->null_dma_buf;
 313                 drv_data->rx_map_len = 4;
 314         } else
 315                 drv_data->rx_map_len = drv_data->len;
 316
 317
 318         /* Modify setup if tx buffer is null */
 319         if (drv_data->tx == NULL) {
 320                 *drv_data->null_dma_buf = 0;
 321                 drv_data->tx = drv_data->null_dma_buf;
 322                 drv_data->tx_map_len = 4;
 323         } else
 324                 drv_data->tx_map_len = drv_data->len;
 325
 326         /* Stream map the rx buffer */
 327         drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
 328                                                 drv_data->rx_map_len,
 329                                                 DMA_FROM_DEVICE);
 330         if (dma_mapping_error(drv_data->rx_dma))
 331                 return 0;
 332
 333         /* Stream map the tx buffer */
 334         drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
 335                                                 drv_data->tx_map_len,
 336                                                 DMA_TO_DEVICE);
 337
 338         if (dma_mapping_error(drv_data->tx_dma)) {
 339                 dma_unmap_single(dev, drv_data->rx_dma,
 340                                         drv_data->rx_map_len, DMA_FROM_DEVICE);
 341                 return 0;
 342         }
 343
 344         return 1;
 345 }
 346
 347 static void unmap_dma_buffers(struct driver_data *drv_data)
 348 {
 349         struct device *dev;
 350
 351         if (!drv_data->dma_mapped)
 352                 return;
 353
 354         if (!drv_data->cur_msg->is_dma_mapped) {
 355                 dev = &drv_data->cur_msg->spi->dev;
 356                 dma_unmap_single(dev, drv_data->rx_dma,
 357                                         drv_data->rx_map_len, DMA_FROM_DEVICE);
 358                 dma_unmap_single(dev, drv_data->tx_dma,
 359                                         drv_data->tx_map_len, DMA_TO_DEVICE);
 360         }
 361
 362         drv_data->dma_mapped = 0;
 363 }
 364
 365 /* caller already set message->status; dma and pio irqs are blocked */
 366 static void giveback(struct driver_data *drv_data)
 367 {
 368         struct spi_transfer* last_transfer;
 369         unsigned long flags;
 370         struct spi_message *msg;
 371
 372         spin_lock_irqsave(&drv_data->lock, flags);
 373         msg = drv_data->cur_msg;
 374         drv_data->cur_msg = NULL;
 375         drv_data->cur_transfer = NULL;
 376         drv_data->cur_chip = NULL;
 377         queue_work(drv_data->workqueue, &drv_data->pump_messages);
 378         spin_unlock_irqrestore(&drv_data->lock, flags);
 379
 380         last_transfer = list_entry(msg->transfers.prev,
 381                                         struct spi_transfer,
 382                                         transfer_list);
 383
 384         if (!last_transfer->cs_change)
 385                 drv_data->cs_control(PXA2XX_CS_DEASSERT);
 386
 387         msg->state = NULL;
 388         if (msg->complete)
 389                 msg->complete(msg->context);
 390 }
 391
 392 static int wait_ssp_rx_stall(void *ioaddr)
 393 {
 394         unsigned long limit = loops_per_jiffy << 1;
 395
 396         while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)
 397                 cpu_relax();
 398
 399         return limit;
 400 }
 401
 402 static int wait_dma_channel_stop(int channel)
 403 {
 404         unsigned long limit = loops_per_jiffy << 1;
 405
 406         while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)
 407                 cpu_relax();
 408
 409         return limit;
 410 }
 411
 412 static void dma_handler(int channel, void *data, struct pt_regs *regs)
 413 {
 414         struct driver_data *drv_data = data;
 415         struct spi_message *msg = drv_data->cur_msg;
 416         void *reg = drv_data->ioaddr;
 417         u32 irq_status = DCSR(channel) & DMA_INT_MASK;
 418         u32 trailing_sssr = 0;
 419
 420         if (irq_status & DCSR_BUSERR) {
 421
 422                 /* Disable interrupts, clear status and reset DMA */
 423                 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 424                 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
 425                 if (drv_data->ssp_type != PXA25x_SSP)
 426                         write_SSTO(0, reg);
 427                 write_SSSR(drv_data->clear_sr, reg);
 428                 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 429                 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 430
 431                 if (flush(drv_data) == 0)
 432                         dev_err(&drv_data->pdev->dev,
 433                                         "dma_handler: flush fail\n");
 434
 435                 unmap_dma_buffers(drv_data);
 436
 437                 if (channel == drv_data->tx_channel)
 438                         dev_err(&drv_data->pdev->dev,
 439                                 "dma_handler: bad bus address on "
 440                                 "tx channel %d, source %x target = %x\n",
 441                                 channel, DSADR(channel), DTADR(channel));
 442                 else
 443                         dev_err(&drv_data->pdev->dev,
 444                                 "dma_handler: bad bus address on "
 445                                 "rx channel %d, source %x target = %x\n",
 446                                 channel, DSADR(channel), DTADR(channel));
 447
 448                 msg->state = ERROR_STATE;
 449                 tasklet_schedule(&drv_data->pump_transfers);
 450         }
 451
 452         /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
 453         if ((drv_data->ssp_type == PXA25x_SSP)
 454                 && (channel == drv_data->tx_channel)
 455                 && (irq_status & DCSR_ENDINTR)) {
 456
 457                 /* Wait for rx to stall */
 458                 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
 459                         dev_err(&drv_data->pdev->dev,
 460                                 "dma_handler: ssp rx stall failed\n");
 461
 462                 /* Clear and disable interrupts on SSP and DMA channels*/
 463                 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
 464                 write_SSSR(drv_data->clear_sr, reg);
 465                 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 466                 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 467                 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
 468                         dev_err(&drv_data->pdev->dev,
 469                                 "dma_handler: dma rx channel stop failed\n");
 470
 471                 unmap_dma_buffers(drv_data);
 472
 473                 /* Read trailing bytes */
 474                 /* Calculate number of trailing bytes, read them */
 475                 trailing_sssr = read_SSSR(reg);
 476                 if ((trailing_sssr & 0xf008) != 0xf000) {
 477                         drv_data->rx = drv_data->rx_end -
 478                                         (((trailing_sssr >> 12) & 0x0f) + 1);
 479                         drv_data->read(drv_data);
 480                 }
 481                 msg->actual_length += drv_data->len;
 482
 483                 /* Release chip select if requested, transfer delays are
 484                  * handled in pump_transfers */
 485                 if (drv_data->cs_change)
 486                         drv_data->cs_control(PXA2XX_CS_DEASSERT);
 487
 488                 /* Move to next transfer */
 489                 msg->state = next_transfer(drv_data);
 490
 491                 /* Schedule transfer tasklet */
 492                 tasklet_schedule(&drv_data->pump_transfers);
 493         }
 494 }
 495
 496 static irqreturn_t dma_transfer(struct driver_data *drv_data)
 497 {
 498         u32 irq_status;
 499         u32 trailing_sssr = 0;
 500         struct spi_message *msg = drv_data->cur_msg;
 501         void *reg = drv_data->ioaddr;
 502
 503         irq_status = read_SSSR(reg) & drv_data->mask_sr;
 504         if (irq_status & SSSR_ROR) {
 505                 /* Clear and disable interrupts on SSP and DMA channels*/
 506                 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 507                 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
 508                 if (drv_data->ssp_type != PXA25x_SSP)
 509                         write_SSTO(0, reg);
 510                 write_SSSR(drv_data->clear_sr, reg);
 511                 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 512                 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 513                 unmap_dma_buffers(drv_data);
 514
 515                 if (flush(drv_data) == 0)
 516                         dev_err(&drv_data->pdev->dev,
 517                                         "dma_transfer: flush fail\n");
 518
 519                 dev_warn(&drv_data->pdev->dev, "dma_transfer: fifo overun\n");
 520
 521                 drv_data->cur_msg->state = ERROR_STATE;
 522                 tasklet_schedule(&drv_data->pump_transfers);
 523
 524                 return IRQ_HANDLED;
 525         }
 526
 527         /* Check for false positive timeout */
 528         if ((irq_status & SSSR_TINT) && DCSR(drv_data->tx_channel) & DCSR_RUN) {
 529                 write_SSSR(SSSR_TINT, reg);
 530                 return IRQ_HANDLED;
 531         }
 532
 533         if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
 534
 535                 /* Clear and disable interrupts on SSP and DMA channels*/
 536                 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
 537                 if (drv_data->ssp_type != PXA25x_SSP)
 538                         write_SSTO(0, reg);
 539                 write_SSSR(drv_data->clear_sr, reg);
 540                 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 541                 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 542
 543                 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
 544                         dev_err(&drv_data->pdev->dev,
 545                                 "dma_transfer: dma rx channel stop failed\n");
 546
 547                 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
 548                         dev_err(&drv_data->pdev->dev,
 549                                 "dma_transfer: ssp rx stall failed\n");
 550
 551                 unmap_dma_buffers(drv_data);
 552
 553                 /* Calculate number of trailing bytes, read them */
 554                 trailing_sssr = read_SSSR(reg);
 555                 if ((trailing_sssr & 0xf008) != 0xf000) {
 556                         drv_data->rx = drv_data->rx_end -
 557                                         (((trailing_sssr >> 12) & 0x0f) + 1);
 558                         drv_data->read(drv_data);
 559                 }
 560                 msg->actual_length += drv_data->len;
 561
 562                 /* Release chip select if requested, transfer delays are
 563                  * handled in pump_transfers */
 564                 if (drv_data->cs_change)
 565                         drv_data->cs_control(PXA2XX_CS_DEASSERT);
 566
 567                 /* Move to next transfer */
 568                 msg->state = next_transfer(drv_data);
 569
 570                 /* Schedule transfer tasklet */
 571                 tasklet_schedule(&drv_data->pump_transfers);
 572
 573                 return IRQ_HANDLED;
 574         }
 575
 576         /* Opps problem detected */
 577         return IRQ_NONE;
 578 }
 579
 580 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 581 {
 582         struct spi_message *msg = drv_data->cur_msg;
 583         void *reg = drv_data->ioaddr;
 584         unsigned long limit = loops_per_jiffy << 1;
 585         u32 irq_status;
 586         u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
 587                         drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 588
 589         while ((irq_status = read_SSSR(reg) & irq_mask)) {
 590
 591                 if (irq_status & SSSR_ROR) {
 592
 593                         /* Clear and disable interrupts */
 594                         write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 595                         write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 596                         if (drv_data->ssp_type != PXA25x_SSP)
 597                                 write_SSTO(0, reg);
 598                         write_SSSR(drv_data->clear_sr, reg);
 599
 600                         if (flush(drv_data) == 0)
 601                                 dev_err(&drv_data->pdev->dev,
 602                                         "interrupt_transfer: flush fail\n");
 603
 604                         /* Stop the SSP */
 605
 606                         dev_warn(&drv_data->pdev->dev,
 607                                         "interrupt_transfer: fifo overun\n");
 608
 609                         msg->state = ERROR_STATE;
 610                         tasklet_schedule(&drv_data->pump_transfers);
 611
 612                         return IRQ_HANDLED;
 613                 }
 614
 615                 /* Look for false positive timeout */
 616                 if ((irq_status & SSSR_TINT)
 617                                 && (drv_data->rx < drv_data->rx_end))
 618                         write_SSSR(SSSR_TINT, reg);
 619
 620                 /* Pump data */
 621                 drv_data->read(drv_data);
 622                 drv_data->write(drv_data);
 623
 624                 if (drv_data->tx == drv_data->tx_end) {
 625                         /* Disable tx interrupt */
 626                         write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
 627                         irq_mask = drv_data->mask_sr & ~SSSR_TFS;
 628
 629                         /* PXA25x_SSP has no timeout, read trailing bytes */
 630                         if (drv_data->ssp_type == PXA25x_SSP) {
 631                                 while ((read_SSSR(reg) & SSSR_BSY) && limit--)
 632                                         drv_data->read(drv_data);
 633
 634                                 if (limit == 0)
 635                                         dev_err(&drv_data->pdev->dev,
 636                                                 "interrupt_transfer: "
 637                                                 "trailing byte read failed\n");
 638                         }
 639                 }
 640
 641                 if ((irq_status & SSSR_TINT)
 642                                 || (drv_data->rx == drv_data->rx_end)) {
 643
 644                         /* Clear timeout */
 645                         write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 646                         if (drv_data->ssp_type != PXA25x_SSP)
 647                                 write_SSTO(0, reg);
 648                         write_SSSR(drv_data->clear_sr, reg);
 649
 650                         /* Update total byte transfered */
 651                         msg->actual_length += drv_data->len;
 652
 653                         /* Release chip select if requested, transfer delays are
 654                          * handled in pump_transfers */
 655                         if (drv_data->cs_change)
 656                                 drv_data->cs_control(PXA2XX_CS_DEASSERT);
 657
 658                         /* Move to next transfer */
 659                         msg->state = next_transfer(drv_data);
 660
 661                         /* Schedule transfer tasklet */
 662                         tasklet_schedule(&drv_data->pump_transfers);
 663                 }
 664         }
 665
 666         /* We did something */
 667         return IRQ_HANDLED;
 668 }
 669
 670 static irqreturn_t ssp_int(int irq, void *dev_id, struct pt_regs *regs)
 671 {
 672         struct driver_data *drv_data = (struct driver_data *)dev_id;
 673         void *reg = drv_data->ioaddr;
 674
 675         if (!drv_data->cur_msg) {
 676
 677                 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 678                 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 679                 if (drv_data->ssp_type != PXA25x_SSP)
 680                         write_SSTO(0, reg);
 681                 write_SSSR(drv_data->clear_sr, reg);
 682
 683                 dev_err(&drv_data->pdev->dev, "bad message state "
 684                                 "in interrupt handler");
 685
 686                 /* Never fail */
 687                 return IRQ_HANDLED;
 688         }
 689
 690         return drv_data->transfer_handler(drv_data);
 691 }
 692
 693 static void pump_transfers(unsigned long data)
 694 {
 695         struct driver_data *drv_data = (struct driver_data *)data;
 696         struct spi_message *message = NULL;
 697         struct spi_transfer *transfer = NULL;
 698         struct spi_transfer *previous = NULL;
 699         struct chip_data *chip = NULL;
 700         void *reg = drv_data->ioaddr;
 701         u32 clk_div = 0;
 702         u8 bits = 0;
 703         u32 speed = 0;
 704         u32 cr0;
 705
 706         /* Get current state information */
 707         message = drv_data->cur_msg;
 708         transfer = drv_data->cur_transfer;
 709         chip = drv_data->cur_chip;
 710
 711         /* Handle for abort */
 712         if (message->state == ERROR_STATE) {
 713                 message->status = -EIO;
 714                 giveback(drv_data);
 715                 return;
 716         }
 717
 718         /* Handle end of message */
 719         if (message->state == DONE_STATE) {
 720                 message->status = 0;
 721                 giveback(drv_data);
 722                 return;
 723         }
 724
 725         /* Delay if requested at end of transfer*/
 726         if (message->state == RUNNING_STATE) {
 727                 previous = list_entry(transfer->transfer_list.prev,
 728                                         struct spi_transfer,
 729                                         transfer_list);
 730                 if (previous->delay_usecs)
 731                         udelay(previous->delay_usecs);
 732         }
 733
 734         /* Setup the transfer state based on the type of transfer */
 735         if (flush(drv_data) == 0) {
 736                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 737                 message->status = -EIO;
 738                 giveback(drv_data);
 739                 return;
 740         }
 741         drv_data->n_bytes = chip->n_bytes;
 742         drv_data->dma_width = chip->dma_width;
 743         drv_data->cs_control = chip->cs_control;
 744         drv_data->tx = (void *)transfer->tx_buf;
 745         drv_data->tx_end = drv_data->tx + transfer->len;
 746         drv_data->rx = transfer->rx_buf;
 747         drv_data->rx_end = drv_data->rx + transfer->len;
 748         drv_data->rx_dma = transfer->rx_dma;
 749         drv_data->tx_dma = transfer->tx_dma;
 750         drv_data->len = transfer->len;
 751         drv_data->write = drv_data->tx ? chip->write : null_writer;
 752         drv_data->read = drv_data->rx ? chip->read : null_reader;
 753         drv_data->cs_change = transfer->cs_change;
 754
 755         /* Change speed and bit per word on a per transfer */
 756         if (transfer->speed_hz || transfer->bits_per_word) {
 757
 758                 /* Disable clock */
 759                 write_SSCR0(chip->cr0 & ~SSCR0_SSE, reg);
 760                 cr0 = chip->cr0;
 761                 bits = chip->bits_per_word;
 762                 speed = chip->speed_hz;
 763
 764                 if (transfer->speed_hz)
 765                         speed = transfer->speed_hz;
 766
 767                 if (transfer->bits_per_word)
 768                         bits = transfer->bits_per_word;
 769
 770                 if (reg == SSP1_VIRT)
 771                         clk_div = SSP1_SerClkDiv(speed);
 772                 else if (reg == SSP2_VIRT)
 773                         clk_div = SSP2_SerClkDiv(speed);
 774                 else if (reg == SSP3_VIRT)
 775                         clk_div = SSP3_SerClkDiv(speed);
 776
 777                 if (bits <= 8) {
 778                         drv_data->n_bytes = 1;
 779                         drv_data->dma_width = DCMD_WIDTH1;
 780                         drv_data->read = drv_data->read != null_reader ?
 781                                                 u8_reader : null_reader;
 782                         drv_data->write = drv_data->write != null_writer ?
 783                                                 u8_writer : null_writer;
 784                 } else if (bits <= 16) {
 785                         drv_data->n_bytes = 2;
 786                         drv_data->dma_width = DCMD_WIDTH2;
 787                         drv_data->read = drv_data->read != null_reader ?
 788                                                 u16_reader : null_reader;
 789                         drv_data->write = drv_data->write != null_writer ?
 790                                                 u16_writer : null_writer;
 791                 } else if (bits <= 32) {
 792                         drv_data->n_bytes = 4;
 793                         drv_data->dma_width = DCMD_WIDTH4;
 794                         drv_data->read = drv_data->read != null_reader ?
 795                                                 u32_reader : null_reader;
 796                         drv_data->write = drv_data->write != null_writer ?
 797                                                 u32_writer : null_writer;
 798                 }
 799
 800                 cr0 = clk_div
 801                         | SSCR0_Motorola
 802                         | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 803                         | SSCR0_SSE
 804                         | (bits > 16 ? SSCR0_EDSS : 0);
 805
 806                 /* Start it back up */
 807                 write_SSCR0(cr0, reg);
 808         }
 809
 810         message->state = RUNNING_STATE;
 811
 812         /* Try to map dma buffer and do a dma transfer if successful */
 813         if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {
 814
 815                 /* Ensure we have the correct interrupt handler */
 816                 drv_data->transfer_handler = dma_transfer;
 817
 818                 /* Setup rx DMA Channel */
 819                 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 820                 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
 821                 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
 822                 if (drv_data->rx == drv_data->null_dma_buf)
 823                         /* No target address increment */
 824                         DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
 825                                                         | drv_data->dma_width
 826                                                         | chip->dma_burst_size
 827                                                         | drv_data->len;
 828                 else
 829                         DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
 830                                                         | DCMD_FLOWSRC
 831                                                         | drv_data->dma_width
 832                                                         | chip->dma_burst_size
 833                                                         | drv_data->len;
 834
 835                 /* Setup tx DMA Channel */
 836                 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 837                 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
 838                 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
 839                 if (drv_data->tx == drv_data->null_dma_buf)
 840                         /* No source address increment */
 841                         DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
 842                                                         | drv_data->dma_width
 843                                                         | chip->dma_burst_size
 844                                                         | drv_data->len;
 845                 else
 846                         DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
 847                                                         | DCMD_FLOWTRG
 848                                                         | drv_data->dma_width
 849                                                         | chip->dma_burst_size
 850                                                         | drv_data->len;
 851
 852                 /* Enable dma end irqs on SSP to detect end of transfer */
 853                 if (drv_data->ssp_type == PXA25x_SSP)
 854                         DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
 855
 856                 /* Fix me, need to handle cs polarity */
 857                 drv_data->cs_control(PXA2XX_CS_ASSERT);
 858
 859                 /* Go baby, go */
 860                 write_SSSR(drv_data->clear_sr, reg);
 861                 DCSR(drv_data->rx_channel) |= DCSR_RUN;
 862                 DCSR(drv_data->tx_channel) |= DCSR_RUN;
 863                 if (drv_data->ssp_type != PXA25x_SSP)
 864                         write_SSTO(chip->timeout, reg);
 865                 write_SSCR1(chip->cr1
 866                                 | chip->dma_threshold
 867                                 | drv_data->dma_cr1,
 868                                 reg);
 869         } else {
 870                 /* Ensure we have the correct interrupt handler */
 871                 drv_data->transfer_handler = interrupt_transfer;
 872
 873                 /* Fix me, need to handle cs polarity */
 874                 drv_data->cs_control(PXA2XX_CS_ASSERT);
 875
 876                 /* Go baby, go */
 877                 write_SSSR(drv_data->clear_sr, reg);
 878                 if (drv_data->ssp_type != PXA25x_SSP)
 879                         write_SSTO(chip->timeout, reg);
 880                 write_SSCR1(chip->cr1
 881                                 | chip->threshold
 882                                 | drv_data->int_cr1,
 883                                 reg);
 884         }
 885 }
 886
 887 static void pump_messages(void *data)
 888 {
 889         struct driver_data *drv_data = data;
 890         unsigned long flags;
 891
 892         /* Lock queue and check for queue work */
 893         spin_lock_irqsave(&drv_data->lock, flags);
 894         if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
 895                 drv_data->busy = 0;
 896                 spin_unlock_irqrestore(&drv_data->lock, flags);
 897                 return;
 898         }
 899
 900         /* Make sure we are not already running a message */
 901         if (drv_data->cur_msg) {
 902                 spin_unlock_irqrestore(&drv_data->lock, flags);
 903                 return;
 904         }
 905
 906         /* Extract head of queue */
 907         drv_data->cur_msg = list_entry(drv_data->queue.next,
 908                                         struct spi_message, queue);
 909         list_del_init(&drv_data->cur_msg->queue);
 910
 911         /* Initial message state*/
 912         drv_data->cur_msg->state = START_STATE;
 913         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
 914                                                 struct spi_transfer,
 915                                                 transfer_list);
 916
 917         /* Setup the SSP using the per chip configuration */
 918         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
 919         restore_state(drv_data);
 920
 921         /* Mark as busy and launch transfers */
 922         tasklet_schedule(&drv_data->pump_transfers);
 923
 924         drv_data->busy = 1;
 925         spin_unlock_irqrestore(&drv_data->lock, flags);
 926 }
 927
 928 static int transfer(struct spi_device *spi, struct spi_message *msg)
 929 {
 930         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 931         unsigned long flags;
 932
 933         spin_lock_irqsave(&drv_data->lock, flags);
 934
 935         if (drv_data->run == QUEUE_STOPPED) {
 936                 spin_unlock_irqrestore(&drv_data->lock, flags);
 937                 return -ESHUTDOWN;
 938         }
 939
 940         msg->actual_length = 0;
 941         msg->status = -EINPROGRESS;
 942         msg->state = START_STATE;
 943
 944         list_add_tail(&msg->queue, &drv_data->queue);
 945
 946         if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
 947                 queue_work(drv_data->workqueue, &drv_data->pump_messages);
 948
 949         spin_unlock_irqrestore(&drv_data->lock, flags);
 950
 951         return 0;
 952 }
 953
 954 static int setup(struct spi_device *spi)
 955 {
 956         struct pxa2xx_spi_chip *chip_info = NULL;
 957         struct chip_data *chip;
 958         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 959         unsigned int clk_div;
 960
 961         if (!spi->bits_per_word)
 962                 spi->bits_per_word = 8;
 963
 964         if (drv_data->ssp_type != PXA25x_SSP
 965                         && (spi->bits_per_word < 4 || spi->bits_per_word > 32))
 966                 return -EINVAL;
 967         else if (spi->bits_per_word < 4 || spi->bits_per_word > 16)
 968                 return -EINVAL;
 969
 970         /* Only alloc (or use chip_info) on first setup */
 971         chip = spi_get_ctldata(spi);
 972         if (chip == NULL) {
 973                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 974                 if (!chip)
 975                         return -ENOMEM;
 976
 977                 chip->cs_control = null_cs_control;
 978                 chip->enable_dma = 0;
 979                 chip->timeout = SSP_TIMEOUT(1000);
 980                 chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
 981                 chip->dma_burst_size = drv_data->master_info->enable_dma ?
 982                                         DCMD_BURST8 : 0;
 983
 984                 chip_info = spi->controller_data;
 985         }
 986
 987         /* chip_info isn't always needed */
 988         if (chip_info) {
 989                 if (chip_info->cs_control)
 990                         chip->cs_control = chip_info->cs_control;
 991
 992                 chip->timeout = SSP_TIMEOUT(chip_info->timeout_microsecs);
 993
 994                 chip->threshold = SSCR1_RxTresh(chip_info->rx_threshold)
 995                                         | SSCR1_TxTresh(chip_info->tx_threshold);
 996
 997                 chip->enable_dma = chip_info->dma_burst_size != 0
 998                                         && drv_data->master_info->enable_dma;
 999                 chip->dma_threshold = 0;
1000
1001                 if (chip->enable_dma) {
1002                         if (chip_info->dma_burst_size <= 8) {
1003                                 chip->dma_threshold = SSCR1_RxTresh(8)
1004                                                         | SSCR1_TxTresh(8);
1005                                 chip->dma_burst_size = DCMD_BURST8;
1006                         } else if (chip_info->dma_burst_size <= 16) {
1007                                 chip->dma_threshold = SSCR1_RxTresh(16)
1008                                                         | SSCR1_TxTresh(16);
1009                                 chip->dma_burst_size = DCMD_BURST16;
1010                         } else {
1011                                 chip->dma_threshold = SSCR1_RxTresh(32)
1012                                                         | SSCR1_TxTresh(32);
1013                                 chip->dma_burst_size = DCMD_BURST32;
1014                         }
1015                 }
1016
1017
1018                 if (chip_info->enable_loopback)
1019                         chip->cr1 = SSCR1_LBM;
1020         }
1021
1022         if (drv_data->ioaddr == SSP1_VIRT)
1023                 clk_div = SSP1_SerClkDiv(spi->max_speed_hz);
1024         else if (drv_data->ioaddr == SSP2_VIRT)
1025                 clk_div = SSP2_SerClkDiv(spi->max_speed_hz);
1026         else if (drv_data->ioaddr == SSP3_VIRT)
1027                 clk_div = SSP3_SerClkDiv(spi->max_speed_hz);
1028         else
1029                 return -ENODEV;
1030         chip->speed_hz = spi->max_speed_hz;
1031
1032         chip->cr0 = clk_div
1033                         | SSCR0_Motorola
1034                         | SSCR0_DataSize(spi->bits_per_word > 16 ?
1035                                 spi->bits_per_word - 16 : spi->bits_per_word)
1036                         | SSCR0_SSE
1037                         | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1038         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) << 4)
1039                         | (((spi->mode & SPI_CPOL) != 0) << 3);
1040
1041         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1042         if (drv_data->ssp_type != PXA25x_SSP)
1043                 dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
1044                                 spi->bits_per_word,
1045                                 (CLOCK_SPEED_HZ)
1046                                         / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1047                                 spi->mode & 0x3);
1048         else
1049                 dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
1050                                 spi->bits_per_word,
1051                                 (CLOCK_SPEED_HZ/2)
1052                                         / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1053                                 spi->mode & 0x3);
1054
1055         if (spi->bits_per_word <= 8) {
1056                 chip->n_bytes = 1;
1057                 chip->dma_width = DCMD_WIDTH1;
1058                 chip->read = u8_reader;
1059                 chip->write = u8_writer;
1060         } else if (spi->bits_per_word <= 16) {
1061                 chip->n_bytes = 2;
1062                 chip->dma_width = DCMD_WIDTH2;
1063                 chip->read = u16_reader;
1064                 chip->write = u16_writer;
1065         } else if (spi->bits_per_word <= 32) {
1066                 chip->cr0 |= SSCR0_EDSS;
1067                 chip->n_bytes = 4;
1068                 chip->dma_width = DCMD_WIDTH4;
1069                 chip->read = u32_reader;
1070                 chip->write = u32_writer;
1071         } else {
1072                 dev_err(&spi->dev, "invalid wordsize\n");
1073                 kfree(chip);
1074                 return -ENODEV;
1075         }
1076         chip->bits_per_word = spi->bits_per_word;
1077
1078         spi_set_ctldata(spi, chip);
1079
1080         return 0;
1081 }
1082
1083 static void cleanup(const struct spi_device *spi)
1084 {
1085         struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
1086
1087         kfree(chip);
1088 }
1089
1090 static int init_queue(struct driver_data *drv_data)
1091 {
1092         INIT_LIST_HEAD(&drv_data->queue);
1093         spin_lock_init(&drv_data->lock);
1094
1095         drv_data->run = QUEUE_STOPPED;
1096         drv_data->busy = 0;
1097
1098         tasklet_init(&drv_data->pump_transfers,
1099                         pump_transfers, (unsigned long)drv_data);
1100
1101         INIT_WORK(&drv_data->pump_messages, pump_messages, drv_data);
1102         drv_data->workqueue = create_singlethread_workqueue(
1103                                         drv_data->master->cdev.dev->bus_id);
1104         if (drv_data->workqueue == NULL)
1105                 return -EBUSY;
1106
1107         return 0;
1108 }
1109
1110 static int start_queue(struct driver_data *drv_data)
1111 {
1112         unsigned long flags;
1113
1114         spin_lock_irqsave(&drv_data->lock, flags);
1115
1116         if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1117                 spin_unlock_irqrestore(&drv_data->lock, flags);
1118                 return -EBUSY;
1119         }
1120
1121         drv_data->run = QUEUE_RUNNING;
1122         drv_data->cur_msg = NULL;
1123         drv_data->cur_transfer = NULL;
1124         drv_data->cur_chip = NULL;
1125         spin_unlock_irqrestore(&drv_data->lock, flags);
1126
1127         queue_work(drv_data->workqueue, &drv_data->pump_messages);
1128
1129         return 0;
1130 }
1131
1132 static int stop_queue(struct driver_data *drv_data)
1133 {
1134         unsigned long flags;
1135         unsigned limit = 500;
1136         int status = 0;
1137
1138         spin_lock_irqsave(&drv_data->lock, flags);
1139
1140         /* This is a bit lame, but is optimized for the common execution path.
1141          * A wait_queue on the drv_data->busy could be used, but then the common
1142          * execution path (pump_messages) would be required to call wake_up or
1143          * friends on every SPI message. Do this instead */
1144         drv_data->run = QUEUE_STOPPED;
1145         while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1146                 spin_unlock_irqrestore(&drv_data->lock, flags);
1147                 msleep(10);
1148                 spin_lock_irqsave(&drv_data->lock, flags);
1149         }
1150
1151         if (!list_empty(&drv_data->queue) || drv_data->busy)
1152                 status = -EBUSY;
1153
1154         spin_unlock_irqrestore(&drv_data->lock, flags);
1155
1156         return status;
1157 }
1158
1159 static int destroy_queue(struct driver_data *drv_data)
1160 {
1161         int status;
1162
1163         status = stop_queue(drv_data);
1164         if (status != 0)
1165                 return status;
1166
1167         destroy_workqueue(drv_data->workqueue);
1168
1169         return 0;
1170 }
1171
1172 static int pxa2xx_spi_probe(struct platform_device *pdev)
1173 {
1174         struct device *dev = &pdev->dev;
1175         struct pxa2xx_spi_master *platform_info;
1176         struct spi_master *master;
1177         struct driver_data *drv_data = 0;
1178         struct resource *memory_resource;
1179         int irq;
1180         int status = 0;
1181
1182         platform_info = dev->platform_data;
1183
1184         if (platform_info->ssp_type == SSP_UNDEFINED) {
1185                 dev_err(&pdev->dev, "undefined SSP\n");
1186                 return -ENODEV;
1187         }
1188
1189         /* Allocate master with space for drv_data and null dma buffer */
1190         master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1191         if (!master) {
1192                 dev_err(&pdev->dev, "can not alloc spi_master\n");
1193                 return -ENOMEM;
1194         }
1195         drv_data = spi_master_get_devdata(master);
1196         drv_data->master = master;
1197         drv_data->master_info = platform_info;
1198         drv_data->pdev = pdev;
1199
1200         master->bus_num = pdev->id;
1201         master->num_chipselect = platform_info->num_chipselect;
1202         master->cleanup = cleanup;
1203         master->setup = setup;
1204         master->transfer = transfer;
1205
1206         drv_data->ssp_type = platform_info->ssp_type;
1207         drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1208                                                 sizeof(struct driver_data)), 8);
1209
1210         /* Setup register addresses */
1211         memory_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1212         if (!memory_resource) {
1213                 dev_err(&pdev->dev, "memory resources not defined\n");
1214                 status = -ENODEV;
1215                 goto out_error_master_alloc;
1216         }
1217
1218         drv_data->ioaddr = (void *)io_p2v((unsigned long)(memory_resource->start));
1219         drv_data->ssdr_physical = memory_resource->start + 0x00000010;
1220         if (platform_info->ssp_type == PXA25x_SSP) {
1221                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1222                 drv_data->dma_cr1 = 0;
1223                 drv_data->clear_sr = SSSR_ROR;
1224                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1225         } else {
1226                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1227                 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1228                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1229                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1230         }
1231
1232         /* Attach to IRQ */
1233         irq = platform_get_irq(pdev, 0);
1234         if (irq < 0) {
1235                 dev_err(&pdev->dev, "irq resource not defined\n");
1236                 status = -ENODEV;
1237                 goto out_error_master_alloc;
1238         }
1239
1240         status = request_irq(irq, ssp_int, 0, dev->bus_id, drv_data);
1241         if (status < 0) {
1242                 dev_err(&pdev->dev, "can not get IRQ\n");
1243                 goto out_error_master_alloc;
1244         }
1245
1246         /* Setup DMA if requested */
1247         drv_data->tx_channel = -1;
1248         drv_data->rx_channel = -1;
1249         if (platform_info->enable_dma) {
1250
1251                 /* Get two DMA channels (rx and tx) */
1252                 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1253                                                         DMA_PRIO_HIGH,
1254                                                         dma_handler,
1255                                                         drv_data);
1256                 if (drv_data->rx_channel < 0) {
1257                         dev_err(dev, "problem (%d) requesting rx channel\n",
1258                                 drv_data->rx_channel);
1259                         status = -ENODEV;
1260                         goto out_error_irq_alloc;
1261                 }
1262                 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1263                                                         DMA_PRIO_MEDIUM,
1264                                                         dma_handler,
1265                                                         drv_data);
1266                 if (drv_data->tx_channel < 0) {
1267                         dev_err(dev, "problem (%d) requesting tx channel\n",
1268                                 drv_data->tx_channel);
1269                         status = -ENODEV;
1270                         goto out_error_dma_alloc;
1271                 }
1272
1273                 if (drv_data->ioaddr == SSP1_VIRT) {
1274                                 DRCMRRXSSDR = DRCMR_MAPVLD
1275                                                 | drv_data->rx_channel;
1276                                 DRCMRTXSSDR = DRCMR_MAPVLD
1277                                                 | drv_data->tx_channel;
1278                 } else if (drv_data->ioaddr == SSP2_VIRT) {
1279                                 DRCMRRXSS2DR = DRCMR_MAPVLD
1280                                                 | drv_data->rx_channel;
1281                                 DRCMRTXSS2DR = DRCMR_MAPVLD
1282                                                 | drv_data->tx_channel;
1283                 } else if (drv_data->ioaddr == SSP3_VIRT) {
1284                                 DRCMRRXSS3DR = DRCMR_MAPVLD
1285                                                 | drv_data->rx_channel;
1286                                 DRCMRTXSS3DR = DRCMR_MAPVLD
1287                                                 | drv_data->tx_channel;
1288                 } else {
1289                         dev_err(dev, "bad SSP type\n");
1290                         goto out_error_dma_alloc;
1291                 }
1292         }
1293
1294         /* Enable SOC clock */
1295         pxa_set_cken(platform_info->clock_enable, 1);
1296
1297         /* Load default SSP configuration */
1298         write_SSCR0(0, drv_data->ioaddr);
1299         write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
1300         write_SSCR0(SSCR0_SerClkDiv(2)
1301                         | SSCR0_Motorola
1302                         | SSCR0_DataSize(8),
1303                         drv_data->ioaddr);
1304         if (drv_data->ssp_type != PXA25x_SSP)
1305                 write_SSTO(0, drv_data->ioaddr);
1306         write_SSPSP(0, drv_data->ioaddr);
1307
1308         /* Initial and start queue */
1309         status = init_queue(drv_data);
1310         if (status != 0) {
1311                 dev_err(&pdev->dev, "problem initializing queue\n");
1312                 goto out_error_clock_enabled;
1313         }
1314         status = start_queue(drv_data);
1315         if (status != 0) {
1316                 dev_err(&pdev->dev, "problem starting queue\n");
1317                 goto out_error_clock_enabled;
1318         }
1319
1320         /* Register with the SPI framework */
1321         platform_set_drvdata(pdev, drv_data);
1322         status = spi_register_master(master);
1323         if (status != 0) {
1324                 dev_err(&pdev->dev, "problem registering spi master\n");
1325                 goto out_error_queue_alloc;
1326         }
1327
1328         return status;
1329
1330 out_error_queue_alloc:
1331         destroy_queue(drv_data);
1332
1333 out_error_clock_enabled:
1334         pxa_set_cken(platform_info->clock_enable, 0);
1335
1336 out_error_dma_alloc:
1337         if (drv_data->tx_channel != -1)
1338                 pxa_free_dma(drv_data->tx_channel);
1339         if (drv_data->rx_channel != -1)
1340                 pxa_free_dma(drv_data->rx_channel);
1341
1342 out_error_irq_alloc:
1343         free_irq(irq, drv_data);
1344
1345 out_error_master_alloc:
1346         spi_master_put(master);
1347         return status;
1348 }
1349
1350 static int pxa2xx_spi_remove(struct platform_device *pdev)
1351 {
1352         struct driver_data *drv_data = platform_get_drvdata(pdev);
1353         int irq;
1354         int status = 0;
1355
1356         if (!drv_data)
1357                 return 0;
1358
1359         /* Remove the queue */
1360         status = destroy_queue(drv_data);
1361         if (status != 0)
1362                 return status;
1363
1364         /* Disable the SSP at the peripheral and SOC level */
1365         write_SSCR0(0, drv_data->ioaddr);
1366         pxa_set_cken(drv_data->master_info->clock_enable, 0);
1367
1368         /* Release DMA */
1369         if (drv_data->master_info->enable_dma) {
1370                 if (drv_data->ioaddr == SSP1_VIRT) {
1371                         DRCMRRXSSDR = 0;
1372                         DRCMRTXSSDR = 0;
1373                 } else if (drv_data->ioaddr == SSP2_VIRT) {
1374                         DRCMRRXSS2DR = 0;
1375                         DRCMRTXSS2DR = 0;
1376                 } else if (drv_data->ioaddr == SSP3_VIRT) {
1377                         DRCMRRXSS3DR = 0;
1378                         DRCMRTXSS3DR = 0;
1379                 }
1380                 pxa_free_dma(drv_data->tx_channel);
1381                 pxa_free_dma(drv_data->rx_channel);
1382         }
1383
1384         /* Release IRQ */
1385         irq = platform_get_irq(pdev, 0);
1386         if (irq >= 0)
1387                 free_irq(irq, drv_data);
1388
1389         /* Disconnect from the SPI framework */
1390         spi_unregister_master(drv_data->master);
1391
1392         /* Prevent double remove */
1393         platform_set_drvdata(pdev, NULL);
1394
1395         return 0;
1396 }
1397
1398 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1399 {
1400         int status = 0;
1401
1402         if ((status = pxa2xx_spi_remove(pdev)) != 0)
1403                 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1404 }
1405
1406 #ifdef CONFIG_PM
1407 static int suspend_devices(struct device *dev, void *pm_message)
1408 {
1409         pm_message_t *state = pm_message;
1410
1411         if (dev->power.power_state.event != state->event) {
1412                 dev_warn(dev, "pm state does not match request\n");
1413                 return -1;
1414         }
1415
1416         return 0;
1417 }
1418
1419 static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1420 {
1421         struct driver_data *drv_data = platform_get_drvdata(pdev);
1422         int status = 0;
1423
1424         /* Check all childern for current power state */
1425         if (device_for_each_child(&pdev->dev, &state, suspend_devices) != 0) {
1426                 dev_warn(&pdev->dev, "suspend aborted\n");
1427                 return -1;
1428         }
1429
1430         status = stop_queue(drv_data);
1431         if (status != 0)
1432                 return status;
1433         write_SSCR0(0, drv_data->ioaddr);
1434         pxa_set_cken(drv_data->master_info->clock_enable, 0);
1435
1436         return 0;
1437 }
1438
1439 static int pxa2xx_spi_resume(struct platform_device *pdev)
1440 {
1441         struct driver_data *drv_data = platform_get_drvdata(pdev);
1442         int status = 0;
1443
1444         /* Enable the SSP clock */
1445         pxa_set_cken(drv_data->master_info->clock_enable, 1);
1446
1447         /* Start the queue running */
1448         status = start_queue(drv_data);
1449         if (status != 0) {
1450                 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1451                 return status;
1452         }
1453
1454         return 0;
1455 }
1456 #else
1457 #define pxa2xx_spi_suspend NULL
1458 #define pxa2xx_spi_resume NULL
1459 #endif /* CONFIG_PM */
1460
1461 static struct platform_driver driver = {
1462         .driver = {
1463                 .name = "pxa2xx-spi",
1464                 .bus = &platform_bus_type,
1465                 .owner = THIS_MODULE,
1466         },
1467         .probe = pxa2xx_spi_probe,
1468         .remove = __devexit_p(pxa2xx_spi_remove),
1469         .shutdown = pxa2xx_spi_shutdown,
1470         .suspend = pxa2xx_spi_suspend,
1471         .resume = pxa2xx_spi_resume,
1472 };
1473
1474 static int __init pxa2xx_spi_init(void)
1475 {
1476         platform_driver_register(&driver);
1477
1478         return 0;
1479 }
1480 module_init(pxa2xx_spi_init);
1481
1482 static void __exit pxa2xx_spi_exit(void)
1483 {
1484         platform_driver_unregister(&driver);
1485 }
1486 module_exit(pxa2xx_spi_exit);