2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
24 #include <linux/irq.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
31 #include <asm/machdep.h>
32 #include <asm/ppc-pci.h>
33 #include <asm/firmware.h>
37 #define DBG(fmt...) printk(fmt)
42 unsigned long pci_probe_only = 1;
43 int pci_assign_all_buses = 0;
45 static void fixup_resource(struct resource *res, struct pci_dev *dev);
46 static void do_bus_setup(struct pci_bus *bus);
47 static void phbs_remap_io(void);
49 /* pci_io_base -- the base address from which io bars are offsets.
50 * This is the lowest I/O base address (so bar values are always positive),
51 * and it *must* be the start of ISA space if an ISA bus exists because
52 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
53 * page is mapped and isa_io_limit prevents access to it.
55 unsigned long isa_io_base; /* NULL if no ISA bus */
56 EXPORT_SYMBOL(isa_io_base);
57 unsigned long pci_io_base;
58 EXPORT_SYMBOL(pci_io_base);
60 void iSeries_pcibios_init(void);
64 struct dma_mapping_ops *pci_dma_ops;
65 EXPORT_SYMBOL(pci_dma_ops);
67 int global_phb_number; /* Global phb counter */
69 /* Cached ISA bridge dev. */
70 struct pci_dev *ppc64_isabridge_dev = NULL;
71 EXPORT_SYMBOL_GPL(ppc64_isabridge_dev);
73 static void fixup_broken_pcnet32(struct pci_dev* dev)
75 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
76 dev->vendor = PCI_VENDOR_ID_AMD;
77 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
80 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
82 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
85 unsigned long offset = 0;
86 struct pci_controller *hose = pci_bus_to_host(dev->bus);
91 if (res->flags & IORESOURCE_IO)
92 offset = (unsigned long)hose->io_base_virt - pci_io_base;
94 if (res->flags & IORESOURCE_MEM)
95 offset = hose->pci_mem_offset;
97 region->start = res->start - offset;
98 region->end = res->end - offset;
101 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
102 struct pci_bus_region *region)
104 unsigned long offset = 0;
105 struct pci_controller *hose = pci_bus_to_host(dev->bus);
110 if (res->flags & IORESOURCE_IO)
111 offset = (unsigned long)hose->io_base_virt - pci_io_base;
113 if (res->flags & IORESOURCE_MEM)
114 offset = hose->pci_mem_offset;
116 res->start = region->start + offset;
117 res->end = region->end + offset;
120 #ifdef CONFIG_HOTPLUG
121 EXPORT_SYMBOL(pcibios_resource_to_bus);
122 EXPORT_SYMBOL(pcibios_bus_to_resource);
126 * We need to avoid collisions with `mirrored' VGA ports
127 * and other strange ISA hardware, so we always want the
128 * addresses to be allocated in the 0x000-0x0ff region
131 * Why? Because some silly external IO cards only decode
132 * the low 10 bits of the IO address. The 0x00-0xff region
133 * is reserved for motherboard devices that decode all 16
134 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
135 * but we want to try to avoid allocating at 0x2900-0x2bff
136 * which might have be mirrored at 0x0100-0x03ff..
138 void pcibios_align_resource(void *data, struct resource *res,
139 resource_size_t size, resource_size_t align)
141 struct pci_dev *dev = data;
142 struct pci_controller *hose = pci_bus_to_host(dev->bus);
143 resource_size_t start = res->start;
144 unsigned long alignto;
146 if (res->flags & IORESOURCE_IO) {
147 unsigned long offset = (unsigned long)hose->io_base_virt -
149 /* Make sure we start at our min on all hoses */
150 if (start - offset < PCIBIOS_MIN_IO)
151 start = PCIBIOS_MIN_IO + offset;
154 * Put everything into 0x00-0xff region modulo 0x400
157 start = (start + 0x3ff) & ~0x3ff;
159 } else if (res->flags & IORESOURCE_MEM) {
160 /* Make sure we start at our min on all hoses */
161 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
162 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
164 /* Align to multiple of size of minimum base. */
165 alignto = max(0x1000UL, align);
166 start = ALIGN(start, alignto);
172 static DEFINE_SPINLOCK(hose_spinlock);
175 * pci_controller(phb) initialized common variables.
177 static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
179 memset(hose, 0, sizeof(struct pci_controller));
181 spin_lock(&hose_spinlock);
182 hose->global_number = global_phb_number++;
183 list_add_tail(&hose->list_node, &hose_list);
184 spin_unlock(&hose_spinlock);
187 struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
189 struct pci_controller *phb;
192 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
194 phb = alloc_bootmem(sizeof (struct pci_controller));
197 pci_setup_pci_controller(phb);
198 phb->arch_data = dev;
199 phb->is_dynamic = mem_init_done;
201 int nid = of_node_to_nid(dev);
203 if (nid < 0 || !node_online(nid))
206 PHB_SET_NODE(phb, nid);
211 void pcibios_free_controller(struct pci_controller *phb)
213 spin_lock(&hose_spinlock);
214 list_del(&phb->list_node);
215 spin_unlock(&hose_spinlock);
221 void __devinit pcibios_claim_one_bus(struct pci_bus *b)
224 struct pci_bus *child_bus;
226 list_for_each_entry(dev, &b->devices, bus_list) {
229 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
230 struct resource *r = &dev->resource[i];
232 if (r->parent || !r->start || !r->flags)
234 pci_claim_resource(dev, i);
238 list_for_each_entry(child_bus, &b->children, node)
239 pcibios_claim_one_bus(child_bus);
241 #ifdef CONFIG_HOTPLUG
242 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
245 static void __init pcibios_claim_of_setup(void)
249 if (firmware_has_feature(FW_FEATURE_ISERIES))
252 list_for_each_entry(b, &pci_root_buses, node)
253 pcibios_claim_one_bus(b);
256 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
261 prop = get_property(np, name, &len);
262 if (prop && len >= 4)
267 static unsigned int pci_parse_of_flags(u32 addr0)
269 unsigned int flags = 0;
271 if (addr0 & 0x02000000) {
272 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
273 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
274 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
275 if (addr0 & 0x40000000)
276 flags |= IORESOURCE_PREFETCH
277 | PCI_BASE_ADDRESS_MEM_PREFETCH;
278 } else if (addr0 & 0x01000000)
279 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
283 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
285 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
289 struct resource *res;
294 addrs = get_property(node, "assigned-addresses", &proplen);
297 DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
298 for (; proplen >= 20; proplen -= 20, addrs += 5) {
299 flags = pci_parse_of_flags(addrs[0]);
302 base = GET_64BIT(addrs, 1);
303 size = GET_64BIT(addrs, 3);
307 DBG(" base: %llx, size: %llx, i: %x\n",
308 (unsigned long long)base, (unsigned long long)size, i);
310 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
311 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
312 } else if (i == dev->rom_base_reg) {
313 res = &dev->resource[PCI_ROM_RESOURCE];
314 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
316 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
320 res->end = base + size - 1;
322 res->name = pci_name(dev);
323 fixup_resource(res, dev);
327 struct pci_dev *of_create_pci_dev(struct device_node *node,
328 struct pci_bus *bus, int devfn)
333 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
336 type = get_property(node, "device_type", NULL);
340 DBG(" create device, devfn: %x, type: %s\n", devfn, type);
344 dev->dev.parent = bus->bridge;
345 dev->dev.bus = &pci_bus_type;
347 dev->multifunction = 0; /* maybe a lie? */
349 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
350 dev->device = get_int_prop(node, "device-id", 0xffff);
351 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
352 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
354 dev->cfg_size = pci_cfg_space_size(dev);
356 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
357 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
358 dev->class = get_int_prop(node, "class-code", 0);
360 DBG(" class: 0x%x\n", dev->class);
362 dev->current_state = 4; /* unknown power state */
364 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
365 /* a PCI-PCI bridge */
366 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
367 dev->rom_base_reg = PCI_ROM_ADDRESS1;
368 } else if (!strcmp(type, "cardbus")) {
369 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
371 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
372 dev->rom_base_reg = PCI_ROM_ADDRESS;
373 /* Maybe do a default OF mapping here */
377 pci_parse_of_addrs(node, dev);
379 DBG(" adding to system ...\n");
381 pci_device_add(dev, bus);
383 /* XXX pci_scan_msi_device(dev); */
387 EXPORT_SYMBOL(of_create_pci_dev);
389 void __devinit of_scan_bus(struct device_node *node,
392 struct device_node *child = NULL;
397 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
399 while ((child = of_get_next_child(node, child)) != NULL) {
400 DBG(" * %s\n", child->full_name);
401 reg = get_property(child, "reg", ®len);
402 if (reg == NULL || reglen < 20)
404 devfn = (reg[0] >> 8) & 0xff;
406 /* create a new pci_dev for this device */
407 dev = of_create_pci_dev(child, bus, devfn);
410 DBG("dev header type: %x\n", dev->hdr_type);
412 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
413 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
414 of_scan_pci_bridge(child, dev);
419 EXPORT_SYMBOL(of_scan_bus);
421 void __devinit of_scan_pci_bridge(struct device_node *node,
425 const u32 *busrange, *ranges;
427 struct resource *res;
431 DBG("of_scan_pci_bridge(%s)\n", node->full_name);
433 /* parse bus-range property */
434 busrange = get_property(node, "bus-range", &len);
435 if (busrange == NULL || len != 8) {
436 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
440 ranges = get_property(node, "ranges", &len);
441 if (ranges == NULL) {
442 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
447 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
449 printk(KERN_ERR "Failed to create pci bus for %s\n",
454 bus->primary = dev->bus->number;
455 bus->subordinate = busrange[1];
459 /* parse ranges property */
460 /* PCI #address-cells == 3 and #size-cells == 2 always */
461 res = &dev->resource[PCI_BRIDGE_RESOURCES];
462 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
464 bus->resource[i] = res;
468 for (; len >= 32; len -= 32, ranges += 8) {
469 flags = pci_parse_of_flags(ranges[0]);
470 size = GET_64BIT(ranges, 6);
471 if (flags == 0 || size == 0)
473 if (flags & IORESOURCE_IO) {
474 res = bus->resource[0];
476 printk(KERN_ERR "PCI: ignoring extra I/O range"
477 " for bridge %s\n", node->full_name);
481 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
482 printk(KERN_ERR "PCI: too many memory ranges"
483 " for bridge %s\n", node->full_name);
486 res = bus->resource[i];
489 res->start = GET_64BIT(ranges, 1);
490 res->end = res->start + size - 1;
492 fixup_resource(res, dev);
494 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
496 DBG(" bus name: %s\n", bus->name);
498 mode = PCI_PROBE_NORMAL;
499 if (ppc_md.pci_probe_mode)
500 mode = ppc_md.pci_probe_mode(bus);
501 DBG(" probe mode: %d\n", mode);
503 if (mode == PCI_PROBE_DEVTREE)
504 of_scan_bus(node, bus);
505 else if (mode == PCI_PROBE_NORMAL)
506 pci_scan_child_bus(bus);
508 EXPORT_SYMBOL(of_scan_pci_bridge);
510 void __devinit scan_phb(struct pci_controller *hose)
513 struct device_node *node = hose->arch_data;
515 struct resource *res;
517 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
519 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
521 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
522 hose->global_number);
525 bus->secondary = hose->first_busno;
528 bus->resource[0] = res = &hose->io_resource;
529 if (res->flags && request_resource(&ioport_resource, res))
530 printk(KERN_ERR "Failed to request PCI IO region "
531 "on PCI domain %04x\n", hose->global_number);
533 for (i = 0; i < 3; ++i) {
534 res = &hose->mem_resources[i];
535 bus->resource[i+1] = res;
536 if (res->flags && request_resource(&iomem_resource, res))
537 printk(KERN_ERR "Failed to request PCI memory region "
538 "on PCI domain %04x\n", hose->global_number);
541 mode = PCI_PROBE_NORMAL;
543 if (node && ppc_md.pci_probe_mode)
544 mode = ppc_md.pci_probe_mode(bus);
545 DBG(" probe mode: %d\n", mode);
546 if (mode == PCI_PROBE_DEVTREE) {
547 bus->subordinate = hose->last_busno;
548 of_scan_bus(node, bus);
551 if (mode == PCI_PROBE_NORMAL)
552 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
555 static int __init pcibios_init(void)
557 struct pci_controller *hose, *tmp;
559 /* For now, override phys_mem_access_prot. If we need it,
560 * later, we may move that initialization to each ppc_md
562 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
564 if (firmware_has_feature(FW_FEATURE_ISERIES))
565 iSeries_pcibios_init();
567 printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
569 /* Scan all of the recorded PCI controllers. */
570 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
572 pci_bus_add_devices(hose->bus);
575 if (!firmware_has_feature(FW_FEATURE_ISERIES)) {
577 pcibios_claim_of_setup();
579 /* FIXME: `else' will be removed when
580 pci_assign_unassigned_resources() is able to work
581 correctly with [partially] allocated PCI tree. */
582 pci_assign_unassigned_resources();
585 /* Call machine dependent final fixup */
586 if (ppc_md.pcibios_fixup)
587 ppc_md.pcibios_fixup();
589 /* Cache the location of the ISA bridge (if we have one) */
590 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
591 if (ppc64_isabridge_dev != NULL)
592 printk(KERN_DEBUG "ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
594 if (!firmware_has_feature(FW_FEATURE_ISERIES))
595 /* map in PCI I/O space */
598 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
603 subsys_initcall(pcibios_init);
605 char __init *pcibios_setup(char *str)
610 int pcibios_enable_device(struct pci_dev *dev, int mask)
615 pci_read_config_word(dev, PCI_COMMAND, &cmd);
618 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
619 struct resource *res = &dev->resource[i];
621 /* Only set up the requested stuff */
622 if (!(mask & (1<<i)))
625 if (res->flags & IORESOURCE_IO)
626 cmd |= PCI_COMMAND_IO;
627 if (res->flags & IORESOURCE_MEM)
628 cmd |= PCI_COMMAND_MEMORY;
632 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
634 /* Enable the appropriate bits in the PCI command register. */
635 pci_write_config_word(dev, PCI_COMMAND, cmd);
641 * Return the domain number for this bus.
643 int pci_domain_nr(struct pci_bus *bus)
645 if (firmware_has_feature(FW_FEATURE_ISERIES))
648 struct pci_controller *hose = pci_bus_to_host(bus);
650 return hose->global_number;
654 EXPORT_SYMBOL(pci_domain_nr);
656 /* Decide whether to display the domain number in /proc */
657 int pci_proc_domain(struct pci_bus *bus)
659 if (firmware_has_feature(FW_FEATURE_ISERIES))
662 struct pci_controller *hose = pci_bus_to_host(bus);
668 * Platform support for /proc/bus/pci/X/Y mmap()s,
669 * modelled on the sparc64 implementation by Dave Miller.
674 * Adjust vm_pgoff of VMA such that it is the physical page offset
675 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
677 * Basically, the user finds the base address for his device which he wishes
678 * to mmap. They read the 32-bit value from the config space base register,
679 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
680 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
682 * Returns negative error code on failure, zero on success.
684 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
685 resource_size_t *offset,
686 enum pci_mmap_state mmap_state)
688 struct pci_controller *hose = pci_bus_to_host(dev->bus);
689 unsigned long io_offset = 0;
693 return NULL; /* should never happen */
695 /* If memory, add on the PCI bridge address offset */
696 if (mmap_state == pci_mmap_mem) {
697 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
698 *offset += hose->pci_mem_offset;
700 res_bit = IORESOURCE_MEM;
702 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
703 *offset += io_offset;
704 res_bit = IORESOURCE_IO;
708 * Check that the offset requested corresponds to one of the
709 * resources of the device.
711 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
712 struct resource *rp = &dev->resource[i];
713 int flags = rp->flags;
715 /* treat ROM as memory (should be already) */
716 if (i == PCI_ROM_RESOURCE)
717 flags |= IORESOURCE_MEM;
719 /* Active and same type? */
720 if ((flags & res_bit) == 0)
723 /* In the range of this resource? */
724 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
727 /* found it! construct the final physical address */
728 if (mmap_state == pci_mmap_io)
729 *offset += hose->io_base_phys - io_offset;
737 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
740 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
742 enum pci_mmap_state mmap_state,
745 unsigned long prot = pgprot_val(protection);
747 /* Write combine is always 0 on non-memory space mappings. On
748 * memory space, if the user didn't pass 1, we check for a
749 * "prefetchable" resource. This is a bit hackish, but we use
750 * this to workaround the inability of /sysfs to provide a write
753 if (mmap_state != pci_mmap_mem)
755 else if (write_combine == 0) {
756 if (rp->flags & IORESOURCE_PREFETCH)
760 /* XXX would be nice to have a way to ask for write-through */
761 prot |= _PAGE_NO_CACHE;
763 prot &= ~_PAGE_GUARDED;
765 prot |= _PAGE_GUARDED;
767 return __pgprot(prot);
771 * This one is used by /dev/mem and fbdev who have no clue about the
772 * PCI device, it tries to find the PCI device first and calls the
775 pgprot_t pci_phys_mem_access_prot(struct file *file,
780 struct pci_dev *pdev = NULL;
781 struct resource *found = NULL;
782 unsigned long prot = pgprot_val(protection);
783 unsigned long offset = pfn << PAGE_SHIFT;
786 if (page_is_ram(pfn))
787 return __pgprot(prot);
789 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
791 for_each_pci_dev(pdev) {
792 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
793 struct resource *rp = &pdev->resource[i];
794 int flags = rp->flags;
796 /* Active and same type? */
797 if ((flags & IORESOURCE_MEM) == 0)
799 /* In the range of this resource? */
800 if (offset < (rp->start & PAGE_MASK) ||
810 if (found->flags & IORESOURCE_PREFETCH)
811 prot &= ~_PAGE_GUARDED;
815 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
817 return __pgprot(prot);
822 * Perform the actual remap of the pages for a PCI device mapping, as
823 * appropriate for this architecture. The region in the process to map
824 * is described by vm_start and vm_end members of VMA, the base physical
825 * address is found in vm_pgoff.
826 * The pci device structure is provided so that architectures may make mapping
827 * decisions on a per-device or per-bus basis.
829 * Returns a negative error code on failure, zero on success.
831 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
832 enum pci_mmap_state mmap_state, int write_combine)
834 resource_size_t offset = vma->vm_pgoff << PAGE_SHIFT;
838 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
842 vma->vm_pgoff = offset >> PAGE_SHIFT;
843 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
845 mmap_state, write_combine);
847 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
848 vma->vm_end - vma->vm_start, vma->vm_page_prot);
853 static ssize_t pci_show_devspec(struct device *dev,
854 struct device_attribute *attr, char *buf)
856 struct pci_dev *pdev;
857 struct device_node *np;
859 pdev = to_pci_dev (dev);
860 np = pci_device_to_OF_node(pdev);
861 if (np == NULL || np->full_name == NULL)
863 return sprintf(buf, "%s", np->full_name);
865 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
867 void pcibios_add_platform_entries(struct pci_dev *pdev)
869 device_create_file(&pdev->dev, &dev_attr_devspec);
872 #define ISA_SPACE_MASK 0x1
873 #define ISA_SPACE_IO 0x1
875 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
876 unsigned long phb_io_base_phys,
877 void __iomem * phb_io_base_virt)
879 /* Remove these asap */
893 struct isa_address isa_addr;
894 struct pci_address pci_addr;
898 const struct isa_range *range;
899 unsigned long pci_addr;
900 unsigned int isa_addr;
904 range = get_property(isa_node, "ranges", &rlen);
905 if (range == NULL || (rlen < sizeof(struct isa_range))) {
906 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
908 __ioremap_explicit(phb_io_base_phys,
909 (unsigned long)phb_io_base_virt,
910 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
914 /* From "ISA Binding to 1275"
915 * The ranges property is laid out as an array of elements,
916 * each of which comprises:
917 * cells 0 - 1: an ISA address
918 * cells 2 - 4: a PCI address
919 * (size depending on dev->n_addr_cells)
920 * cell 5: the size of the range
922 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
923 isa_addr = range->isa_addr.a_lo;
924 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
925 range->pci_addr.a_lo;
927 /* Assume these are both zero */
928 if ((pci_addr != 0) || (isa_addr != 0)) {
929 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
934 size = PAGE_ALIGN(range->size);
936 __ioremap_explicit(phb_io_base_phys,
937 (unsigned long) phb_io_base_virt,
938 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
942 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
943 struct device_node *dev, int prim)
945 const unsigned int *ranges;
946 unsigned int pci_space;
950 struct resource *res;
951 int np, na = prom_n_addr_cells(dev);
952 unsigned long pci_addr, cpu_phys_addr;
956 /* From "PCI Binding to 1275"
957 * The ranges property is laid out as an array of elements,
958 * each of which comprises:
959 * cells 0 - 2: a PCI address
960 * cells 3 or 3+4: a CPU physical address
961 * (size depending on dev->n_addr_cells)
962 * cells 4+5 or 5+6: the size of the range
964 ranges = get_property(dev, "ranges", &rlen);
967 hose->io_base_phys = 0;
968 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
970 pci_space = ranges[0];
971 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
972 cpu_phys_addr = of_translate_address(dev, &ranges[3]);
973 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
978 /* Now consume following elements while they are contiguous */
979 while (rlen >= np * sizeof(unsigned int)) {
980 unsigned long addr, phys;
982 if (ranges[0] != pci_space)
984 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
987 phys = (phys << 32) | ranges[4];
988 if (addr != pci_addr + size ||
989 phys != cpu_phys_addr + size)
992 size += ((unsigned long)ranges[na+3] << 32)
995 rlen -= np * sizeof(unsigned int);
998 switch ((pci_space >> 24) & 0x3) {
999 case 1: /* I/O space */
1000 hose->io_base_phys = cpu_phys_addr;
1001 hose->pci_io_size = size;
1003 res = &hose->io_resource;
1004 res->flags = IORESOURCE_IO;
1005 res->start = pci_addr;
1006 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
1007 res->start, res->start + size - 1);
1009 case 2: /* memory space */
1011 while (memno < 3 && hose->mem_resources[memno].flags)
1015 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
1017 res = &hose->mem_resources[memno];
1018 res->flags = IORESOURCE_MEM;
1019 res->start = cpu_phys_addr;
1020 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
1021 res->start, res->start + size - 1);
1026 res->name = dev->full_name;
1027 res->end = res->start + size - 1;
1029 res->sibling = NULL;
1035 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
1037 unsigned long size = hose->pci_io_size;
1038 unsigned long io_virt_offset;
1039 struct resource *res;
1040 struct device_node *isa_dn;
1042 hose->io_base_virt = reserve_phb_iospace(size);
1043 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1044 hose->global_number, hose->io_base_phys,
1045 (unsigned long) hose->io_base_virt);
1048 pci_io_base = (unsigned long)hose->io_base_virt;
1049 isa_dn = of_find_node_by_type(NULL, "isa");
1051 isa_io_base = pci_io_base;
1052 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
1053 hose->io_base_virt);
1054 of_node_put(isa_dn);
1058 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1059 res = &hose->io_resource;
1060 res->start += io_virt_offset;
1061 res->end += io_virt_offset;
1064 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
1067 unsigned long size = hose->pci_io_size;
1068 unsigned long io_virt_offset;
1069 struct resource *res;
1071 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
1072 _PAGE_NO_CACHE | _PAGE_GUARDED);
1073 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1074 hose->global_number, hose->io_base_phys,
1075 (unsigned long) hose->io_base_virt);
1078 pci_io_base = (unsigned long)hose->io_base_virt;
1080 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1081 res = &hose->io_resource;
1082 res->start += io_virt_offset;
1083 res->end += io_virt_offset;
1087 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1088 unsigned long *start_virt, unsigned long *size)
1090 struct pci_controller *hose = pci_bus_to_host(bus);
1091 struct pci_bus_region region;
1092 struct resource *res;
1095 res = bus->resource[0];
1096 pcibios_resource_to_bus(bus->self, ®ion, res);
1097 *start_phys = hose->io_base_phys + region.start;
1098 *start_virt = (unsigned long) hose->io_base_virt +
1100 if (region.end > region.start)
1101 *size = region.end - region.start + 1;
1103 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1104 __FUNCTION__, region.start, region.end);
1110 res = &hose->io_resource;
1111 *start_phys = hose->io_base_phys;
1112 *start_virt = (unsigned long) hose->io_base_virt;
1113 if (res->end > res->start)
1114 *size = res->end - res->start + 1;
1116 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1117 __FUNCTION__, res->start, res->end);
1125 int unmap_bus_range(struct pci_bus *bus)
1127 unsigned long start_phys;
1128 unsigned long start_virt;
1132 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1136 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1138 if (__iounmap_explicit((void __iomem *) start_virt, size))
1143 EXPORT_SYMBOL(unmap_bus_range);
1145 int remap_bus_range(struct pci_bus *bus)
1147 unsigned long start_phys;
1148 unsigned long start_virt;
1152 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1157 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1159 if (start_phys == 0)
1161 printk(KERN_DEBUG "mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
1162 if (__ioremap_explicit(start_phys, start_virt, size,
1163 _PAGE_NO_CACHE | _PAGE_GUARDED))
1168 EXPORT_SYMBOL(remap_bus_range);
1170 static void phbs_remap_io(void)
1172 struct pci_controller *hose, *tmp;
1174 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1175 remap_bus_range(hose->bus);
1178 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1180 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1181 unsigned long offset;
1183 if (res->flags & IORESOURCE_IO) {
1184 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1186 res->start += offset;
1188 } else if (res->flags & IORESOURCE_MEM) {
1189 res->start += hose->pci_mem_offset;
1190 res->end += hose->pci_mem_offset;
1194 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
1195 struct pci_bus *bus)
1197 /* Update device resources. */
1200 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1201 if (dev->resource[i].flags)
1202 fixup_resource(&dev->resource[i], dev);
1204 EXPORT_SYMBOL(pcibios_fixup_device_resources);
1206 void __devinit pcibios_setup_new_device(struct pci_dev *dev)
1208 struct dev_archdata *sd = &dev->dev.archdata;
1210 sd->of_node = pci_device_to_OF_node(dev);
1212 DBG("PCI device %s OF node: %s\n", pci_name(dev),
1213 sd->of_node ? sd->of_node->full_name : "<none>");
1215 sd->dma_ops = pci_dma_ops;
1217 sd->numa_node = pcibus_to_node(dev->bus);
1221 if (ppc_md.pci_dma_dev_setup)
1222 ppc_md.pci_dma_dev_setup(dev);
1224 EXPORT_SYMBOL(pcibios_setup_new_device);
1226 static void __devinit do_bus_setup(struct pci_bus *bus)
1228 struct pci_dev *dev;
1230 if (ppc_md.pci_dma_bus_setup)
1231 ppc_md.pci_dma_bus_setup(bus);
1233 list_for_each_entry(dev, &bus->devices, bus_list)
1234 pcibios_setup_new_device(dev);
1236 /* Read default IRQs and fixup if necessary */
1237 list_for_each_entry(dev, &bus->devices, bus_list) {
1238 pci_read_irq_line(dev);
1239 if (ppc_md.pci_irq_fixup)
1240 ppc_md.pci_irq_fixup(dev);
1244 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1246 struct pci_dev *dev = bus->self;
1247 struct device_node *np;
1249 np = pci_bus_to_OF_node(bus);
1251 DBG("pcibios_fixup_bus(%s)\n", np ? np->full_name : "<???>");
1253 if (dev && pci_probe_only &&
1254 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1255 /* This is a subordinate bridge */
1257 pci_read_bridge_bases(bus);
1258 pcibios_fixup_device_resources(dev, bus);
1263 if (!pci_probe_only)
1266 list_for_each_entry(dev, &bus->devices, bus_list)
1267 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1268 pcibios_fixup_device_resources(dev, bus);
1270 EXPORT_SYMBOL(pcibios_fixup_bus);
1273 * Reads the interrupt pin to determine if interrupt is use by card.
1274 * If the interrupt is used, then gets the interrupt line from the
1275 * openfirmware and sets it in the pci_dev and pci_config line.
1277 int pci_read_irq_line(struct pci_dev *pci_dev)
1282 DBG("Try to map irq for %s...\n", pci_name(pci_dev));
1285 memset(&oirq, 0xff, sizeof(oirq));
1287 /* Try to get a mapping from the device-tree */
1288 if (of_irq_map_pci(pci_dev, &oirq)) {
1291 /* If that fails, lets fallback to what is in the config
1292 * space and map that through the default controller. We
1293 * also set the type to level low since that's what PCI
1294 * interrupts are. If your platform does differently, then
1295 * either provide a proper interrupt tree or don't use this
1298 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
1302 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
1306 DBG(" -> no map ! Using irq line %d from PCI config\n", line);
1308 virq = irq_create_mapping(NULL, line);
1310 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
1312 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
1313 oirq.size, oirq.specifier[0], oirq.specifier[1],
1314 oirq.controller->full_name);
1316 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
1319 if(virq == NO_IRQ) {
1320 DBG(" -> failed to map !\n");
1324 DBG(" -> mapped to linux irq %d\n", virq);
1326 pci_dev->irq = virq;
1327 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq);
1331 EXPORT_SYMBOL(pci_read_irq_line);
1333 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1334 const struct resource *rsrc,
1335 resource_size_t *start, resource_size_t *end)
1337 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1338 resource_size_t offset = 0;
1343 if (rsrc->flags & IORESOURCE_IO)
1344 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1346 /* We pass a fully fixed up address to userland for MMIO instead of
1347 * a BAR value because X is lame and expects to be able to use that
1348 * to pass to /dev/mem !
1350 * That means that we'll have potentially 64 bits values where some
1351 * userland apps only expect 32 (like X itself since it thinks only
1352 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
1355 * Hopefully, the sysfs insterface is immune to that gunk. Once X
1356 * has been fixed (and the fix spread enough), we can re-enable the
1357 * 2 lines below and pass down a BAR value to userland. In that case
1358 * we'll also have to re-enable the matching code in
1359 * __pci_mmap_make_offset().
1364 else if (rsrc->flags & IORESOURCE_MEM)
1365 offset = hose->pci_mem_offset;
1368 *start = rsrc->start - offset;
1369 *end = rsrc->end - offset;
1372 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
1377 struct pci_controller *hose, *tmp;
1378 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1379 if (hose->arch_data == node)
1381 node = node->parent;
1386 unsigned long pci_address_to_pio(phys_addr_t address)
1388 struct pci_controller *hose, *tmp;
1390 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1391 if (address >= hose->io_base_phys &&
1392 address < (hose->io_base_phys + hose->pci_io_size)) {
1393 unsigned long base =
1394 (unsigned long)hose->io_base_virt - pci_io_base;
1395 return base + (address - hose->io_base_phys);
1398 return (unsigned int)-1;
1400 EXPORT_SYMBOL_GPL(pci_address_to_pio);
1403 #define IOBASE_BRIDGE_NUMBER 0
1404 #define IOBASE_MEMORY 1
1406 #define IOBASE_ISA_IO 3
1407 #define IOBASE_ISA_MEM 4
1409 long sys_pciconfig_iobase(long which, unsigned long in_bus,
1410 unsigned long in_devfn)
1412 struct pci_controller* hose;
1413 struct list_head *ln;
1414 struct pci_bus *bus = NULL;
1415 struct device_node *hose_node;
1417 /* Argh ! Please forgive me for that hack, but that's the
1418 * simplest way to get existing XFree to not lockup on some
1419 * G5 machines... So when something asks for bus 0 io base
1420 * (bus 0 is HT root), we return the AGP one instead.
1422 if (machine_is_compatible("MacRISC4"))
1426 /* That syscall isn't quite compatible with PCI domains, but it's
1427 * used on pre-domains setup. We return the first match
1430 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1431 bus = pci_bus_b(ln);
1432 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate))
1436 if (bus == NULL || bus->sysdata == NULL)
1439 hose_node = (struct device_node *)bus->sysdata;
1440 hose = PCI_DN(hose_node)->phb;
1443 case IOBASE_BRIDGE_NUMBER:
1444 return (long)hose->first_busno;
1446 return (long)hose->pci_mem_offset;
1448 return (long)hose->io_base_phys;
1450 return (long)isa_io_base;
1451 case IOBASE_ISA_MEM:
1459 int pcibus_to_node(struct pci_bus *bus)
1461 struct pci_controller *phb = pci_bus_to_host(bus);
1464 EXPORT_SYMBOL(pcibus_to_node);