git.oblomov.eu Git - linux-2.6/blob - drivers/serial/sunzilog.c

   1 /* sunzilog.c: Zilog serial driver for Sparc systems.
   2  *
   3  * Driver for Zilog serial chips found on Sun workstations and
   4  * servers.  This driver could actually be made more generic.
   5  *
   6  * This is based on the old drivers/sbus/char/zs.c code.  A lot
   7  * of code has been simply moved over directly from there but
   8  * much has been rewritten.  Credits therefore go out to Eddie
   9  * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
  10  * work there.
  11  *
  12  * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net)
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/errno.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/tty_flip.h>
  21 #include <linux/major.h>
  22 #include <linux/string.h>
  23 #include <linux/ptrace.h>
  24 #include <linux/ioport.h>
  25 #include <linux/slab.h>
  26 #include <linux/circ_buf.h>
  27 #include <linux/serial.h>
  28 #include <linux/sysrq.h>
  29 #include <linux/console.h>
  30 #include <linux/spinlock.h>
  31 #ifdef CONFIG_SERIO
  32 #include <linux/serio.h>
  33 #endif
  34 #include <linux/init.h>
  35 #include <linux/of_device.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/prom.h>
  40
  41 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  42 #define SUPPORT_SYSRQ
  43 #endif
  44
  45 #include <linux/serial_core.h>
  46
  47 #include "suncore.h"
  48 #include "sunzilog.h"
  49
  50 /* On 32-bit sparcs we need to delay after register accesses
  51  * to accommodate sun4 systems, but we do not need to flush writes.
  52  * On 64-bit sparc we only need to flush single writes to ensure
  53  * completion.
  54  */
  55 #ifndef CONFIG_SPARC64
  56 #define ZSDELAY()               udelay(5)
  57 #define ZSDELAY_LONG()          udelay(20)
  58 #define ZS_WSYNC(channel)       do { } while (0)
  59 #else
  60 #define ZSDELAY()
  61 #define ZSDELAY_LONG()
  62 #define ZS_WSYNC(__channel) \
  63         readb(&((__channel)->control))
  64 #endif
  65
  66 #define ZS_CLOCK                4915200 /* Zilog input clock rate. */
  67 #define ZS_CLOCK_DIVISOR        16      /* Divisor this driver uses. */
  68
  69 /*
  70  * We wrap our port structure around the generic uart_port.
  71  */
  72 struct uart_sunzilog_port {
  73         struct uart_port                port;
  74
  75         /* IRQ servicing chain.  */
  76         struct uart_sunzilog_port       *next;
  77
  78         /* Current values of Zilog write registers.  */
  79         unsigned char                   curregs[NUM_ZSREGS];
  80
  81         unsigned int                    flags;
  82 #define SUNZILOG_FLAG_CONS_KEYB         0x00000001
  83 #define SUNZILOG_FLAG_CONS_MOUSE        0x00000002
  84 #define SUNZILOG_FLAG_IS_CONS           0x00000004
  85 #define SUNZILOG_FLAG_IS_KGDB           0x00000008
  86 #define SUNZILOG_FLAG_MODEM_STATUS      0x00000010
  87 #define SUNZILOG_FLAG_IS_CHANNEL_A      0x00000020
  88 #define SUNZILOG_FLAG_REGS_HELD         0x00000040
  89 #define SUNZILOG_FLAG_TX_STOPPED        0x00000080
  90 #define SUNZILOG_FLAG_TX_ACTIVE         0x00000100
  91 #define SUNZILOG_FLAG_ESCC              0x00000200
  92 #define SUNZILOG_FLAG_ISR_HANDLER       0x00000400
  93
  94         unsigned int cflag;
  95
  96         unsigned char                   parity_mask;
  97         unsigned char                   prev_status;
  98
  99 #ifdef CONFIG_SERIO
 100         struct serio                    serio;
 101         int                             serio_open;
 102 #endif
 103 };
 104
 105 #define ZILOG_CHANNEL_FROM_PORT(PORT)   ((struct zilog_channel __iomem *)((PORT)->membase))
 106 #define UART_ZILOG(PORT)                ((struct uart_sunzilog_port *)(PORT))
 107
 108 #define ZS_IS_KEYB(UP)  ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
 109 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
 110 #define ZS_IS_CONS(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
 111 #define ZS_IS_KGDB(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
 112 #define ZS_WANTS_MODEM_STATUS(UP)       ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
 113 #define ZS_IS_CHANNEL_A(UP)     ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
 114 #define ZS_REGS_HELD(UP)        ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
 115 #define ZS_TX_STOPPED(UP)       ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
 116 #define ZS_TX_ACTIVE(UP)        ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
 117
 118 /* Reading and writing Zilog8530 registers.  The delays are to make this
 119  * driver work on the Sun4 which needs a settling delay after each chip
 120  * register access, other machines handle this in hardware via auxiliary
 121  * flip-flops which implement the settle time we do in software.
 122  *
 123  * The port lock must be held and local IRQs must be disabled
 124  * when {read,write}_zsreg is invoked.
 125  */
 126 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
 127                                 unsigned char reg)
 128 {
 129         unsigned char retval;
 130
 131         writeb(reg, &channel->control);
 132         ZSDELAY();
 133         retval = readb(&channel->control);
 134         ZSDELAY();
 135
 136         return retval;
 137 }
 138
 139 static void write_zsreg(struct zilog_channel __iomem *channel,
 140                         unsigned char reg, unsigned char value)
 141 {
 142         writeb(reg, &channel->control);
 143         ZSDELAY();
 144         writeb(value, &channel->control);
 145         ZSDELAY();
 146 }
 147
 148 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
 149 {
 150         int i;
 151
 152         for (i = 0; i < 32; i++) {
 153                 unsigned char regval;
 154
 155                 regval = readb(&channel->control);
 156                 ZSDELAY();
 157                 if (regval & Rx_CH_AV)
 158                         break;
 159
 160                 regval = read_zsreg(channel, R1);
 161                 readb(&channel->data);
 162                 ZSDELAY();
 163
 164                 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
 165                         writeb(ERR_RES, &channel->control);
 166                         ZSDELAY();
 167                         ZS_WSYNC(channel);
 168                 }
 169         }
 170 }
 171
 172 /* This function must only be called when the TX is not busy.  The UART
 173  * port lock must be held and local interrupts disabled.
 174  */
 175 static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
 176 {
 177         int i;
 178         int escc;
 179         unsigned char r15;
 180
 181         /* Let pending transmits finish.  */
 182         for (i = 0; i < 1000; i++) {
 183                 unsigned char stat = read_zsreg(channel, R1);
 184                 if (stat & ALL_SNT)
 185                         break;
 186                 udelay(100);
 187         }
 188
 189         writeb(ERR_RES, &channel->control);
 190         ZSDELAY();
 191         ZS_WSYNC(channel);
 192
 193         sunzilog_clear_fifo(channel);
 194
 195         /* Disable all interrupts.  */
 196         write_zsreg(channel, R1,
 197                     regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
 198
 199         /* Set parity, sync config, stop bits, and clock divisor.  */
 200         write_zsreg(channel, R4, regs[R4]);
 201
 202         /* Set misc. TX/RX control bits.  */
 203         write_zsreg(channel, R10, regs[R10]);
 204
 205         /* Set TX/RX controls sans the enable bits.  */
 206         write_zsreg(channel, R3, regs[R3] & ~RxENAB);
 207         write_zsreg(channel, R5, regs[R5] & ~TxENAB);
 208
 209         /* Synchronous mode config.  */
 210         write_zsreg(channel, R6, regs[R6]);
 211         write_zsreg(channel, R7, regs[R7]);
 212
 213         /* Don't mess with the interrupt vector (R2, unused by us) and
 214          * master interrupt control (R9).  We make sure this is setup
 215          * properly at probe time then never touch it again.
 216          */
 217
 218         /* Disable baud generator.  */
 219         write_zsreg(channel, R14, regs[R14] & ~BRENAB);
 220
 221         /* Clock mode control.  */
 222         write_zsreg(channel, R11, regs[R11]);
 223
 224         /* Lower and upper byte of baud rate generator divisor.  */
 225         write_zsreg(channel, R12, regs[R12]);
 226         write_zsreg(channel, R13, regs[R13]);
 227
 228         /* Now rewrite R14, with BRENAB (if set).  */
 229         write_zsreg(channel, R14, regs[R14]);
 230
 231         /* External status interrupt control.  */
 232         write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
 233
 234         /* ESCC Extension Register */
 235         r15 = read_zsreg(channel, R15);
 236         if (r15 & 0x01) {
 237                 write_zsreg(channel, R7,  regs[R7p]);
 238
 239                 /* External status interrupt and FIFO control.  */
 240                 write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
 241                 escc = 1;
 242         } else {
 243                  /* Clear FIFO bit case it is an issue */
 244                 regs[R15] &= ~FIFOEN;
 245                 escc = 0;
 246         }
 247
 248         /* Reset external status interrupts.  */
 249         write_zsreg(channel, R0, RES_EXT_INT); /* First Latch  */
 250         write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
 251
 252         /* Rewrite R3/R5, this time without enables masked.  */
 253         write_zsreg(channel, R3, regs[R3]);
 254         write_zsreg(channel, R5, regs[R5]);
 255
 256         /* Rewrite R1, this time without IRQ enabled masked.  */
 257         write_zsreg(channel, R1, regs[R1]);
 258
 259         return escc;
 260 }
 261
 262 /* Reprogram the Zilog channel HW registers with the copies found in the
 263  * software state struct.  If the transmitter is busy, we defer this update
 264  * until the next TX complete interrupt.  Else, we do it right now.
 265  *
 266  * The UART port lock must be held and local interrupts disabled.
 267  */
 268 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
 269                                        struct zilog_channel __iomem *channel)
 270 {
 271         if (!ZS_REGS_HELD(up)) {
 272                 if (ZS_TX_ACTIVE(up)) {
 273                         up->flags |= SUNZILOG_FLAG_REGS_HELD;
 274                 } else {
 275                         __load_zsregs(channel, up->curregs);
 276                 }
 277         }
 278 }
 279
 280 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
 281 {
 282         unsigned int cur_cflag = up->cflag;
 283         int brg, new_baud;
 284
 285         up->cflag &= ~CBAUD;
 286         up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
 287
 288         brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
 289         up->curregs[R12] = (brg & 0xff);
 290         up->curregs[R13] = (brg >> 8) & 0xff;
 291         sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
 292 }
 293
 294 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
 295                                          unsigned char ch, int is_break)
 296 {
 297         if (ZS_IS_KEYB(up)) {
 298                 /* Stop-A is handled by drivers/char/keyboard.c now. */
 299 #ifdef CONFIG_SERIO
 300                 if (up->serio_open)
 301                         serio_interrupt(&up->serio, ch, 0);
 302 #endif
 303         } else if (ZS_IS_MOUSE(up)) {
 304                 int ret = suncore_mouse_baud_detection(ch, is_break);
 305
 306                 switch (ret) {
 307                 case 2:
 308                         sunzilog_change_mouse_baud(up);
 309                         /* fallthru */
 310                 case 1:
 311                         break;
 312
 313                 case 0:
 314 #ifdef CONFIG_SERIO
 315                         if (up->serio_open)
 316                                 serio_interrupt(&up->serio, ch, 0);
 317 #endif
 318                         break;
 319                 };
 320         }
 321 }
 322
 323 static struct tty_struct *
 324 sunzilog_receive_chars(struct uart_sunzilog_port *up,
 325                        struct zilog_channel __iomem *channel)
 326 {
 327         struct tty_struct *tty;
 328         unsigned char ch, r1, flag;
 329
 330         tty = NULL;
 331         if (up->port.info != NULL &&            /* Unopened serial console */
 332             up->port.info->port.tty != NULL)    /* Keyboard || mouse */
 333                 tty = up->port.info->port.tty;
 334
 335         for (;;) {
 336
 337                 r1 = read_zsreg(channel, R1);
 338                 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
 339                         writeb(ERR_RES, &channel->control);
 340                         ZSDELAY();
 341                         ZS_WSYNC(channel);
 342                 }
 343
 344                 ch = readb(&channel->control);
 345                 ZSDELAY();
 346
 347                 /* This funny hack depends upon BRK_ABRT not interfering
 348                  * with the other bits we care about in R1.
 349                  */
 350                 if (ch & BRK_ABRT)
 351                         r1 |= BRK_ABRT;
 352
 353                 if (!(ch & Rx_CH_AV))
 354                         break;
 355
 356                 ch = readb(&channel->data);
 357                 ZSDELAY();
 358
 359                 ch &= up->parity_mask;
 360
 361                 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
 362                         sunzilog_kbdms_receive_chars(up, ch, 0);
 363                         continue;
 364                 }
 365
 366                 if (tty == NULL) {
 367                         uart_handle_sysrq_char(&up->port, ch);
 368                         continue;
 369                 }
 370
 371                 /* A real serial line, record the character and status.  */
 372                 flag = TTY_NORMAL;
 373                 up->port.icount.rx++;
 374                 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
 375                         if (r1 & BRK_ABRT) {
 376                                 r1 &= ~(PAR_ERR | CRC_ERR);
 377                                 up->port.icount.brk++;
 378                                 if (uart_handle_break(&up->port))
 379                                         continue;
 380                         }
 381                         else if (r1 & PAR_ERR)
 382                                 up->port.icount.parity++;
 383                         else if (r1 & CRC_ERR)
 384                                 up->port.icount.frame++;
 385                         if (r1 & Rx_OVR)
 386                                 up->port.icount.overrun++;
 387                         r1 &= up->port.read_status_mask;
 388                         if (r1 & BRK_ABRT)
 389                                 flag = TTY_BREAK;
 390                         else if (r1 & PAR_ERR)
 391                                 flag = TTY_PARITY;
 392                         else if (r1 & CRC_ERR)
 393                                 flag = TTY_FRAME;
 394                 }
 395                 if (uart_handle_sysrq_char(&up->port, ch))
 396                         continue;
 397
 398                 if (up->port.ignore_status_mask == 0xff ||
 399                     (r1 & up->port.ignore_status_mask) == 0) {
 400                         tty_insert_flip_char(tty, ch, flag);
 401                 }
 402                 if (r1 & Rx_OVR)
 403                         tty_insert_flip_char(tty, 0, TTY_OVERRUN);
 404         }
 405
 406         return tty;
 407 }
 408
 409 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
 410                                    struct zilog_channel __iomem *channel)
 411 {
 412         unsigned char status;
 413
 414         status = readb(&channel->control);
 415         ZSDELAY();
 416
 417         writeb(RES_EXT_INT, &channel->control);
 418         ZSDELAY();
 419         ZS_WSYNC(channel);
 420
 421         if (status & BRK_ABRT) {
 422                 if (ZS_IS_MOUSE(up))
 423                         sunzilog_kbdms_receive_chars(up, 0, 1);
 424                 if (ZS_IS_CONS(up)) {
 425                         /* Wait for BREAK to deassert to avoid potentially
 426                          * confusing the PROM.
 427                          */
 428                         while (1) {
 429                                 status = readb(&channel->control);
 430                                 ZSDELAY();
 431                                 if (!(status & BRK_ABRT))
 432                                         break;
 433                         }
 434                         sun_do_break();
 435                         return;
 436                 }
 437         }
 438
 439         if (ZS_WANTS_MODEM_STATUS(up)) {
 440                 if (status & SYNC)
 441                         up->port.icount.dsr++;
 442
 443                 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
 444                  * But it does not tell us which bit has changed, we have to keep
 445                  * track of this ourselves.
 446                  */
 447                 if ((status ^ up->prev_status) ^ DCD)
 448                         uart_handle_dcd_change(&up->port,
 449                                                (status & DCD));
 450                 if ((status ^ up->prev_status) ^ CTS)
 451                         uart_handle_cts_change(&up->port,
 452                                                (status & CTS));
 453
 454                 wake_up_interruptible(&up->port.info->delta_msr_wait);
 455         }
 456
 457         up->prev_status = status;
 458 }
 459
 460 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
 461                                     struct zilog_channel __iomem *channel)
 462 {
 463         struct circ_buf *xmit;
 464
 465         if (ZS_IS_CONS(up)) {
 466                 unsigned char status = readb(&channel->control);
 467                 ZSDELAY();
 468
 469                 /* TX still busy?  Just wait for the next TX done interrupt.
 470                  *
 471                  * It can occur because of how we do serial console writes.  It would
 472                  * be nice to transmit console writes just like we normally would for
 473                  * a TTY line. (ie. buffered and TX interrupt driven).  That is not
 474                  * easy because console writes cannot sleep.  One solution might be
 475                  * to poll on enough port->xmit space becomming free.  -DaveM
 476                  */
 477                 if (!(status & Tx_BUF_EMP))
 478                         return;
 479         }
 480
 481         up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
 482
 483         if (ZS_REGS_HELD(up)) {
 484                 __load_zsregs(channel, up->curregs);
 485                 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
 486         }
 487
 488         if (ZS_TX_STOPPED(up)) {
 489                 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
 490                 goto ack_tx_int;
 491         }
 492
 493         if (up->port.x_char) {
 494                 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 495                 writeb(up->port.x_char, &channel->data);
 496                 ZSDELAY();
 497                 ZS_WSYNC(channel);
 498
 499                 up->port.icount.tx++;
 500                 up->port.x_char = 0;
 501                 return;
 502         }
 503
 504         if (up->port.info == NULL)
 505                 goto ack_tx_int;
 506         xmit = &up->port.info->xmit;
 507         if (uart_circ_empty(xmit))
 508                 goto ack_tx_int;
 509
 510         if (uart_tx_stopped(&up->port))
 511                 goto ack_tx_int;
 512
 513         up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 514         writeb(xmit->buf[xmit->tail], &channel->data);
 515         ZSDELAY();
 516         ZS_WSYNC(channel);
 517
 518         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 519         up->port.icount.tx++;
 520
 521         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 522                 uart_write_wakeup(&up->port);
 523
 524         return;
 525
 526 ack_tx_int:
 527         writeb(RES_Tx_P, &channel->control);
 528         ZSDELAY();
 529         ZS_WSYNC(channel);
 530 }
 531
 532 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
 533 {
 534         struct uart_sunzilog_port *up = dev_id;
 535
 536         while (up) {
 537                 struct zilog_channel __iomem *channel
 538                         = ZILOG_CHANNEL_FROM_PORT(&up->port);
 539                 struct tty_struct *tty;
 540                 unsigned char r3;
 541
 542                 spin_lock(&up->port.lock);
 543                 r3 = read_zsreg(channel, R3);
 544
 545                 /* Channel A */
 546                 tty = NULL;
 547                 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
 548                         writeb(RES_H_IUS, &channel->control);
 549                         ZSDELAY();
 550                         ZS_WSYNC(channel);
 551
 552                         if (r3 & CHARxIP)
 553                                 tty = sunzilog_receive_chars(up, channel);
 554                         if (r3 & CHAEXT)
 555                                 sunzilog_status_handle(up, channel);
 556                         if (r3 & CHATxIP)
 557                                 sunzilog_transmit_chars(up, channel);
 558                 }
 559                 spin_unlock(&up->port.lock);
 560
 561                 if (tty)
 562                         tty_flip_buffer_push(tty);
 563
 564                 /* Channel B */
 565                 up = up->next;
 566                 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 567
 568                 spin_lock(&up->port.lock);
 569                 tty = NULL;
 570                 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
 571                         writeb(RES_H_IUS, &channel->control);
 572                         ZSDELAY();
 573                         ZS_WSYNC(channel);
 574
 575                         if (r3 & CHBRxIP)
 576                                 tty = sunzilog_receive_chars(up, channel);
 577                         if (r3 & CHBEXT)
 578                                 sunzilog_status_handle(up, channel);
 579                         if (r3 & CHBTxIP)
 580                                 sunzilog_transmit_chars(up, channel);
 581                 }
 582                 spin_unlock(&up->port.lock);
 583
 584                 if (tty)
 585                         tty_flip_buffer_push(tty);
 586
 587                 up = up->next;
 588         }
 589
 590         return IRQ_HANDLED;
 591 }
 592
 593 /* A convenient way to quickly get R0 status.  The caller must _not_ hold the
 594  * port lock, it is acquired here.
 595  */
 596 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
 597 {
 598         struct zilog_channel __iomem *channel;
 599         unsigned char status;
 600
 601         channel = ZILOG_CHANNEL_FROM_PORT(port);
 602         status = readb(&channel->control);
 603         ZSDELAY();
 604
 605         return status;
 606 }
 607
 608 /* The port lock is not held.  */
 609 static unsigned int sunzilog_tx_empty(struct uart_port *port)
 610 {
 611         unsigned long flags;
 612         unsigned char status;
 613         unsigned int ret;
 614
 615         spin_lock_irqsave(&port->lock, flags);
 616
 617         status = sunzilog_read_channel_status(port);
 618
 619         spin_unlock_irqrestore(&port->lock, flags);
 620
 621         if (status & Tx_BUF_EMP)
 622                 ret = TIOCSER_TEMT;
 623         else
 624                 ret = 0;
 625
 626         return ret;
 627 }
 628
 629 /* The port lock is held and interrupts are disabled.  */
 630 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
 631 {
 632         unsigned char status;
 633         unsigned int ret;
 634
 635         status = sunzilog_read_channel_status(port);
 636
 637         ret = 0;
 638         if (status & DCD)
 639                 ret |= TIOCM_CAR;
 640         if (status & SYNC)
 641                 ret |= TIOCM_DSR;
 642         if (status & CTS)
 643                 ret |= TIOCM_CTS;
 644
 645         return ret;
 646 }
 647
 648 /* The port lock is held and interrupts are disabled.  */
 649 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
 650 {
 651         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 652         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 653         unsigned char set_bits, clear_bits;
 654
 655         set_bits = clear_bits = 0;
 656
 657         if (mctrl & TIOCM_RTS)
 658                 set_bits |= RTS;
 659         else
 660                 clear_bits |= RTS;
 661         if (mctrl & TIOCM_DTR)
 662                 set_bits |= DTR;
 663         else
 664                 clear_bits |= DTR;
 665
 666         /* NOTE: Not subject to 'transmitter active' rule.  */
 667         up->curregs[R5] |= set_bits;
 668         up->curregs[R5] &= ~clear_bits;
 669         write_zsreg(channel, R5, up->curregs[R5]);
 670 }
 671
 672 /* The port lock is held and interrupts are disabled.  */
 673 static void sunzilog_stop_tx(struct uart_port *port)
 674 {
 675         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 676
 677         up->flags |= SUNZILOG_FLAG_TX_STOPPED;
 678 }
 679
 680 /* The port lock is held and interrupts are disabled.  */
 681 static void sunzilog_start_tx(struct uart_port *port)
 682 {
 683         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 684         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 685         unsigned char status;
 686
 687         up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 688         up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
 689
 690         status = readb(&channel->control);
 691         ZSDELAY();
 692
 693         /* TX busy?  Just wait for the TX done interrupt.  */
 694         if (!(status & Tx_BUF_EMP))
 695                 return;
 696
 697         /* Send the first character to jump-start the TX done
 698          * IRQ sending engine.
 699          */
 700         if (port->x_char) {
 701                 writeb(port->x_char, &channel->data);
 702                 ZSDELAY();
 703                 ZS_WSYNC(channel);
 704
 705                 port->icount.tx++;
 706                 port->x_char = 0;
 707         } else {
 708                 struct circ_buf *xmit = &port->info->xmit;
 709
 710                 writeb(xmit->buf[xmit->tail], &channel->data);
 711                 ZSDELAY();
 712                 ZS_WSYNC(channel);
 713
 714                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 715                 port->icount.tx++;
 716
 717                 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 718                         uart_write_wakeup(&up->port);
 719         }
 720 }
 721
 722 /* The port lock is held.  */
 723 static void sunzilog_stop_rx(struct uart_port *port)
 724 {
 725         struct uart_sunzilog_port *up = UART_ZILOG(port);
 726         struct zilog_channel __iomem *channel;
 727
 728         if (ZS_IS_CONS(up))
 729                 return;
 730
 731         channel = ZILOG_CHANNEL_FROM_PORT(port);
 732
 733         /* Disable all RX interrupts.  */
 734         up->curregs[R1] &= ~RxINT_MASK;
 735         sunzilog_maybe_update_regs(up, channel);
 736 }
 737
 738 /* The port lock is held.  */
 739 static void sunzilog_enable_ms(struct uart_port *port)
 740 {
 741         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 742         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 743         unsigned char new_reg;
 744
 745         new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
 746         if (new_reg != up->curregs[R15]) {
 747                 up->curregs[R15] = new_reg;
 748
 749                 /* NOTE: Not subject to 'transmitter active' rule.  */
 750                 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
 751         }
 752 }
 753
 754 /* The port lock is not held.  */
 755 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
 756 {
 757         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 758         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 759         unsigned char set_bits, clear_bits, new_reg;
 760         unsigned long flags;
 761
 762         set_bits = clear_bits = 0;
 763
 764         if (break_state)
 765                 set_bits |= SND_BRK;
 766         else
 767                 clear_bits |= SND_BRK;
 768
 769         spin_lock_irqsave(&port->lock, flags);
 770
 771         new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
 772         if (new_reg != up->curregs[R5]) {
 773                 up->curregs[R5] = new_reg;
 774
 775                 /* NOTE: Not subject to 'transmitter active' rule.  */
 776                 write_zsreg(channel, R5, up->curregs[R5]);
 777         }
 778
 779         spin_unlock_irqrestore(&port->lock, flags);
 780 }
 781
 782 static void __sunzilog_startup(struct uart_sunzilog_port *up)
 783 {
 784         struct zilog_channel __iomem *channel;
 785
 786         channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 787         up->prev_status = readb(&channel->control);
 788
 789         /* Enable receiver and transmitter.  */
 790         up->curregs[R3] |= RxENAB;
 791         up->curregs[R5] |= TxENAB;
 792
 793         up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
 794         sunzilog_maybe_update_regs(up, channel);
 795 }
 796
 797 static int sunzilog_startup(struct uart_port *port)
 798 {
 799         struct uart_sunzilog_port *up = UART_ZILOG(port);
 800         unsigned long flags;
 801
 802         if (ZS_IS_CONS(up))
 803                 return 0;
 804
 805         spin_lock_irqsave(&port->lock, flags);
 806         __sunzilog_startup(up);
 807         spin_unlock_irqrestore(&port->lock, flags);
 808         return 0;
 809 }
 810
 811 /*
 812  * The test for ZS_IS_CONS is explained by the following e-mail:
 813  *****
 814  * From: Russell King <rmk@arm.linux.org.uk>
 815  * Date: Sun, 8 Dec 2002 10:18:38 +0000
 816  *
 817  * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
 818  * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
 819  * > and I noticed that something is not right with reference
 820  * > counting in this case. It seems that when the console
 821  * > is open by kernel initially, this is not accounted
 822  * > as an open, and uart_startup is not called.
 823  *
 824  * That is correct.  We are unable to call uart_startup when the serial
 825  * console is initialised because it may need to allocate memory (as
 826  * request_irq does) and the memory allocators may not have been
 827  * initialised.
 828  *
 829  * 1. initialise the port into a state where it can send characters in the
 830  *    console write method.
 831  *
 832  * 2. don't do the actual hardware shutdown in your shutdown() method (but
 833  *    do the normal software shutdown - ie, free irqs etc)
 834  *****
 835  */
 836 static void sunzilog_shutdown(struct uart_port *port)
 837 {
 838         struct uart_sunzilog_port *up = UART_ZILOG(port);
 839         struct zilog_channel __iomem *channel;
 840         unsigned long flags;
 841
 842         if (ZS_IS_CONS(up))
 843                 return;
 844
 845         spin_lock_irqsave(&port->lock, flags);
 846
 847         channel = ZILOG_CHANNEL_FROM_PORT(port);
 848
 849         /* Disable receiver and transmitter.  */
 850         up->curregs[R3] &= ~RxENAB;
 851         up->curregs[R5] &= ~TxENAB;
 852
 853         /* Disable all interrupts and BRK assertion.  */
 854         up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
 855         up->curregs[R5] &= ~SND_BRK;
 856         sunzilog_maybe_update_regs(up, channel);
 857
 858         spin_unlock_irqrestore(&port->lock, flags);
 859 }
 860
 861 /* Shared by TTY driver and serial console setup.  The port lock is held
 862  * and local interrupts are disabled.
 863  */
 864 static void
 865 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
 866                        unsigned int iflag, int brg)
 867 {
 868
 869         up->curregs[R10] = NRZ;
 870         up->curregs[R11] = TCBR | RCBR;
 871
 872         /* Program BAUD and clock source. */
 873         up->curregs[R4] &= ~XCLK_MASK;
 874         up->curregs[R4] |= X16CLK;
 875         up->curregs[R12] = brg & 0xff;
 876         up->curregs[R13] = (brg >> 8) & 0xff;
 877         up->curregs[R14] = BRSRC | BRENAB;
 878
 879         /* Character size, stop bits, and parity. */
 880         up->curregs[R3] &= ~RxN_MASK;
 881         up->curregs[R5] &= ~TxN_MASK;
 882         switch (cflag & CSIZE) {
 883         case CS5:
 884                 up->curregs[R3] |= Rx5;
 885                 up->curregs[R5] |= Tx5;
 886                 up->parity_mask = 0x1f;
 887                 break;
 888         case CS6:
 889                 up->curregs[R3] |= Rx6;
 890                 up->curregs[R5] |= Tx6;
 891                 up->parity_mask = 0x3f;
 892                 break;
 893         case CS7:
 894                 up->curregs[R3] |= Rx7;
 895                 up->curregs[R5] |= Tx7;
 896                 up->parity_mask = 0x7f;
 897                 break;
 898         case CS8:
 899         default:
 900                 up->curregs[R3] |= Rx8;
 901                 up->curregs[R5] |= Tx8;
 902                 up->parity_mask = 0xff;
 903                 break;
 904         };
 905         up->curregs[R4] &= ~0x0c;
 906         if (cflag & CSTOPB)
 907                 up->curregs[R4] |= SB2;
 908         else
 909                 up->curregs[R4] |= SB1;
 910         if (cflag & PARENB)
 911                 up->curregs[R4] |= PAR_ENAB;
 912         else
 913                 up->curregs[R4] &= ~PAR_ENAB;
 914         if (!(cflag & PARODD))
 915                 up->curregs[R4] |= PAR_EVEN;
 916         else
 917                 up->curregs[R4] &= ~PAR_EVEN;
 918
 919         up->port.read_status_mask = Rx_OVR;
 920         if (iflag & INPCK)
 921                 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
 922         if (iflag & (BRKINT | PARMRK))
 923                 up->port.read_status_mask |= BRK_ABRT;
 924
 925         up->port.ignore_status_mask = 0;
 926         if (iflag & IGNPAR)
 927                 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
 928         if (iflag & IGNBRK) {
 929                 up->port.ignore_status_mask |= BRK_ABRT;
 930                 if (iflag & IGNPAR)
 931                         up->port.ignore_status_mask |= Rx_OVR;
 932         }
 933
 934         if ((cflag & CREAD) == 0)
 935                 up->port.ignore_status_mask = 0xff;
 936 }
 937
 938 /* The port lock is not held.  */
 939 static void
 940 sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
 941                      struct ktermios *old)
 942 {
 943         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 944         unsigned long flags;
 945         int baud, brg;
 946
 947         baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
 948
 949         spin_lock_irqsave(&up->port.lock, flags);
 950
 951         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
 952
 953         sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
 954
 955         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 956                 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
 957         else
 958                 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
 959
 960         up->cflag = termios->c_cflag;
 961
 962         sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
 963
 964         uart_update_timeout(port, termios->c_cflag, baud);
 965
 966         spin_unlock_irqrestore(&up->port.lock, flags);
 967 }
 968
 969 static const char *sunzilog_type(struct uart_port *port)
 970 {
 971         struct uart_sunzilog_port *up = UART_ZILOG(port);
 972
 973         return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
 974 }
 975
 976 /* We do not request/release mappings of the registers here, this
 977  * happens at early serial probe time.
 978  */
 979 static void sunzilog_release_port(struct uart_port *port)
 980 {
 981 }
 982
 983 static int sunzilog_request_port(struct uart_port *port)
 984 {
 985         return 0;
 986 }
 987
 988 /* These do not need to do anything interesting either.  */
 989 static void sunzilog_config_port(struct uart_port *port, int flags)
 990 {
 991 }
 992
 993 /* We do not support letting the user mess with the divisor, IRQ, etc. */
 994 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
 995 {
 996         return -EINVAL;
 997 }
 998
 999 static struct uart_ops sunzilog_pops = {
1000         .tx_empty       =       sunzilog_tx_empty,
1001         .set_mctrl      =       sunzilog_set_mctrl,
1002         .get_mctrl      =       sunzilog_get_mctrl,
1003         .stop_tx        =       sunzilog_stop_tx,
1004         .start_tx       =       sunzilog_start_tx,
1005         .stop_rx        =       sunzilog_stop_rx,
1006         .enable_ms      =       sunzilog_enable_ms,
1007         .break_ctl      =       sunzilog_break_ctl,
1008         .startup        =       sunzilog_startup,
1009         .shutdown       =       sunzilog_shutdown,
1010         .set_termios    =       sunzilog_set_termios,
1011         .type           =       sunzilog_type,
1012         .release_port   =       sunzilog_release_port,
1013         .request_port   =       sunzilog_request_port,
1014         .config_port    =       sunzilog_config_port,
1015         .verify_port    =       sunzilog_verify_port,
1016 };
1017
1018 static int uart_chip_count;
1019 static struct uart_sunzilog_port *sunzilog_port_table;
1020 static struct zilog_layout __iomem **sunzilog_chip_regs;
1021
1022 static struct uart_sunzilog_port *sunzilog_irq_chain;
1023
1024 static struct uart_driver sunzilog_reg = {
1025         .owner          =       THIS_MODULE,
1026         .driver_name    =       "sunzilog",
1027         .dev_name       =       "ttyS",
1028         .major          =       TTY_MAJOR,
1029 };
1030
1031 static int __init sunzilog_alloc_tables(int num_sunzilog)
1032 {
1033         struct uart_sunzilog_port *up;
1034         unsigned long size;
1035         int num_channels = num_sunzilog * 2;
1036         int i;
1037
1038         size = num_channels * sizeof(struct uart_sunzilog_port);
1039         sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1040         if (!sunzilog_port_table)
1041                 return -ENOMEM;
1042
1043         for (i = 0; i < num_channels; i++) {
1044                 up = &sunzilog_port_table[i];
1045
1046                 spin_lock_init(&up->port.lock);
1047
1048                 if (i == 0)
1049                         sunzilog_irq_chain = up;
1050
1051                 if (i < num_channels - 1)
1052                         up->next = up + 1;
1053                 else
1054                         up->next = NULL;
1055         }
1056
1057         size = num_sunzilog * sizeof(struct zilog_layout __iomem *);
1058         sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1059         if (!sunzilog_chip_regs) {
1060                 kfree(sunzilog_port_table);
1061                 sunzilog_irq_chain = NULL;
1062                 return -ENOMEM;
1063         }
1064
1065         return 0;
1066 }
1067
1068 static void sunzilog_free_tables(void)
1069 {
1070         kfree(sunzilog_port_table);
1071         sunzilog_irq_chain = NULL;
1072         kfree(sunzilog_chip_regs);
1073 }
1074
1075 #define ZS_PUT_CHAR_MAX_DELAY   2000    /* 10 ms */
1076
1077 static void sunzilog_putchar(struct uart_port *port, int ch)
1078 {
1079         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
1080         int loops = ZS_PUT_CHAR_MAX_DELAY;
1081
1082         /* This is a timed polling loop so do not switch the explicit
1083          * udelay with ZSDELAY as that is a NOP on some platforms.  -DaveM
1084          */
1085         do {
1086                 unsigned char val = readb(&channel->control);
1087                 if (val & Tx_BUF_EMP) {
1088                         ZSDELAY();
1089                         break;
1090                 }
1091                 udelay(5);
1092         } while (--loops);
1093
1094         writeb(ch, &channel->data);
1095         ZSDELAY();
1096         ZS_WSYNC(channel);
1097 }
1098
1099 #ifdef CONFIG_SERIO
1100
1101 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1102
1103 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1104 {
1105         struct uart_sunzilog_port *up = serio->port_data;
1106         unsigned long flags;
1107
1108         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1109
1110         sunzilog_putchar(&up->port, ch);
1111
1112         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1113
1114         return 0;
1115 }
1116
1117 static int sunzilog_serio_open(struct serio *serio)
1118 {
1119         struct uart_sunzilog_port *up = serio->port_data;
1120         unsigned long flags;
1121         int ret;
1122
1123         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1124         if (!up->serio_open) {
1125                 up->serio_open = 1;
1126                 ret = 0;
1127         } else
1128                 ret = -EBUSY;
1129         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1130
1131         return ret;
1132 }
1133
1134 static void sunzilog_serio_close(struct serio *serio)
1135 {
1136         struct uart_sunzilog_port *up = serio->port_data;
1137         unsigned long flags;
1138
1139         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1140         up->serio_open = 0;
1141         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1142 }
1143
1144 #endif /* CONFIG_SERIO */
1145
1146 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1147 static void
1148 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1149 {
1150         struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1151         unsigned long flags;
1152         int locked = 1;
1153
1154         local_irq_save(flags);
1155         if (up->port.sysrq) {
1156                 locked = 0;
1157         } else if (oops_in_progress) {
1158                 locked = spin_trylock(&up->port.lock);
1159         } else
1160                 spin_lock(&up->port.lock);
1161
1162         uart_console_write(&up->port, s, count, sunzilog_putchar);
1163         udelay(2);
1164
1165         if (locked)
1166                 spin_unlock(&up->port.lock);
1167         local_irq_restore(flags);
1168 }
1169
1170 static int __init sunzilog_console_setup(struct console *con, char *options)
1171 {
1172         struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1173         unsigned long flags;
1174         int baud, brg;
1175
1176         if (up->port.type != PORT_SUNZILOG)
1177                 return -1;
1178
1179         printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1180                (sunzilog_reg.minor - 64) + con->index, con->index);
1181
1182         /* Get firmware console settings.  */
1183         sunserial_console_termios(con);
1184
1185         /* Firmware console speed is limited to 150-->38400 baud so
1186          * this hackish cflag thing is OK.
1187          */
1188         switch (con->cflag & CBAUD) {
1189         case B150: baud = 150; break;
1190         case B300: baud = 300; break;
1191         case B600: baud = 600; break;
1192         case B1200: baud = 1200; break;
1193         case B2400: baud = 2400; break;
1194         case B4800: baud = 4800; break;
1195         default: case B9600: baud = 9600; break;
1196         case B19200: baud = 19200; break;
1197         case B38400: baud = 38400; break;
1198         };
1199
1200         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1201
1202         spin_lock_irqsave(&up->port.lock, flags);
1203
1204         up->curregs[R15] |= BRKIE;
1205         sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1206
1207         sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1208         __sunzilog_startup(up);
1209
1210         spin_unlock_irqrestore(&up->port.lock, flags);
1211
1212         return 0;
1213 }
1214
1215 static struct console sunzilog_console_ops = {
1216         .name   =       "ttyS",
1217         .write  =       sunzilog_console_write,
1218         .device =       uart_console_device,
1219         .setup  =       sunzilog_console_setup,
1220         .flags  =       CON_PRINTBUFFER,
1221         .index  =       -1,
1222         .data   =       &sunzilog_reg,
1223 };
1224
1225 static inline struct console *SUNZILOG_CONSOLE(void)
1226 {
1227         return &sunzilog_console_ops;
1228 }
1229
1230 #else
1231 #define SUNZILOG_CONSOLE()      (NULL)
1232 #endif
1233
1234 static void __devinit sunzilog_init_kbdms(struct uart_sunzilog_port *up)
1235 {
1236         int baud, brg;
1237
1238         if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1239                 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1240                 baud = 1200;
1241         } else {
1242                 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1243                 baud = 4800;
1244         }
1245
1246         up->curregs[R15] |= BRKIE;
1247         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1248         sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1249         sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1250         __sunzilog_startup(up);
1251 }
1252
1253 #ifdef CONFIG_SERIO
1254 static void __devinit sunzilog_register_serio(struct uart_sunzilog_port *up)
1255 {
1256         struct serio *serio = &up->serio;
1257
1258         serio->port_data = up;
1259
1260         serio->id.type = SERIO_RS232;
1261         if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1262                 serio->id.proto = SERIO_SUNKBD;
1263                 strlcpy(serio->name, "zskbd", sizeof(serio->name));
1264         } else {
1265                 serio->id.proto = SERIO_SUN;
1266                 serio->id.extra = 1;
1267                 strlcpy(serio->name, "zsms", sizeof(serio->name));
1268         }
1269         strlcpy(serio->phys,
1270                 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1271                  "zs/serio0" : "zs/serio1"),
1272                 sizeof(serio->phys));
1273
1274         serio->write = sunzilog_serio_write;
1275         serio->open = sunzilog_serio_open;
1276         serio->close = sunzilog_serio_close;
1277         serio->dev.parent = up->port.dev;
1278
1279         serio_register_port(serio);
1280 }
1281 #endif
1282
1283 static void __devinit sunzilog_init_hw(struct uart_sunzilog_port *up)
1284 {
1285         struct zilog_channel __iomem *channel;
1286         unsigned long flags;
1287         int baud, brg;
1288
1289         channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1290
1291         spin_lock_irqsave(&up->port.lock, flags);
1292         if (ZS_IS_CHANNEL_A(up)) {
1293                 write_zsreg(channel, R9, FHWRES);
1294                 ZSDELAY_LONG();
1295                 (void) read_zsreg(channel, R0);
1296         }
1297
1298         if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1299                          SUNZILOG_FLAG_CONS_MOUSE)) {
1300                 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1301                 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1302                 up->curregs[R3] = RxENAB | Rx8;
1303                 up->curregs[R5] = TxENAB | Tx8;
1304                 up->curregs[R6] = 0x00; /* SDLC Address */
1305                 up->curregs[R7] = 0x7E; /* SDLC Flag    */
1306                 up->curregs[R9] = NV;
1307                 up->curregs[R7p] = 0x00;
1308                 sunzilog_init_kbdms(up);
1309                 /* Only enable interrupts if an ISR handler available */
1310                 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1311                         up->curregs[R9] |= MIE;
1312                 write_zsreg(channel, R9, up->curregs[R9]);
1313         } else {
1314                 /* Normal serial TTY. */
1315                 up->parity_mask = 0xff;
1316                 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1317                 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1318                 up->curregs[R3] = RxENAB | Rx8;
1319                 up->curregs[R5] = TxENAB | Tx8;
1320                 up->curregs[R6] = 0x00; /* SDLC Address */
1321                 up->curregs[R7] = 0x7E; /* SDLC Flag    */
1322                 up->curregs[R9] = NV;
1323                 up->curregs[R10] = NRZ;
1324                 up->curregs[R11] = TCBR | RCBR;
1325                 baud = 9600;
1326                 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1327                 up->curregs[R12] = (brg & 0xff);
1328                 up->curregs[R13] = (brg >> 8) & 0xff;
1329                 up->curregs[R14] = BRSRC | BRENAB;
1330                 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1331                 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1332                 if (__load_zsregs(channel, up->curregs)) {
1333                         up->flags |= SUNZILOG_FLAG_ESCC;
1334                 }
1335                 /* Only enable interrupts if an ISR handler available */
1336                 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1337                         up->curregs[R9] |= MIE;
1338                 write_zsreg(channel, R9, up->curregs[R9]);
1339         }
1340
1341         spin_unlock_irqrestore(&up->port.lock, flags);
1342
1343 #ifdef CONFIG_SERIO
1344         if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1345                          SUNZILOG_FLAG_CONS_MOUSE))
1346                 sunzilog_register_serio(up);
1347 #endif
1348 }
1349
1350 static int zilog_irq = -1;
1351
1352 static int __devinit zs_probe(struct of_device *op, const struct of_device_id *match)
1353 {
1354         static int kbm_inst, uart_inst;
1355         int inst;
1356         struct uart_sunzilog_port *up;
1357         struct zilog_layout __iomem *rp;
1358         int keyboard_mouse = 0;
1359         int err;
1360
1361         if (of_find_property(op->node, "keyboard", NULL))
1362                 keyboard_mouse = 1;
1363
1364         /* uarts must come before keyboards/mice */
1365         if (keyboard_mouse)
1366                 inst = uart_chip_count + kbm_inst;
1367         else
1368                 inst = uart_inst;
1369
1370         sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1371                                               sizeof(struct zilog_layout),
1372                                               "zs");
1373         if (!sunzilog_chip_regs[inst])
1374                 return -ENOMEM;
1375
1376         rp = sunzilog_chip_regs[inst];
1377
1378         if (zilog_irq == -1)
1379                 zilog_irq = op->irqs[0];
1380
1381         up = &sunzilog_port_table[inst * 2];
1382
1383         /* Channel A */
1384         up[0].port.mapbase = op->resource[0].start + 0x00;
1385         up[0].port.membase = (void __iomem *) &rp->channelA;
1386         up[0].port.iotype = UPIO_MEM;
1387         up[0].port.irq = op->irqs[0];
1388         up[0].port.uartclk = ZS_CLOCK;
1389         up[0].port.fifosize = 1;
1390         up[0].port.ops = &sunzilog_pops;
1391         up[0].port.type = PORT_SUNZILOG;
1392         up[0].port.flags = 0;
1393         up[0].port.line = (inst * 2) + 0;
1394         up[0].port.dev = &op->dev;
1395         up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1396         if (keyboard_mouse)
1397                 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1398         sunzilog_init_hw(&up[0]);
1399
1400         /* Channel B */
1401         up[1].port.mapbase = op->resource[0].start + 0x04;
1402         up[1].port.membase = (void __iomem *) &rp->channelB;
1403         up[1].port.iotype = UPIO_MEM;
1404         up[1].port.irq = op->irqs[0];
1405         up[1].port.uartclk = ZS_CLOCK;
1406         up[1].port.fifosize = 1;
1407         up[1].port.ops = &sunzilog_pops;
1408         up[1].port.type = PORT_SUNZILOG;
1409         up[1].port.flags = 0;
1410         up[1].port.line = (inst * 2) + 1;
1411         up[1].port.dev = &op->dev;
1412         up[1].flags |= 0;
1413         if (keyboard_mouse)
1414                 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1415         sunzilog_init_hw(&up[1]);
1416
1417         if (!keyboard_mouse) {
1418                 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->node,
1419                                             &sunzilog_reg, up[0].port.line))
1420                         up->flags |= SUNZILOG_FLAG_IS_CONS;
1421                 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1422                 if (err) {
1423                         of_iounmap(&op->resource[0],
1424                                    rp, sizeof(struct zilog_layout));
1425                         return err;
1426                 }
1427                 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->node,
1428                                             &sunzilog_reg, up[1].port.line))
1429                         up->flags |= SUNZILOG_FLAG_IS_CONS;
1430                 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1431                 if (err) {
1432                         uart_remove_one_port(&sunzilog_reg, &up[0].port);
1433                         of_iounmap(&op->resource[0],
1434                                    rp, sizeof(struct zilog_layout));
1435                         return err;
1436                 }
1437                 uart_inst++;
1438         } else {
1439                 printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) "
1440                        "is a %s\n",
1441                        op->dev.bus_id,
1442                        (unsigned long long) up[0].port.mapbase,
1443                        op->irqs[0], sunzilog_type(&up[0].port));
1444                 printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) "
1445                        "is a %s\n",
1446                        op->dev.bus_id,
1447                        (unsigned long long) up[1].port.mapbase,
1448                        op->irqs[0], sunzilog_type(&up[1].port));
1449                 kbm_inst++;
1450         }
1451
1452         dev_set_drvdata(&op->dev, &up[0]);
1453
1454         return 0;
1455 }
1456
1457 static void __devexit zs_remove_one(struct uart_sunzilog_port *up)
1458 {
1459         if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1460 #ifdef CONFIG_SERIO
1461                 serio_unregister_port(&up->serio);
1462 #endif
1463         } else
1464                 uart_remove_one_port(&sunzilog_reg, &up->port);
1465 }
1466
1467 static int __devexit zs_remove(struct of_device *op)
1468 {
1469         struct uart_sunzilog_port *up = dev_get_drvdata(&op->dev);
1470         struct zilog_layout __iomem *regs;
1471
1472         zs_remove_one(&up[0]);
1473         zs_remove_one(&up[1]);
1474
1475         regs = sunzilog_chip_regs[up[0].port.line / 2];
1476         of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
1477
1478         dev_set_drvdata(&op->dev, NULL);
1479
1480         return 0;
1481 }
1482
1483 static const struct of_device_id zs_match[] = {
1484         {
1485                 .name = "zs",
1486         },
1487         {},
1488 };
1489 MODULE_DEVICE_TABLE(of, zs_match);
1490
1491 static struct of_platform_driver zs_driver = {
1492         .name           = "zs",
1493         .match_table    = zs_match,
1494         .probe          = zs_probe,
1495         .remove         = __devexit_p(zs_remove),
1496 };
1497
1498 static int __init sunzilog_init(void)
1499 {
1500         struct device_node *dp;
1501         int err;
1502         int num_keybms = 0;
1503         int num_sunzilog = 0;
1504
1505         for_each_node_by_name(dp, "zs") {
1506                 num_sunzilog++;
1507                 if (of_find_property(dp, "keyboard", NULL))
1508                         num_keybms++;
1509         }
1510
1511         if (num_sunzilog) {
1512                 err = sunzilog_alloc_tables(num_sunzilog);
1513                 if (err)
1514                         goto out;
1515
1516                 uart_chip_count = num_sunzilog - num_keybms;
1517
1518                 err = sunserial_register_minors(&sunzilog_reg,
1519                                                 uart_chip_count * 2);
1520                 if (err)
1521                         goto out_free_tables;
1522         }
1523
1524         err = of_register_driver(&zs_driver, &of_bus_type);
1525         if (err)
1526                 goto out_unregister_uart;
1527
1528         if (zilog_irq != -1) {
1529                 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1530                 err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1531                                   "zs", sunzilog_irq_chain);
1532                 if (err)
1533                         goto out_unregister_driver;
1534
1535                 /* Enable Interrupts */
1536                 while (up) {
1537                         struct zilog_channel __iomem *channel;
1538
1539                         /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1540                         channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1541                         up->flags       |= SUNZILOG_FLAG_ISR_HANDLER;
1542                         up->curregs[R9] |= MIE;
1543                         write_zsreg(channel, R9, up->curregs[R9]);
1544                         up = up->next;
1545                 }
1546         }
1547
1548 out:
1549         return err;
1550
1551 out_unregister_driver:
1552         of_unregister_driver(&zs_driver);
1553
1554 out_unregister_uart:
1555         if (num_sunzilog) {
1556                 sunserial_unregister_minors(&sunzilog_reg, num_sunzilog);
1557                 sunzilog_reg.cons = NULL;
1558         }
1559
1560 out_free_tables:
1561         sunzilog_free_tables();
1562         goto out;
1563 }
1564
1565 static void __exit sunzilog_exit(void)
1566 {
1567         of_unregister_driver(&zs_driver);
1568
1569         if (zilog_irq != -1) {
1570                 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1571
1572                 /* Disable Interrupts */
1573                 while (up) {
1574                         struct zilog_channel __iomem *channel;
1575
1576                         /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1577                         channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1578                         up->flags       &= ~SUNZILOG_FLAG_ISR_HANDLER;
1579                         up->curregs[R9] &= ~MIE;
1580                         write_zsreg(channel, R9, up->curregs[R9]);
1581                         up = up->next;
1582                 }
1583
1584                 free_irq(zilog_irq, sunzilog_irq_chain);
1585                 zilog_irq = -1;
1586         }
1587
1588         if (sunzilog_reg.nr) {
1589                 sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr);
1590                 sunzilog_free_tables();
1591         }
1592 }
1593
1594 module_init(sunzilog_init);
1595 module_exit(sunzilog_exit);
1596
1597 MODULE_AUTHOR("David S. Miller");
1598 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1599 MODULE_VERSION("2.0");
1600 MODULE_LICENSE("GPL");