git.oblomov.eu Git - linux-2.6/blob - drivers/net/ixgbe/ixgbe_82598.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34
  35 #define IXGBE_82598_MAX_TX_QUEUES 32
  36 #define IXGBE_82598_MAX_RX_QUEUES 64
  37 #define IXGBE_82598_RAR_ENTRIES   16
  38 #define IXGBE_82598_MC_TBL_SIZE  128
  39 #define IXGBE_82598_VFT_TBL_SIZE 128
  40
  41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
  42                                              ixgbe_link_speed *speed,
  43                                              bool *autoneg);
  44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
  45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
  46                                                ixgbe_link_speed speed,
  47                                                bool autoneg,
  48                                                bool autoneg_wait_to_complete);
  49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
  50                                        u8 *eeprom_data);
  51
  52 /**
  53  *  ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Read PCIe configuration space, and get the MSI-X vector count from
  57  *  the capabilities table.
  58  **/
  59 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_adapter *adapter = hw->back;
  62         u16 msix_count;
  63         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
  64                              &msix_count);
  65         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
  66
  67         /* MSI-X count is zero-based in HW, so increment to give proper value */
  68         msix_count++;
  69
  70         return msix_count;
  71 }
  72
  73 /**
  74  */
  75 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
  76 {
  77         struct ixgbe_mac_info *mac = &hw->mac;
  78         struct ixgbe_phy_info *phy = &hw->phy;
  79         s32 ret_val = 0;
  80         u16 list_offset, data_offset;
  81
  82         /* Call PHY identify routine to get the phy type */
  83         ixgbe_identify_phy_generic(hw);
  84
  85         /* PHY Init */
  86         switch (phy->type) {
  87         case ixgbe_phy_tn:
  88                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
  89                 phy->ops.get_firmware_version =
  90                              &ixgbe_get_phy_firmware_version_tnx;
  91                 break;
  92         case ixgbe_phy_nl:
  93                 phy->ops.reset = &ixgbe_reset_phy_nl;
  94
  95                 /* Call SFP+ identify routine to get the SFP+ module type */
  96                 ret_val = phy->ops.identify_sfp(hw);
  97                 if (ret_val != 0)
  98                         goto out;
  99                 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
 100                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 101                         goto out;
 102                 }
 103
 104                 /* Check to see if SFP+ module is supported */
 105                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
 106                                                               &list_offset,
 107                                                               &data_offset);
 108                 if (ret_val != 0) {
 109                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 110                         goto out;
 111                 }
 112                 break;
 113         default:
 114                 break;
 115         }
 116
 117         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 118                 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
 119                 mac->ops.setup_link_speed =
 120                                      &ixgbe_setup_copper_link_speed_82598;
 121                 mac->ops.get_link_capabilities =
 122                                      &ixgbe_get_copper_link_capabilities_82598;
 123         }
 124
 125         mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
 126         mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
 127         mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
 128         mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
 129         mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
 130         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
 131
 132 out:
 133         return ret_val;
 134 }
 135
 136 /**
 137  *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
 138  *  @hw: pointer to hardware structure
 139  *  @speed: pointer to link speed
 140  *  @autoneg: boolean auto-negotiation value
 141  *
 142  *  Determines the link capabilities by reading the AUTOC register.
 143  **/
 144 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
 145                                              ixgbe_link_speed *speed,
 146                                              bool *autoneg)
 147 {
 148         s32 status = 0;
 149
 150         /*
 151          * Determine link capabilities based on the stored value of AUTOC,
 152          * which represents EEPROM defaults.
 153          */
 154         switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
 155         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 156                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 157                 *autoneg = false;
 158                 break;
 159
 160         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 161                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 162                 *autoneg = false;
 163                 break;
 164
 165         case IXGBE_AUTOC_LMS_1G_AN:
 166                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 167                 *autoneg = true;
 168                 break;
 169
 170         case IXGBE_AUTOC_LMS_KX4_AN:
 171         case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
 172                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
 173                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 174                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 175                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
 176                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 177                 *autoneg = true;
 178                 break;
 179
 180         default:
 181                 status = IXGBE_ERR_LINK_SETUP;
 182                 break;
 183         }
 184
 185         return status;
 186 }
 187
 188 /**
 189  *  ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
 190  *  @hw: pointer to hardware structure
 191  *  @speed: pointer to link speed
 192  *  @autoneg: boolean auto-negotiation value
 193  *
 194  *  Determines the link capabilities by reading the AUTOC register.
 195  **/
 196 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
 197                                                     ixgbe_link_speed *speed,
 198                                                     bool *autoneg)
 199 {
 200         s32 status = IXGBE_ERR_LINK_SETUP;
 201         u16 speed_ability;
 202
 203         *speed = 0;
 204         *autoneg = true;
 205
 206         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 207                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 208                                       &speed_ability);
 209
 210         if (status == 0) {
 211                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 212                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 213                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 214                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 215         }
 216
 217         return status;
 218 }
 219
 220 /**
 221  *  ixgbe_get_media_type_82598 - Determines media type
 222  *  @hw: pointer to hardware structure
 223  *
 224  *  Returns the media type (fiber, copper, backplane)
 225  **/
 226 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
 227 {
 228         enum ixgbe_media_type media_type;
 229
 230         /* Media type for I82598 is based on device ID */
 231         switch (hw->device_id) {
 232         case IXGBE_DEV_ID_82598:
 233         case IXGBE_DEV_ID_82598_BX:
 234                 media_type = ixgbe_media_type_backplane;
 235                 break;
 236         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
 237         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
 238         case IXGBE_DEV_ID_82598EB_CX4:
 239         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
 240         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
 241         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
 242         case IXGBE_DEV_ID_82598EB_XF_LR:
 243         case IXGBE_DEV_ID_82598EB_SFP_LOM:
 244                 media_type = ixgbe_media_type_fiber;
 245                 break;
 246         case IXGBE_DEV_ID_82598AT:
 247                 media_type = ixgbe_media_type_copper;
 248                 break;
 249         default:
 250                 media_type = ixgbe_media_type_unknown;
 251                 break;
 252         }
 253
 254         return media_type;
 255 }
 256
 257 /**
 258  *  ixgbe_fc_enable_82598 - Enable flow control
 259  *  @hw: pointer to hardware structure
 260  *  @packetbuf_num: packet buffer number (0-7)
 261  *
 262  *  Enable flow control according to the current settings.
 263  **/
 264 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 265 {
 266         s32 ret_val = 0;
 267         u32 fctrl_reg;
 268         u32 rmcs_reg;
 269         u32 reg;
 270
 271         fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 272         fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
 273
 274         rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
 275         rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
 276
 277         /*
 278          * The possible values of fc.current_mode are:
 279          * 0: Flow control is completely disabled
 280          * 1: Rx flow control is enabled (we can receive pause frames,
 281          *    but not send pause frames).
 282          * 2:  Tx flow control is enabled (we can send pause frames but
 283          *     we do not support receiving pause frames).
 284          * 3: Both Rx and Tx flow control (symmetric) are enabled.
 285          * other: Invalid.
 286          */
 287         switch (hw->fc.current_mode) {
 288         case ixgbe_fc_none:
 289                 /* Flow control completely disabled by software override. */
 290                 break;
 291         case ixgbe_fc_rx_pause:
 292                 /*
 293                  * Rx Flow control is enabled and Tx Flow control is
 294                  * disabled by software override. Since there really
 295                  * isn't a way to advertise that we are capable of RX
 296                  * Pause ONLY, we will advertise that we support both
 297                  * symmetric and asymmetric Rx PAUSE.  Later, we will
 298                  * disable the adapter's ability to send PAUSE frames.
 299                  */
 300                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 301                 break;
 302         case ixgbe_fc_tx_pause:
 303                 /*
 304                  * Tx Flow control is enabled, and Rx Flow control is
 305                  * disabled by software override.
 306                  */
 307                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 308                 break;
 309         case ixgbe_fc_full:
 310                 /* Flow control (both Rx and Tx) is enabled by SW override. */
 311                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 312                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 313                 break;
 314         default:
 315                 hw_dbg(hw, "Flow control param set incorrectly\n");
 316                 ret_val = -IXGBE_ERR_CONFIG;
 317                 goto out;
 318                 break;
 319         }
 320
 321         /* Enable 802.3x based flow control settings. */
 322         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
 323         IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
 324
 325         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
 326         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
 327                 if (hw->fc.send_xon) {
 328                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 329                                         (hw->fc.low_water | IXGBE_FCRTL_XONE));
 330                 } else {
 331                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 332                                         hw->fc.low_water);
 333                 }
 334
 335                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
 336                                 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
 337         }
 338
 339         /* Configure pause time (2 TCs per register) */
 340         reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
 341         if ((packetbuf_num & 1) == 0)
 342                 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
 343         else
 344                 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
 345         IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
 346
 347         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
 348
 349 out:
 350         return ret_val;
 351 }
 352
 353 /**
 354  *  ixgbe_setup_fc_82598 - Configure flow control settings
 355  *  @hw: pointer to hardware structure
 356  *  @packetbuf_num: packet buffer number (0-7)
 357  *
 358  *  Configures the flow control settings based on SW configuration.  This
 359  *  function is used for 802.3x flow control configuration only.
 360  **/
 361 static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 362 {
 363         s32 ret_val = 0;
 364         ixgbe_link_speed speed;
 365         bool link_up;
 366
 367         /* Validate the packetbuf configuration */
 368         if (packetbuf_num < 0 || packetbuf_num > 7) {
 369                 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
 370                           " 0-7\n", packetbuf_num);
 371                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 372                 goto out;
 373         }
 374
 375         /*
 376          * Validate the water mark configuration.  Zero water marks are invalid
 377          * because it causes the controller to just blast out fc packets.
 378          */
 379         if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
 380                 hw_dbg(hw, "Invalid water mark configuration\n");
 381                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 382                 goto out;
 383         }
 384
 385         /*
 386          * Validate the requested mode.  Strict IEEE mode does not allow
 387          * ixgbe_fc_rx_pause because it will cause testing anomalies.
 388          */
 389         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 390                 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 391                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 392                 goto out;
 393         }
 394
 395         /*
 396          * 10gig parts do not have a word in the EEPROM to determine the
 397          * default flow control setting, so we explicitly set it to full.
 398          */
 399         if (hw->fc.requested_mode == ixgbe_fc_default)
 400                 hw->fc.requested_mode = ixgbe_fc_full;
 401
 402         /*
 403          * Save off the requested flow control mode for use later.  Depending
 404          * on the link partner's capabilities, we may or may not use this mode.
 405          */
 406
 407         hw->fc.current_mode = hw->fc.requested_mode;
 408
 409         /* Decide whether to use autoneg or not. */
 410         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 411         if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL))
 412                 ret_val = ixgbe_fc_autoneg(hw);
 413
 414         if (ret_val)
 415                 goto out;
 416
 417         ret_val = ixgbe_fc_enable_82598(hw, packetbuf_num);
 418
 419 out:
 420         return ret_val;
 421 }
 422
 423 /**
 424  *  ixgbe_setup_mac_link_82598 - Configures MAC link settings
 425  *  @hw: pointer to hardware structure
 426  *
 427  *  Configures link settings based on values in the ixgbe_hw struct.
 428  *  Restarts the link.  Performs autonegotiation if needed.
 429  **/
 430 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
 431 {
 432         u32 autoc_reg;
 433         u32 links_reg;
 434         u32 i;
 435         s32 status = 0;
 436
 437         /* Restart link */
 438         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 439         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 440         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 441
 442         /* Only poll for autoneg to complete if specified to do so */
 443         if (hw->phy.autoneg_wait_to_complete) {
 444                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 445                      IXGBE_AUTOC_LMS_KX4_AN ||
 446                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 447                      IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 448                         links_reg = 0; /* Just in case Autoneg time = 0 */
 449                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 450                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 451                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 452                                         break;
 453                                 msleep(100);
 454                         }
 455                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 456                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 457                                 hw_dbg(hw, "Autonegotiation did not complete.\n");
 458                         }
 459                 }
 460         }
 461
 462         /*
 463          * We want to save off the original Flow Control configuration just in
 464          * case we get disconnected and then reconnected into a different hub
 465          * or switch with different Flow Control capabilities.
 466          */
 467         ixgbe_setup_fc_82598(hw, 0);
 468
 469         /* Add delay to filter out noises during initial link setup */
 470         msleep(50);
 471
 472         return status;
 473 }
 474
 475 /**
 476  *  ixgbe_check_mac_link_82598 - Get link/speed status
 477  *  @hw: pointer to hardware structure
 478  *  @speed: pointer to link speed
 479  *  @link_up: true is link is up, false otherwise
 480  *  @link_up_wait_to_complete: bool used to wait for link up or not
 481  *
 482  *  Reads the links register to determine if link is up and the current speed
 483  **/
 484 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
 485                                       ixgbe_link_speed *speed, bool *link_up,
 486                                       bool link_up_wait_to_complete)
 487 {
 488         u32 links_reg;
 489         u32 i;
 490         u16 link_reg, adapt_comp_reg;
 491
 492         /*
 493          * SERDES PHY requires us to read link status from register 0xC79F.
 494          * Bit 0 set indicates link is up/ready; clear indicates link down.
 495          * 0xC00C is read to check that the XAUI lanes are active.  Bit 0
 496          * clear indicates active; set indicates inactive.
 497          */
 498         if (hw->phy.type == ixgbe_phy_nl) {
 499                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 500                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 501                 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
 502                                      &adapt_comp_reg);
 503                 if (link_up_wait_to_complete) {
 504                         for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 505                                 if ((link_reg & 1) &&
 506                                     ((adapt_comp_reg & 1) == 0)) {
 507                                         *link_up = true;
 508                                         break;
 509                                 } else {
 510                                         *link_up = false;
 511                                 }
 512                                 msleep(100);
 513                                 hw->phy.ops.read_reg(hw, 0xC79F,
 514                                                      IXGBE_TWINAX_DEV,
 515                                                      &link_reg);
 516                                 hw->phy.ops.read_reg(hw, 0xC00C,
 517                                                      IXGBE_TWINAX_DEV,
 518                                                      &adapt_comp_reg);
 519                         }
 520                 } else {
 521                         if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
 522                                 *link_up = true;
 523                         else
 524                                 *link_up = false;
 525                 }
 526
 527                 if (*link_up == false)
 528                         goto out;
 529         }
 530
 531         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 532         if (link_up_wait_to_complete) {
 533                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 534                         if (links_reg & IXGBE_LINKS_UP) {
 535                                 *link_up = true;
 536                                 break;
 537                         } else {
 538                                 *link_up = false;
 539                         }
 540                         msleep(100);
 541                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 542                 }
 543         } else {
 544                 if (links_reg & IXGBE_LINKS_UP)
 545                         *link_up = true;
 546                 else
 547                         *link_up = false;
 548         }
 549
 550         if (links_reg & IXGBE_LINKS_SPEED)
 551                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 552         else
 553                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 554
 555 out:
 556         return 0;
 557 }
 558
 559
 560 /**
 561  *  ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
 562  *  @hw: pointer to hardware structure
 563  *  @speed: new link speed
 564  *  @autoneg: true if auto-negotiation enabled
 565  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 566  *
 567  *  Set the link speed in the AUTOC register and restarts link.
 568  **/
 569 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
 570                                            ixgbe_link_speed speed, bool autoneg,
 571                                            bool autoneg_wait_to_complete)
 572 {
 573         s32              status            = 0;
 574         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 575         u32              curr_autoc        = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 576         u32              autoc             = curr_autoc;
 577         u32              link_mode         = autoc & IXGBE_AUTOC_LMS_MASK;
 578
 579         /* Check to see if speed passed in is supported. */
 580         ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
 581         speed &= link_capabilities;
 582
 583         if (speed == IXGBE_LINK_SPEED_UNKNOWN)
 584                 status = IXGBE_ERR_LINK_SETUP;
 585
 586         /* Set KX4/KX support according to speed requested */
 587         else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
 588                  link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 589                 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
 590                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 591                         autoc |= IXGBE_AUTOC_KX4_SUPP;
 592                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 593                         autoc |= IXGBE_AUTOC_KX_SUPP;
 594                 if (autoc != curr_autoc)
 595                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
 596         }
 597
 598         if (status == 0) {
 599                 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
 600
 601                 /*
 602                  * Setup and restart the link based on the new values in
 603                  * ixgbe_hw This will write the AUTOC register based on the new
 604                  * stored values
 605                  */
 606                 status = ixgbe_setup_mac_link_82598(hw);
 607         }
 608
 609         return status;
 610 }
 611
 612
 613 /**
 614  *  ixgbe_setup_copper_link_82598 - Setup copper link settings
 615  *  @hw: pointer to hardware structure
 616  *
 617  *  Configures link settings based on values in the ixgbe_hw struct.
 618  *  Restarts the link.  Performs autonegotiation if needed.  Restart
 619  *  phy and wait for autonegotiate to finish.  Then synchronize the
 620  *  MAC and PHY.
 621  **/
 622 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
 623 {
 624         s32 status;
 625
 626         /* Restart autonegotiation on PHY */
 627         status = hw->phy.ops.setup_link(hw);
 628
 629         /* Set up MAC */
 630         ixgbe_setup_mac_link_82598(hw);
 631
 632         return status;
 633 }
 634
 635 /**
 636  *  ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
 637  *  @hw: pointer to hardware structure
 638  *  @speed: new link speed
 639  *  @autoneg: true if autonegotiation enabled
 640  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 641  *
 642  *  Sets the link speed in the AUTOC register in the MAC and restarts link.
 643  **/
 644 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
 645                                                ixgbe_link_speed speed,
 646                                                bool autoneg,
 647                                                bool autoneg_wait_to_complete)
 648 {
 649         s32 status;
 650
 651         /* Setup the PHY according to input speed */
 652         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 653                                               autoneg_wait_to_complete);
 654
 655         /* Set up MAC */
 656         ixgbe_setup_mac_link_82598(hw);
 657
 658         return status;
 659 }
 660
 661 /**
 662  *  ixgbe_reset_hw_82598 - Performs hardware reset
 663  *  @hw: pointer to hardware structure
 664  *
 665  *  Resets the hardware by resetting the transmit and receive units, masks and
 666  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
 667  *  reset.
 668  **/
 669 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
 670 {
 671         s32 status = 0;
 672         u32 ctrl;
 673         u32 gheccr;
 674         u32 i;
 675         u32 autoc;
 676         u8  analog_val;
 677
 678         /* Call adapter stop to disable tx/rx and clear interrupts */
 679         hw->mac.ops.stop_adapter(hw);
 680
 681         /*
 682          * Power up the Atlas Tx lanes if they are currently powered down.
 683          * Atlas Tx lanes are powered down for MAC loopback tests, but
 684          * they are not automatically restored on reset.
 685          */
 686         hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
 687         if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
 688                 /* Enable Tx Atlas so packets can be transmitted again */
 689                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 690                                              &analog_val);
 691                 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
 692                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 693                                               analog_val);
 694
 695                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 696                                              &analog_val);
 697                 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
 698                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 699                                               analog_val);
 700
 701                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 702                                              &analog_val);
 703                 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
 704                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 705                                               analog_val);
 706
 707                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 708                                              &analog_val);
 709                 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
 710                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 711                                               analog_val);
 712         }
 713
 714         /* Reset PHY */
 715         if (hw->phy.reset_disable == false)
 716                 hw->phy.ops.reset(hw);
 717
 718         /*
 719          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 720          * access and verify no pending requests before reset
 721          */
 722         if (ixgbe_disable_pcie_master(hw) != 0) {
 723                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 724                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 725         }
 726
 727         /*
 728          * Issue global reset to the MAC.  This needs to be a SW reset.
 729          * If link reset is used, it might reset the MAC when mng is using it
 730          */
 731         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 732         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
 733         IXGBE_WRITE_FLUSH(hw);
 734
 735         /* Poll for reset bit to self-clear indicating reset is complete */
 736         for (i = 0; i < 10; i++) {
 737                 udelay(1);
 738                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 739                 if (!(ctrl & IXGBE_CTRL_RST))
 740                         break;
 741         }
 742         if (ctrl & IXGBE_CTRL_RST) {
 743                 status = IXGBE_ERR_RESET_FAILED;
 744                 hw_dbg(hw, "Reset polling failed to complete.\n");
 745         }
 746
 747         msleep(50);
 748
 749         gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
 750         gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
 751         IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
 752
 753         /*
 754          * Store the original AUTOC value if it has not been
 755          * stored off yet.  Otherwise restore the stored original
 756          * AUTOC value since the reset operation sets back to deaults.
 757          */
 758         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 759         if (hw->mac.orig_link_settings_stored == false) {
 760                 hw->mac.orig_autoc = autoc;
 761                 hw->mac.orig_link_settings_stored = true;
 762         } else if (autoc != hw->mac.orig_autoc) {
 763                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
 764         }
 765
 766         /* Store the permanent mac address */
 767         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 768
 769         return status;
 770 }
 771
 772 /**
 773  *  ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
 774  *  @hw: pointer to hardware struct
 775  *  @rar: receive address register index to associate with a VMDq index
 776  *  @vmdq: VMDq set index
 777  **/
 778 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 779 {
 780         u32 rar_high;
 781
 782         rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 783         rar_high &= ~IXGBE_RAH_VIND_MASK;
 784         rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
 785         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 786         return 0;
 787 }
 788
 789 /**
 790  *  ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
 791  *  @hw: pointer to hardware struct
 792  *  @rar: receive address register index to associate with a VMDq index
 793  *  @vmdq: VMDq clear index (not used in 82598, but elsewhere)
 794  **/
 795 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 796 {
 797         u32 rar_high;
 798         u32 rar_entries = hw->mac.num_rar_entries;
 799
 800         if (rar < rar_entries) {
 801                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 802                 if (rar_high & IXGBE_RAH_VIND_MASK) {
 803                         rar_high &= ~IXGBE_RAH_VIND_MASK;
 804                         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 805                 }
 806         } else {
 807                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 808         }
 809
 810         return 0;
 811 }
 812
 813 /**
 814  *  ixgbe_set_vfta_82598 - Set VLAN filter table
 815  *  @hw: pointer to hardware structure
 816  *  @vlan: VLAN id to write to VLAN filter
 817  *  @vind: VMDq output index that maps queue to VLAN id in VFTA
 818  *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
 819  *
 820  *  Turn on/off specified VLAN in the VLAN filter table.
 821  **/
 822 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
 823                                 bool vlan_on)
 824 {
 825         u32 regindex;
 826         u32 bitindex;
 827         u32 bits;
 828         u32 vftabyte;
 829
 830         if (vlan > 4095)
 831                 return IXGBE_ERR_PARAM;
 832
 833         /* Determine 32-bit word position in array */
 834         regindex = (vlan >> 5) & 0x7F;   /* upper seven bits */
 835
 836         /* Determine the location of the (VMD) queue index */
 837         vftabyte =  ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
 838         bitindex = (vlan & 0x7) << 2;    /* lower 3 bits indicate nibble */
 839
 840         /* Set the nibble for VMD queue index */
 841         bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
 842         bits &= (~(0x0F << bitindex));
 843         bits |= (vind << bitindex);
 844         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
 845
 846         /* Determine the location of the bit for this VLAN id */
 847         bitindex = vlan & 0x1F;   /* lower five bits */
 848
 849         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
 850         if (vlan_on)
 851                 /* Turn on this VLAN id */
 852                 bits |= (1 << bitindex);
 853         else
 854                 /* Turn off this VLAN id */
 855                 bits &= ~(1 << bitindex);
 856         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
 857
 858         return 0;
 859 }
 860
 861 /**
 862  *  ixgbe_clear_vfta_82598 - Clear VLAN filter table
 863  *  @hw: pointer to hardware structure
 864  *
 865  *  Clears the VLAN filer table, and the VMDq index associated with the filter
 866  **/
 867 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
 868 {
 869         u32 offset;
 870         u32 vlanbyte;
 871
 872         for (offset = 0; offset < hw->mac.vft_size; offset++)
 873                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
 874
 875         for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
 876                 for (offset = 0; offset < hw->mac.vft_size; offset++)
 877                         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
 878                                         0);
 879
 880         return 0;
 881 }
 882
 883 /**
 884  *  ixgbe_blink_led_start_82598 - Blink LED based on index.
 885  *  @hw: pointer to hardware structure
 886  *  @index: led number to blink
 887  **/
 888 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
 889 {
 890         ixgbe_link_speed speed = 0;
 891         bool link_up = 0;
 892         u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 893         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 894
 895         /*
 896          * Link must be up to auto-blink the LEDs on the 82598EB MAC;
 897          * force it if link is down.
 898          */
 899         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 900
 901         if (!link_up) {
 902                 autoc_reg |= IXGBE_AUTOC_FLU;
 903                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 904                 msleep(10);
 905         }
 906
 907         led_reg &= ~IXGBE_LED_MODE_MASK(index);
 908         led_reg |= IXGBE_LED_BLINK(index);
 909         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 910         IXGBE_WRITE_FLUSH(hw);
 911
 912         return 0;
 913 }
 914
 915 /**
 916  *  ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
 917  *  @hw: pointer to hardware structure
 918  *  @index: led number to stop blinking
 919  **/
 920 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
 921 {
 922         u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 923         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 924
 925         autoc_reg &= ~IXGBE_AUTOC_FLU;
 926         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 927         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 928
 929         led_reg &= ~IXGBE_LED_MODE_MASK(index);
 930         led_reg &= ~IXGBE_LED_BLINK(index);
 931         led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 932         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 933         IXGBE_WRITE_FLUSH(hw);
 934
 935         return 0;
 936 }
 937
 938 /**
 939  *  ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
 940  *  @hw: pointer to hardware structure
 941  *  @reg: analog register to read
 942  *  @val: read value
 943  *
 944  *  Performs read operation to Atlas analog register specified.
 945  **/
 946 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
 947 {
 948         u32  atlas_ctl;
 949
 950         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
 951                         IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
 952         IXGBE_WRITE_FLUSH(hw);
 953         udelay(10);
 954         atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 955         *val = (u8)atlas_ctl;
 956
 957         return 0;
 958 }
 959
 960 /**
 961  *  ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
 962  *  @hw: pointer to hardware structure
 963  *  @reg: atlas register to write
 964  *  @val: value to write
 965  *
 966  *  Performs write operation to Atlas analog register specified.
 967  **/
 968 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
 969 {
 970         u32  atlas_ctl;
 971
 972         atlas_ctl = (reg << 8) | val;
 973         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
 974         IXGBE_WRITE_FLUSH(hw);
 975         udelay(10);
 976
 977         return 0;
 978 }
 979
 980 /**
 981  *  ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
 982  *  over I2C interface through an intermediate phy.
 983  *  @hw: pointer to hardware structure
 984  *  @byte_offset: EEPROM byte offset to read
 985  *  @eeprom_data: value read
 986  *
 987  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
 988  **/
 989 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
 990                                        u8 *eeprom_data)
 991 {
 992         s32 status = 0;
 993         u16 sfp_addr = 0;
 994         u16 sfp_data = 0;
 995         u16 sfp_stat = 0;
 996         u32 i;
 997
 998         if (hw->phy.type == ixgbe_phy_nl) {
 999                 /*
1000                  * phy SDA/SCL registers are at addresses 0xC30A to
1001                  * 0xC30D.  These registers are used to talk to the SFP+
1002                  * module's EEPROM through the SDA/SCL (I2C) interface.
1003                  */
1004                 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1005                 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1006                 hw->phy.ops.write_reg(hw,
1007                                       IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1008                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1009                                       sfp_addr);
1010
1011                 /* Poll status */
1012                 for (i = 0; i < 100; i++) {
1013                         hw->phy.ops.read_reg(hw,
1014                                              IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1015                                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1016                                              &sfp_stat);
1017                         sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1018                         if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1019                                 break;
1020                         msleep(10);
1021                 }
1022
1023                 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1024                         hw_dbg(hw, "EEPROM read did not pass.\n");
1025                         status = IXGBE_ERR_SFP_NOT_PRESENT;
1026                         goto out;
1027                 }
1028
1029                 /* Read data */
1030                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1031                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1032
1033                 *eeprom_data = (u8)(sfp_data >> 8);
1034         } else {
1035                 status = IXGBE_ERR_PHY;
1036                 goto out;
1037         }
1038
1039 out:
1040         return status;
1041 }
1042
1043 /**
1044  *  ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1045  *  @hw: pointer to hardware structure
1046  *
1047  *  Determines physical layer capabilities of the current configuration.
1048  **/
1049 static s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1050 {
1051         s32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1052
1053         switch (hw->device_id) {
1054         case IXGBE_DEV_ID_82598:
1055                 /* Default device ID is mezzanine card KX/KX4 */
1056                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1057                                   IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1058                 break;
1059         case IXGBE_DEV_ID_82598_BX:
1060                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1061         case IXGBE_DEV_ID_82598EB_CX4:
1062         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1063                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1064                 break;
1065         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1066                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1067                 break;
1068         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1069         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1070         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1071                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1072                 break;
1073         case IXGBE_DEV_ID_82598EB_XF_LR:
1074                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1075                 break;
1076         case IXGBE_DEV_ID_82598AT:
1077                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1078                                   IXGBE_PHYSICAL_LAYER_1000BASE_T);
1079                 break;
1080         case IXGBE_DEV_ID_82598EB_SFP_LOM:
1081                 hw->phy.ops.identify_sfp(hw);
1082
1083                 switch (hw->phy.sfp_type) {
1084                 case ixgbe_sfp_type_da_cu:
1085                         physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1086                         break;
1087                 case ixgbe_sfp_type_sr:
1088                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1089                         break;
1090                 case ixgbe_sfp_type_lr:
1091                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1092                         break;
1093                 default:
1094                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1095                         break;
1096                 }
1097                 break;
1098
1099         default:
1100                 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1101                 break;
1102         }
1103
1104         return physical_layer;
1105 }
1106
1107 static struct ixgbe_mac_operations mac_ops_82598 = {
1108         .init_hw                = &ixgbe_init_hw_generic,
1109         .reset_hw               = &ixgbe_reset_hw_82598,
1110         .start_hw               = &ixgbe_start_hw_generic,
1111         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1112         .get_media_type         = &ixgbe_get_media_type_82598,
1113         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1114         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1115         .stop_adapter           = &ixgbe_stop_adapter_generic,
1116         .read_analog_reg8       = &ixgbe_read_analog_reg8_82598,
1117         .write_analog_reg8      = &ixgbe_write_analog_reg8_82598,
1118         .setup_link             = &ixgbe_setup_mac_link_82598,
1119         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82598,
1120         .check_link             = &ixgbe_check_mac_link_82598,
1121         .get_link_capabilities  = &ixgbe_get_link_capabilities_82598,
1122         .led_on                 = &ixgbe_led_on_generic,
1123         .led_off                = &ixgbe_led_off_generic,
1124         .blink_led_start        = &ixgbe_blink_led_start_82598,
1125         .blink_led_stop         = &ixgbe_blink_led_stop_82598,
1126         .set_rar                = &ixgbe_set_rar_generic,
1127         .clear_rar              = &ixgbe_clear_rar_generic,
1128         .set_vmdq               = &ixgbe_set_vmdq_82598,
1129         .clear_vmdq             = &ixgbe_clear_vmdq_82598,
1130         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1131         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1132         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1133         .enable_mc              = &ixgbe_enable_mc_generic,
1134         .disable_mc             = &ixgbe_disable_mc_generic,
1135         .clear_vfta             = &ixgbe_clear_vfta_82598,
1136         .set_vfta               = &ixgbe_set_vfta_82598,
1137         .setup_fc               = &ixgbe_setup_fc_82598,
1138 };
1139
1140 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1141         .init_params            = &ixgbe_init_eeprom_params_generic,
1142         .read                   = &ixgbe_read_eeprom_generic,
1143         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1144         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1145 };
1146
1147 static struct ixgbe_phy_operations phy_ops_82598 = {
1148         .identify               = &ixgbe_identify_phy_generic,
1149         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1150         .reset                  = &ixgbe_reset_phy_generic,
1151         .read_reg               = &ixgbe_read_phy_reg_generic,
1152         .write_reg              = &ixgbe_write_phy_reg_generic,
1153         .setup_link             = &ixgbe_setup_phy_link_generic,
1154         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1155         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_82598,
1156 };
1157
1158 struct ixgbe_info ixgbe_82598_info = {
1159         .mac                    = ixgbe_mac_82598EB,
1160         .get_invariants         = &ixgbe_get_invariants_82598,
1161         .mac_ops                = &mac_ops_82598,
1162         .eeprom_ops             = &eeprom_ops_82598,
1163         .phy_ops                = &phy_ops_82598,
1164 };
1165