git.oblomov.eu Git - linux-2.6/blob - drivers/isdn/hardware/mISDN/hfcpci.c

   1 /*
   2  *
   3  * hfcpci.c     low level driver for CCD's hfc-pci based cards
   4  *
   5  * Author     Werner Cornelius (werner@isdn4linux.de)
   6  *            based on existing driver for CCD hfc ISA cards
   7  *            type approval valid for HFC-S PCI A based card
   8  *
   9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  10  * Copyright 2008  by Karsten Keil <kkeil@novell.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2, or (at your option)
  15  * any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30 #include <linux/delay.h>
  31 #include <linux/mISDNhw.h>
  32
  33 #include "hfc_pci.h"
  34
  35 static const char *hfcpci_revision = "2.0";
  36
  37 #define MAX_CARDS       8
  38 static int HFC_cnt;
  39 static uint debug;
  40
  41 MODULE_AUTHOR("Karsten Keil");
  42 MODULE_LICENSE("GPL");
  43 module_param(debug, uint, 0);
  44
  45 static LIST_HEAD(HFClist);
  46 DEFINE_RWLOCK(HFClock);
  47
  48 enum {
  49         HFC_CCD_2BD0,
  50         HFC_CCD_B000,
  51         HFC_CCD_B006,
  52         HFC_CCD_B007,
  53         HFC_CCD_B008,
  54         HFC_CCD_B009,
  55         HFC_CCD_B00A,
  56         HFC_CCD_B00B,
  57         HFC_CCD_B00C,
  58         HFC_CCD_B100,
  59         HFC_CCD_B700,
  60         HFC_CCD_B701,
  61         HFC_ASUS_0675,
  62         HFC_BERKOM_A1T,
  63         HFC_BERKOM_TCONCEPT,
  64         HFC_ANIGMA_MC145575,
  65         HFC_ZOLTRIX_2BD0,
  66         HFC_DIGI_DF_M_IOM2_E,
  67         HFC_DIGI_DF_M_E,
  68         HFC_DIGI_DF_M_IOM2_A,
  69         HFC_DIGI_DF_M_A,
  70         HFC_ABOCOM_2BD1,
  71         HFC_SITECOM_DC105V2,
  72 };
  73
  74 struct hfcPCI_hw {
  75         unsigned char           cirm;
  76         unsigned char           ctmt;
  77         unsigned char           clkdel;
  78         unsigned char           states;
  79         unsigned char           conn;
  80         unsigned char           mst_m;
  81         unsigned char           int_m1;
  82         unsigned char           int_m2;
  83         unsigned char           sctrl;
  84         unsigned char           sctrl_r;
  85         unsigned char           sctrl_e;
  86         unsigned char           trm;
  87         unsigned char           fifo_en;
  88         unsigned char           bswapped;
  89         unsigned char           protocol;
  90         int                     nt_timer;
  91         unsigned char           *pci_io; /* start of PCI IO memory */
  92         dma_addr_t              dmahandle;
  93         void                    *fifos; /* FIFO memory */
  94         int                     last_bfifo_cnt[2];
  95             /* marker saving last b-fifo frame count */
  96         struct timer_list       timer;
  97 };
  98
  99 #define HFC_CFG_MASTER          1
 100 #define HFC_CFG_SLAVE           2
 101 #define HFC_CFG_PCM             3
 102 #define HFC_CFG_2HFC            4
 103 #define HFC_CFG_SLAVEHFC        5
 104 #define HFC_CFG_NEG_F0          6
 105 #define HFC_CFG_SW_DD_DU        7
 106
 107 #define FLG_HFC_TIMER_T1        16
 108 #define FLG_HFC_TIMER_T3        17
 109
 110 #define NT_T1_COUNT     1120    /* number of 3.125ms interrupts (3.5s) */
 111 #define NT_T3_COUNT     31      /* number of 3.125ms interrupts (97 ms) */
 112 #define CLKDEL_TE       0x0e    /* CLKDEL in TE mode */
 113 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode */
 114
 115
 116 struct hfc_pci {
 117         struct list_head        list;
 118         u_char                  subtype;
 119         u_char                  chanlimit;
 120         u_char                  initdone;
 121         u_long                  cfg;
 122         u_int                   irq;
 123         u_int                   irqcnt;
 124         struct pci_dev          *pdev;
 125         struct hfcPCI_hw        hw;
 126         spinlock_t              lock;   /* card lock */
 127         struct dchannel         dch;
 128         struct bchannel         bch[2];
 129 };
 130
 131 /* Interface functions */
 132 static void
 133 enable_hwirq(struct hfc_pci *hc)
 134 {
 135         hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
 136         Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
 137 }
 138
 139 static void
 140 disable_hwirq(struct hfc_pci *hc)
 141 {
 142         hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
 143         Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
 144 }
 145
 146 /*
 147  * free hardware resources used by driver
 148  */
 149 static void
 150 release_io_hfcpci(struct hfc_pci *hc)
 151 {
 152         /* disable memory mapped ports + busmaster */
 153         pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
 154         del_timer(&hc->hw.timer);
 155         pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
 156         iounmap((void *)hc->hw.pci_io);
 157 }
 158
 159 /*
 160  * set mode (NT or TE)
 161  */
 162 static void
 163 hfcpci_setmode(struct hfc_pci *hc)
 164 {
 165         if (hc->hw.protocol == ISDN_P_NT_S0) {
 166                 hc->hw.clkdel = CLKDEL_NT;      /* ST-Bit delay for NT-Mode */
 167                 hc->hw.sctrl |= SCTRL_MODE_NT;  /* NT-MODE */
 168                 hc->hw.states = 1;              /* G1 */
 169         } else {
 170                 hc->hw.clkdel = CLKDEL_TE;      /* ST-Bit delay for TE-Mode */
 171                 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
 172                 hc->hw.states = 2;              /* F2 */
 173         }
 174         Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
 175         Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
 176         udelay(10);
 177         Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
 178         Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
 179 }
 180
 181 /*
 182  * function called to reset the HFC PCI chip. A complete software reset of chip
 183  * and fifos is done.
 184  */
 185 static void
 186 reset_hfcpci(struct hfc_pci *hc)
 187 {
 188         u_char  val;
 189         int     cnt = 0;
 190
 191         printk(KERN_DEBUG "reset_hfcpci: entered\n");
 192         val = Read_hfc(hc, HFCPCI_CHIP_ID);
 193         printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
 194         /* enable memory mapped ports, disable busmaster */
 195         pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
 196         disable_hwirq(hc);
 197         /* enable memory ports + busmaster */
 198         pci_write_config_word(hc->pdev, PCI_COMMAND,
 199             PCI_ENA_MEMIO + PCI_ENA_MASTER);
 200         val = Read_hfc(hc, HFCPCI_STATUS);
 201         printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
 202         hc->hw.cirm = HFCPCI_RESET;     /* Reset On */
 203         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
 204         set_current_state(TASK_UNINTERRUPTIBLE);
 205         mdelay(10);                     /* Timeout 10ms */
 206         hc->hw.cirm = 0;                /* Reset Off */
 207         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
 208         val = Read_hfc(hc, HFCPCI_STATUS);
 209         printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
 210         while (cnt < 50000) { /* max 50000 us */
 211                 udelay(5);
 212                 cnt += 5;
 213                 val = Read_hfc(hc, HFCPCI_STATUS);
 214                 if (!(val & 2))
 215                         break;
 216         }
 217         printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
 218
 219         hc->hw.fifo_en = 0x30;  /* only D fifos enabled */
 220
 221         hc->hw.bswapped = 0;    /* no exchange */
 222         hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
 223         hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
 224         hc->hw.sctrl = 0x40;    /* set tx_lo mode, error in datasheet ! */
 225         hc->hw.sctrl_r = 0;
 226         hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE;     /* S/T Auto awake */
 227         hc->hw.mst_m = 0;
 228         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
 229                 hc->hw.mst_m |= HFCPCI_MASTER;  /* HFC Master Mode */
 230         if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
 231                 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
 232         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 233         Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
 234         Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
 235         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
 236
 237         hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
 238             HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
 239         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 240
 241         /* Clear already pending ints */
 242         if (Read_hfc(hc, HFCPCI_INT_S1));
 243
 244         /* set NT/TE mode */
 245         hfcpci_setmode(hc);
 246
 247         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
 248         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
 249
 250         /*
 251          * Init GCI/IOM2 in master mode
 252          * Slots 0 and 1 are set for B-chan 1 and 2
 253          * D- and monitor/CI channel are not enabled
 254          * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
 255          * STIO2 is used as data input, B1+B2 from IOM->ST
 256          * ST B-channel send disabled -> continous 1s
 257          * The IOM slots are always enabled
 258          */
 259         if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
 260                 /* set data flow directions: connect B1,B2: HFC to/from PCM */
 261                 hc->hw.conn = 0x09;
 262         } else {
 263                 hc->hw.conn = 0x36;     /* set data flow directions */
 264                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
 265                         Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
 266                         Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
 267                         Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
 268                         Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
 269                 } else {
 270                         Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
 271                         Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
 272                         Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
 273                         Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
 274                 }
 275         }
 276         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
 277         val = Read_hfc(hc, HFCPCI_INT_S2);
 278 }
 279
 280 /*
 281  * Timer function called when kernel timer expires
 282  */
 283 static void
 284 hfcpci_Timer(struct hfc_pci *hc)
 285 {
 286         hc->hw.timer.expires = jiffies + 75;
 287         /* WD RESET */
 288 /*
 289  *      WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
 290  *      add_timer(&hc->hw.timer);
 291  */
 292 }
 293
 294
 295 /*
 296  * select a b-channel entry matching and active
 297  */
 298 static struct bchannel *
 299 Sel_BCS(struct hfc_pci *hc, int channel)
 300 {
 301         if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
 302                 (hc->bch[0].nr & channel))
 303                 return &hc->bch[0];
 304         else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
 305                 (hc->bch[1].nr & channel))
 306                 return &hc->bch[1];
 307         else
 308                 return NULL;
 309 }
 310
 311 /*
 312  * clear the desired B-channel rx fifo
 313  */
 314 static void
 315 hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
 316 {
 317         u_char          fifo_state;
 318         struct bzfifo   *bzr;
 319
 320         if (fifo) {
 321                 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
 322                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
 323         } else {
 324                 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
 325                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
 326         }
 327         if (fifo_state)
 328                 hc->hw.fifo_en ^= fifo_state;
 329         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 330         hc->hw.last_bfifo_cnt[fifo] = 0;
 331         bzr->f1 = MAX_B_FRAMES;
 332         bzr->f2 = bzr->f1;      /* init F pointers to remain constant */
 333         bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
 334         bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
 335             le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
 336         if (fifo_state)
 337                 hc->hw.fifo_en |= fifo_state;
 338         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 339 }
 340
 341 /*
 342  * clear the desired B-channel tx fifo
 343  */
 344 static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
 345 {
 346         u_char          fifo_state;
 347         struct bzfifo   *bzt;
 348
 349         if (fifo) {
 350                 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
 351                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
 352         } else {
 353                 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
 354                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
 355         }
 356         if (fifo_state)
 357                 hc->hw.fifo_en ^= fifo_state;
 358         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 359         if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
 360                 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
 361                     "z1(%x) z2(%x) state(%x)\n",
 362                     fifo, bzt->f1, bzt->f2,
 363                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
 364                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
 365                     fifo_state);
 366         bzt->f2 = MAX_B_FRAMES;
 367         bzt->f1 = bzt->f2;      /* init F pointers to remain constant */
 368         bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
 369         bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
 370         if (fifo_state)
 371                 hc->hw.fifo_en |= fifo_state;
 372         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 373         if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
 374                 printk(KERN_DEBUG
 375                     "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
 376                     fifo, bzt->f1, bzt->f2,
 377                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
 378                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
 379 }
 380
 381 /*
 382  * read a complete B-frame out of the buffer
 383  */
 384 static void
 385 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
 386     u_char *bdata, int count)
 387 {
 388         u_char          *ptr, *ptr1, new_f2;
 389         int             total, maxlen, new_z2;
 390         struct zt       *zp;
 391
 392         if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
 393                 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
 394         zp = &bz->za[bz->f2];   /* point to Z-Regs */
 395         new_z2 = le16_to_cpu(zp->z2) + count;   /* new position in fifo */
 396         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
 397                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
 398         new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
 399         if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
 400             (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
 401                 if (bch->debug & DEBUG_HW)
 402                         printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
 403                             "invalid length %d or crc\n", count);
 404 #ifdef ERROR_STATISTIC
 405                 bch->err_inv++;
 406 #endif
 407                 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
 408                 bz->f2 = new_f2;        /* next buffer */
 409         } else {
 410                 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
 411                 if (!bch->rx_skb) {
 412                         printk(KERN_WARNING "HFCPCI: receive out of memory\n");
 413                         return;
 414                 }
 415                 total = count;
 416                 count -= 3;
 417                 ptr = skb_put(bch->rx_skb, count);
 418
 419                 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
 420                         maxlen = count;         /* complete transfer */
 421                 else
 422                         maxlen = B_FIFO_SIZE + B_SUB_VAL -
 423                             le16_to_cpu(zp->z2);        /* maximum */
 424
 425                 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
 426                     /* start of data */
 427                 memcpy(ptr, ptr1, maxlen);      /* copy data */
 428                 count -= maxlen;
 429
 430                 if (count) {    /* rest remaining */
 431                         ptr += maxlen;
 432                         ptr1 = bdata;   /* start of buffer */
 433                         memcpy(ptr, ptr1, count);       /* rest */
 434                 }
 435                 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
 436                 bz->f2 = new_f2;        /* next buffer */
 437                 recv_Bchannel(bch);
 438         }
 439 }
 440
 441 /*
 442  * D-channel receive procedure
 443  */
 444 static int
 445 receive_dmsg(struct hfc_pci *hc)
 446 {
 447         struct dchannel *dch = &hc->dch;
 448         int             maxlen;
 449         int             rcnt, total;
 450         int             count = 5;
 451         u_char          *ptr, *ptr1;
 452         struct dfifo    *df;
 453         struct zt       *zp;
 454
 455         df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
 456         while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
 457                 zp = &df->za[df->f2 & D_FREG_MASK];
 458                 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
 459                 if (rcnt < 0)
 460                         rcnt += D_FIFO_SIZE;
 461                 rcnt++;
 462                 if (dch->debug & DEBUG_HW_DCHANNEL)
 463                         printk(KERN_DEBUG
 464                             "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
 465                                 df->f1, df->f2,
 466                                 le16_to_cpu(zp->z1),
 467                                 le16_to_cpu(zp->z2),
 468                                 rcnt);
 469
 470                 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
 471                     (df->data[le16_to_cpu(zp->z1)])) {
 472                         if (dch->debug & DEBUG_HW)
 473                                 printk(KERN_DEBUG
 474                                     "empty_fifo hfcpci paket inv. len "
 475                                     "%d or crc %d\n",
 476                                     rcnt,
 477                                     df->data[le16_to_cpu(zp->z1)]);
 478 #ifdef ERROR_STATISTIC
 479                         cs->err_rx++;
 480 #endif
 481                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
 482                             (MAX_D_FRAMES + 1); /* next buffer */
 483                         df->za[df->f2 & D_FREG_MASK].z2 =
 484                             cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) & (D_FIFO_SIZE - 1));
 485                 } else {
 486                         dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
 487                         if (!dch->rx_skb) {
 488                                 printk(KERN_WARNING
 489                                     "HFC-PCI: D receive out of memory\n");
 490                                 break;
 491                         }
 492                         total = rcnt;
 493                         rcnt -= 3;
 494                         ptr = skb_put(dch->rx_skb, rcnt);
 495
 496                         if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
 497                                 maxlen = rcnt;  /* complete transfer */
 498                         else
 499                                 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
 500                                     /* maximum */
 501
 502                         ptr1 = df->data + le16_to_cpu(zp->z2);
 503                             /* start of data */
 504                         memcpy(ptr, ptr1, maxlen);      /* copy data */
 505                         rcnt -= maxlen;
 506
 507                         if (rcnt) {     /* rest remaining */
 508                                 ptr += maxlen;
 509                                 ptr1 = df->data;        /* start of buffer */
 510                                 memcpy(ptr, ptr1, rcnt);        /* rest */
 511                         }
 512                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
 513                             (MAX_D_FRAMES + 1); /* next buffer */
 514                         df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
 515                             le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
 516                         recv_Dchannel(dch);
 517                 }
 518         }
 519         return 1;
 520 }
 521
 522 /*
 523  * check for transparent receive data and read max one threshold size if avail
 524  */
 525 int
 526 hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *bz, u_char *bdata)
 527 {
 528          __le16 *z1r, *z2r;
 529         int             new_z2, fcnt, maxlen;
 530         u_char          *ptr, *ptr1;
 531
 532         z1r = &bz->za[MAX_B_FRAMES].z1;         /* pointer to z reg */
 533         z2r = z1r + 1;
 534
 535         fcnt = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
 536         if (!fcnt)
 537                 return 0;       /* no data avail */
 538
 539         if (fcnt <= 0)
 540                 fcnt += B_FIFO_SIZE;    /* bytes actually buffered */
 541         if (fcnt > HFCPCI_BTRANS_THRESHOLD)
 542                 fcnt = HFCPCI_BTRANS_THRESHOLD;         /* limit size */
 543
 544         new_z2 = le16_to_cpu(*z2r) + fcnt;      /* new position in fifo */
 545         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
 546                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
 547
 548         bch->rx_skb = mI_alloc_skb(fcnt, GFP_ATOMIC);
 549         if (bch->rx_skb) {
 550                 ptr = skb_put(bch->rx_skb, fcnt);
 551                 if (le16_to_cpu(*z2r) + fcnt <= B_FIFO_SIZE + B_SUB_VAL)
 552                         maxlen = fcnt;  /* complete transfer */
 553                 else
 554                         maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
 555                             /* maximum */
 556
 557                 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
 558                     /* start of data */
 559                 memcpy(ptr, ptr1, maxlen);      /* copy data */
 560                 fcnt -= maxlen;
 561
 562                 if (fcnt) {     /* rest remaining */
 563                         ptr += maxlen;
 564                         ptr1 = bdata;   /* start of buffer */
 565                         memcpy(ptr, ptr1, fcnt);        /* rest */
 566                 }
 567                 recv_Bchannel(bch);
 568         } else
 569                 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
 570
 571         *z2r = cpu_to_le16(new_z2);             /* new position */
 572         return 1;
 573 }
 574
 575 /*
 576  * B-channel main receive routine
 577  */
 578 void
 579 main_rec_hfcpci(struct bchannel *bch)
 580 {
 581         struct hfc_pci  *hc = bch->hw;
 582         int             rcnt, real_fifo;
 583         int             receive, count = 5;
 584         struct bzfifo   *bz;
 585         u_char          *bdata;
 586         struct zt       *zp;
 587
 588
 589         if ((bch->nr & 2) && (!hc->hw.bswapped)) {
 590                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
 591                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
 592                 real_fifo = 1;
 593         } else {
 594                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
 595                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
 596                 real_fifo = 0;
 597         }
 598 Begin:
 599         count--;
 600         if (bz->f1 != bz->f2) {
 601                 if (bch->debug & DEBUG_HW_BCHANNEL)
 602                         printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
 603                             bch->nr, bz->f1, bz->f2);
 604                 zp = &bz->za[bz->f2];
 605
 606                 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
 607                 if (rcnt < 0)
 608                         rcnt += B_FIFO_SIZE;
 609                 rcnt++;
 610                 if (bch->debug & DEBUG_HW_BCHANNEL)
 611                         printk(KERN_DEBUG
 612                             "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
 613                             bch->nr, le16_to_cpu(zp->z1),
 614                             le16_to_cpu(zp->z2), rcnt);
 615                 hfcpci_empty_bfifo(bch, bz, bdata, rcnt);
 616                 rcnt = bz->f1 - bz->f2;
 617                 if (rcnt < 0)
 618                         rcnt += MAX_B_FRAMES + 1;
 619                 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
 620                         rcnt = 0;
 621                         hfcpci_clear_fifo_rx(hc, real_fifo);
 622                 }
 623                 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
 624                 if (rcnt > 1)
 625                         receive = 1;
 626                 else
 627                         receive = 0;
 628         } else if (test_bit(FLG_TRANSPARENT, &bch->Flags))
 629                 receive = hfcpci_empty_fifo_trans(bch, bz, bdata);
 630         else
 631                 receive = 0;
 632         if (count && receive)
 633                 goto Begin;
 634
 635 }
 636
 637 /*
 638  * D-channel send routine
 639  */
 640 static void
 641 hfcpci_fill_dfifo(struct hfc_pci *hc)
 642 {
 643         struct dchannel *dch = &hc->dch;
 644         int             fcnt;
 645         int             count, new_z1, maxlen;
 646         struct dfifo    *df;
 647         u_char          *src, *dst, new_f1;
 648
 649         if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
 650                 printk(KERN_DEBUG "%s\n", __func__);
 651
 652         if (!dch->tx_skb)
 653                 return;
 654         count = dch->tx_skb->len - dch->tx_idx;
 655         if (count <= 0)
 656                 return;
 657         df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
 658
 659         if (dch->debug & DEBUG_HW_DFIFO)
 660                 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
 661                     df->f1, df->f2,
 662                     le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
 663         fcnt = df->f1 - df->f2; /* frame count actually buffered */
 664         if (fcnt < 0)
 665                 fcnt += (MAX_D_FRAMES + 1);     /* if wrap around */
 666         if (fcnt > (MAX_D_FRAMES - 1)) {
 667                 if (dch->debug & DEBUG_HW_DCHANNEL)
 668                         printk(KERN_DEBUG
 669                             "hfcpci_fill_Dfifo more as 14 frames\n");
 670 #ifdef ERROR_STATISTIC
 671                 cs->err_tx++;
 672 #endif
 673                 return;
 674         }
 675         /* now determine free bytes in FIFO buffer */
 676         maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
 677             le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
 678         if (maxlen <= 0)
 679                 maxlen += D_FIFO_SIZE;  /* count now contains available bytes */
 680
 681         if (dch->debug & DEBUG_HW_DCHANNEL)
 682                 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
 683                         count, maxlen);
 684         if (count > maxlen) {
 685                 if (dch->debug & DEBUG_HW_DCHANNEL)
 686                         printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
 687                 return;
 688         }
 689         new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
 690             (D_FIFO_SIZE - 1);
 691         new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
 692         src = dch->tx_skb->data + dch->tx_idx;  /* source pointer */
 693         dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
 694         maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
 695             /* end fifo */
 696         if (maxlen > count)
 697                 maxlen = count; /* limit size */
 698         memcpy(dst, src, maxlen);       /* first copy */
 699
 700         count -= maxlen;        /* remaining bytes */
 701         if (count) {
 702                 dst = df->data; /* start of buffer */
 703                 src += maxlen;  /* new position */
 704                 memcpy(dst, src, count);
 705         }
 706         df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
 707             /* for next buffer */
 708         df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
 709             /* new pos actual buffer */
 710         df->f1 = new_f1;        /* next frame */
 711         dch->tx_idx = dch->tx_skb->len;
 712 }
 713
 714 /*
 715  * B-channel send routine
 716  */
 717 static void
 718 hfcpci_fill_fifo(struct bchannel *bch)
 719 {
 720         struct hfc_pci  *hc = bch->hw;
 721         int             maxlen, fcnt;
 722         int             count, new_z1;
 723         struct bzfifo   *bz;
 724         u_char          *bdata;
 725         u_char          new_f1, *src, *dst;
 726         __le16 *z1t, *z2t;
 727
 728         if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
 729                 printk(KERN_DEBUG "%s\n", __func__);
 730         if ((!bch->tx_skb) || bch->tx_skb->len <= 0)
 731                 return;
 732         count = bch->tx_skb->len - bch->tx_idx;
 733         if ((bch->nr & 2) && (!hc->hw.bswapped)) {
 734                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
 735                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
 736         } else {
 737                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
 738                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
 739         }
 740
 741         if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
 742                 z1t = &bz->za[MAX_B_FRAMES].z1;
 743                 z2t = z1t + 1;
 744                 if (bch->debug & DEBUG_HW_BCHANNEL)
 745                         printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
 746                             "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
 747                             le16_to_cpu(*z1t), le16_to_cpu(*z2t));
 748                 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
 749                 if (fcnt <= 0)
 750                         fcnt += B_FIFO_SIZE;
 751                             /* fcnt contains available bytes in fifo */
 752                 fcnt = B_FIFO_SIZE - fcnt;
 753                     /* remaining bytes to send (bytes in fifo) */
 754 next_t_frame:
 755                 count = bch->tx_skb->len - bch->tx_idx;
 756                 /* maximum fill shall be HFCPCI_BTRANS_MAX */
 757                 if (count > HFCPCI_BTRANS_MAX - fcnt)
 758                         count = HFCPCI_BTRANS_MAX - fcnt;
 759                 if (count <= 0)
 760                         return;
 761                 /* data is suitable for fifo */
 762                 new_z1 = le16_to_cpu(*z1t) + count;
 763                     /* new buffer Position */
 764                 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 765                         new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 766                 src = bch->tx_skb->data + bch->tx_idx;
 767                     /* source pointer */
 768                 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
 769                 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
 770                     /* end of fifo */
 771                 if (bch->debug & DEBUG_HW_BFIFO)
 772                         printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
 773                             "maxl(%d) nz1(%x) dst(%p)\n",
 774                             fcnt, maxlen, new_z1, dst);
 775                 fcnt += count;
 776                 bch->tx_idx += count;
 777                 if (maxlen > count)
 778                         maxlen = count;         /* limit size */
 779                 memcpy(dst, src, maxlen);       /* first copy */
 780                 count -= maxlen;        /* remaining bytes */
 781                 if (count) {
 782                         dst = bdata;    /* start of buffer */
 783                         src += maxlen;  /* new position */
 784                         memcpy(dst, src, count);
 785                 }
 786                 *z1t = cpu_to_le16(new_z1);     /* now send data */
 787                 if (bch->tx_idx < bch->tx_skb->len)
 788                         return;
 789                 /* send confirm, on trans, free on hdlc. */
 790                 if (test_bit(FLG_TRANSPARENT, &bch->Flags))
 791                         confirm_Bsend(bch);
 792                 dev_kfree_skb(bch->tx_skb);
 793                 if (get_next_bframe(bch))
 794                         goto next_t_frame;
 795                 return;
 796         }
 797         if (bch->debug & DEBUG_HW_BCHANNEL)
 798                 printk(KERN_DEBUG
 799                     "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
 800                     __func__, bch->nr, bz->f1, bz->f2,
 801                     bz->za[bz->f1].z1);
 802         fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
 803         if (fcnt < 0)
 804                 fcnt += (MAX_B_FRAMES + 1);     /* if wrap around */
 805         if (fcnt > (MAX_B_FRAMES - 1)) {
 806                 if (bch->debug & DEBUG_HW_BCHANNEL)
 807                         printk(KERN_DEBUG
 808                             "hfcpci_fill_Bfifo more as 14 frames\n");
 809                 return;
 810         }
 811         /* now determine free bytes in FIFO buffer */
 812         maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
 813             le16_to_cpu(bz->za[bz->f1].z1) - 1;
 814         if (maxlen <= 0)
 815                 maxlen += B_FIFO_SIZE;  /* count now contains available bytes */
 816
 817         if (bch->debug & DEBUG_HW_BCHANNEL)
 818                 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
 819                         bch->nr, count, maxlen);
 820
 821         if (maxlen < count) {
 822                 if (bch->debug & DEBUG_HW_BCHANNEL)
 823                         printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
 824                 return;
 825         }
 826         new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
 827             /* new buffer Position */
 828         if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 829                 new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 830
 831         new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
 832         src = bch->tx_skb->data + bch->tx_idx;  /* source pointer */
 833         dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
 834         maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
 835             /* end fifo */
 836         if (maxlen > count)
 837                 maxlen = count; /* limit size */
 838         memcpy(dst, src, maxlen);       /* first copy */
 839
 840         count -= maxlen;        /* remaining bytes */
 841         if (count) {
 842                 dst = bdata;    /* start of buffer */
 843                 src += maxlen;  /* new position */
 844                 memcpy(dst, src, count);
 845         }
 846         bz->za[new_f1].z1 = cpu_to_le16(new_z1);        /* for next buffer */
 847         bz->f1 = new_f1;        /* next frame */
 848         dev_kfree_skb(bch->tx_skb);
 849         get_next_bframe(bch);
 850 }
 851
 852
 853
 854 /*
 855  * handle L1 state changes TE
 856  */
 857
 858 static void
 859 ph_state_te(struct dchannel *dch)
 860 {
 861         if (dch->debug)
 862                 printk(KERN_DEBUG "%s: TE newstate %x\n",
 863                         __func__, dch->state);
 864         switch (dch->state) {
 865         case 0:
 866                 l1_event(dch->l1, HW_RESET_IND);
 867                 break;
 868         case 3:
 869                 l1_event(dch->l1, HW_DEACT_IND);
 870                 break;
 871         case 5:
 872         case 8:
 873                 l1_event(dch->l1, ANYSIGNAL);
 874                 break;
 875         case 6:
 876                 l1_event(dch->l1, INFO2);
 877                 break;
 878         case 7:
 879                 l1_event(dch->l1, INFO4_P8);
 880                 break;
 881         }
 882 }
 883
 884 /*
 885  * handle L1 state changes NT
 886  */
 887
 888 static void
 889 handle_nt_timer3(struct dchannel *dch) {
 890         struct hfc_pci  *hc = dch->hw;
 891
 892         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 893         hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 894         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 895         hc->hw.nt_timer = 0;
 896         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
 897         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
 898                 hc->hw.mst_m |= HFCPCI_MASTER;
 899         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
 900         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
 901             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
 902 }
 903
 904 static void
 905 ph_state_nt(struct dchannel *dch)
 906 {
 907         struct hfc_pci  *hc = dch->hw;
 908
 909         if (dch->debug)
 910                 printk(KERN_DEBUG "%s: NT newstate %x\n",
 911                         __func__, dch->state);
 912         switch (dch->state) {
 913         case 2:
 914                 if (hc->hw.nt_timer < 0) {
 915                         hc->hw.nt_timer = 0;
 916                         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 917                         test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 918                         hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 919                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 920                         /* Clear already pending ints */
 921                         if (Read_hfc(hc, HFCPCI_INT_S1));
 922                         Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
 923                         udelay(10);
 924                         Write_hfc(hc, HFCPCI_STATES, 4);
 925                         dch->state = 4;
 926                 } else if (hc->hw.nt_timer == 0) {
 927                         hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
 928                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 929                         hc->hw.nt_timer = NT_T1_COUNT;
 930                         hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
 931                         hc->hw.ctmt |= HFCPCI_TIM3_125;
 932                         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
 933                                 HFCPCI_CLTIMER);
 934                         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 935                         test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 936                         /* allow G2 -> G3 transition */
 937                         Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
 938                 } else {
 939                         Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
 940                 }
 941                 break;
 942         case 1:
 943                 hc->hw.nt_timer = 0;
 944                 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 945                 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 946                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 947                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 948                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
 949                 hc->hw.mst_m &= ~HFCPCI_MASTER;
 950                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
 951                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
 952                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
 953                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
 954                 break;
 955         case 4:
 956                 hc->hw.nt_timer = 0;
 957                 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 958                 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 959                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 960                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 961                 break;
 962         case 3:
 963                 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
 964                         if (!test_and_clear_bit(FLG_L2_ACTIVATED,
 965                             &dch->Flags)) {
 966                                 handle_nt_timer3(dch);
 967                                 break;
 968                         }
 969                         test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 970                         hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
 971                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 972                         hc->hw.nt_timer = NT_T3_COUNT;
 973                         hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
 974                         hc->hw.ctmt |= HFCPCI_TIM3_125;
 975                         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
 976                                 HFCPCI_CLTIMER);
 977                 }
 978                 break;
 979         }
 980 }
 981
 982 static void
 983 ph_state(struct dchannel *dch)
 984 {
 985         struct hfc_pci  *hc = dch->hw;
 986
 987         if (hc->hw.protocol == ISDN_P_NT_S0) {
 988                 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
 989                     hc->hw.nt_timer < 0)
 990                         handle_nt_timer3(dch);
 991                 else
 992                         ph_state_nt(dch);
 993         } else
 994                 ph_state_te(dch);
 995 }
 996
 997 /*
 998  * Layer 1 callback function
 999  */
1000 static int
1001 hfc_l1callback(struct dchannel *dch, u_int cmd)
1002 {
1003         struct hfc_pci          *hc = dch->hw;
1004
1005         switch (cmd) {
1006         case INFO3_P8:
1007         case INFO3_P10:
1008                 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1009                         hc->hw.mst_m |= HFCPCI_MASTER;
1010                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1011                 break;
1012         case HW_RESET_REQ:
1013                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1014                 /* HFC ST 3 */
1015                 udelay(6);
1016                 Write_hfc(hc, HFCPCI_STATES, 3);        /* HFC ST 2 */
1017                 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1018                         hc->hw.mst_m |= HFCPCI_MASTER;
1019                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1020                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1021                    HFCPCI_DO_ACTION);
1022                 l1_event(dch->l1, HW_POWERUP_IND);
1023                 break;
1024         case HW_DEACT_REQ:
1025                 hc->hw.mst_m &= ~HFCPCI_MASTER;
1026                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1027                 skb_queue_purge(&dch->squeue);
1028                 if (dch->tx_skb) {
1029                         dev_kfree_skb(dch->tx_skb);
1030                         dch->tx_skb = NULL;
1031                 }
1032                 dch->tx_idx = 0;
1033                 if (dch->rx_skb) {
1034                         dev_kfree_skb(dch->rx_skb);
1035                         dch->rx_skb = NULL;
1036                 }
1037                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1038                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1039                         del_timer(&dch->timer);
1040                 break;
1041         case HW_POWERUP_REQ:
1042                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1043                 break;
1044         case PH_ACTIVATE_IND:
1045                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1046                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1047                         GFP_ATOMIC);
1048                 break;
1049         case PH_DEACTIVATE_IND:
1050                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1051                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1052                         GFP_ATOMIC);
1053                 break;
1054         default:
1055                 if (dch->debug & DEBUG_HW)
1056                         printk(KERN_DEBUG "%s: unknown command %x\n",
1057                             __func__, cmd);
1058                 return -1;
1059         }
1060         return 0;
1061 }
1062
1063 /*
1064  * Interrupt handler
1065  */
1066 static inline void
1067 tx_birq(struct bchannel *bch)
1068 {
1069         if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1070                 hfcpci_fill_fifo(bch);
1071         else {
1072                 if (bch->tx_skb)
1073                         dev_kfree_skb(bch->tx_skb);
1074                 if (get_next_bframe(bch))
1075                         hfcpci_fill_fifo(bch);
1076         }
1077 }
1078
1079 static inline void
1080 tx_dirq(struct dchannel *dch)
1081 {
1082         if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1083                 hfcpci_fill_dfifo(dch->hw);
1084         else {
1085                 if (dch->tx_skb)
1086                         dev_kfree_skb(dch->tx_skb);
1087                 if (get_next_dframe(dch))
1088                         hfcpci_fill_dfifo(dch->hw);
1089         }
1090 }
1091
1092 static irqreturn_t
1093 hfcpci_int(int intno, void *dev_id)
1094 {
1095         struct hfc_pci  *hc = dev_id;
1096         u_char          exval;
1097         struct bchannel *bch;
1098         u_char          val, stat;
1099
1100         spin_lock(&hc->lock);
1101         if (!(hc->hw.int_m2 & 0x08)) {
1102                 spin_unlock(&hc->lock);
1103                 return IRQ_NONE; /* not initialised */
1104         }
1105         stat = Read_hfc(hc, HFCPCI_STATUS);
1106         if (HFCPCI_ANYINT & stat) {
1107                 val = Read_hfc(hc, HFCPCI_INT_S1);
1108                 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1109                         printk(KERN_DEBUG
1110                             "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1111         } else {
1112                 /* shared */
1113                 spin_unlock(&hc->lock);
1114                 return IRQ_NONE;
1115         }
1116         hc->irqcnt++;
1117
1118         if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1119                 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1120         val &= hc->hw.int_m1;
1121         if (val & 0x40) {       /* state machine irq */
1122                 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1123                 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1124                         printk(KERN_DEBUG "ph_state chg %d->%d\n",
1125                                 hc->dch.state, exval);
1126                 hc->dch.state = exval;
1127                 schedule_event(&hc->dch, FLG_PHCHANGE);
1128                 val &= ~0x40;
1129         }
1130         if (val & 0x80) {       /* timer irq */
1131                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1132                         if ((--hc->hw.nt_timer) < 0)
1133                                 schedule_event(&hc->dch, FLG_PHCHANGE);
1134                 }
1135                 val &= ~0x80;
1136                 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1137         }
1138         if (val & 0x08) {
1139                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1140                 if (bch)
1141                         main_rec_hfcpci(bch);
1142                 else if (hc->dch.debug)
1143                         printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1144         }
1145         if (val & 0x10) {
1146                 bch = Sel_BCS(hc, 2);
1147                 if (bch)
1148                         main_rec_hfcpci(bch);
1149                 else if (hc->dch.debug)
1150                         printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1151         }
1152         if (val & 0x01) {
1153                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1154                 if (bch)
1155                         tx_birq(bch);
1156                 else if (hc->dch.debug)
1157                         printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1158         }
1159         if (val & 0x02) {
1160                 bch = Sel_BCS(hc, 2);
1161                 if (bch)
1162                         tx_birq(bch);
1163                 else if (hc->dch.debug)
1164                         printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1165         }
1166         if (val & 0x20)
1167                 receive_dmsg(hc);
1168         if (val & 0x04) {       /* dframe transmitted */
1169                 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1170                         del_timer(&hc->dch.timer);
1171                 tx_dirq(&hc->dch);
1172         }
1173         spin_unlock(&hc->lock);
1174         return IRQ_HANDLED;
1175 }
1176
1177 /*
1178  * timer callback for D-chan busy resolution. Currently no function
1179  */
1180 static void
1181 hfcpci_dbusy_timer(struct hfc_pci *hc)
1182 {
1183 }
1184
1185 /*
1186  * activate/deactivate hardware for selected channels and mode
1187  */
1188 static int
1189 mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1190 {
1191         struct hfc_pci  *hc = bch->hw;
1192         int             fifo2;
1193         u_char          rx_slot = 0, tx_slot = 0, pcm_mode;
1194
1195         if (bch->debug & DEBUG_HW_BCHANNEL)
1196                 printk(KERN_DEBUG
1197                     "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1198                     bch->state, protocol, bch->nr, bc);
1199
1200         fifo2 = bc;
1201         pcm_mode = (bc>>24) & 0xff;
1202         if (pcm_mode) { /* PCM SLOT USE */
1203                 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1204                         printk(KERN_WARNING
1205                             "%s: pcm channel id without HFC_CFG_PCM\n",
1206                             __func__);
1207                 rx_slot = (bc>>8) & 0xff;
1208                 tx_slot = (bc>>16) & 0xff;
1209                 bc = bc & 0xff;
1210         } else if (test_bit(HFC_CFG_PCM, &hc->cfg) &&
1211             (protocol > ISDN_P_NONE))
1212                 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1213                     __func__);
1214         if (hc->chanlimit > 1) {
1215                 hc->hw.bswapped = 0;    /* B1 and B2 normal mode */
1216                 hc->hw.sctrl_e &= ~0x80;
1217         } else {
1218                 if (bc & 2) {
1219                         if (protocol != ISDN_P_NONE) {
1220                                 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1221                                 hc->hw.sctrl_e |= 0x80;
1222                         } else {
1223                                 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1224                                 hc->hw.sctrl_e &= ~0x80;
1225                         }
1226                         fifo2 = 1;
1227                 } else {
1228                         hc->hw.bswapped = 0;    /* B1 and B2 normal mode */
1229                         hc->hw.sctrl_e &= ~0x80;
1230                 }
1231         }
1232         switch (protocol) {
1233         case (-1): /* used for init */
1234                 bch->state = -1;
1235                 bch->nr = bc;
1236         case (ISDN_P_NONE):
1237                 if (bch->state == ISDN_P_NONE)
1238                         return 0;
1239                 if (bc & 2) {
1240                         hc->hw.sctrl &= ~SCTRL_B2_ENA;
1241                         hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1242                 } else {
1243                         hc->hw.sctrl &= ~SCTRL_B1_ENA;
1244                         hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1245                 }
1246                 if (fifo2 & 2) {
1247                         hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1248                         hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS +
1249                                 HFCPCI_INTS_B2REC);
1250                 } else {
1251                         hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1252                         hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS +
1253                                 HFCPCI_INTS_B1REC);
1254                 }
1255 #ifdef REVERSE_BITORDER
1256                 if (bch->nr & 2)
1257                         hc->hw.cirm &= 0x7f;
1258                 else
1259                         hc->hw.cirm &= 0xbf;
1260 #endif
1261                 bch->state = ISDN_P_NONE;
1262                 bch->nr = bc;
1263                 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1264                 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1265                 break;
1266         case (ISDN_P_B_RAW):
1267                 bch->state = protocol;
1268                 bch->nr = bc;
1269                 hfcpci_clear_fifo_rx(hc, (fifo2 & 2)?1:0);
1270                 hfcpci_clear_fifo_tx(hc, (fifo2 & 2)?1:0);
1271                 if (bc & 2) {
1272                         hc->hw.sctrl |= SCTRL_B2_ENA;
1273                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1274 #ifdef REVERSE_BITORDER
1275                         hc->hw.cirm |= 0x80;
1276 #endif
1277                 } else {
1278                         hc->hw.sctrl |= SCTRL_B1_ENA;
1279                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1280 #ifdef REVERSE_BITORDER
1281                         hc->hw.cirm |= 0x40;
1282 #endif
1283                 }
1284                 if (fifo2 & 2) {
1285                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1286                         hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1287                             HFCPCI_INTS_B2REC);
1288                         hc->hw.ctmt |= 2;
1289                         hc->hw.conn &= ~0x18;
1290                 } else {
1291                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1292                         hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1293                             HFCPCI_INTS_B1REC);
1294                         hc->hw.ctmt |= 1;
1295                         hc->hw.conn &= ~0x03;
1296                 }
1297                 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1298                 break;
1299         case (ISDN_P_B_HDLC):
1300                 bch->state = protocol;
1301                 bch->nr = bc;
1302                 hfcpci_clear_fifo_rx(hc, (fifo2 & 2)?1:0);
1303                 hfcpci_clear_fifo_tx(hc, (fifo2 & 2)?1:0);
1304                 if (bc & 2) {
1305                         hc->hw.sctrl |= SCTRL_B2_ENA;
1306                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1307                 } else {
1308                         hc->hw.sctrl |= SCTRL_B1_ENA;
1309                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1310                 }
1311                 if (fifo2 & 2) {
1312                         hc->hw.last_bfifo_cnt[1] = 0;
1313                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1314                         hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1315                             HFCPCI_INTS_B2REC);
1316                         hc->hw.ctmt &= ~2;
1317                         hc->hw.conn &= ~0x18;
1318                 } else {
1319                         hc->hw.last_bfifo_cnt[0] = 0;
1320                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1321                         hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1322                             HFCPCI_INTS_B1REC);
1323                         hc->hw.ctmt &= ~1;
1324                         hc->hw.conn &= ~0x03;
1325                 }
1326                 test_and_set_bit(FLG_HDLC, &bch->Flags);
1327                 break;
1328         default:
1329                 printk(KERN_DEBUG "prot not known %x\n", protocol);
1330                 return -ENOPROTOOPT;
1331         }
1332         if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1333                 if ((protocol == ISDN_P_NONE) ||
1334                         (protocol == -1)) {     /* init case */
1335                         rx_slot = 0;
1336                         tx_slot = 0;
1337                 } else {
1338                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1339                                 rx_slot |= 0xC0;
1340                                 tx_slot |= 0xC0;
1341                         } else {
1342                                 rx_slot |= 0x80;
1343                                 tx_slot |= 0x80;
1344                         }
1345                 }
1346                 if (bc & 2) {
1347                         hc->hw.conn &= 0xc7;
1348                         hc->hw.conn |= 0x08;
1349                         printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1350                                 __func__, tx_slot);
1351                         printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1352                                 __func__, rx_slot);
1353                         Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1354                         Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1355                 } else {
1356                         hc->hw.conn &= 0xf8;
1357                         hc->hw.conn |= 0x01;
1358                         printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1359                                 __func__, tx_slot);
1360                         printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1361                                 __func__, rx_slot);
1362                         Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1363                         Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1364                 }
1365         }
1366         Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1367         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1368         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1369         Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1370         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1371         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1372         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1373 #ifdef REVERSE_BITORDER
1374         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1375 #endif
1376         return 0;
1377 }
1378
1379 static int
1380 set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1381 {
1382         struct hfc_pci  *hc = bch->hw;
1383
1384         if (bch->debug & DEBUG_HW_BCHANNEL)
1385                 printk(KERN_DEBUG
1386                     "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1387                     bch->state, protocol, bch->nr, chan);
1388         if (bch->nr != chan) {
1389                 printk(KERN_DEBUG
1390                     "HFCPCI rxtest wrong channel parameter %x/%x\n",
1391                     bch->nr, chan);
1392                 return -EINVAL;
1393         }
1394         switch (protocol) {
1395         case (ISDN_P_B_RAW):
1396                 bch->state = protocol;
1397                 hfcpci_clear_fifo_rx(hc, (chan & 2)?1:0);
1398                 if (chan & 2) {
1399                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1400                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1401                         hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1402                         hc->hw.ctmt |= 2;
1403                         hc->hw.conn &= ~0x18;
1404 #ifdef REVERSE_BITORDER
1405                         hc->hw.cirm |= 0x80;
1406 #endif
1407                 } else {
1408                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1409                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1410                         hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1411                         hc->hw.ctmt |= 1;
1412                         hc->hw.conn &= ~0x03;
1413 #ifdef REVERSE_BITORDER
1414                         hc->hw.cirm |= 0x40;
1415 #endif
1416                 }
1417                 break;
1418         case (ISDN_P_B_HDLC):
1419                 bch->state = protocol;
1420                 hfcpci_clear_fifo_rx(hc, (chan & 2)?1:0);
1421                 if (chan & 2) {
1422                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1423                         hc->hw.last_bfifo_cnt[1] = 0;
1424                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1425                         hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1426                         hc->hw.ctmt &= ~2;
1427                         hc->hw.conn &= ~0x18;
1428                 } else {
1429                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1430                         hc->hw.last_bfifo_cnt[0] = 0;
1431                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1432                         hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1433                         hc->hw.ctmt &= ~1;
1434                         hc->hw.conn &= ~0x03;
1435                 }
1436                 break;
1437         default:
1438                 printk(KERN_DEBUG "prot not known %x\n", protocol);
1439                 return -ENOPROTOOPT;
1440         }
1441         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1442         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1443         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1444         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1445         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1446 #ifdef REVERSE_BITORDER
1447         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1448 #endif
1449         return 0;
1450 }
1451
1452 static void
1453 deactivate_bchannel(struct bchannel *bch)
1454 {
1455         struct hfc_pci  *hc = bch->hw;
1456         u_long          flags;
1457
1458         spin_lock_irqsave(&hc->lock, flags);
1459         if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
1460                 dev_kfree_skb(bch->next_skb);
1461                 bch->next_skb = NULL;
1462         }
1463         if (bch->tx_skb) {
1464                 dev_kfree_skb(bch->tx_skb);
1465                 bch->tx_skb = NULL;
1466         }
1467         bch->tx_idx = 0;
1468         if (bch->rx_skb) {
1469                 dev_kfree_skb(bch->rx_skb);
1470                 bch->rx_skb = NULL;
1471         }
1472         mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1473         test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
1474         test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
1475         spin_unlock_irqrestore(&hc->lock, flags);
1476 }
1477
1478 /*
1479  * Layer 1 B-channel hardware access
1480  */
1481 static int
1482 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1483 {
1484         int                     ret = 0;
1485
1486         switch (cq->op) {
1487         case MISDN_CTRL_GETOP:
1488                 cq->op = 0;
1489                 break;
1490         default:
1491                 printk(KERN_WARNING "%s: unknown Op %x\n", __func__, cq->op);
1492                 ret = -EINVAL;
1493                 break;
1494         }
1495         return ret;
1496 }
1497 static int
1498 hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1499 {
1500         struct bchannel *bch = container_of(ch, struct bchannel, ch);
1501         struct hfc_pci  *hc = bch->hw;
1502         int             ret = -EINVAL;
1503         u_long          flags;
1504
1505         if (bch->debug & DEBUG_HW)
1506                 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1507         switch (cmd) {
1508         case HW_TESTRX_RAW:
1509                 spin_lock_irqsave(&hc->lock, flags);
1510                 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1511                 spin_unlock_irqrestore(&hc->lock, flags);
1512                 break;
1513         case HW_TESTRX_HDLC:
1514                 spin_lock_irqsave(&hc->lock, flags);
1515                 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1516                 spin_unlock_irqrestore(&hc->lock, flags);
1517                 break;
1518         case HW_TESTRX_OFF:
1519                 spin_lock_irqsave(&hc->lock, flags);
1520                 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1521                 spin_unlock_irqrestore(&hc->lock, flags);
1522                 ret = 0;
1523                 break;
1524         case CLOSE_CHANNEL:
1525                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1526                 if (test_bit(FLG_ACTIVE, &bch->Flags))
1527                         deactivate_bchannel(bch);
1528                 ch->protocol = ISDN_P_NONE;
1529                 ch->peer = NULL;
1530                 module_put(THIS_MODULE);
1531                 ret = 0;
1532                 break;
1533         case CONTROL_CHANNEL:
1534                 ret = channel_bctrl(bch, arg);
1535                 break;
1536         default:
1537                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1538                         __func__, cmd);
1539         }
1540         return ret;
1541 }
1542
1543 /*
1544  * Layer2 -> Layer 1 Dchannel data
1545  */
1546 static int
1547 hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1548 {
1549         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
1550         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
1551         struct hfc_pci          *hc = dch->hw;
1552         int                     ret = -EINVAL;
1553         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
1554         unsigned int            id;
1555         u_long                  flags;
1556
1557         switch (hh->prim) {
1558         case PH_DATA_REQ:
1559                 spin_lock_irqsave(&hc->lock, flags);
1560                 ret = dchannel_senddata(dch, skb);
1561                 if (ret > 0) { /* direct TX */
1562                         id = hh->id; /* skb can be freed */
1563                         hfcpci_fill_dfifo(dch->hw);
1564                         ret = 0;
1565                         spin_unlock_irqrestore(&hc->lock, flags);
1566                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1567                 } else
1568                         spin_unlock_irqrestore(&hc->lock, flags);
1569                 return ret;
1570         case PH_ACTIVATE_REQ:
1571                 spin_lock_irqsave(&hc->lock, flags);
1572                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1573                         ret = 0;
1574                         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1575                                 hc->hw.mst_m |= HFCPCI_MASTER;
1576                         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1577                         if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1578                                 spin_unlock_irqrestore(&hc->lock, flags);
1579                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1580                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1581                                 break;
1582                         }
1583                         test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1584                         Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1585                             HFCPCI_DO_ACTION | 1);
1586                 } else
1587                         ret = l1_event(dch->l1, hh->prim);
1588                 spin_unlock_irqrestore(&hc->lock, flags);
1589                 break;
1590         case PH_DEACTIVATE_REQ:
1591                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1592                 spin_lock_irqsave(&hc->lock, flags);
1593                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1594                         /* prepare deactivation */
1595                         Write_hfc(hc, HFCPCI_STATES, 0x40);
1596                         skb_queue_purge(&dch->squeue);
1597                         if (dch->tx_skb) {
1598                                 dev_kfree_skb(dch->tx_skb);
1599                                 dch->tx_skb = NULL;
1600                         }
1601                         dch->tx_idx = 0;
1602                         if (dch->rx_skb) {
1603                                 dev_kfree_skb(dch->rx_skb);
1604                                 dch->rx_skb = NULL;
1605                         }
1606                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1607                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1608                                 del_timer(&dch->timer);
1609 #ifdef FIXME
1610                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1611                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1612 #endif
1613                         hc->hw.mst_m &= ~HFCPCI_MASTER;
1614                         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1615                         ret = 0;
1616                 } else {
1617                         ret = l1_event(dch->l1, hh->prim);
1618                 }
1619                 spin_unlock_irqrestore(&hc->lock, flags);
1620                 break;
1621         }
1622         if (!ret)
1623                 dev_kfree_skb(skb);
1624         return ret;
1625 }
1626
1627 /*
1628  * Layer2 -> Layer 1 Bchannel data
1629  */
1630 static int
1631 hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1632 {
1633         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
1634         struct hfc_pci          *hc = bch->hw;
1635         int                     ret = -EINVAL;
1636         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
1637         unsigned int            id;
1638         u_long                  flags;
1639
1640         switch (hh->prim) {
1641         case PH_DATA_REQ:
1642                 spin_lock_irqsave(&hc->lock, flags);
1643                 ret = bchannel_senddata(bch, skb);
1644                 if (ret > 0) { /* direct TX */
1645                         id = hh->id; /* skb can be freed */
1646                         hfcpci_fill_fifo(bch);
1647                         ret = 0;
1648                         spin_unlock_irqrestore(&hc->lock, flags);
1649                         if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1650                                 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1651                 } else
1652                         spin_unlock_irqrestore(&hc->lock, flags);
1653                 return ret;
1654         case PH_ACTIVATE_REQ:
1655                 spin_lock_irqsave(&hc->lock, flags);
1656                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1657                         ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1658                 else
1659                         ret = 0;
1660                 spin_unlock_irqrestore(&hc->lock, flags);
1661                 if (!ret)
1662                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1663                                 NULL, GFP_KERNEL);
1664                 break;
1665         case PH_DEACTIVATE_REQ:
1666                 deactivate_bchannel(bch);
1667                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1668                         NULL, GFP_KERNEL);
1669                 ret = 0;
1670                 break;
1671         }
1672         if (!ret)
1673                 dev_kfree_skb(skb);
1674         return ret;
1675 }
1676
1677 /*
1678  * called for card init message
1679  */
1680
1681 void
1682 inithfcpci(struct hfc_pci *hc)
1683 {
1684         printk(KERN_DEBUG "inithfcpci: entered\n");
1685         hc->dch.timer.function = (void *) hfcpci_dbusy_timer;
1686         hc->dch.timer.data = (long) &hc->dch;
1687         init_timer(&hc->dch.timer);
1688         hc->chanlimit = 2;
1689         mode_hfcpci(&hc->bch[0], 1, -1);
1690         mode_hfcpci(&hc->bch[1], 2, -1);
1691 }
1692
1693
1694 static int
1695 init_card(struct hfc_pci *hc)
1696 {
1697         int     cnt = 3;
1698         u_long  flags;
1699
1700         printk(KERN_DEBUG "init_card: entered\n");
1701
1702
1703         spin_lock_irqsave(&hc->lock, flags);
1704         disable_hwirq(hc);
1705         spin_unlock_irqrestore(&hc->lock, flags);
1706         if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1707                 printk(KERN_WARNING
1708                     "mISDN: couldn't get interrupt %d\n", hc->irq);
1709                 return -EIO;
1710         }
1711         spin_lock_irqsave(&hc->lock, flags);
1712         reset_hfcpci(hc);
1713         while (cnt) {
1714                 inithfcpci(hc);
1715                 /*
1716                  * Finally enable IRQ output
1717                  * this is only allowed, if an IRQ routine is allready
1718                  * established for this HFC, so don't do that earlier
1719                  */
1720                 enable_hwirq(hc);
1721                 spin_unlock_irqrestore(&hc->lock, flags);
1722                 /* Timeout 80ms */
1723                 current->state = TASK_UNINTERRUPTIBLE;
1724                 schedule_timeout((80*HZ)/1000);
1725                 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1726                         hc->irq, hc->irqcnt);
1727                 /* now switch timer interrupt off */
1728                 spin_lock_irqsave(&hc->lock, flags);
1729                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1730                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1731                 /* reinit mode reg */
1732                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1733                 if (!hc->irqcnt) {
1734                         printk(KERN_WARNING
1735                             "HFC PCI: IRQ(%d) getting no interrupts "
1736                             "during init %d\n", hc->irq, 4 - cnt);
1737                         if (cnt == 1) {
1738                                 spin_unlock_irqrestore(&hc->lock, flags);
1739                                 return -EIO;
1740                         } else {
1741                                 reset_hfcpci(hc);
1742                                 cnt--;
1743                         }
1744                 } else {
1745                         spin_unlock_irqrestore(&hc->lock, flags);
1746                         hc->initdone = 1;
1747                         return 0;
1748                 }
1749         }
1750         disable_hwirq(hc);
1751         spin_unlock_irqrestore(&hc->lock, flags);
1752         free_irq(hc->irq, hc);
1753         return -EIO;
1754 }
1755
1756 static int
1757 channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1758 {
1759         int     ret = 0;
1760         u_char  slot;
1761
1762         switch (cq->op) {
1763         case MISDN_CTRL_GETOP:
1764                 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1765                     MISDN_CTRL_DISCONNECT;
1766                 break;
1767         case MISDN_CTRL_LOOP:
1768                 /* channel 0 disabled loop */
1769                 if (cq->channel < 0 || cq->channel > 2) {
1770                         ret = -EINVAL;
1771                         break;
1772                 }
1773                 if (cq->channel & 1) {
1774                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1775                                 slot = 0xC0;
1776                         else
1777                                 slot = 0x80;
1778                         printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1779                             __func__, slot);
1780                         Write_hfc(hc, HFCPCI_B1_SSL, slot);
1781                         Write_hfc(hc, HFCPCI_B1_RSL, slot);
1782                         hc->hw.conn = (hc->hw.conn & ~7) | 6;
1783                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1784                 }
1785                 if (cq->channel & 2) {
1786                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1787                                 slot = 0xC1;
1788                         else
1789                                 slot = 0x81;
1790                         printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1791                             __func__, slot);
1792                         Write_hfc(hc, HFCPCI_B2_SSL, slot);
1793                         Write_hfc(hc, HFCPCI_B2_RSL, slot);
1794                         hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1795                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1796                 }
1797                 if (cq->channel & 3)
1798                         hc->hw.trm |= 0x80;     /* enable IOM-loop */
1799                 else {
1800                         hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1801                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1802                         hc->hw.trm &= 0x7f;     /* disable IOM-loop */
1803                 }
1804                 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1805                 break;
1806         case MISDN_CTRL_CONNECT:
1807                 if (cq->channel == cq->p1) {
1808                         ret = -EINVAL;
1809                         break;
1810                 }
1811                 if (cq->channel < 1 || cq->channel > 2 ||
1812                     cq->p1 < 1 || cq->p1 > 2) {
1813                         ret = -EINVAL;
1814                         break;
1815                 }
1816                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1817                         slot = 0xC0;
1818                 else
1819                         slot = 0x80;
1820                 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1821                     __func__, slot);
1822                 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1823                 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1824                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1825                         slot = 0xC1;
1826                 else
1827                         slot = 0x81;
1828                 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1829                     __func__, slot);
1830                 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1831                 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1832                 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1833                 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1834                 hc->hw.trm |= 0x80;
1835                 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1836                 break;
1837         case MISDN_CTRL_DISCONNECT:
1838                 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1839                 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1840                 hc->hw.trm &= 0x7f;     /* disable IOM-loop */
1841                 break;
1842         default:
1843                 printk(KERN_WARNING "%s: unknown Op %x\n",
1844                     __func__, cq->op);
1845                 ret = -EINVAL;
1846                 break;
1847         }
1848         return ret;
1849 }
1850
1851 static int
1852 open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1853     struct channel_req *rq)
1854 {
1855         int err = 0;
1856
1857         if (debug & DEBUG_HW_OPEN)
1858                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1859                     hc->dch.dev.id, __builtin_return_address(0));
1860         if (rq->protocol == ISDN_P_NONE)
1861                 return -EINVAL;
1862         if (!hc->initdone) {
1863                 if (rq->protocol == ISDN_P_TE_S0) {
1864                         err = create_l1(&hc->dch, hfc_l1callback);
1865                         if (err)
1866                                 return err;
1867                 }
1868                 hc->hw.protocol = rq->protocol;
1869                 ch->protocol = rq->protocol;
1870                 err = init_card(hc);
1871                 if (err)
1872                         return err;
1873         } else {
1874                 if (rq->protocol != ch->protocol) {
1875                         if (hc->hw.protocol == ISDN_P_TE_S0)
1876                                 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1877                         hc->hw.protocol = rq->protocol;
1878                         ch->protocol = rq->protocol;
1879                         hfcpci_setmode(hc);
1880                 }
1881         }
1882
1883         if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1884             ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1885                 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1886                     0, NULL, GFP_KERNEL);
1887         }
1888         rq->ch = ch;
1889         if (!try_module_get(THIS_MODULE))
1890                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1891         return 0;
1892 }
1893
1894 static int
1895 open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1896 {
1897         struct bchannel         *bch;
1898
1899         if (rq->adr.channel > 2)
1900                 return -EINVAL;
1901         if (rq->protocol == ISDN_P_NONE)
1902                 return -EINVAL;
1903         bch = &hc->bch[rq->adr.channel - 1];
1904         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1905                 return -EBUSY; /* b-channel can be only open once */
1906         bch->ch.protocol = rq->protocol;
1907         rq->ch = &bch->ch; /* TODO: E-channel */
1908         if (!try_module_get(THIS_MODULE))
1909                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1910         return 0;
1911 }
1912
1913 /*
1914  * device control function
1915  */
1916 static int
1917 hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1918 {
1919         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
1920         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
1921         struct hfc_pci          *hc = dch->hw;
1922         struct channel_req      *rq;
1923         int                     err = 0;
1924
1925         if (dch->debug & DEBUG_HW)
1926                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
1927                     __func__, cmd, arg);
1928         switch (cmd) {
1929         case OPEN_CHANNEL:
1930                 rq = arg;
1931                 if (rq->adr.channel == 0)
1932                         err = open_dchannel(hc, ch, rq);
1933                 else
1934                         err = open_bchannel(hc, rq);
1935                 break;
1936         case CLOSE_CHANNEL:
1937                 if (debug & DEBUG_HW_OPEN)
1938                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
1939                             __func__, hc->dch.dev.id,
1940                             __builtin_return_address(0));
1941                 module_put(THIS_MODULE);
1942                 break;
1943         case CONTROL_CHANNEL:
1944                 err = channel_ctrl(hc, arg);
1945                 break;
1946         default:
1947                 if (dch->debug & DEBUG_HW)
1948                         printk(KERN_DEBUG "%s: unknown command %x\n",
1949                             __func__, cmd);
1950                 return -EINVAL;
1951         }
1952         return err;
1953 }
1954
1955 static int
1956 setup_hw(struct hfc_pci *hc)
1957 {
1958         void    *buffer;
1959
1960         printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
1961         hc->hw.cirm = 0;
1962         hc->dch.state = 0;
1963         pci_set_master(hc->pdev);
1964         if (!hc->irq) {
1965                 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
1966                 return 1;
1967         }
1968         hc->hw.pci_io = (char *)(ulong)hc->pdev->resource[1].start;
1969
1970         if (!hc->hw.pci_io) {
1971                 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
1972                 return 1;
1973         }
1974         /* Allocate memory for FIFOS */
1975         /* the memory needs to be on a 32k boundary within the first 4G */
1976         pci_set_dma_mask(hc->pdev, 0xFFFF8000);
1977         buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
1978         /* We silently assume the address is okay if nonzero */
1979         if (!buffer) {
1980                 printk(KERN_WARNING
1981                     "HFC-PCI: Error allocating memory for FIFO!\n");
1982                 return 1;
1983         }
1984         hc->hw.fifos = buffer;
1985         pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
1986         hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
1987         printk(KERN_INFO
1988                 "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
1989                 (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos,
1990                 (u_long) hc->hw.dmahandle, hc->irq, HZ);
1991         /* enable memory mapped ports, disable busmaster */
1992         pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
1993         hc->hw.int_m2 = 0;
1994         disable_hwirq(hc);
1995         hc->hw.int_m1 = 0;
1996         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1997         /* At this point the needed PCI config is done */
1998         /* fifos are still not enabled */
1999         hc->hw.timer.function = (void *) hfcpci_Timer;
2000         hc->hw.timer.data = (long) hc;
2001         init_timer(&hc->hw.timer);
2002         /* default PCM master */
2003         test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2004         return 0;
2005 }
2006
2007 static void
2008 release_card(struct hfc_pci *hc) {
2009         u_long  flags;
2010
2011         spin_lock_irqsave(&hc->lock, flags);
2012         hc->hw.int_m2 = 0; /* interrupt output off ! */
2013         disable_hwirq(hc);
2014         mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2015         mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2016         if (hc->dch.timer.function != NULL) {
2017                 del_timer(&hc->dch.timer);
2018                 hc->dch.timer.function = NULL;
2019         }
2020         spin_unlock_irqrestore(&hc->lock, flags);
2021         if (hc->hw.protocol == ISDN_P_TE_S0)
2022                 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2023         if (hc->initdone)
2024                 free_irq(hc->irq, hc);
2025         release_io_hfcpci(hc); /* must release after free_irq! */
2026         mISDN_unregister_device(&hc->dch.dev);
2027         mISDN_freebchannel(&hc->bch[1]);
2028         mISDN_freebchannel(&hc->bch[0]);
2029         mISDN_freedchannel(&hc->dch);
2030         list_del(&hc->list);
2031         pci_set_drvdata(hc->pdev, NULL);
2032         kfree(hc);
2033 }
2034
2035 static int
2036 setup_card(struct hfc_pci *card)
2037 {
2038         int             err = -EINVAL;
2039         u_int           i;
2040         u_long          flags;
2041         char            name[MISDN_MAX_IDLEN];
2042
2043         if (HFC_cnt >= MAX_CARDS)
2044                 return -EINVAL; /* maybe better value */
2045
2046         card->dch.debug = debug;
2047         spin_lock_init(&card->lock);
2048         mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2049         card->dch.hw = card;
2050         card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2051         card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2052             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2053         card->dch.dev.D.send = hfcpci_l2l1D;
2054         card->dch.dev.D.ctrl = hfc_dctrl;
2055         card->dch.dev.nrbchan = 2;
2056         for (i = 0; i < 2; i++) {
2057                 card->bch[i].nr = i + 1;
2058                 set_channelmap(i + 1, card->dch.dev.channelmap);
2059                 card->bch[i].debug = debug;
2060                 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM);
2061                 card->bch[i].hw = card;
2062                 card->bch[i].ch.send = hfcpci_l2l1B;
2063                 card->bch[i].ch.ctrl = hfc_bctrl;
2064                 card->bch[i].ch.nr = i + 1;
2065                 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2066         }
2067         err = setup_hw(card);
2068         if (err)
2069                 goto error;
2070         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
2071         err = mISDN_register_device(&card->dch.dev, name);
2072         if (err)
2073                 goto error;
2074         HFC_cnt++;
2075         write_lock_irqsave(&HFClock, flags);
2076         list_add_tail(&card->list, &HFClist);
2077         write_unlock_irqrestore(&HFClock, flags);
2078         printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2079         return 0;
2080 error:
2081         mISDN_freebchannel(&card->bch[1]);
2082         mISDN_freebchannel(&card->bch[0]);
2083         mISDN_freedchannel(&card->dch);
2084         kfree(card);
2085         return err;
2086 }
2087
2088 /* private data in the PCI devices list */
2089 struct _hfc_map {
2090         u_int   subtype;
2091         u_int   flag;
2092         char    *name;
2093 };
2094
2095 static const struct _hfc_map hfc_map[] =
2096 {
2097         {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2098         {HFC_CCD_B000, 0, "Billion B000"},
2099         {HFC_CCD_B006, 0, "Billion B006"},
2100         {HFC_CCD_B007, 0, "Billion B007"},
2101         {HFC_CCD_B008, 0, "Billion B008"},
2102         {HFC_CCD_B009, 0, "Billion B009"},
2103         {HFC_CCD_B00A, 0, "Billion B00A"},
2104         {HFC_CCD_B00B, 0, "Billion B00B"},
2105         {HFC_CCD_B00C, 0, "Billion B00C"},
2106         {HFC_CCD_B100, 0, "Seyeon B100"},
2107         {HFC_CCD_B700, 0, "Primux II S0 B700"},
2108         {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2109         {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2110         {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2111         {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2112         {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2113         {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2114         {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2115         {HFC_DIGI_DF_M_IOM2_E, 0,
2116             "Digi International DataFire Micro V IOM2 (Europe)"},
2117         {HFC_DIGI_DF_M_E, 0,
2118             "Digi International DataFire Micro V (Europe)"},
2119         {HFC_DIGI_DF_M_IOM2_A, 0,
2120             "Digi International DataFire Micro V IOM2 (North America)"},
2121         {HFC_DIGI_DF_M_A, 0,
2122             "Digi International DataFire Micro V (North America)"},
2123         {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2124         {},
2125 };
2126
2127 static struct pci_device_id hfc_ids[] =
2128 {
2129         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_2BD0,
2130                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[0]},
2131         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B000,
2132                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[1]},
2133         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B006,
2134                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[2]},
2135         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B007,
2136                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[3]},
2137         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B008,
2138                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[4]},
2139         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B009,
2140                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[5]},
2141         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00A,
2142                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[6]},
2143         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00B,
2144                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[7]},
2145         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00C,
2146                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[8]},
2147         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B100,
2148                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[9]},
2149         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B700,
2150                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[10]},
2151         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B701,
2152                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[11]},
2153         {PCI_VENDOR_ID_ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1,
2154                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[12]},
2155         {PCI_VENDOR_ID_ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675,
2156                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[13]},
2157         {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT,
2158                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[14]},
2159         {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T,
2160                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[15]},
2161         {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575,
2162                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[16]},
2163         {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0,
2164                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[17]},
2165         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,
2166                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[18]},
2167         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,
2168                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[19]},
2169         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,
2170                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[20]},
2171         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,
2172                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[21]},
2173         {PCI_VENDOR_ID_SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2,
2174                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[22]},
2175         {},
2176 };
2177
2178 static int __devinit
2179 hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2180 {
2181         int             err = -ENOMEM;
2182         struct hfc_pci  *card;
2183         struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2184
2185         card = kzalloc(sizeof(struct hfc_pci), GFP_ATOMIC);
2186         if (!card) {
2187                 printk(KERN_ERR "No kmem for HFC card\n");
2188                 return err;
2189         }
2190         card->pdev = pdev;
2191         card->subtype = m->subtype;
2192         err = pci_enable_device(pdev);
2193         if (err) {
2194                 kfree(card);
2195                 return err;
2196         }
2197
2198         printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2199                m->name, pci_name(pdev));
2200
2201         card->irq = pdev->irq;
2202         pci_set_drvdata(pdev, card);
2203         err = setup_card(card);
2204         if (err)
2205                 pci_set_drvdata(pdev, NULL);
2206         return err;
2207 }
2208
2209 static void __devexit
2210 hfc_remove_pci(struct pci_dev *pdev)
2211 {
2212         struct hfc_pci  *card = pci_get_drvdata(pdev);
2213         u_long          flags;
2214
2215         if (card) {
2216                 write_lock_irqsave(&HFClock, flags);
2217                 release_card(card);
2218                 write_unlock_irqrestore(&HFClock, flags);
2219         } else
2220                 if (debug)
2221                         printk(KERN_WARNING "%s: drvdata allready removed\n",
2222                             __func__);
2223 }
2224
2225
2226 static struct pci_driver hfc_driver = {
2227         .name = "hfcpci",
2228         .probe = hfc_probe,
2229         .remove = __devexit_p(hfc_remove_pci),
2230         .id_table = hfc_ids,
2231 };
2232
2233 static int __init
2234 HFC_init(void)
2235 {
2236         int             err;
2237
2238         err = pci_register_driver(&hfc_driver);
2239         return err;
2240 }
2241
2242 static void __exit
2243 HFC_cleanup(void)
2244 {
2245         struct hfc_pci  *card, *next;
2246
2247         list_for_each_entry_safe(card, next, &HFClist, list) {
2248                 release_card(card);
2249         }
2250         pci_unregister_driver(&hfc_driver);
2251 }
2252
2253 module_init(HFC_init);
2254 module_exit(HFC_cleanup);