2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__FUNCTION__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work = 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit = 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
98 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
99 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
100 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
101 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
102 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
103 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
104 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
105 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
106 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
107 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
108 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
111 #define _R(NAME,MAC,MASK) \
112 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
114 static const struct {
117 u32 RxConfigMask; /* Clears the bits supported by this chip */
118 } rtl_chip_info[] = {
119 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
120 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
121 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
122 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
123 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
124 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
125 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
126 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
127 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
128 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
129 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
130 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
131 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
132 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
133 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
134 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
144 static void rtl_hw_start_8169(struct net_device *);
145 static void rtl_hw_start_8168(struct net_device *);
146 static void rtl_hw_start_8101(struct net_device *);
148 static struct pci_device_id rtl8169_pci_tbl[] = {
149 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
150 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
151 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
152 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
153 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
154 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
155 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
156 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
157 { PCI_VENDOR_ID_LINKSYS, 0x1032,
158 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
160 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
164 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
166 static int rx_copybreak = 200;
173 MAC0 = 0, /* Ethernet hardware address. */
175 MAR0 = 8, /* Multicast filter. */
176 CounterAddrLow = 0x10,
177 CounterAddrHigh = 0x14,
178 TxDescStartAddrLow = 0x20,
179 TxDescStartAddrHigh = 0x24,
180 TxHDescStartAddrLow = 0x28,
181 TxHDescStartAddrHigh = 0x2c,
204 RxDescAddrLow = 0xe4,
205 RxDescAddrHigh = 0xe8,
208 FuncEventMask = 0xf4,
209 FuncPresetState = 0xf8,
210 FuncForceEvent = 0xfc,
213 enum rtl8110_registers {
219 enum rtl8168_8101_registers {
222 #define CSIAR_FLAG 0x80000000
223 #define CSIAR_WRITE_CMD 0x80000000
224 #define CSIAR_BYTE_ENABLE 0x0f
225 #define CSIAR_BYTE_ENABLE_SHIFT 12
226 #define CSIAR_ADDR_MASK 0x0fff
229 #define EPHYAR_FLAG 0x80000000
230 #define EPHYAR_WRITE_CMD 0x80000000
231 #define EPHYAR_REG_MASK 0x1f
232 #define EPHYAR_REG_SHIFT 16
233 #define EPHYAR_DATA_MASK 0xffff
235 #define FIX_NAK_1 (1 << 4)
236 #define FIX_NAK_2 (1 << 3)
239 enum rtl_register_content {
240 /* InterruptStatusBits */
244 TxDescUnavail = 0x0080,
266 /* TXPoll register p.5 */
267 HPQ = 0x80, /* Poll cmd on the high prio queue */
268 NPQ = 0x40, /* Poll cmd on the low prio queue */
269 FSWInt = 0x01, /* Forced software interrupt */
273 Cfg9346_Unlock = 0xc0,
278 AcceptBroadcast = 0x08,
279 AcceptMulticast = 0x04,
281 AcceptAllPhys = 0x01,
288 TxInterFrameGapShift = 24,
289 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
291 /* Config1 register p.24 */
294 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
295 Speed_down = (1 << 4),
299 PMEnable = (1 << 0), /* Power Management Enable */
301 /* Config2 register p. 25 */
302 PCI_Clock_66MHz = 0x01,
303 PCI_Clock_33MHz = 0x00,
305 /* Config3 register p.25 */
306 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
307 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
308 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
310 /* Config5 register p.27 */
311 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
312 MWF = (1 << 5), /* Accept Multicast wakeup frame */
313 UWF = (1 << 4), /* Accept Unicast wakeup frame */
314 LanWake = (1 << 1), /* LanWake enable/disable */
315 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
318 TBIReset = 0x80000000,
319 TBILoopback = 0x40000000,
320 TBINwEnable = 0x20000000,
321 TBINwRestart = 0x10000000,
322 TBILinkOk = 0x02000000,
323 TBINwComplete = 0x01000000,
326 EnableBist = (1 << 15), // 8168 8101
327 Mac_dbgo_oe = (1 << 14), // 8168 8101
328 Normal_mode = (1 << 13), // unused
329 Force_half_dup = (1 << 12), // 8168 8101
330 Force_rxflow_en = (1 << 11), // 8168 8101
331 Force_txflow_en = (1 << 10), // 8168 8101
332 Cxpl_dbg_sel = (1 << 9), // 8168 8101
333 ASF = (1 << 8), // 8168 8101
334 PktCntrDisable = (1 << 7), // 8168 8101
335 Mac_dbgo_sel = 0x001c, // 8168
340 INTT_0 = 0x0000, // 8168
341 INTT_1 = 0x0001, // 8168
342 INTT_2 = 0x0002, // 8168
343 INTT_3 = 0x0003, // 8168
345 /* rtl8169_PHYstatus */
356 TBILinkOK = 0x02000000,
358 /* DumpCounterCommand */
362 enum desc_status_bit {
363 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
364 RingEnd = (1 << 30), /* End of descriptor ring */
365 FirstFrag = (1 << 29), /* First segment of a packet */
366 LastFrag = (1 << 28), /* Final segment of a packet */
369 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
370 MSSShift = 16, /* MSS value position */
371 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
372 IPCS = (1 << 18), /* Calculate IP checksum */
373 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
374 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
375 TxVlanTag = (1 << 17), /* Add VLAN tag */
378 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
379 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
381 #define RxProtoUDP (PID1)
382 #define RxProtoTCP (PID0)
383 #define RxProtoIP (PID1 | PID0)
384 #define RxProtoMask RxProtoIP
386 IPFail = (1 << 16), /* IP checksum failed */
387 UDPFail = (1 << 15), /* UDP/IP checksum failed */
388 TCPFail = (1 << 14), /* TCP/IP checksum failed */
389 RxVlanTag = (1 << 16), /* VLAN tag available */
392 #define RsvdMask 0x3fffc000
409 u8 __pad[sizeof(void *) - sizeof(u32)];
413 RTL_FEATURE_WOL = (1 << 0),
414 RTL_FEATURE_MSI = (1 << 1),
415 RTL_FEATURE_GMII = (1 << 2),
418 struct rtl8169_private {
419 void __iomem *mmio_addr; /* memory map physical address */
420 struct pci_dev *pci_dev; /* Index of PCI device */
421 struct net_device *dev;
422 struct napi_struct napi;
423 spinlock_t lock; /* spin lock flag */
427 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
428 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
431 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
432 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
433 dma_addr_t TxPhyAddr;
434 dma_addr_t RxPhyAddr;
435 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
436 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
439 struct timer_list timer;
444 int phy_auto_nego_reg;
445 int phy_1000_ctrl_reg;
446 #ifdef CONFIG_R8169_VLAN
447 struct vlan_group *vlgrp;
449 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
450 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
451 void (*phy_reset_enable)(void __iomem *);
452 void (*hw_start)(struct net_device *);
453 unsigned int (*phy_reset_pending)(void __iomem *);
454 unsigned int (*link_ok)(void __iomem *);
456 struct delayed_work task;
459 struct mii_if_info mii;
462 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
463 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
464 module_param(rx_copybreak, int, 0);
465 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
466 module_param(use_dac, int, 0);
467 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
468 module_param_named(debug, debug.msg_enable, int, 0);
469 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
470 MODULE_LICENSE("GPL");
471 MODULE_VERSION(RTL8169_VERSION);
473 static int rtl8169_open(struct net_device *dev);
474 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
475 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
476 static int rtl8169_init_ring(struct net_device *dev);
477 static void rtl_hw_start(struct net_device *dev);
478 static int rtl8169_close(struct net_device *dev);
479 static void rtl_set_rx_mode(struct net_device *dev);
480 static void rtl8169_tx_timeout(struct net_device *dev);
481 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
482 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
483 void __iomem *, u32 budget);
484 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
485 static void rtl8169_down(struct net_device *dev);
486 static void rtl8169_rx_clear(struct rtl8169_private *tp);
487 static int rtl8169_poll(struct napi_struct *napi, int budget);
489 static const unsigned int rtl8169_rx_config =
490 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
492 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
496 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
498 for (i = 20; i > 0; i--) {
500 * Check if the RTL8169 has completed writing to the specified
503 if (!(RTL_R32(PHYAR) & 0x80000000))
509 static int mdio_read(void __iomem *ioaddr, int reg_addr)
513 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
515 for (i = 20; i > 0; i--) {
517 * Check if the RTL8169 has completed retrieving data from
518 * the specified MII register.
520 if (RTL_R32(PHYAR) & 0x80000000) {
521 value = RTL_R32(PHYAR) & 0xffff;
529 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
532 struct rtl8169_private *tp = netdev_priv(dev);
533 void __iomem *ioaddr = tp->mmio_addr;
535 mdio_write(ioaddr, location, val);
538 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
540 struct rtl8169_private *tp = netdev_priv(dev);
541 void __iomem *ioaddr = tp->mmio_addr;
543 return mdio_read(ioaddr, location);
546 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
548 RTL_W16(IntrMask, 0x0000);
550 RTL_W16(IntrStatus, 0xffff);
553 static void rtl8169_asic_down(void __iomem *ioaddr)
555 RTL_W8(ChipCmd, 0x00);
556 rtl8169_irq_mask_and_ack(ioaddr);
560 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
562 return RTL_R32(TBICSR) & TBIReset;
565 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
567 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
570 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
572 return RTL_R32(TBICSR) & TBILinkOk;
575 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
577 return RTL_R8(PHYstatus) & LinkStatus;
580 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
582 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
585 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
589 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
590 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
593 static void rtl8169_check_link_status(struct net_device *dev,
594 struct rtl8169_private *tp,
595 void __iomem *ioaddr)
599 spin_lock_irqsave(&tp->lock, flags);
600 if (tp->link_ok(ioaddr)) {
601 netif_carrier_on(dev);
602 if (netif_msg_ifup(tp))
603 printk(KERN_INFO PFX "%s: link up\n", dev->name);
605 if (netif_msg_ifdown(tp))
606 printk(KERN_INFO PFX "%s: link down\n", dev->name);
607 netif_carrier_off(dev);
609 spin_unlock_irqrestore(&tp->lock, flags);
612 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
614 struct rtl8169_private *tp = netdev_priv(dev);
615 void __iomem *ioaddr = tp->mmio_addr;
620 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
621 wol->supported = WAKE_ANY;
623 spin_lock_irq(&tp->lock);
625 options = RTL_R8(Config1);
626 if (!(options & PMEnable))
629 options = RTL_R8(Config3);
630 if (options & LinkUp)
631 wol->wolopts |= WAKE_PHY;
632 if (options & MagicPacket)
633 wol->wolopts |= WAKE_MAGIC;
635 options = RTL_R8(Config5);
637 wol->wolopts |= WAKE_UCAST;
639 wol->wolopts |= WAKE_BCAST;
641 wol->wolopts |= WAKE_MCAST;
644 spin_unlock_irq(&tp->lock);
647 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
649 struct rtl8169_private *tp = netdev_priv(dev);
650 void __iomem *ioaddr = tp->mmio_addr;
657 { WAKE_ANY, Config1, PMEnable },
658 { WAKE_PHY, Config3, LinkUp },
659 { WAKE_MAGIC, Config3, MagicPacket },
660 { WAKE_UCAST, Config5, UWF },
661 { WAKE_BCAST, Config5, BWF },
662 { WAKE_MCAST, Config5, MWF },
663 { WAKE_ANY, Config5, LanWake }
666 spin_lock_irq(&tp->lock);
668 RTL_W8(Cfg9346, Cfg9346_Unlock);
670 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
671 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
672 if (wol->wolopts & cfg[i].opt)
673 options |= cfg[i].mask;
674 RTL_W8(cfg[i].reg, options);
677 RTL_W8(Cfg9346, Cfg9346_Lock);
680 tp->features |= RTL_FEATURE_WOL;
682 tp->features &= ~RTL_FEATURE_WOL;
684 spin_unlock_irq(&tp->lock);
689 static void rtl8169_get_drvinfo(struct net_device *dev,
690 struct ethtool_drvinfo *info)
692 struct rtl8169_private *tp = netdev_priv(dev);
694 strcpy(info->driver, MODULENAME);
695 strcpy(info->version, RTL8169_VERSION);
696 strcpy(info->bus_info, pci_name(tp->pci_dev));
699 static int rtl8169_get_regs_len(struct net_device *dev)
701 return R8169_REGS_SIZE;
704 static int rtl8169_set_speed_tbi(struct net_device *dev,
705 u8 autoneg, u16 speed, u8 duplex)
707 struct rtl8169_private *tp = netdev_priv(dev);
708 void __iomem *ioaddr = tp->mmio_addr;
712 reg = RTL_R32(TBICSR);
713 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
714 (duplex == DUPLEX_FULL)) {
715 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
716 } else if (autoneg == AUTONEG_ENABLE)
717 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
719 if (netif_msg_link(tp)) {
720 printk(KERN_WARNING "%s: "
721 "incorrect speed setting refused in TBI mode\n",
730 static int rtl8169_set_speed_xmii(struct net_device *dev,
731 u8 autoneg, u16 speed, u8 duplex)
733 struct rtl8169_private *tp = netdev_priv(dev);
734 void __iomem *ioaddr = tp->mmio_addr;
735 int auto_nego, giga_ctrl;
737 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
738 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
739 ADVERTISE_100HALF | ADVERTISE_100FULL);
740 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
741 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
743 if (autoneg == AUTONEG_ENABLE) {
744 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
745 ADVERTISE_100HALF | ADVERTISE_100FULL);
746 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
748 if (speed == SPEED_10)
749 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
750 else if (speed == SPEED_100)
751 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
752 else if (speed == SPEED_1000)
753 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
755 if (duplex == DUPLEX_HALF)
756 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
758 if (duplex == DUPLEX_FULL)
759 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
761 /* This tweak comes straight from Realtek's driver. */
762 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
763 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
764 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
765 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
769 /* The 8100e/8101e do Fast Ethernet only. */
770 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
771 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
772 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
773 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
774 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
775 netif_msg_link(tp)) {
776 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
779 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
782 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
784 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
785 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
786 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
787 mdio_write(ioaddr, 0x1f, 0x0000);
788 mdio_write(ioaddr, 0x0e, 0x0000);
791 tp->phy_auto_nego_reg = auto_nego;
792 tp->phy_1000_ctrl_reg = giga_ctrl;
794 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
795 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
796 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
800 static int rtl8169_set_speed(struct net_device *dev,
801 u8 autoneg, u16 speed, u8 duplex)
803 struct rtl8169_private *tp = netdev_priv(dev);
806 ret = tp->set_speed(dev, autoneg, speed, duplex);
808 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
809 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
814 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
816 struct rtl8169_private *tp = netdev_priv(dev);
820 spin_lock_irqsave(&tp->lock, flags);
821 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
822 spin_unlock_irqrestore(&tp->lock, flags);
827 static u32 rtl8169_get_rx_csum(struct net_device *dev)
829 struct rtl8169_private *tp = netdev_priv(dev);
831 return tp->cp_cmd & RxChkSum;
834 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
836 struct rtl8169_private *tp = netdev_priv(dev);
837 void __iomem *ioaddr = tp->mmio_addr;
840 spin_lock_irqsave(&tp->lock, flags);
843 tp->cp_cmd |= RxChkSum;
845 tp->cp_cmd &= ~RxChkSum;
847 RTL_W16(CPlusCmd, tp->cp_cmd);
850 spin_unlock_irqrestore(&tp->lock, flags);
855 #ifdef CONFIG_R8169_VLAN
857 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
860 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
861 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
864 static void rtl8169_vlan_rx_register(struct net_device *dev,
865 struct vlan_group *grp)
867 struct rtl8169_private *tp = netdev_priv(dev);
868 void __iomem *ioaddr = tp->mmio_addr;
871 spin_lock_irqsave(&tp->lock, flags);
874 tp->cp_cmd |= RxVlan;
876 tp->cp_cmd &= ~RxVlan;
877 RTL_W16(CPlusCmd, tp->cp_cmd);
879 spin_unlock_irqrestore(&tp->lock, flags);
882 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
885 u32 opts2 = le32_to_cpu(desc->opts2);
886 struct vlan_group *vlgrp = tp->vlgrp;
889 if (vlgrp && (opts2 & RxVlanTag)) {
890 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
898 #else /* !CONFIG_R8169_VLAN */
900 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
906 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
914 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
916 struct rtl8169_private *tp = netdev_priv(dev);
917 void __iomem *ioaddr = tp->mmio_addr;
921 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
922 cmd->port = PORT_FIBRE;
923 cmd->transceiver = XCVR_INTERNAL;
925 status = RTL_R32(TBICSR);
926 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
927 cmd->autoneg = !!(status & TBINwEnable);
929 cmd->speed = SPEED_1000;
930 cmd->duplex = DUPLEX_FULL; /* Always set */
935 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
937 struct rtl8169_private *tp = netdev_priv(dev);
939 return mii_ethtool_gset(&tp->mii, cmd);
942 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
944 struct rtl8169_private *tp = netdev_priv(dev);
948 spin_lock_irqsave(&tp->lock, flags);
950 rc = tp->get_settings(dev, cmd);
952 spin_unlock_irqrestore(&tp->lock, flags);
956 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
959 struct rtl8169_private *tp = netdev_priv(dev);
962 if (regs->len > R8169_REGS_SIZE)
963 regs->len = R8169_REGS_SIZE;
965 spin_lock_irqsave(&tp->lock, flags);
966 memcpy_fromio(p, tp->mmio_addr, regs->len);
967 spin_unlock_irqrestore(&tp->lock, flags);
970 static u32 rtl8169_get_msglevel(struct net_device *dev)
972 struct rtl8169_private *tp = netdev_priv(dev);
974 return tp->msg_enable;
977 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
979 struct rtl8169_private *tp = netdev_priv(dev);
981 tp->msg_enable = value;
984 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
991 "tx_single_collisions",
992 "tx_multi_collisions",
1000 struct rtl8169_counters {
1006 __le16 align_errors;
1007 __le32 tx_one_collision;
1008 __le32 tx_multi_collision;
1010 __le64 rx_broadcast;
1011 __le32 rx_multicast;
1016 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1020 return ARRAY_SIZE(rtl8169_gstrings);
1026 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1027 struct ethtool_stats *stats, u64 *data)
1029 struct rtl8169_private *tp = netdev_priv(dev);
1030 void __iomem *ioaddr = tp->mmio_addr;
1031 struct rtl8169_counters *counters;
1037 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1041 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1042 cmd = (u64)paddr & DMA_32BIT_MASK;
1043 RTL_W32(CounterAddrLow, cmd);
1044 RTL_W32(CounterAddrLow, cmd | CounterDump);
1046 while (RTL_R32(CounterAddrLow) & CounterDump) {
1047 if (msleep_interruptible(1))
1051 RTL_W32(CounterAddrLow, 0);
1052 RTL_W32(CounterAddrHigh, 0);
1054 data[0] = le64_to_cpu(counters->tx_packets);
1055 data[1] = le64_to_cpu(counters->rx_packets);
1056 data[2] = le64_to_cpu(counters->tx_errors);
1057 data[3] = le32_to_cpu(counters->rx_errors);
1058 data[4] = le16_to_cpu(counters->rx_missed);
1059 data[5] = le16_to_cpu(counters->align_errors);
1060 data[6] = le32_to_cpu(counters->tx_one_collision);
1061 data[7] = le32_to_cpu(counters->tx_multi_collision);
1062 data[8] = le64_to_cpu(counters->rx_unicast);
1063 data[9] = le64_to_cpu(counters->rx_broadcast);
1064 data[10] = le32_to_cpu(counters->rx_multicast);
1065 data[11] = le16_to_cpu(counters->tx_aborted);
1066 data[12] = le16_to_cpu(counters->tx_underun);
1068 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1071 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1075 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1080 static const struct ethtool_ops rtl8169_ethtool_ops = {
1081 .get_drvinfo = rtl8169_get_drvinfo,
1082 .get_regs_len = rtl8169_get_regs_len,
1083 .get_link = ethtool_op_get_link,
1084 .get_settings = rtl8169_get_settings,
1085 .set_settings = rtl8169_set_settings,
1086 .get_msglevel = rtl8169_get_msglevel,
1087 .set_msglevel = rtl8169_set_msglevel,
1088 .get_rx_csum = rtl8169_get_rx_csum,
1089 .set_rx_csum = rtl8169_set_rx_csum,
1090 .set_tx_csum = ethtool_op_set_tx_csum,
1091 .set_sg = ethtool_op_set_sg,
1092 .set_tso = ethtool_op_set_tso,
1093 .get_regs = rtl8169_get_regs,
1094 .get_wol = rtl8169_get_wol,
1095 .set_wol = rtl8169_set_wol,
1096 .get_strings = rtl8169_get_strings,
1097 .get_sset_count = rtl8169_get_sset_count,
1098 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1101 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1102 int bitnum, int bitval)
1106 val = mdio_read(ioaddr, reg);
1107 val = (bitval == 1) ?
1108 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1109 mdio_write(ioaddr, reg, val & 0xffff);
1112 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1113 void __iomem *ioaddr)
1116 * The driver currently handles the 8168Bf and the 8168Be identically
1117 * but they can be identified more specifically through the test below
1120 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1122 * Same thing for the 8101Eb and the 8101Ec:
1124 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1132 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1133 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1134 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1135 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1138 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1139 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1140 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1141 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1144 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1145 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1146 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1147 /* FIXME: where did these entries come from ? -- FR */
1148 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1149 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1152 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1153 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1154 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1155 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1156 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1157 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1159 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1163 reg = RTL_R32(TxConfig);
1164 while ((reg & p->mask) != p->val)
1166 tp->mac_version = p->mac_version;
1168 if (p->mask == 0x00000000) {
1169 struct pci_dev *pdev = tp->pci_dev;
1171 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1175 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1177 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1185 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1188 mdio_write(ioaddr, regs->reg, regs->val);
1193 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1196 u16 regs[5]; /* Beware of bit-sign propagation */
1197 } phy_magic[5] = { {
1198 { 0x0000, //w 4 15 12 0
1199 0x00a1, //w 3 15 0 00a1
1200 0x0008, //w 2 15 0 0008
1201 0x1020, //w 1 15 0 1020
1202 0x1000 } },{ //w 0 15 0 1000
1203 { 0x7000, //w 4 15 12 7
1204 0xff41, //w 3 15 0 ff41
1205 0xde60, //w 2 15 0 de60
1206 0x0140, //w 1 15 0 0140
1207 0x0077 } },{ //w 0 15 0 0077
1208 { 0xa000, //w 4 15 12 a
1209 0xdf01, //w 3 15 0 df01
1210 0xdf20, //w 2 15 0 df20
1211 0xff95, //w 1 15 0 ff95
1212 0xfa00 } },{ //w 0 15 0 fa00
1213 { 0xb000, //w 4 15 12 b
1214 0xff41, //w 3 15 0 ff41
1215 0xde20, //w 2 15 0 de20
1216 0x0140, //w 1 15 0 0140
1217 0x00bb } },{ //w 0 15 0 00bb
1218 { 0xf000, //w 4 15 12 f
1219 0xdf01, //w 3 15 0 df01
1220 0xdf20, //w 2 15 0 df20
1221 0xff95, //w 1 15 0 ff95
1222 0xbf00 } //w 0 15 0 bf00
1227 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1228 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1229 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1230 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1232 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1235 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1236 mdio_write(ioaddr, pos, val);
1238 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1239 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1240 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1242 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1245 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1247 struct phy_reg phy_reg_init[] = {
1253 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1256 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1258 struct phy_reg phy_reg_init[] = {
1266 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1269 static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1271 struct phy_reg phy_reg_init[] = {
1288 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1291 static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1293 struct phy_reg phy_reg_init[] = {
1304 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1307 static void rtl_hw_phy_config(struct net_device *dev)
1309 struct rtl8169_private *tp = netdev_priv(dev);
1310 void __iomem *ioaddr = tp->mmio_addr;
1312 rtl8169_print_mac_version(tp);
1314 switch (tp->mac_version) {
1315 case RTL_GIGA_MAC_VER_01:
1317 case RTL_GIGA_MAC_VER_02:
1318 case RTL_GIGA_MAC_VER_03:
1319 rtl8169s_hw_phy_config(ioaddr);
1321 case RTL_GIGA_MAC_VER_04:
1322 rtl8169sb_hw_phy_config(ioaddr);
1324 case RTL_GIGA_MAC_VER_18:
1325 rtl8168cp_hw_phy_config(ioaddr);
1327 case RTL_GIGA_MAC_VER_19:
1328 rtl8168c_hw_phy_config(ioaddr);
1330 case RTL_GIGA_MAC_VER_20:
1331 rtl8168cx_hw_phy_config(ioaddr);
1338 static void rtl8169_phy_timer(unsigned long __opaque)
1340 struct net_device *dev = (struct net_device *)__opaque;
1341 struct rtl8169_private *tp = netdev_priv(dev);
1342 struct timer_list *timer = &tp->timer;
1343 void __iomem *ioaddr = tp->mmio_addr;
1344 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1346 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1348 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1351 spin_lock_irq(&tp->lock);
1353 if (tp->phy_reset_pending(ioaddr)) {
1355 * A busy loop could burn quite a few cycles on nowadays CPU.
1356 * Let's delay the execution of the timer for a few ticks.
1362 if (tp->link_ok(ioaddr))
1365 if (netif_msg_link(tp))
1366 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1368 tp->phy_reset_enable(ioaddr);
1371 mod_timer(timer, jiffies + timeout);
1373 spin_unlock_irq(&tp->lock);
1376 static inline void rtl8169_delete_timer(struct net_device *dev)
1378 struct rtl8169_private *tp = netdev_priv(dev);
1379 struct timer_list *timer = &tp->timer;
1381 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1384 del_timer_sync(timer);
1387 static inline void rtl8169_request_timer(struct net_device *dev)
1389 struct rtl8169_private *tp = netdev_priv(dev);
1390 struct timer_list *timer = &tp->timer;
1392 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1395 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1398 #ifdef CONFIG_NET_POLL_CONTROLLER
1400 * Polling 'interrupt' - used by things like netconsole to send skbs
1401 * without having to re-enable interrupts. It's not called while
1402 * the interrupt routine is executing.
1404 static void rtl8169_netpoll(struct net_device *dev)
1406 struct rtl8169_private *tp = netdev_priv(dev);
1407 struct pci_dev *pdev = tp->pci_dev;
1409 disable_irq(pdev->irq);
1410 rtl8169_interrupt(pdev->irq, dev);
1411 enable_irq(pdev->irq);
1415 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1416 void __iomem *ioaddr)
1419 pci_release_regions(pdev);
1420 pci_disable_device(pdev);
1424 static void rtl8169_phy_reset(struct net_device *dev,
1425 struct rtl8169_private *tp)
1427 void __iomem *ioaddr = tp->mmio_addr;
1430 tp->phy_reset_enable(ioaddr);
1431 for (i = 0; i < 100; i++) {
1432 if (!tp->phy_reset_pending(ioaddr))
1436 if (netif_msg_link(tp))
1437 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1440 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1442 void __iomem *ioaddr = tp->mmio_addr;
1444 rtl_hw_phy_config(dev);
1446 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1447 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1451 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1453 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1454 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1456 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1457 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1459 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1460 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1463 rtl8169_phy_reset(dev, tp);
1466 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1467 * only 8101. Don't panic.
1469 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1471 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1472 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1475 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1477 void __iomem *ioaddr = tp->mmio_addr;
1481 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1482 high = addr[4] | (addr[5] << 8);
1484 spin_lock_irq(&tp->lock);
1486 RTL_W8(Cfg9346, Cfg9346_Unlock);
1488 RTL_W32(MAC4, high);
1489 RTL_W8(Cfg9346, Cfg9346_Lock);
1491 spin_unlock_irq(&tp->lock);
1494 static int rtl_set_mac_address(struct net_device *dev, void *p)
1496 struct rtl8169_private *tp = netdev_priv(dev);
1497 struct sockaddr *addr = p;
1499 if (!is_valid_ether_addr(addr->sa_data))
1500 return -EADDRNOTAVAIL;
1502 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1504 rtl_rar_set(tp, dev->dev_addr);
1509 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1511 struct rtl8169_private *tp = netdev_priv(dev);
1512 struct mii_ioctl_data *data = if_mii(ifr);
1514 if (!netif_running(dev))
1519 data->phy_id = 32; /* Internal PHY */
1523 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1527 if (!capable(CAP_NET_ADMIN))
1529 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1535 static const struct rtl_cfg_info {
1536 void (*hw_start)(struct net_device *);
1537 unsigned int region;
1542 } rtl_cfg_infos [] = {
1544 .hw_start = rtl_hw_start_8169,
1547 .intr_event = SYSErr | LinkChg | RxOverflow |
1548 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1549 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1550 .features = RTL_FEATURE_GMII
1553 .hw_start = rtl_hw_start_8168,
1556 .intr_event = SYSErr | LinkChg | RxOverflow |
1557 TxErr | TxOK | RxOK | RxErr,
1558 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1559 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1562 .hw_start = rtl_hw_start_8101,
1565 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1566 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1567 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1568 .features = RTL_FEATURE_MSI
1572 /* Cfg9346_Unlock assumed. */
1573 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1574 const struct rtl_cfg_info *cfg)
1579 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1580 if (cfg->features & RTL_FEATURE_MSI) {
1581 if (pci_enable_msi(pdev)) {
1582 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1585 msi = RTL_FEATURE_MSI;
1588 RTL_W8(Config2, cfg2);
1592 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1594 if (tp->features & RTL_FEATURE_MSI) {
1595 pci_disable_msi(pdev);
1596 tp->features &= ~RTL_FEATURE_MSI;
1600 static int __devinit
1601 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1603 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1604 const unsigned int region = cfg->region;
1605 struct rtl8169_private *tp;
1606 struct mii_if_info *mii;
1607 struct net_device *dev;
1608 void __iomem *ioaddr;
1612 if (netif_msg_drv(&debug)) {
1613 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1614 MODULENAME, RTL8169_VERSION);
1617 dev = alloc_etherdev(sizeof (*tp));
1619 if (netif_msg_drv(&debug))
1620 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1625 SET_NETDEV_DEV(dev, &pdev->dev);
1626 tp = netdev_priv(dev);
1629 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1633 mii->mdio_read = rtl_mdio_read;
1634 mii->mdio_write = rtl_mdio_write;
1635 mii->phy_id_mask = 0x1f;
1636 mii->reg_num_mask = 0x1f;
1637 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1639 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1640 rc = pci_enable_device(pdev);
1642 if (netif_msg_probe(tp))
1643 dev_err(&pdev->dev, "enable failure\n");
1644 goto err_out_free_dev_1;
1647 rc = pci_set_mwi(pdev);
1649 goto err_out_disable_2;
1651 /* make sure PCI base addr 1 is MMIO */
1652 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1653 if (netif_msg_probe(tp)) {
1655 "region #%d not an MMIO resource, aborting\n",
1662 /* check for weird/broken PCI region reporting */
1663 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1664 if (netif_msg_probe(tp)) {
1666 "Invalid PCI region size(s), aborting\n");
1672 rc = pci_request_regions(pdev, MODULENAME);
1674 if (netif_msg_probe(tp))
1675 dev_err(&pdev->dev, "could not request regions.\n");
1679 tp->cp_cmd = PCIMulRW | RxChkSum;
1681 if ((sizeof(dma_addr_t) > 4) &&
1682 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1683 tp->cp_cmd |= PCIDAC;
1684 dev->features |= NETIF_F_HIGHDMA;
1686 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1688 if (netif_msg_probe(tp)) {
1690 "DMA configuration failed.\n");
1692 goto err_out_free_res_4;
1696 pci_set_master(pdev);
1698 /* ioremap MMIO region */
1699 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1701 if (netif_msg_probe(tp))
1702 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1704 goto err_out_free_res_4;
1707 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1708 if (!tp->pcie_cap && netif_msg_probe(tp))
1709 dev_info(&pdev->dev, "no PCI Express capability\n");
1711 /* Unneeded ? Don't mess with Mrs. Murphy. */
1712 rtl8169_irq_mask_and_ack(ioaddr);
1714 /* Soft reset the chip. */
1715 RTL_W8(ChipCmd, CmdReset);
1717 /* Check that the chip has finished the reset. */
1718 for (i = 0; i < 100; i++) {
1719 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1721 msleep_interruptible(1);
1724 /* Identify chip attached to board */
1725 rtl8169_get_mac_version(tp, ioaddr);
1727 rtl8169_print_mac_version(tp);
1729 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1730 if (tp->mac_version == rtl_chip_info[i].mac_version)
1733 if (i == ARRAY_SIZE(rtl_chip_info)) {
1734 /* Unknown chip: assume array element #0, original RTL-8169 */
1735 if (netif_msg_probe(tp)) {
1736 dev_printk(KERN_DEBUG, &pdev->dev,
1737 "unknown chip version, assuming %s\n",
1738 rtl_chip_info[0].name);
1744 RTL_W8(Cfg9346, Cfg9346_Unlock);
1745 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1746 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1747 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1748 RTL_W8(Cfg9346, Cfg9346_Lock);
1750 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1751 (RTL_R8(PHYstatus) & TBI_Enable)) {
1752 tp->set_speed = rtl8169_set_speed_tbi;
1753 tp->get_settings = rtl8169_gset_tbi;
1754 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1755 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1756 tp->link_ok = rtl8169_tbi_link_ok;
1758 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1760 tp->set_speed = rtl8169_set_speed_xmii;
1761 tp->get_settings = rtl8169_gset_xmii;
1762 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1763 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1764 tp->link_ok = rtl8169_xmii_link_ok;
1766 dev->do_ioctl = rtl8169_ioctl;
1769 /* Get MAC address. FIXME: read EEPROM */
1770 for (i = 0; i < MAC_ADDR_LEN; i++)
1771 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1772 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1774 dev->open = rtl8169_open;
1775 dev->hard_start_xmit = rtl8169_start_xmit;
1776 dev->get_stats = rtl8169_get_stats;
1777 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1778 dev->stop = rtl8169_close;
1779 dev->tx_timeout = rtl8169_tx_timeout;
1780 dev->set_multicast_list = rtl_set_rx_mode;
1781 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1782 dev->irq = pdev->irq;
1783 dev->base_addr = (unsigned long) ioaddr;
1784 dev->change_mtu = rtl8169_change_mtu;
1785 dev->set_mac_address = rtl_set_mac_address;
1787 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1789 #ifdef CONFIG_R8169_VLAN
1790 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1791 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1794 #ifdef CONFIG_NET_POLL_CONTROLLER
1795 dev->poll_controller = rtl8169_netpoll;
1798 tp->intr_mask = 0xffff;
1799 tp->mmio_addr = ioaddr;
1800 tp->align = cfg->align;
1801 tp->hw_start = cfg->hw_start;
1802 tp->intr_event = cfg->intr_event;
1803 tp->napi_event = cfg->napi_event;
1805 init_timer(&tp->timer);
1806 tp->timer.data = (unsigned long) dev;
1807 tp->timer.function = rtl8169_phy_timer;
1809 spin_lock_init(&tp->lock);
1811 rc = register_netdev(dev);
1815 pci_set_drvdata(pdev, dev);
1817 if (netif_msg_probe(tp)) {
1818 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1820 printk(KERN_INFO "%s: %s at 0x%lx, "
1821 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1822 "XID %08x IRQ %d\n",
1824 rtl_chip_info[tp->chipset].name,
1826 dev->dev_addr[0], dev->dev_addr[1],
1827 dev->dev_addr[2], dev->dev_addr[3],
1828 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1831 rtl8169_init_phy(dev, tp);
1837 rtl_disable_msi(pdev, tp);
1840 pci_release_regions(pdev);
1842 pci_clear_mwi(pdev);
1844 pci_disable_device(pdev);
1850 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1852 struct net_device *dev = pci_get_drvdata(pdev);
1853 struct rtl8169_private *tp = netdev_priv(dev);
1855 flush_scheduled_work();
1857 unregister_netdev(dev);
1858 rtl_disable_msi(pdev, tp);
1859 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1860 pci_set_drvdata(pdev, NULL);
1863 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1864 struct net_device *dev)
1866 unsigned int mtu = dev->mtu;
1868 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1871 static int rtl8169_open(struct net_device *dev)
1873 struct rtl8169_private *tp = netdev_priv(dev);
1874 struct pci_dev *pdev = tp->pci_dev;
1875 int retval = -ENOMEM;
1878 rtl8169_set_rxbufsize(tp, dev);
1881 * Rx and Tx desscriptors needs 256 bytes alignment.
1882 * pci_alloc_consistent provides more.
1884 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1886 if (!tp->TxDescArray)
1889 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1891 if (!tp->RxDescArray)
1894 retval = rtl8169_init_ring(dev);
1898 INIT_DELAYED_WORK(&tp->task, NULL);
1902 retval = request_irq(dev->irq, rtl8169_interrupt,
1903 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
1906 goto err_release_ring_2;
1908 napi_enable(&tp->napi);
1912 rtl8169_request_timer(dev);
1914 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1919 rtl8169_rx_clear(tp);
1921 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1924 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1929 static void rtl8169_hw_reset(void __iomem *ioaddr)
1931 /* Disable interrupts */
1932 rtl8169_irq_mask_and_ack(ioaddr);
1934 /* Reset the chipset */
1935 RTL_W8(ChipCmd, CmdReset);
1941 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1943 void __iomem *ioaddr = tp->mmio_addr;
1944 u32 cfg = rtl8169_rx_config;
1946 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1947 RTL_W32(RxConfig, cfg);
1949 /* Set DMA burst size and Interframe Gap Time */
1950 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1951 (InterFrameGap << TxInterFrameGapShift));
1954 static void rtl_hw_start(struct net_device *dev)
1956 struct rtl8169_private *tp = netdev_priv(dev);
1957 void __iomem *ioaddr = tp->mmio_addr;
1960 /* Soft reset the chip. */
1961 RTL_W8(ChipCmd, CmdReset);
1963 /* Check that the chip has finished the reset. */
1964 for (i = 0; i < 100; i++) {
1965 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1967 msleep_interruptible(1);
1972 netif_start_queue(dev);
1976 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1977 void __iomem *ioaddr)
1980 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1981 * register to be written before TxDescAddrLow to work.
1982 * Switching from MMIO to I/O access fixes the issue as well.
1984 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1985 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1986 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1987 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1990 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1994 cmd = RTL_R16(CPlusCmd);
1995 RTL_W16(CPlusCmd, cmd);
1999 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2001 /* Low hurts. Let's disable the filtering. */
2002 RTL_W16(RxMaxSize, 16383);
2005 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2012 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2013 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2014 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2015 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2020 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2021 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2022 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2023 RTL_W32(0x7c, p->val);
2029 static void rtl_hw_start_8169(struct net_device *dev)
2031 struct rtl8169_private *tp = netdev_priv(dev);
2032 void __iomem *ioaddr = tp->mmio_addr;
2033 struct pci_dev *pdev = tp->pci_dev;
2035 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2036 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2037 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2040 RTL_W8(Cfg9346, Cfg9346_Unlock);
2041 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2042 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2043 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2044 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2045 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2047 RTL_W8(EarlyTxThres, EarlyTxThld);
2049 rtl_set_rx_max_size(ioaddr);
2051 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2052 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2053 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2054 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2055 rtl_set_rx_tx_config_registers(tp);
2057 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2059 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2060 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2061 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2062 "Bit-3 and bit-14 MUST be 1\n");
2063 tp->cp_cmd |= (1 << 14);
2066 RTL_W16(CPlusCmd, tp->cp_cmd);
2068 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2071 * Undocumented corner. Supposedly:
2072 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2074 RTL_W16(IntrMitigate, 0x0000);
2076 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2078 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2079 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2080 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2081 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2082 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2083 rtl_set_rx_tx_config_registers(tp);
2086 RTL_W8(Cfg9346, Cfg9346_Lock);
2088 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2091 RTL_W32(RxMissed, 0);
2093 rtl_set_rx_mode(dev);
2095 /* no early-rx interrupts */
2096 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2098 /* Enable all known interrupts by setting the interrupt mask. */
2099 RTL_W16(IntrMask, tp->intr_event);
2102 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2104 struct net_device *dev = pci_get_drvdata(pdev);
2105 struct rtl8169_private *tp = netdev_priv(dev);
2106 int cap = tp->pcie_cap;
2111 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2112 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2113 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2117 static void rtl_hw_start_8168(struct net_device *dev)
2119 struct rtl8169_private *tp = netdev_priv(dev);
2120 void __iomem *ioaddr = tp->mmio_addr;
2121 struct pci_dev *pdev = tp->pci_dev;
2123 RTL_W8(Cfg9346, Cfg9346_Unlock);
2125 RTL_W8(EarlyTxThres, EarlyTxThld);
2127 rtl_set_rx_max_size(ioaddr);
2129 rtl_set_rx_tx_config_registers(tp);
2131 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2133 RTL_W16(CPlusCmd, tp->cp_cmd);
2135 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2137 RTL_W16(IntrMitigate, 0x5151);
2139 /* Work around for RxFIFO overflow. */
2140 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2141 tp->intr_event |= RxFIFOOver | PCSTimeout;
2142 tp->intr_event &= ~RxOverflow;
2145 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2147 RTL_W8(Cfg9346, Cfg9346_Lock);
2151 RTL_W32(RxMissed, 0);
2153 rtl_set_rx_mode(dev);
2155 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2157 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2159 RTL_W16(IntrMask, tp->intr_event);
2162 static void rtl_hw_start_8101(struct net_device *dev)
2164 struct rtl8169_private *tp = netdev_priv(dev);
2165 void __iomem *ioaddr = tp->mmio_addr;
2166 struct pci_dev *pdev = tp->pci_dev;
2168 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2169 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2170 int cap = tp->pcie_cap;
2173 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2174 PCI_EXP_DEVCTL_NOSNOOP_EN);
2178 RTL_W8(Cfg9346, Cfg9346_Unlock);
2180 RTL_W8(EarlyTxThres, EarlyTxThld);
2182 rtl_set_rx_max_size(ioaddr);
2184 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2186 RTL_W16(CPlusCmd, tp->cp_cmd);
2188 RTL_W16(IntrMitigate, 0x0000);
2190 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2192 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2193 rtl_set_rx_tx_config_registers(tp);
2195 RTL_W8(Cfg9346, Cfg9346_Lock);
2199 RTL_W32(RxMissed, 0);
2201 rtl_set_rx_mode(dev);
2203 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2205 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2207 RTL_W16(IntrMask, tp->intr_event);
2210 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2212 struct rtl8169_private *tp = netdev_priv(dev);
2215 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2220 if (!netif_running(dev))
2225 rtl8169_set_rxbufsize(tp, dev);
2227 ret = rtl8169_init_ring(dev);
2231 napi_enable(&tp->napi);
2235 rtl8169_request_timer(dev);
2241 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2243 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2244 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2247 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2248 struct sk_buff **sk_buff, struct RxDesc *desc)
2250 struct pci_dev *pdev = tp->pci_dev;
2252 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2253 PCI_DMA_FROMDEVICE);
2254 dev_kfree_skb(*sk_buff);
2256 rtl8169_make_unusable_by_asic(desc);
2259 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2261 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2263 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2266 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2269 desc->addr = cpu_to_le64(mapping);
2271 rtl8169_mark_to_asic(desc, rx_buf_sz);
2274 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2275 struct net_device *dev,
2276 struct RxDesc *desc, int rx_buf_sz,
2279 struct sk_buff *skb;
2283 pad = align ? align : NET_IP_ALIGN;
2285 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2289 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2291 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2292 PCI_DMA_FROMDEVICE);
2294 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2299 rtl8169_make_unusable_by_asic(desc);
2303 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2307 for (i = 0; i < NUM_RX_DESC; i++) {
2308 if (tp->Rx_skbuff[i]) {
2309 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2310 tp->RxDescArray + i);
2315 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2320 for (cur = start; end - cur != 0; cur++) {
2321 struct sk_buff *skb;
2322 unsigned int i = cur % NUM_RX_DESC;
2324 WARN_ON((s32)(end - cur) < 0);
2326 if (tp->Rx_skbuff[i])
2329 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2330 tp->RxDescArray + i,
2331 tp->rx_buf_sz, tp->align);
2335 tp->Rx_skbuff[i] = skb;
2340 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2342 desc->opts1 |= cpu_to_le32(RingEnd);
2345 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2347 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2350 static int rtl8169_init_ring(struct net_device *dev)
2352 struct rtl8169_private *tp = netdev_priv(dev);
2354 rtl8169_init_ring_indexes(tp);
2356 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2357 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2359 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2362 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2367 rtl8169_rx_clear(tp);
2371 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2372 struct TxDesc *desc)
2374 unsigned int len = tx_skb->len;
2376 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2383 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2387 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2388 unsigned int entry = i % NUM_TX_DESC;
2389 struct ring_info *tx_skb = tp->tx_skb + entry;
2390 unsigned int len = tx_skb->len;
2393 struct sk_buff *skb = tx_skb->skb;
2395 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2396 tp->TxDescArray + entry);
2401 tp->dev->stats.tx_dropped++;
2404 tp->cur_tx = tp->dirty_tx = 0;
2407 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2409 struct rtl8169_private *tp = netdev_priv(dev);
2411 PREPARE_DELAYED_WORK(&tp->task, task);
2412 schedule_delayed_work(&tp->task, 4);
2415 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2417 struct rtl8169_private *tp = netdev_priv(dev);
2418 void __iomem *ioaddr = tp->mmio_addr;
2420 synchronize_irq(dev->irq);
2422 /* Wait for any pending NAPI task to complete */
2423 napi_disable(&tp->napi);
2425 rtl8169_irq_mask_and_ack(ioaddr);
2427 tp->intr_mask = 0xffff;
2428 RTL_W16(IntrMask, tp->intr_event);
2429 napi_enable(&tp->napi);
2432 static void rtl8169_reinit_task(struct work_struct *work)
2434 struct rtl8169_private *tp =
2435 container_of(work, struct rtl8169_private, task.work);
2436 struct net_device *dev = tp->dev;
2441 if (!netif_running(dev))
2444 rtl8169_wait_for_quiescence(dev);
2447 ret = rtl8169_open(dev);
2448 if (unlikely(ret < 0)) {
2449 if (net_ratelimit() && netif_msg_drv(tp)) {
2450 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2451 " Rescheduling.\n", dev->name, ret);
2453 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2460 static void rtl8169_reset_task(struct work_struct *work)
2462 struct rtl8169_private *tp =
2463 container_of(work, struct rtl8169_private, task.work);
2464 struct net_device *dev = tp->dev;
2468 if (!netif_running(dev))
2471 rtl8169_wait_for_quiescence(dev);
2473 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2474 rtl8169_tx_clear(tp);
2476 if (tp->dirty_rx == tp->cur_rx) {
2477 rtl8169_init_ring_indexes(tp);
2479 netif_wake_queue(dev);
2480 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2482 if (net_ratelimit() && netif_msg_intr(tp)) {
2483 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2486 rtl8169_schedule_work(dev, rtl8169_reset_task);
2493 static void rtl8169_tx_timeout(struct net_device *dev)
2495 struct rtl8169_private *tp = netdev_priv(dev);
2497 rtl8169_hw_reset(tp->mmio_addr);
2499 /* Let's wait a bit while any (async) irq lands on */
2500 rtl8169_schedule_work(dev, rtl8169_reset_task);
2503 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2506 struct skb_shared_info *info = skb_shinfo(skb);
2507 unsigned int cur_frag, entry;
2508 struct TxDesc * uninitialized_var(txd);
2511 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2512 skb_frag_t *frag = info->frags + cur_frag;
2517 entry = (entry + 1) % NUM_TX_DESC;
2519 txd = tp->TxDescArray + entry;
2521 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2522 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2524 /* anti gcc 2.95.3 bugware (sic) */
2525 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2527 txd->opts1 = cpu_to_le32(status);
2528 txd->addr = cpu_to_le64(mapping);
2530 tp->tx_skb[entry].len = len;
2534 tp->tx_skb[entry].skb = skb;
2535 txd->opts1 |= cpu_to_le32(LastFrag);
2541 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2543 if (dev->features & NETIF_F_TSO) {
2544 u32 mss = skb_shinfo(skb)->gso_size;
2547 return LargeSend | ((mss & MSSMask) << MSSShift);
2549 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2550 const struct iphdr *ip = ip_hdr(skb);
2552 if (ip->protocol == IPPROTO_TCP)
2553 return IPCS | TCPCS;
2554 else if (ip->protocol == IPPROTO_UDP)
2555 return IPCS | UDPCS;
2556 WARN_ON(1); /* we need a WARN() */
2561 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2563 struct rtl8169_private *tp = netdev_priv(dev);
2564 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2565 struct TxDesc *txd = tp->TxDescArray + entry;
2566 void __iomem *ioaddr = tp->mmio_addr;
2570 int ret = NETDEV_TX_OK;
2572 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2573 if (netif_msg_drv(tp)) {
2575 "%s: BUG! Tx Ring full when queue awake!\n",
2581 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2584 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2586 frags = rtl8169_xmit_frags(tp, skb, opts1);
2588 len = skb_headlen(skb);
2593 if (unlikely(len < ETH_ZLEN)) {
2594 if (skb_padto(skb, ETH_ZLEN))
2595 goto err_update_stats;
2599 opts1 |= FirstFrag | LastFrag;
2600 tp->tx_skb[entry].skb = skb;
2603 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2605 tp->tx_skb[entry].len = len;
2606 txd->addr = cpu_to_le64(mapping);
2607 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2611 /* anti gcc 2.95.3 bugware (sic) */
2612 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2613 txd->opts1 = cpu_to_le32(status);
2615 dev->trans_start = jiffies;
2617 tp->cur_tx += frags + 1;
2621 RTL_W8(TxPoll, NPQ); /* set polling bit */
2623 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2624 netif_stop_queue(dev);
2626 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2627 netif_wake_queue(dev);
2634 netif_stop_queue(dev);
2635 ret = NETDEV_TX_BUSY;
2637 dev->stats.tx_dropped++;
2641 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2643 struct rtl8169_private *tp = netdev_priv(dev);
2644 struct pci_dev *pdev = tp->pci_dev;
2645 void __iomem *ioaddr = tp->mmio_addr;
2646 u16 pci_status, pci_cmd;
2648 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2649 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2651 if (netif_msg_intr(tp)) {
2653 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2654 dev->name, pci_cmd, pci_status);
2658 * The recovery sequence below admits a very elaborated explanation:
2659 * - it seems to work;
2660 * - I did not see what else could be done;
2661 * - it makes iop3xx happy.
2663 * Feel free to adjust to your needs.
2665 if (pdev->broken_parity_status)
2666 pci_cmd &= ~PCI_COMMAND_PARITY;
2668 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2670 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2672 pci_write_config_word(pdev, PCI_STATUS,
2673 pci_status & (PCI_STATUS_DETECTED_PARITY |
2674 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2675 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2677 /* The infamous DAC f*ckup only happens at boot time */
2678 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2679 if (netif_msg_intr(tp))
2680 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2681 tp->cp_cmd &= ~PCIDAC;
2682 RTL_W16(CPlusCmd, tp->cp_cmd);
2683 dev->features &= ~NETIF_F_HIGHDMA;
2686 rtl8169_hw_reset(ioaddr);
2688 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2691 static void rtl8169_tx_interrupt(struct net_device *dev,
2692 struct rtl8169_private *tp,
2693 void __iomem *ioaddr)
2695 unsigned int dirty_tx, tx_left;
2697 dirty_tx = tp->dirty_tx;
2699 tx_left = tp->cur_tx - dirty_tx;
2701 while (tx_left > 0) {
2702 unsigned int entry = dirty_tx % NUM_TX_DESC;
2703 struct ring_info *tx_skb = tp->tx_skb + entry;
2704 u32 len = tx_skb->len;
2708 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2709 if (status & DescOwn)
2712 dev->stats.tx_bytes += len;
2713 dev->stats.tx_packets++;
2715 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2717 if (status & LastFrag) {
2718 dev_kfree_skb_irq(tx_skb->skb);
2725 if (tp->dirty_tx != dirty_tx) {
2726 tp->dirty_tx = dirty_tx;
2728 if (netif_queue_stopped(dev) &&
2729 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2730 netif_wake_queue(dev);
2733 * 8168 hack: TxPoll requests are lost when the Tx packets are
2734 * too close. Let's kick an extra TxPoll request when a burst
2735 * of start_xmit activity is detected (if it is not detected,
2736 * it is slow enough). -- FR
2739 if (tp->cur_tx != dirty_tx)
2740 RTL_W8(TxPoll, NPQ);
2744 static inline int rtl8169_fragmented_frame(u32 status)
2746 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2749 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2751 u32 opts1 = le32_to_cpu(desc->opts1);
2752 u32 status = opts1 & RxProtoMask;
2754 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2755 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2756 ((status == RxProtoIP) && !(opts1 & IPFail)))
2757 skb->ip_summed = CHECKSUM_UNNECESSARY;
2759 skb->ip_summed = CHECKSUM_NONE;
2762 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2763 struct rtl8169_private *tp, int pkt_size,
2766 struct sk_buff *skb;
2769 if (pkt_size >= rx_copybreak)
2772 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2776 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2777 PCI_DMA_FROMDEVICE);
2778 skb_reserve(skb, NET_IP_ALIGN);
2779 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2786 static int rtl8169_rx_interrupt(struct net_device *dev,
2787 struct rtl8169_private *tp,
2788 void __iomem *ioaddr, u32 budget)
2790 unsigned int cur_rx, rx_left;
2791 unsigned int delta, count;
2793 cur_rx = tp->cur_rx;
2794 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2795 rx_left = min(rx_left, budget);
2797 for (; rx_left > 0; rx_left--, cur_rx++) {
2798 unsigned int entry = cur_rx % NUM_RX_DESC;
2799 struct RxDesc *desc = tp->RxDescArray + entry;
2803 status = le32_to_cpu(desc->opts1);
2805 if (status & DescOwn)
2807 if (unlikely(status & RxRES)) {
2808 if (netif_msg_rx_err(tp)) {
2810 "%s: Rx ERROR. status = %08x\n",
2813 dev->stats.rx_errors++;
2814 if (status & (RxRWT | RxRUNT))
2815 dev->stats.rx_length_errors++;
2817 dev->stats.rx_crc_errors++;
2818 if (status & RxFOVF) {
2819 rtl8169_schedule_work(dev, rtl8169_reset_task);
2820 dev->stats.rx_fifo_errors++;
2822 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2824 struct sk_buff *skb = tp->Rx_skbuff[entry];
2825 dma_addr_t addr = le64_to_cpu(desc->addr);
2826 int pkt_size = (status & 0x00001FFF) - 4;
2827 struct pci_dev *pdev = tp->pci_dev;
2830 * The driver does not support incoming fragmented
2831 * frames. They are seen as a symptom of over-mtu
2834 if (unlikely(rtl8169_fragmented_frame(status))) {
2835 dev->stats.rx_dropped++;
2836 dev->stats.rx_length_errors++;
2837 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2841 rtl8169_rx_csum(skb, desc);
2843 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2844 pci_dma_sync_single_for_device(pdev, addr,
2845 pkt_size, PCI_DMA_FROMDEVICE);
2846 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2848 pci_unmap_single(pdev, addr, pkt_size,
2849 PCI_DMA_FROMDEVICE);
2850 tp->Rx_skbuff[entry] = NULL;
2853 skb_put(skb, pkt_size);
2854 skb->protocol = eth_type_trans(skb, dev);
2856 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2857 netif_receive_skb(skb);
2859 dev->last_rx = jiffies;
2860 dev->stats.rx_bytes += pkt_size;
2861 dev->stats.rx_packets++;
2864 /* Work around for AMD plateform. */
2865 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
2866 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2872 count = cur_rx - tp->cur_rx;
2873 tp->cur_rx = cur_rx;
2875 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2876 if (!delta && count && netif_msg_intr(tp))
2877 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2878 tp->dirty_rx += delta;
2881 * FIXME: until there is periodic timer to try and refill the ring,
2882 * a temporary shortage may definitely kill the Rx process.
2883 * - disable the asic to try and avoid an overflow and kick it again
2885 * - how do others driver handle this condition (Uh oh...).
2887 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2888 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2893 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2895 struct net_device *dev = dev_instance;
2896 struct rtl8169_private *tp = netdev_priv(dev);
2897 void __iomem *ioaddr = tp->mmio_addr;
2901 status = RTL_R16(IntrStatus);
2903 /* hotplug/major error/no more work/shared irq */
2904 if ((status == 0xffff) || !status)
2909 if (unlikely(!netif_running(dev))) {
2910 rtl8169_asic_down(ioaddr);
2914 status &= tp->intr_mask;
2916 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2918 if (!(status & tp->intr_event))
2921 /* Work around for rx fifo overflow */
2922 if (unlikely(status & RxFIFOOver) &&
2923 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2924 netif_stop_queue(dev);
2925 rtl8169_tx_timeout(dev);
2929 if (unlikely(status & SYSErr)) {
2930 rtl8169_pcierr_interrupt(dev);
2934 if (status & LinkChg)
2935 rtl8169_check_link_status(dev, tp, ioaddr);
2937 if (status & tp->napi_event) {
2938 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2939 tp->intr_mask = ~tp->napi_event;
2941 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2942 __netif_rx_schedule(dev, &tp->napi);
2943 else if (netif_msg_intr(tp)) {
2944 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2949 return IRQ_RETVAL(handled);
2952 static int rtl8169_poll(struct napi_struct *napi, int budget)
2954 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2955 struct net_device *dev = tp->dev;
2956 void __iomem *ioaddr = tp->mmio_addr;
2959 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
2960 rtl8169_tx_interrupt(dev, tp, ioaddr);
2962 if (work_done < budget) {
2963 netif_rx_complete(dev, napi);
2964 tp->intr_mask = 0xffff;
2966 * 20040426: the barrier is not strictly required but the
2967 * behavior of the irq handler could be less predictable
2968 * without it. Btw, the lack of flush for the posted pci
2969 * write is safe - FR
2972 RTL_W16(IntrMask, tp->intr_event);
2978 static void rtl8169_down(struct net_device *dev)
2980 struct rtl8169_private *tp = netdev_priv(dev);
2981 void __iomem *ioaddr = tp->mmio_addr;
2982 unsigned int intrmask;
2984 rtl8169_delete_timer(dev);
2986 netif_stop_queue(dev);
2988 napi_disable(&tp->napi);
2991 spin_lock_irq(&tp->lock);
2993 rtl8169_asic_down(ioaddr);
2995 /* Update the error counts. */
2996 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
2997 RTL_W32(RxMissed, 0);
2999 spin_unlock_irq(&tp->lock);
3001 synchronize_irq(dev->irq);
3003 /* Give a racing hard_start_xmit a few cycles to complete. */
3004 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3007 * And now for the 50k$ question: are IRQ disabled or not ?
3009 * Two paths lead here:
3011 * -> netif_running() is available to sync the current code and the
3012 * IRQ handler. See rtl8169_interrupt for details.
3013 * 2) dev->change_mtu
3014 * -> rtl8169_poll can not be issued again and re-enable the
3015 * interruptions. Let's simply issue the IRQ down sequence again.
3017 * No loop if hotpluged or major error (0xffff).
3019 intrmask = RTL_R16(IntrMask);
3020 if (intrmask && (intrmask != 0xffff))
3023 rtl8169_tx_clear(tp);
3025 rtl8169_rx_clear(tp);
3028 static int rtl8169_close(struct net_device *dev)
3030 struct rtl8169_private *tp = netdev_priv(dev);
3031 struct pci_dev *pdev = tp->pci_dev;
3035 free_irq(dev->irq, dev);
3037 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3039 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3041 tp->TxDescArray = NULL;
3042 tp->RxDescArray = NULL;
3047 static void rtl_set_rx_mode(struct net_device *dev)
3049 struct rtl8169_private *tp = netdev_priv(dev);
3050 void __iomem *ioaddr = tp->mmio_addr;
3051 unsigned long flags;
3052 u32 mc_filter[2]; /* Multicast hash filter */
3056 if (dev->flags & IFF_PROMISC) {
3057 /* Unconditionally log net taps. */
3058 if (netif_msg_link(tp)) {
3059 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3063 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3065 mc_filter[1] = mc_filter[0] = 0xffffffff;
3066 } else if ((dev->mc_count > multicast_filter_limit)
3067 || (dev->flags & IFF_ALLMULTI)) {
3068 /* Too many to filter perfectly -- accept all multicasts. */
3069 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3070 mc_filter[1] = mc_filter[0] = 0xffffffff;
3072 struct dev_mc_list *mclist;
3075 rx_mode = AcceptBroadcast | AcceptMyPhys;
3076 mc_filter[1] = mc_filter[0] = 0;
3077 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3078 i++, mclist = mclist->next) {
3079 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3080 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3081 rx_mode |= AcceptMulticast;
3085 spin_lock_irqsave(&tp->lock, flags);
3087 tmp = rtl8169_rx_config | rx_mode |
3088 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3090 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3091 u32 data = mc_filter[0];
3093 mc_filter[0] = swab32(mc_filter[1]);
3094 mc_filter[1] = swab32(data);
3097 RTL_W32(MAR0 + 0, mc_filter[0]);
3098 RTL_W32(MAR0 + 4, mc_filter[1]);
3100 RTL_W32(RxConfig, tmp);
3102 spin_unlock_irqrestore(&tp->lock, flags);
3106 * rtl8169_get_stats - Get rtl8169 read/write statistics
3107 * @dev: The Ethernet Device to get statistics for
3109 * Get TX/RX statistics for rtl8169
3111 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3113 struct rtl8169_private *tp = netdev_priv(dev);
3114 void __iomem *ioaddr = tp->mmio_addr;
3115 unsigned long flags;
3117 if (netif_running(dev)) {
3118 spin_lock_irqsave(&tp->lock, flags);
3119 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3120 RTL_W32(RxMissed, 0);
3121 spin_unlock_irqrestore(&tp->lock, flags);
3129 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3131 struct net_device *dev = pci_get_drvdata(pdev);
3132 struct rtl8169_private *tp = netdev_priv(dev);
3133 void __iomem *ioaddr = tp->mmio_addr;
3135 if (!netif_running(dev))
3136 goto out_pci_suspend;
3138 netif_device_detach(dev);
3139 netif_stop_queue(dev);
3141 spin_lock_irq(&tp->lock);
3143 rtl8169_asic_down(ioaddr);
3145 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3146 RTL_W32(RxMissed, 0);
3148 spin_unlock_irq(&tp->lock);
3151 pci_save_state(pdev);
3152 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3153 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3154 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3159 static int rtl8169_resume(struct pci_dev *pdev)
3161 struct net_device *dev = pci_get_drvdata(pdev);
3163 pci_set_power_state(pdev, PCI_D0);
3164 pci_restore_state(pdev);
3165 pci_enable_wake(pdev, PCI_D0, 0);
3167 if (!netif_running(dev))
3170 netif_device_attach(dev);
3172 rtl8169_schedule_work(dev, rtl8169_reset_task);
3177 #endif /* CONFIG_PM */
3179 static struct pci_driver rtl8169_pci_driver = {
3181 .id_table = rtl8169_pci_tbl,
3182 .probe = rtl8169_init_one,
3183 .remove = __devexit_p(rtl8169_remove_one),
3185 .suspend = rtl8169_suspend,
3186 .resume = rtl8169_resume,
3190 static int __init rtl8169_init_module(void)
3192 return pci_register_driver(&rtl8169_pci_driver);
3195 static void __exit rtl8169_cleanup_module(void)
3197 pci_unregister_driver(&rtl8169_pci_driver);
3200 module_init(rtl8169_init_module);
3201 module_exit(rtl8169_cleanup_module);