2 * arch/sh/kernel/cpu/sh4/probe.c
4 * CPU Subtype Probing for SH-4.
6 * Copyright (C) 2001 - 2006 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/init.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
19 int __init detect_cpu_and_cache_system(void)
21 unsigned long pvr, prr, cvr;
24 static unsigned long sizes[16] = {
32 pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
33 prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
34 cvr = (ctrl_inl(CCN_CVR));
37 * Setup some sane SH-4 defaults for the icache
39 cpu_data->icache.way_incr = (1 << 13);
40 cpu_data->icache.entry_shift = 5;
41 cpu_data->icache.sets = 256;
42 cpu_data->icache.ways = 1;
43 cpu_data->icache.linesz = L1_CACHE_BYTES;
46 * And again for the dcache ..
48 cpu_data->dcache.way_incr = (1 << 14);
49 cpu_data->dcache.entry_shift = 5;
50 cpu_data->dcache.sets = 512;
51 cpu_data->dcache.ways = 1;
52 cpu_data->dcache.linesz = L1_CACHE_BYTES;
55 * Setup some generic flags we can probe
56 * (L2 and DSP detection only work on SH-4A)
58 if (((pvr >> 16) & 0xff) == 0x10) {
59 if ((cvr & 0x02000000) == 0)
60 cpu_data->flags |= CPU_HAS_L2_CACHE;
61 if ((cvr & 0x10000000) == 0)
62 cpu_data->flags |= CPU_HAS_DSP;
64 cpu_data->flags |= CPU_HAS_LLSC;
67 /* FPU detection works for everyone */
68 if ((cvr & 0x20000000) == 1)
69 cpu_data->flags |= CPU_HAS_FPU;
71 /* Mask off the upper chip ID */
75 * Probe the underlying processor version/revision and
76 * adjust cpu_data setup accordingly.
80 cpu_data->type = CPU_SH7750;
81 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
85 cpu_data->type = CPU_SH7750S;
86 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
90 cpu_data->type = CPU_SH7751;
91 cpu_data->flags |= CPU_HAS_FPU;
94 cpu_data->type = CPU_SH73180;
95 cpu_data->icache.ways = 4;
96 cpu_data->dcache.ways = 4;
97 cpu_data->flags |= CPU_HAS_LLSC;
101 cpu_data->type = CPU_SH7770;
102 cpu_data->icache.ways = 4;
103 cpu_data->dcache.ways = 4;
105 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
110 cpu_data->type = CPU_SH7781;
112 cpu_data->type = CPU_SH7780;
114 cpu_data->icache.ways = 4;
115 cpu_data->dcache.ways = 4;
117 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
122 cpu_data->type = CPU_SH7343;
123 cpu_data->icache.ways = 4;
124 cpu_data->dcache.ways = 4;
125 cpu_data->flags |= CPU_HAS_LLSC;
128 cpu_data->type = CPU_ST40RA;
129 cpu_data->flags |= CPU_HAS_FPU;
132 cpu_data->type = CPU_ST40GX1;
133 cpu_data->flags |= CPU_HAS_FPU;
136 cpu_data->type = CPU_SH4_501;
137 cpu_data->icache.ways = 2;
138 cpu_data->dcache.ways = 2;
141 cpu_data->type = CPU_SH4_202;
142 cpu_data->icache.ways = 2;
143 cpu_data->dcache.ways = 2;
144 cpu_data->flags |= CPU_HAS_FPU;
146 case 0x500 ... 0x501:
149 cpu_data->type = CPU_SH7750R;
152 cpu_data->type = CPU_SH7751R;
155 cpu_data->type = CPU_SH7760;
159 cpu_data->icache.ways = 2;
160 cpu_data->dcache.ways = 2;
162 cpu_data->flags |= CPU_HAS_FPU;
166 cpu_data->type = CPU_SH_NONE;
170 #ifdef CONFIG_SH_DIRECT_MAPPED
171 cpu_data->icache.ways = 1;
172 cpu_data->dcache.ways = 1;
175 #ifdef CONFIG_CPU_HAS_PTEA
176 cpu_data->flags |= CPU_HAS_PTEA;
180 * On anything that's not a direct-mapped cache, look to the CVR
181 * for I/D-cache specifics.
183 if (cpu_data->icache.ways > 1) {
184 size = sizes[(cvr >> 20) & 0xf];
185 cpu_data->icache.way_incr = (size >> 1);
186 cpu_data->icache.sets = (size >> 6);
190 /* Setup the rest of the I-cache info */
191 cpu_data->icache.entry_mask = cpu_data->icache.way_incr -
192 cpu_data->icache.linesz;
194 cpu_data->icache.way_size = cpu_data->icache.sets *
195 cpu_data->icache.linesz;
197 /* And the rest of the D-cache */
198 if (cpu_data->dcache.ways > 1) {
199 size = sizes[(cvr >> 16) & 0xf];
200 cpu_data->dcache.way_incr = (size >> 1);
201 cpu_data->dcache.sets = (size >> 6);
204 cpu_data->dcache.entry_mask = cpu_data->dcache.way_incr -
205 cpu_data->dcache.linesz;
207 cpu_data->dcache.way_size = cpu_data->dcache.sets *
208 cpu_data->dcache.linesz;
211 * Setup the L2 cache desc
213 * SH-4A's have an optional PIPT L2.
215 if (cpu_data->flags & CPU_HAS_L2_CACHE) {
217 * Size calculation is much more sensible
218 * than it is for the L1.
220 * Sizes are 128KB, 258KB, 512KB, and 1MB.
222 size = (cvr & 0xf) << 17;
226 cpu_data->scache.way_incr = (1 << 16);
227 cpu_data->scache.entry_shift = 5;
228 cpu_data->scache.ways = 4;
229 cpu_data->scache.linesz = L1_CACHE_BYTES;
230 cpu_data->scache.entry_mask =
231 (cpu_data->scache.way_incr - cpu_data->scache.linesz);
232 cpu_data->scache.sets = size /
233 (cpu_data->scache.linesz * cpu_data->scache.ways);
234 cpu_data->scache.way_size =
235 (cpu_data->scache.sets * cpu_data->scache.linesz);