git.oblomov.eu Git - linux-2.6/blob - drivers/ide/pci/serverworks.c

   1 /*
   2  * linux/drivers/ide/pci/serverworks.c          Version 0.8      25 Ebr 2003
   3  *
   4  * Copyright (C) 1998-2000 Michel Aubry
   5  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
   6  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   7  * Portions copyright (c) 2001 Sun Microsystems
   8  *
   9  *
  10  * RCC/ServerWorks IDE driver for Linux
  11  *
  12  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  13  *         supports UDMA mode 2 (33 MB/s)
  14  *
  15  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  16  *         all revisions support UDMA mode 4 (66 MB/s)
  17  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  18  *
  19  *         *** The CSB5 does not provide ANY register ***
  20  *         *** to detect 80-conductor cable presence. ***
  21  *
  22  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  23  *
  24  *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
  25  *   controller same as the CSB6. Single channel ATA100 only.
  26  *
  27  * Documentation:
  28  *      Available under NDA only. Errata info very hard to get.
  29  *
  30  */
  31
  32 #include <linux/config.h>
  33 #include <linux/types.h>
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/ioport.h>
  37 #include <linux/pci.h>
  38 #include <linux/hdreg.h>
  39 #include <linux/ide.h>
  40 #include <linux/init.h>
  41 #include <linux/delay.h>
  42
  43 #include <asm/io.h>
  44
  45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  46 #define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  47
  48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  49  * can overrun their FIFOs when used with the CSB5 */
  50 static const char *svwks_bad_ata100[] = {
  51         "ST320011A",
  52         "ST340016A",
  53         "ST360021A",
  54         "ST380021A",
  55         NULL
  56 };
  57
  58 static u8 svwks_revision = 0;
  59 static struct pci_dev *isa_dev;
  60
  61 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  62 {
  63         while (*list)
  64                 if (!strcmp(*list++, drive->id->model))
  65                         return 1;
  66         return 0;
  67 }
  68
  69 static u8 svwks_ratemask (ide_drive_t *drive)
  70 {
  71         struct pci_dev *dev     = HWIF(drive)->pci_dev;
  72         u8 mode = 0;
  73
  74         if (!svwks_revision)
  75                 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
  76
  77         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
  78                 return 2;
  79         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  80                 u32 reg = 0;
  81                 if (isa_dev)
  82                         pci_read_config_dword(isa_dev, 0x64, &reg);
  83
  84                 /*
  85                  *      Don't enable UDMA on disk devices for the moment
  86                  */
  87                 if(drive->media == ide_disk)
  88                         return 0;
  89                 /* Check the OSB4 DMA33 enable bit */
  90                 return ((reg & 0x00004000) == 0x00004000) ? 1 : 0;
  91         } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
  92                 return 1;
  93         } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
  94                 u8 btr = 0;
  95                 pci_read_config_byte(dev, 0x5A, &btr);
  96                 mode = btr & 0x3;
  97                 if (!eighty_ninty_three(drive))
  98                         mode = min(mode, (u8)1);
  99                 /* If someone decides to do UDMA133 on CSB5 the same
 100                    issue will bite so be inclusive */
 101                 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
 102                         mode = 2;
 103         }
 104         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 105              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 106             (!(PCI_FUNC(dev->devfn) & 1)))
 107                 mode = 2;
 108         return mode;
 109 }
 110
 111 static u8 svwks_csb_check (struct pci_dev *dev)
 112 {
 113         switch (dev->device) {
 114                 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 115                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 116                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 117                 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 118                         return 1;
 119                 default:
 120                         break;
 121         }
 122         return 0;
 123 }
 124 static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 125 {
 126         static const u8 udma_modes[]            = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
 127         static const u8 dma_modes[]             = { 0x77, 0x21, 0x20 };
 128         static const u8 pio_modes[]             = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 129         static const u8 drive_pci[]             = { 0x41, 0x40, 0x43, 0x42 };
 130         static const u8 drive_pci2[]            = { 0x45, 0x44, 0x47, 0x46 };
 131
 132         ide_hwif_t *hwif        = HWIF(drive);
 133         struct pci_dev *dev     = hwif->pci_dev;
 134         u8 speed;
 135         u8 pio                  = ide_get_best_pio_mode(drive, 255, 5, NULL);
 136         u8 unit                 = (drive->select.b.unit & 0x01);
 137         u8 csb5                 = svwks_csb_check(dev);
 138         u8 ultra_enable         = 0, ultra_timing = 0;
 139         u8 dma_timing           = 0, pio_timing = 0;
 140         u16 csb5_pio            = 0;
 141
 142         if (xferspeed == 255)   /* PIO auto-tuning */
 143                 speed = XFER_PIO_0 + pio;
 144         else
 145                 speed = ide_rate_filter(svwks_ratemask(drive), xferspeed);
 146
 147         /* If we are about to put a disk into UDMA mode we screwed up.
 148            Our code assumes we never _ever_ do this on an OSB4 */
 149
 150         if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
 151                 drive->media == ide_disk && speed >= XFER_UDMA_0)
 152                         BUG();
 153
 154         pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
 155         pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
 156         pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
 157         pci_read_config_word(dev, 0x4A, &csb5_pio);
 158         pci_read_config_byte(dev, 0x54, &ultra_enable);
 159
 160         /* Per Specified Design by OEM, and ASIC Architect */
 161         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 162             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 163                 if (!drive->init_speed) {
 164                         u8 dma_stat = hwif->INB(hwif->dma_status);
 165
 166 dma_pio:
 167                         if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
 168                             ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
 169                                 drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
 170                                 return 0;
 171                         } else if ((dma_timing) &&
 172                                    ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
 173                                 u8 dmaspeed = dma_timing;
 174
 175                                 dma_timing &= ~0xFF;
 176                                 if ((dmaspeed & 0x20) == 0x20)
 177                                         dmaspeed = XFER_MW_DMA_2;
 178                                 else if ((dmaspeed & 0x21) == 0x21)
 179                                         dmaspeed = XFER_MW_DMA_1;
 180                                 else if ((dmaspeed & 0x77) == 0x77)
 181                                         dmaspeed = XFER_MW_DMA_0;
 182                                 else
 183                                         goto dma_pio;
 184                                 drive->current_speed = drive->init_speed = dmaspeed;
 185                                 return 0;
 186                         } else if (pio_timing) {
 187                                 u8 piospeed = pio_timing;
 188
 189                                 pio_timing &= ~0xFF;
 190                                 if ((piospeed & 0x20) == 0x20)
 191                                         piospeed = XFER_PIO_4;
 192                                 else if ((piospeed & 0x22) == 0x22)
 193                                         piospeed = XFER_PIO_3;
 194                                 else if ((piospeed & 0x34) == 0x34)
 195                                         piospeed = XFER_PIO_2;
 196                                 else if ((piospeed & 0x47) == 0x47)
 197                                         piospeed = XFER_PIO_1;
 198                                 else if ((piospeed & 0x5d) == 0x5d)
 199                                         piospeed = XFER_PIO_0;
 200                                 else
 201                                         goto oem_setup_failed;
 202                                 drive->current_speed = drive->init_speed = piospeed;
 203                                 return 0;
 204                         }
 205                 }
 206         }
 207
 208 oem_setup_failed:
 209
 210         pio_timing      &= ~0xFF;
 211         dma_timing      &= ~0xFF;
 212         ultra_timing    &= ~(0x0F << (4*unit));
 213         ultra_enable    &= ~(0x01 << drive->dn);
 214         csb5_pio        &= ~(0x0F << (4*drive->dn));
 215
 216         switch(speed) {
 217                 case XFER_PIO_4:
 218                 case XFER_PIO_3:
 219                 case XFER_PIO_2:
 220                 case XFER_PIO_1:
 221                 case XFER_PIO_0:
 222                         pio_timing |= pio_modes[speed - XFER_PIO_0];
 223                         csb5_pio   |= ((speed - XFER_PIO_0) << (4*drive->dn));
 224                         break;
 225
 226                 case XFER_MW_DMA_2:
 227                 case XFER_MW_DMA_1:
 228                 case XFER_MW_DMA_0:
 229                         pio_timing |= pio_modes[pio];
 230                         csb5_pio   |= (pio << (4*drive->dn));
 231                         dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
 232                         break;
 233
 234                 case XFER_UDMA_5:
 235                 case XFER_UDMA_4:
 236                 case XFER_UDMA_3:
 237                 case XFER_UDMA_2:
 238                 case XFER_UDMA_1:
 239                 case XFER_UDMA_0:
 240                         pio_timing   |= pio_modes[pio];
 241                         csb5_pio     |= (pio << (4*drive->dn));
 242                         dma_timing   |= dma_modes[2];
 243                         ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
 244                         ultra_enable |= (0x01 << drive->dn);
 245                 default:
 246                         break;
 247         }
 248
 249         pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
 250         if (csb5)
 251                 pci_write_config_word(dev, 0x4A, csb5_pio);
 252
 253         pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
 254         pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
 255         pci_write_config_byte(dev, 0x54, ultra_enable);
 256
 257         return (ide_config_drive_speed(drive, speed));
 258 }
 259
 260 static void config_chipset_for_pio (ide_drive_t *drive)
 261 {
 262         u16 eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
 263         u16 xfer_pio = drive->id->eide_pio_modes;
 264         u8 timing, speed, pio;
 265
 266         pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
 267
 268         if (xfer_pio > 4)
 269                 xfer_pio = 0;
 270
 271         if (drive->id->eide_pio_iordy > 0)
 272                 for (xfer_pio = 5;
 273                         xfer_pio>0 &&
 274                         drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
 275                         xfer_pio--);
 276         else
 277                 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
 278                            (drive->id->eide_pio_modes & 2) ? 0x04 :
 279                            (drive->id->eide_pio_modes & 1) ? 0x03 :
 280                            (drive->id->tPIO & 2) ? 0x02 :
 281                            (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
 282
 283         timing = (xfer_pio >= pio) ? xfer_pio : pio;
 284
 285         switch(timing) {
 286                 case 4: speed = XFER_PIO_4;break;
 287                 case 3: speed = XFER_PIO_3;break;
 288                 case 2: speed = XFER_PIO_2;break;
 289                 case 1: speed = XFER_PIO_1;break;
 290                 default:
 291                         speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
 292                         break;
 293         }
 294         (void) svwks_tune_chipset(drive, speed);
 295         drive->current_speed = speed;
 296 }
 297
 298 static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
 299 {
 300         if(pio == 255)
 301                 (void) svwks_tune_chipset(drive, 255);
 302         else
 303                 (void) svwks_tune_chipset(drive, (XFER_PIO_0 + pio));
 304 }
 305
 306 static int config_chipset_for_dma (ide_drive_t *drive)
 307 {
 308         u8 speed = ide_dma_speed(drive, svwks_ratemask(drive));
 309
 310         if (!(speed))
 311                 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
 312
 313         (void) svwks_tune_chipset(drive, speed);
 314         return ide_dma_enable(drive);
 315 }
 316
 317 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
 318 {
 319         ide_hwif_t *hwif        = HWIF(drive);
 320         struct hd_driveid *id   = drive->id;
 321
 322         drive->init_speed = 0;
 323
 324         if ((id->capability & 1) && drive->autodma) {
 325
 326                 if (ide_use_dma(drive)) {
 327                         if (config_chipset_for_dma(drive))
 328                                 return hwif->ide_dma_on(drive);
 329                 }
 330
 331                 goto fast_ata_pio;
 332
 333         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 334 fast_ata_pio:
 335                 config_chipset_for_pio(drive);
 336                 //      hwif->tuneproc(drive, 5);
 337                 return hwif->ide_dma_off_quietly(drive);
 338         }
 339         /* IORDY not supported */
 340         return 0;
 341 }
 342
 343 /* This can go soon */
 344
 345 static int svwks_ide_dma_end (ide_drive_t *drive)
 346 {
 347         return __ide_dma_end(drive);
 348 }
 349
 350 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
 351 {
 352         unsigned int reg;
 353         u8 btr;
 354
 355         /* save revision id to determine DMA capability */
 356         pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
 357
 358         /* force Master Latency Timer value to 64 PCICLKs */
 359         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
 360
 361         /* OSB4 : South Bridge and IDE */
 362         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 363                 isa_dev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
 364                           PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 365                 if (isa_dev) {
 366                         pci_read_config_dword(isa_dev, 0x64, &reg);
 367                         reg &= ~0x00002000; /* disable 600ns interrupt mask */
 368                         if(!(reg & 0x00004000))
 369                                 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
 370                         reg |=  0x00004000; /* enable UDMA/33 support */
 371                         pci_write_config_dword(isa_dev, 0x64, reg);
 372                 }
 373         }
 374
 375         /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 376         else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 377                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 378                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 379
 380                 /* Third Channel Test */
 381                 if (!(PCI_FUNC(dev->devfn) & 1)) {
 382                         struct pci_dev * findev = NULL;
 383                         u32 reg4c = 0;
 384                         findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
 385                                 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 386                         if (findev) {
 387                                 pci_read_config_dword(findev, 0x4C, &reg4c);
 388                                 reg4c &= ~0x000007FF;
 389                                 reg4c |=  0x00000040;
 390                                 reg4c |=  0x00000020;
 391                                 pci_write_config_dword(findev, 0x4C, reg4c);
 392                         }
 393                         outb_p(0x06, 0x0c00);
 394                         dev->irq = inb_p(0x0c01);
 395                 } else {
 396                         struct pci_dev * findev = NULL;
 397                         u8 reg41 = 0;
 398
 399                         findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
 400                                         PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 401                         if (findev) {
 402                                 pci_read_config_byte(findev, 0x41, &reg41);
 403                                 reg41 &= ~0x40;
 404                                 pci_write_config_byte(findev, 0x41, reg41);
 405                         }
 406                         /*
 407                          * This is a device pin issue on CSB6.
 408                          * Since there will be a future raid mode,
 409                          * early versions of the chipset require the
 410                          * interrupt pin to be set, and it is a compatibility
 411                          * mode issue.
 412                          */
 413                         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 414                                 dev->irq = 0;
 415                 }
 416 //              pci_read_config_dword(dev, 0x40, &pioreg)
 417 //              pci_write_config_dword(dev, 0x40, 0x99999999);
 418 //              pci_read_config_dword(dev, 0x44, &dmareg);
 419 //              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
 420                 /* setup the UDMA Control register
 421                  *
 422                  * 1. clear bit 6 to enable DMA
 423                  * 2. enable DMA modes with bits 0-1
 424                  *      00 : legacy
 425                  *      01 : udma2
 426                  *      10 : udma2/udma4
 427                  *      11 : udma2/udma4/udma5
 428                  */
 429                 pci_read_config_byte(dev, 0x5A, &btr);
 430                 btr &= ~0x40;
 431                 if (!(PCI_FUNC(dev->devfn) & 1))
 432                         btr |= 0x2;
 433                 else
 434                         btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 435                 pci_write_config_byte(dev, 0x5A, btr);
 436         }
 437         /* Setup HT1000 SouthBridge Controller - Single Channel Only */
 438         else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
 439                 pci_read_config_byte(dev, 0x5A, &btr);
 440                 btr &= ~0x40;
 441                 btr |= 0x3;
 442                 pci_write_config_byte(dev, 0x5A, btr);
 443         }
 444
 445         return dev->irq;
 446 }
 447
 448 static unsigned int __devinit ata66_svwks_svwks (ide_hwif_t *hwif)
 449 {
 450         return 1;
 451 }
 452
 453 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 454  * of the subsystem device ID indicate presence of an 80-pin cable.
 455  * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 456  * Bit 15 set   = secondary IDE channel has 80-pin cable.
 457  * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 458  * Bit 14 set   = primary IDE channel has 80-pin cable.
 459  */
 460 static unsigned int __devinit ata66_svwks_dell (ide_hwif_t *hwif)
 461 {
 462         struct pci_dev *dev = hwif->pci_dev;
 463         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
 464             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 465             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
 466              dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
 467                 return ((1 << (hwif->channel + 14)) &
 468                         dev->subsystem_device) ? 1 : 0;
 469         return 0;
 470 }
 471
 472 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
 473  * detect issue by attaching the drives directly to the board.
 474  * This check follows the Dell precedent (how scary is that?!)
 475  *
 476  * WARNING: this only works on Alpine hardware!
 477  */
 478 static unsigned int __devinit ata66_svwks_cobalt (ide_hwif_t *hwif)
 479 {
 480         struct pci_dev *dev = hwif->pci_dev;
 481         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
 482             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 483             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
 484                 return ((1 << (hwif->channel + 14)) &
 485                         dev->subsystem_device) ? 1 : 0;
 486         return 0;
 487 }
 488
 489 static unsigned int __devinit ata66_svwks (ide_hwif_t *hwif)
 490 {
 491         struct pci_dev *dev = hwif->pci_dev;
 492
 493         /* Server Works */
 494         if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
 495                 return ata66_svwks_svwks (hwif);
 496
 497         /* Dell PowerEdge */
 498         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
 499                 return ata66_svwks_dell (hwif);
 500
 501         /* Cobalt Alpine */
 502         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
 503                 return ata66_svwks_cobalt (hwif);
 504
 505         /* Per Specified Design by OEM, and ASIC Architect */
 506         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 507             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
 508                 return 1;
 509
 510         return 0;
 511 }
 512
 513 static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
 514 {
 515         u8 dma_stat = 0;
 516
 517         if (!hwif->irq)
 518                 hwif->irq = hwif->channel ? 15 : 14;
 519
 520         hwif->tuneproc = &svwks_tune_drive;
 521         hwif->speedproc = &svwks_tune_chipset;
 522
 523         hwif->atapi_dma = 1;
 524
 525         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
 526                 hwif->ultra_mask = 0x3f;
 527
 528         hwif->mwdma_mask = 0x07;
 529
 530         hwif->autodma = 0;
 531
 532         if (!hwif->dma_base) {
 533                 hwif->drives[0].autotune = 1;
 534                 hwif->drives[1].autotune = 1;
 535                 return;
 536         }
 537
 538         hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
 539         if (hwif->pci_dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
 540                 hwif->ide_dma_end = &svwks_ide_dma_end;
 541         else if (!(hwif->udma_four))
 542                 hwif->udma_four = ata66_svwks(hwif);
 543         if (!noautodma)
 544                 hwif->autodma = 1;
 545
 546         dma_stat = hwif->INB(hwif->dma_status);
 547         hwif->drives[0].autodma = (dma_stat & 0x20);
 548         hwif->drives[1].autodma = (dma_stat & 0x40);
 549         hwif->drives[0].autotune = (!(dma_stat & 0x20));
 550         hwif->drives[1].autotune = (!(dma_stat & 0x40));
 551 }
 552
 553 /*
 554  * We allow the BM-DMA driver to only work on enabled interfaces.
 555  */
 556 static void __devinit init_dma_svwks (ide_hwif_t *hwif, unsigned long dmabase)
 557 {
 558         struct pci_dev *dev = hwif->pci_dev;
 559
 560         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 561              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 562             (!(PCI_FUNC(dev->devfn) & 1)) && (hwif->channel))
 563                 return;
 564
 565         ide_setup_dma(hwif, dmabase, 8);
 566 }
 567
 568 static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
 569 {
 570         return ide_setup_pci_device(dev, d);
 571 }
 572
 573 static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
 574 {
 575         if (!(PCI_FUNC(dev->devfn) & 1)) {
 576                 d->bootable = NEVER_BOARD;
 577                 if (dev->resource[0].start == 0x01f1)
 578                         d->bootable = ON_BOARD;
 579         }
 580
 581         d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
 582                         dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
 583                        (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
 584
 585         return ide_setup_pci_device(dev, d);
 586 }
 587
 588 static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
 589         {       /* 0 */
 590                 .name           = "SvrWks OSB4",
 591                 .init_setup     = init_setup_svwks,
 592                 .init_chipset   = init_chipset_svwks,
 593                 .init_hwif      = init_hwif_svwks,
 594                 .channels       = 2,
 595                 .autodma        = AUTODMA,
 596                 .bootable       = ON_BOARD,
 597         },{     /* 1 */
 598                 .name           = "SvrWks CSB5",
 599                 .init_setup     = init_setup_svwks,
 600                 .init_chipset   = init_chipset_svwks,
 601                 .init_hwif      = init_hwif_svwks,
 602                 .init_dma       = init_dma_svwks,
 603                 .channels       = 2,
 604                 .autodma        = AUTODMA,
 605                 .bootable       = ON_BOARD,
 606         },{     /* 2 */
 607                 .name           = "SvrWks CSB6",
 608                 .init_setup     = init_setup_csb6,
 609                 .init_chipset   = init_chipset_svwks,
 610                 .init_hwif      = init_hwif_svwks,
 611                 .init_dma       = init_dma_svwks,
 612                 .channels       = 2,
 613                 .autodma        = AUTODMA,
 614                 .bootable       = ON_BOARD,
 615         },{     /* 3 */
 616                 .name           = "SvrWks CSB6",
 617                 .init_setup     = init_setup_csb6,
 618                 .init_chipset   = init_chipset_svwks,
 619                 .init_hwif      = init_hwif_svwks,
 620                 .init_dma       = init_dma_svwks,
 621                 .channels       = 1,    /* 2 */
 622                 .autodma        = AUTODMA,
 623                 .bootable       = ON_BOARD,
 624         },{     /* 4 */
 625                 .name           = "SvrWks HT1000",
 626                 .init_setup     = init_setup_svwks,
 627                 .init_chipset   = init_chipset_svwks,
 628                 .init_hwif      = init_hwif_svwks,
 629                 .init_dma       = init_dma_svwks,
 630                 .channels       = 1,    /* 2 */
 631                 .autodma        = AUTODMA,
 632                 .bootable       = ON_BOARD,
 633         }
 634 };
 635
 636 /**
 637  *      svwks_init_one  -       called when a OSB/CSB is found
 638  *      @dev: the svwks device
 639  *      @id: the matching pci id
 640  *
 641  *      Called when the PCI registration layer (or the IDE initialization)
 642  *      finds a device matching our IDE device tables.
 643  */
 644
 645 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 646 {
 647         ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
 648
 649         return d->init_setup(dev, d);
 650 }
 651
 652 static struct pci_device_id svwks_pci_tbl[] = {
 653         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
 654         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1},
 655         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
 656         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3},
 657         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4},
 658         { 0, },
 659 };
 660 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
 661
 662 static struct pci_driver driver = {
 663         .name           = "Serverworks_IDE",
 664         .id_table       = svwks_pci_tbl,
 665         .probe          = svwks_init_one,
 666 };
 667
 668 static int svwks_ide_init(void)
 669 {
 670         return ide_pci_register_driver(&driver);
 671 }
 672
 673 module_init(svwks_ide_init);
 674
 675 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
 676 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
 677 MODULE_LICENSE("GPL");