2 * linux/arch/arm/mm/proc-v6.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Modified by Catalin Marinas for noMMU support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This is the "shell" of the ARMv6 processor support.
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
17 #include <asm/hardware/arm_scu.h>
18 #include <asm/pgtable-hwdef.h>
19 #include <asm/pgtable.h>
21 #include "proc-macros.S"
23 #define D_CACHE_LINE_SIZE 32
25 #define TTB_C (1 << 0)
26 #define TTB_S (1 << 1)
27 #define TTB_IMP (1 << 2)
28 #define TTB_RGN_NC (0 << 3)
29 #define TTB_RGN_WBWA (1 << 3)
30 #define TTB_RGN_WT (2 << 3)
31 #define TTB_RGN_WB (3 << 3)
34 #define TTB_FLAGS TTB_RGN_WBWA
36 #define TTB_FLAGS TTB_RGN_WBWA|TTB_S
39 ENTRY(cpu_v6_proc_init)
42 ENTRY(cpu_v6_proc_fin)
44 cpsid if @ disable interrupts
45 bl v6_flush_kern_cache_all
46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
47 bic r0, r0, #0x1000 @ ...i............
48 bic r0, r0, #0x0006 @ .............ca.
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 * Perform a soft reset of the system. Put the CPU into the
56 * same state as it would be if it had been reset, and branch
57 * to what would be the reset vector.
59 * - loc - location to jump to for soft reset
70 * Idle the processor (eg, wait for interrupt).
72 * IRQs are already disabled.
75 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
78 ENTRY(cpu_v6_dcache_clean_area)
79 #ifndef TLB_CAN_READ_FROM_L1_CACHE
80 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
81 add r0, r0, #D_CACHE_LINE_SIZE
82 subs r1, r1, #D_CACHE_LINE_SIZE
88 * cpu_arm926_switch_mm(pgd_phys, tsk)
90 * Set the translation table base pointer to be pgd_phys
92 * - pgd_phys - physical address of new TTB
95 * - we are not using split page tables
97 ENTRY(cpu_v6_switch_mm)
100 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
101 orr r0, r0, #TTB_FLAGS
102 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
103 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
104 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
105 mcr p15, 0, r1, c13, c0, 1 @ set context ID
110 * cpu_v6_set_pte_ext(ptep, pte, ext)
112 * Set a level 2 translation table entry.
114 * - ptep - pointer to level 2 translation table entry
115 * (hardware version is stored at -1024 bytes)
116 * - pte - PTE value to store
117 * - ext - value for extended PTE bits
120 * YUWD APX AP1 AP0 SVC User
121 * 0xxx 0 0 0 no acc no acc
122 * 100x 1 0 1 r/o no acc
123 * 10x0 1 0 1 r/o no acc
124 * 1011 0 0 1 r/w no acc
129 ENTRY(cpu_v6_set_pte_ext)
131 str r1, [r0], #-2048 @ linux version
133 bic r3, r1, #0x000003f0
134 bic r3, r3, #0x00000003
136 orr r3, r3, #PTE_EXT_AP0 | 2
139 tstne r1, #L_PTE_DIRTY
140 orreq r3, r3, #PTE_EXT_APX
143 orrne r3, r3, #PTE_EXT_AP1
144 tstne r3, #PTE_EXT_APX
145 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
148 biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
151 orreq r3, r3, #PTE_EXT_XN
153 tst r1, #L_PTE_PRESENT
157 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
165 .asciz "ARMv6-compatible processor"
168 .section ".text.init", #alloc, #execinstr
173 * Initialise TLB, Caches, and MMU state ready to switch the MMU
174 * on. Return in r0 the new CP15 C1 control register setting.
176 * We automatically detect if we have a Harvard cache, and use the
177 * Harvard cache control instructions insead of the unified cache
178 * control instructions.
180 * This should be able to cover all ARMv6 cores.
182 * It is assumed that:
183 * - cache type register is implemented
187 /* Set up the SCU on core 0 only */
188 mrc p15, 0, r0, c0, c0, 5 @ CPU core number
190 moveq r0, #0x10000000 @ SCU_BASE
191 orreq r0, r0, #0x00100000
192 ldreq r5, [r0, #SCU_CTRL]
194 streq r5, [r0, #SCU_CTRL]
196 #ifndef CONFIG_CPU_DCACHE_DISABLE
197 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
199 mcr p15, 0, r0, c1, c0, 1
204 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
205 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
206 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
207 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
209 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
210 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
211 orr r4, r4, #TTB_FLAGS
212 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
213 #endif /* CONFIG_MMU */
216 mrc p15, 0, r0, c1, c0, 0 @ read control register
217 bic r0, r0, r5 @ clear bits them
218 orr r0, r0, r6 @ set them
219 mov pc, lr @ return to head.S:__ret
223 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
224 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
225 * 0 110 0011 1.00 .111 1101 < we want
227 .type v6_crval, #object
229 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
231 .type v6_processor_functions, #object
232 ENTRY(v6_processor_functions)
234 .word cpu_v6_proc_init
235 .word cpu_v6_proc_fin
238 .word cpu_v6_dcache_clean_area
239 .word cpu_v6_switch_mm
240 .word cpu_v6_set_pte_ext
241 .size v6_processor_functions, . - v6_processor_functions
243 .type cpu_arch_name, #object
246 .size cpu_arch_name, . - cpu_arch_name
248 .type cpu_elf_name, #object
251 .size cpu_elf_name, . - cpu_elf_name
254 .section ".proc.info.init", #alloc, #execinstr
257 * Match any ARMv6 processor core.
259 .type __v6_proc_info, #object
263 .long PMD_TYPE_SECT | \
264 PMD_SECT_BUFFERABLE | \
265 PMD_SECT_CACHEABLE | \
266 PMD_SECT_AP_WRITE | \
268 .long PMD_TYPE_SECT | \
270 PMD_SECT_AP_WRITE | \
275 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
277 .long v6_processor_functions
281 .size __v6_proc_info, . - __v6_proc_info