2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
37 #include <linux/init.h>
38 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
45 #include <linux/bitops.h>
46 #include <linux/delay.h>
47 #include <linux/ethtool.h>
48 #include <linux/platform_device.h>
50 #include <linux/module.h>
51 #include <linux/kernel.h>
52 #include <linux/spinlock.h>
53 #include <linux/workqueue.h>
54 #include <linux/mii.h>
56 #include <linux/mv643xx_eth.h>
59 #include <asm/types.h>
60 #include <asm/pgtable.h>
61 #include <asm/system.h>
62 #include <asm/delay.h>
63 #include <asm/dma-mapping.h>
65 #define MV643XX_CHECKSUM_OFFLOAD_TX
67 #define MV643XX_TX_FAST_REFILL
70 #define MV643XX_TX_COAL 100
72 #define MV643XX_RX_COAL 100
75 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
76 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
78 #define MAX_DESCS_PER_SKB 1
81 #define ETH_VLAN_HLEN 4
83 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
84 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
85 ETH_VLAN_HLEN + ETH_FCS_LEN)
86 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
87 dma_get_cache_alignment())
90 * Registers shared between all ports.
92 #define PHY_ADDR_REG 0x0000
93 #define SMI_REG 0x0004
94 #define WINDOW_BASE(i) (0x0200 + ((i) << 3))
95 #define WINDOW_SIZE(i) (0x0204 + ((i) << 3))
96 #define WINDOW_REMAP_HIGH(i) (0x0280 + ((i) << 2))
97 #define WINDOW_BAR_ENABLE 0x0290
98 #define WINDOW_PROTECT(i) (0x0294 + ((i) << 4))
101 * Per-port registers.
103 #define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10))
104 #define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10))
105 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
106 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
107 #define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10))
108 #define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10))
109 #define PORT_STATUS_REG(p) (0x0444 + ((p) << 10))
110 #define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10))
111 #define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10))
112 #define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10))
113 #define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10))
114 #define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10))
115 #define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10))
116 #define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10))
117 #define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10))
118 #define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10))
119 #define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10))
120 #define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7))
121 #define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10))
122 #define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10))
123 #define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10))
125 /* These macros describe Ethernet Port configuration reg (Px_cR) bits */
126 #define UNICAST_NORMAL_MODE (0 << 0)
127 #define UNICAST_PROMISCUOUS_MODE (1 << 0)
128 #define DEFAULT_RX_QUEUE(queue) ((queue) << 1)
129 #define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4)
130 #define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7)
131 #define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
132 #define RECEIVE_BC_IF_IP (0 << 8)
133 #define REJECT_BC_IF_IP (1 << 8)
134 #define RECEIVE_BC_IF_ARP (0 << 9)
135 #define REJECT_BC_IF_ARP (1 << 9)
136 #define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12)
137 #define CAPTURE_TCP_FRAMES_DIS (0 << 14)
138 #define CAPTURE_TCP_FRAMES_EN (1 << 14)
139 #define CAPTURE_UDP_FRAMES_DIS (0 << 15)
140 #define CAPTURE_UDP_FRAMES_EN (1 << 15)
141 #define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16)
142 #define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19)
143 #define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22)
145 #define PORT_CONFIG_DEFAULT_VALUE \
146 UNICAST_NORMAL_MODE | \
147 DEFAULT_RX_QUEUE(0) | \
148 DEFAULT_RX_ARP_QUEUE(0) | \
149 RECEIVE_BC_IF_NOT_IP_OR_ARP | \
151 RECEIVE_BC_IF_ARP | \
152 CAPTURE_TCP_FRAMES_DIS | \
153 CAPTURE_UDP_FRAMES_DIS | \
154 DEFAULT_RX_TCP_QUEUE(0) | \
155 DEFAULT_RX_UDP_QUEUE(0) | \
156 DEFAULT_RX_BPDU_QUEUE(0)
158 /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
159 #define CLASSIFY_EN (1 << 0)
160 #define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1)
161 #define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1)
162 #define PARTITION_DISABLE (0 << 2)
163 #define PARTITION_ENABLE (1 << 2)
165 #define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
166 SPAN_BPDU_PACKETS_AS_NORMAL | \
169 /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
170 #define RIFB (1 << 0)
171 #define RX_BURST_SIZE_1_64BIT (0 << 1)
172 #define RX_BURST_SIZE_2_64BIT (1 << 1)
173 #define RX_BURST_SIZE_4_64BIT (2 << 1)
174 #define RX_BURST_SIZE_8_64BIT (3 << 1)
175 #define RX_BURST_SIZE_16_64BIT (4 << 1)
176 #define BLM_RX_NO_SWAP (1 << 4)
177 #define BLM_RX_BYTE_SWAP (0 << 4)
178 #define BLM_TX_NO_SWAP (1 << 5)
179 #define BLM_TX_BYTE_SWAP (0 << 5)
180 #define DESCRIPTORS_BYTE_SWAP (1 << 6)
181 #define DESCRIPTORS_NO_SWAP (0 << 6)
182 #define IPG_INT_RX(value) (((value) & 0x3fff) << 8)
183 #define TX_BURST_SIZE_1_64BIT (0 << 22)
184 #define TX_BURST_SIZE_2_64BIT (1 << 22)
185 #define TX_BURST_SIZE_4_64BIT (2 << 22)
186 #define TX_BURST_SIZE_8_64BIT (3 << 22)
187 #define TX_BURST_SIZE_16_64BIT (4 << 22)
189 #if defined(__BIG_ENDIAN)
190 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
191 RX_BURST_SIZE_4_64BIT | \
193 TX_BURST_SIZE_4_64BIT
194 #elif defined(__LITTLE_ENDIAN)
195 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
196 RX_BURST_SIZE_4_64BIT | \
200 TX_BURST_SIZE_4_64BIT
202 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
205 /* These macros describe Ethernet Port serial control reg (PSCR) bits */
206 #define SERIAL_PORT_DISABLE (0 << 0)
207 #define SERIAL_PORT_ENABLE (1 << 0)
208 #define DO_NOT_FORCE_LINK_PASS (0 << 1)
209 #define FORCE_LINK_PASS (1 << 1)
210 #define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2)
211 #define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2)
212 #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3)
213 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
214 #define ADV_NO_FLOW_CTRL (0 << 4)
215 #define ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
216 #define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5)
217 #define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
218 #define FORCE_BP_MODE_NO_JAM (0 << 7)
219 #define FORCE_BP_MODE_JAM_TX (1 << 7)
220 #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7)
221 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
222 #define FORCE_LINK_FAIL (0 << 10)
223 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
224 #define RETRANSMIT_16_ATTEMPTS (0 << 11)
225 #define RETRANSMIT_FOREVER (1 << 11)
226 #define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13)
227 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
228 #define DTE_ADV_0 (0 << 14)
229 #define DTE_ADV_1 (1 << 14)
230 #define DISABLE_AUTO_NEG_BYPASS (0 << 15)
231 #define ENABLE_AUTO_NEG_BYPASS (1 << 15)
232 #define AUTO_NEG_NO_CHANGE (0 << 16)
233 #define RESTART_AUTO_NEG (1 << 16)
234 #define MAX_RX_PACKET_1518BYTE (0 << 17)
235 #define MAX_RX_PACKET_1522BYTE (1 << 17)
236 #define MAX_RX_PACKET_1552BYTE (2 << 17)
237 #define MAX_RX_PACKET_9022BYTE (3 << 17)
238 #define MAX_RX_PACKET_9192BYTE (4 << 17)
239 #define MAX_RX_PACKET_9700BYTE (5 << 17)
240 #define MAX_RX_PACKET_MASK (7 << 17)
241 #define CLR_EXT_LOOPBACK (0 << 20)
242 #define SET_EXT_LOOPBACK (1 << 20)
243 #define SET_HALF_DUPLEX_MODE (0 << 21)
244 #define SET_FULL_DUPLEX_MODE (1 << 21)
245 #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22)
246 #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
247 #define SET_GMII_SPEED_TO_10_100 (0 << 23)
248 #define SET_GMII_SPEED_TO_1000 (1 << 23)
249 #define SET_MII_SPEED_TO_10 (0 << 24)
250 #define SET_MII_SPEED_TO_100 (1 << 24)
252 #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \
253 DO_NOT_FORCE_LINK_PASS | \
254 ENABLE_AUTO_NEG_FOR_DUPLX | \
255 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
256 ADV_SYMMETRIC_FLOW_CTRL | \
257 FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
258 FORCE_BP_MODE_NO_JAM | \
259 (1 << 9) /* reserved */ | \
260 DO_NOT_FORCE_LINK_FAIL | \
261 RETRANSMIT_16_ATTEMPTS | \
262 ENABLE_AUTO_NEG_SPEED_GMII | \
264 DISABLE_AUTO_NEG_BYPASS | \
265 AUTO_NEG_NO_CHANGE | \
266 MAX_RX_PACKET_9700BYTE | \
268 SET_FULL_DUPLEX_MODE | \
269 ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
271 /* These macros describe Ethernet Serial Status reg (PSR) bits */
272 #define PORT_STATUS_MODE_10_BIT (1 << 0)
273 #define PORT_STATUS_LINK_UP (1 << 1)
274 #define PORT_STATUS_FULL_DUPLEX (1 << 2)
275 #define PORT_STATUS_FLOW_CONTROL (1 << 3)
276 #define PORT_STATUS_GMII_1000 (1 << 4)
277 #define PORT_STATUS_MII_100 (1 << 5)
278 /* PSR bit 6 is undocumented */
279 #define PORT_STATUS_TX_IN_PROGRESS (1 << 7)
280 #define PORT_STATUS_AUTONEG_BYPASSED (1 << 8)
281 #define PORT_STATUS_PARTITION (1 << 9)
282 #define PORT_STATUS_TX_FIFO_EMPTY (1 << 10)
283 /* PSR bits 11-31 are reserved */
285 #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
286 #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
290 #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
291 #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
293 #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
294 #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
295 #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
296 #define ETH_INT_CAUSE_EXT 0x00000002
297 #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
299 #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
300 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
301 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
302 #define ETH_INT_CAUSE_PHY 0x00010000
303 #define ETH_INT_CAUSE_STATE 0x00100000
304 #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
307 #define ETH_INT_MASK_ALL 0x00000000
308 #define ETH_INT_MASK_ALL_EXT 0x00000000
310 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
311 #define PHY_WAIT_MICRO_SECONDS 10
313 /* Buffer offset from buffer pointer */
314 #define RX_BUF_OFFSET 0x2
316 /* Gigabit Ethernet Unit Global Registers */
318 /* MIB Counters register definitions */
319 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
320 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
321 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
322 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
323 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
324 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
325 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
326 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
327 #define ETH_MIB_FRAMES_64_OCTETS 0x20
328 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
329 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
330 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
331 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
332 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
333 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
334 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
335 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
336 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
337 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
338 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
339 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
340 #define ETH_MIB_FC_SENT 0x54
341 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
342 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
343 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
344 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
345 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
346 #define ETH_MIB_JABBER_RECEIVED 0x6c
347 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
348 #define ETH_MIB_BAD_CRC_EVENT 0x74
349 #define ETH_MIB_COLLISION 0x78
350 #define ETH_MIB_LATE_COLLISION 0x7c
352 /* Port serial status reg (PSR) */
353 #define ETH_INTERFACE_PCM 0x00000001
354 #define ETH_LINK_IS_UP 0x00000002
355 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
356 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
357 #define ETH_GMII_SPEED_1000 0x00000010
358 #define ETH_MII_SPEED_100 0x00000020
359 #define ETH_TX_IN_PROGRESS 0x00000080
360 #define ETH_BYPASS_ACTIVE 0x00000100
361 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
362 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
365 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
366 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
367 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
368 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
370 /* Interrupt Cause Register Bit Definitions */
372 /* SDMA command status fields macros */
374 /* Tx & Rx descriptors status */
375 #define ETH_ERROR_SUMMARY 0x00000001
377 /* Tx & Rx descriptors command */
378 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
380 /* Tx descriptors status */
381 #define ETH_LC_ERROR 0
382 #define ETH_UR_ERROR 0x00000002
383 #define ETH_RL_ERROR 0x00000004
384 #define ETH_LLC_SNAP_FORMAT 0x00000200
386 /* Rx descriptors status */
387 #define ETH_OVERRUN_ERROR 0x00000002
388 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
389 #define ETH_RESOURCE_ERROR 0x00000006
390 #define ETH_VLAN_TAGGED 0x00080000
391 #define ETH_BPDU_FRAME 0x00100000
392 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
393 #define ETH_OTHER_FRAME_TYPE 0x00400000
394 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
395 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
396 #define ETH_FRAME_HEADER_OK 0x02000000
397 #define ETH_RX_LAST_DESC 0x04000000
398 #define ETH_RX_FIRST_DESC 0x08000000
399 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
400 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
401 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
403 /* Rx descriptors byte count */
404 #define ETH_FRAME_FRAGMENTED 0x00000004
406 /* Tx descriptors command */
407 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
408 #define ETH_FRAME_SET_TO_VLAN 0x00008000
409 #define ETH_UDP_FRAME 0x00010000
410 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
411 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
412 #define ETH_ZERO_PADDING 0x00080000
413 #define ETH_TX_LAST_DESC 0x00100000
414 #define ETH_TX_FIRST_DESC 0x00200000
415 #define ETH_GEN_CRC 0x00400000
416 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
417 #define ETH_AUTO_MODE 0x40000000
419 #define ETH_TX_IHL_SHIFT 11
423 typedef enum _eth_func_ret_status {
424 ETH_OK, /* Returned as expected. */
425 ETH_ERROR, /* Fundamental error. */
426 ETH_RETRY, /* Could not process request. Try later.*/
427 ETH_END_OF_JOB, /* Ring has nothing to process. */
428 ETH_QUEUE_FULL, /* Ring resource error. */
429 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
430 } ETH_FUNC_RET_STATUS;
432 /* These are for big-endian machines. Little endian needs different
435 #if defined(__BIG_ENDIAN)
437 u16 byte_cnt; /* Descriptor buffer byte count */
438 u16 buf_size; /* Buffer size */
439 u32 cmd_sts; /* Descriptor command status */
440 u32 next_desc_ptr; /* Next descriptor pointer */
441 u32 buf_ptr; /* Descriptor buffer pointer */
445 u16 byte_cnt; /* buffer byte count */
446 u16 l4i_chk; /* CPU provided TCP checksum */
447 u32 cmd_sts; /* Command/status field */
448 u32 next_desc_ptr; /* Pointer to next descriptor */
449 u32 buf_ptr; /* pointer to buffer for this descriptor*/
451 #elif defined(__LITTLE_ENDIAN)
453 u32 cmd_sts; /* Descriptor command status */
454 u16 buf_size; /* Buffer size */
455 u16 byte_cnt; /* Descriptor buffer byte count */
456 u32 buf_ptr; /* Descriptor buffer pointer */
457 u32 next_desc_ptr; /* Next descriptor pointer */
461 u32 cmd_sts; /* Command/status field */
462 u16 l4i_chk; /* CPU provided TCP checksum */
463 u16 byte_cnt; /* buffer byte count */
464 u32 buf_ptr; /* pointer to buffer for this descriptor*/
465 u32 next_desc_ptr; /* Pointer to next descriptor */
468 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
471 /* Unified struct for Rx and Tx operations. The user is not required to */
472 /* be familier with neither Tx nor Rx descriptors. */
474 unsigned short byte_cnt; /* Descriptor buffer byte count */
475 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
476 unsigned int cmd_sts; /* Descriptor command status */
477 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
478 struct sk_buff *return_info; /* User resource return information */
481 /* Ethernet port specific information */
482 struct mv643xx_mib_counters {
483 u64 good_octets_received;
484 u32 bad_octets_received;
485 u32 internal_mac_transmit_err;
486 u32 good_frames_received;
487 u32 bad_frames_received;
488 u32 broadcast_frames_received;
489 u32 multicast_frames_received;
490 u32 frames_64_octets;
491 u32 frames_65_to_127_octets;
492 u32 frames_128_to_255_octets;
493 u32 frames_256_to_511_octets;
494 u32 frames_512_to_1023_octets;
495 u32 frames_1024_to_max_octets;
496 u64 good_octets_sent;
497 u32 good_frames_sent;
498 u32 excessive_collision;
499 u32 multicast_frames_sent;
500 u32 broadcast_frames_sent;
501 u32 unrec_mac_control_received;
503 u32 good_fc_received;
505 u32 undersize_received;
506 u32 fragments_received;
507 u32 oversize_received;
509 u32 mac_receive_error;
515 struct mv643xx_shared_private {
516 void __iomem *eth_base;
518 /* used to protect SMI_REG, which is shared across ports */
524 struct mv643xx_private {
525 struct mv643xx_shared_private *shared;
526 int port_num; /* User Ethernet port number */
528 u32 rx_sram_addr; /* Base address of rx sram area */
529 u32 rx_sram_size; /* Size of rx sram area */
530 u32 tx_sram_addr; /* Base address of tx sram area */
531 u32 tx_sram_size; /* Size of tx sram area */
533 int rx_resource_err; /* Rx ring resource error flag */
535 /* Tx/Rx rings managment indexes fields. For driver use */
537 /* Next available and first returning Rx resource */
538 int rx_curr_desc_q, rx_used_desc_q;
540 /* Next available and first returning Tx resource */
541 int tx_curr_desc_q, tx_used_desc_q;
543 #ifdef MV643XX_TX_FAST_REFILL
544 u32 tx_clean_threshold;
547 struct eth_rx_desc *p_rx_desc_area;
548 dma_addr_t rx_desc_dma;
549 int rx_desc_area_size;
550 struct sk_buff **rx_skb;
552 struct eth_tx_desc *p_tx_desc_area;
553 dma_addr_t tx_desc_dma;
554 int tx_desc_area_size;
555 struct sk_buff **tx_skb;
557 struct work_struct tx_timeout_task;
559 struct net_device *dev;
560 struct napi_struct napi;
561 struct net_device_stats stats;
562 struct mv643xx_mib_counters mib_counters;
564 /* Size of Tx Ring per queue */
566 /* Number of tx descriptors in use */
568 /* Size of Rx Ring per queue */
570 /* Number of rx descriptors in use */
574 * Used in case RX Ring is empty, which can be caused when
575 * system does not have resources (skb's)
577 struct timer_list timeout;
581 struct mii_if_info mii;
584 /* Static function declarations */
585 static void eth_port_init(struct mv643xx_private *mp);
586 static void eth_port_reset(struct mv643xx_private *mp);
587 static void eth_port_start(struct net_device *dev);
589 static void ethernet_phy_reset(struct mv643xx_private *mp);
591 static void eth_port_write_smi_reg(struct mv643xx_private *mp,
592 unsigned int phy_reg, unsigned int value);
594 static void eth_port_read_smi_reg(struct mv643xx_private *mp,
595 unsigned int phy_reg, unsigned int *value);
597 static void eth_clear_mib_counters(struct mv643xx_private *mp);
599 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
600 struct pkt_info *p_pkt_info);
601 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
602 struct pkt_info *p_pkt_info);
604 static void eth_port_uc_addr_get(struct mv643xx_private *mp,
605 unsigned char *p_addr);
606 static void eth_port_uc_addr_set(struct mv643xx_private *mp,
607 unsigned char *p_addr);
608 static void eth_port_set_multicast_list(struct net_device *);
609 static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
610 unsigned int queues);
611 static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
612 unsigned int queues);
613 static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp);
614 static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp);
615 static int mv643xx_eth_open(struct net_device *);
616 static int mv643xx_eth_stop(struct net_device *);
617 static void eth_port_init_mac_tables(struct mv643xx_private *mp);
619 static int mv643xx_poll(struct napi_struct *napi, int budget);
621 static int ethernet_phy_get(struct mv643xx_private *mp);
622 static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr);
623 static int ethernet_phy_detect(struct mv643xx_private *mp);
624 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
625 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
626 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
627 static const struct ethtool_ops mv643xx_ethtool_ops;
629 static char mv643xx_driver_name[] = "mv643xx_eth";
630 static char mv643xx_driver_version[] = "1.0";
632 static inline u32 rdl(struct mv643xx_private *mp, int offset)
634 return readl(mp->shared->eth_base + offset);
637 static inline void wrl(struct mv643xx_private *mp, int offset, u32 data)
639 writel(data, mp->shared->eth_base + offset);
643 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
645 * Input : pointer to ethernet interface network device structure
647 * Output : 0 upon success, -EINVAL upon failure
649 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
651 if ((new_mtu > 9500) || (new_mtu < 64))
655 if (!netif_running(dev))
659 * Stop and then re-open the interface. This will allocate RX
660 * skbs of the new MTU.
661 * There is a possible danger that the open will not succeed,
662 * due to memory being full, which might fail the open function.
664 mv643xx_eth_stop(dev);
665 if (mv643xx_eth_open(dev)) {
666 printk(KERN_ERR "%s: Fatal error on opening device\n",
674 * mv643xx_eth_rx_refill_descs
676 * Fills / refills RX queue on a certain gigabit ethernet port
678 * Input : pointer to ethernet interface network device structure
681 static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
683 struct mv643xx_private *mp = netdev_priv(dev);
684 struct pkt_info pkt_info;
688 while (mp->rx_desc_count < mp->rx_ring_size) {
689 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
693 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
695 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
696 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
697 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
698 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
699 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
700 pkt_info.return_info = skb;
701 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
703 "%s: Error allocating RX Ring\n", dev->name);
706 skb_reserve(skb, ETH_HW_IP_ALIGN);
709 * If RX ring is empty of SKB, set a timer to try allocating
710 * again at a later time.
712 if (mp->rx_desc_count == 0) {
713 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
714 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
715 add_timer(&mp->timeout);
720 * mv643xx_eth_rx_refill_descs_timer_wrapper
722 * Timer routine to wake up RX queue filling task. This function is
723 * used only in case the RX queue is empty, and all alloc_skb has
724 * failed (due to out of memory event).
726 * Input : pointer to ethernet interface network device structure
729 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
731 mv643xx_eth_rx_refill_descs((struct net_device *)data);
735 * mv643xx_eth_update_mac_address
737 * Update the MAC address of the port in the address table
739 * Input : pointer to ethernet interface network device structure
742 static void mv643xx_eth_update_mac_address(struct net_device *dev)
744 struct mv643xx_private *mp = netdev_priv(dev);
746 eth_port_init_mac_tables(mp);
747 eth_port_uc_addr_set(mp, dev->dev_addr);
751 * mv643xx_eth_set_rx_mode
753 * Change from promiscuos to regular rx mode
755 * Input : pointer to ethernet interface network device structure
758 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
760 struct mv643xx_private *mp = netdev_priv(dev);
763 config_reg = rdl(mp, PORT_CONFIG_REG(mp->port_num));
764 if (dev->flags & IFF_PROMISC)
765 config_reg |= (u32) UNICAST_PROMISCUOUS_MODE;
767 config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE;
768 wrl(mp, PORT_CONFIG_REG(mp->port_num), config_reg);
770 eth_port_set_multicast_list(dev);
774 * mv643xx_eth_set_mac_address
776 * Change the interface's mac address.
777 * No special hardware thing should be done because interface is always
778 * put in promiscuous mode.
780 * Input : pointer to ethernet interface network device structure and
781 * a pointer to the designated entry to be added to the cache.
782 * Output : zero upon success, negative upon failure
784 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
788 for (i = 0; i < 6; i++)
789 /* +2 is for the offset of the HW addr type */
790 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
791 mv643xx_eth_update_mac_address(dev);
796 * mv643xx_eth_tx_timeout
798 * Called upon a timeout on transmitting a packet
800 * Input : pointer to ethernet interface network device structure.
803 static void mv643xx_eth_tx_timeout(struct net_device *dev)
805 struct mv643xx_private *mp = netdev_priv(dev);
807 printk(KERN_INFO "%s: TX timeout ", dev->name);
809 /* Do the reset outside of interrupt context */
810 schedule_work(&mp->tx_timeout_task);
814 * mv643xx_eth_tx_timeout_task
816 * Actual routine to reset the adapter when a timeout on Tx has occurred
818 static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
820 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
822 struct net_device *dev = mp->dev;
824 if (!netif_running(dev))
827 netif_stop_queue(dev);
832 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
833 netif_wake_queue(dev);
837 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
839 * If force is non-zero, frees uncompleted descriptors as well
841 static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
843 struct mv643xx_private *mp = netdev_priv(dev);
844 struct eth_tx_desc *desc;
853 while (mp->tx_desc_count > 0) {
854 spin_lock_irqsave(&mp->lock, flags);
856 /* tx_desc_count might have changed before acquiring the lock */
857 if (mp->tx_desc_count <= 0) {
858 spin_unlock_irqrestore(&mp->lock, flags);
862 tx_index = mp->tx_used_desc_q;
863 desc = &mp->p_tx_desc_area[tx_index];
864 cmd_sts = desc->cmd_sts;
866 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
867 spin_unlock_irqrestore(&mp->lock, flags);
871 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
874 addr = desc->buf_ptr;
875 count = desc->byte_cnt;
876 skb = mp->tx_skb[tx_index];
878 mp->tx_skb[tx_index] = NULL;
880 if (cmd_sts & ETH_ERROR_SUMMARY) {
881 printk("%s: Error in TX\n", dev->name);
882 dev->stats.tx_errors++;
885 spin_unlock_irqrestore(&mp->lock, flags);
887 if (cmd_sts & ETH_TX_FIRST_DESC)
888 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
890 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
893 dev_kfree_skb_irq(skb);
901 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
903 struct mv643xx_private *mp = netdev_priv(dev);
905 if (mv643xx_eth_free_tx_descs(dev, 0) &&
906 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
907 netif_wake_queue(dev);
910 static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
912 mv643xx_eth_free_tx_descs(dev, 1);
916 * mv643xx_eth_receive
918 * This function is forward packets that are received from the port's
919 * queues toward kernel core or FastRoute them to another interface.
921 * Input : dev - a pointer to the required interface
922 * max - maximum number to receive (0 means unlimted)
924 * Output : number of served packets
926 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
928 struct mv643xx_private *mp = netdev_priv(dev);
929 struct net_device_stats *stats = &dev->stats;
930 unsigned int received_packets = 0;
932 struct pkt_info pkt_info;
934 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
935 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
942 * Note byte count includes 4 byte CRC count
945 stats->rx_bytes += pkt_info.byte_cnt;
946 skb = pkt_info.return_info;
948 * In case received a packet without first / last bits on OR
949 * the error summary bit is on, the packets needs to be dropeed.
951 if (((pkt_info.cmd_sts
952 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
953 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
954 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
956 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
957 ETH_RX_LAST_DESC)) !=
958 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
961 "%s: Received packet spread "
962 "on multiple descriptors\n",
965 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
968 dev_kfree_skb_irq(skb);
971 * The -4 is for the CRC in the trailer of the
974 skb_put(skb, pkt_info.byte_cnt - 4);
976 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
977 skb->ip_summed = CHECKSUM_UNNECESSARY;
979 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
981 skb->protocol = eth_type_trans(skb, dev);
983 netif_receive_skb(skb);
988 dev->last_rx = jiffies;
990 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
992 return received_packets;
995 /* Set the mv643xx port configuration register for the speed/duplex mode. */
996 static void mv643xx_eth_update_pscr(struct net_device *dev,
997 struct ethtool_cmd *ecmd)
999 struct mv643xx_private *mp = netdev_priv(dev);
1000 int port_num = mp->port_num;
1002 unsigned int queues;
1004 o_pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num));
1007 /* clear speed, duplex and rx buffer size fields */
1008 n_pscr &= ~(SET_MII_SPEED_TO_100 |
1009 SET_GMII_SPEED_TO_1000 |
1010 SET_FULL_DUPLEX_MODE |
1011 MAX_RX_PACKET_MASK);
1013 if (ecmd->duplex == DUPLEX_FULL)
1014 n_pscr |= SET_FULL_DUPLEX_MODE;
1016 if (ecmd->speed == SPEED_1000)
1017 n_pscr |= SET_GMII_SPEED_TO_1000 |
1018 MAX_RX_PACKET_9700BYTE;
1020 if (ecmd->speed == SPEED_100)
1021 n_pscr |= SET_MII_SPEED_TO_100;
1022 n_pscr |= MAX_RX_PACKET_1522BYTE;
1025 if (n_pscr != o_pscr) {
1026 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
1027 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
1029 queues = mv643xx_eth_port_disable_tx(mp);
1031 o_pscr &= ~SERIAL_PORT_ENABLE;
1032 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), o_pscr);
1033 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
1034 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
1036 mv643xx_eth_port_enable_tx(mp, queues);
1042 * mv643xx_eth_int_handler
1044 * Main interrupt handler for the gigbit ethernet ports
1046 * Input : irq - irq number (not used)
1047 * dev_id - a pointer to the required interface's data structure
1052 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1054 struct net_device *dev = (struct net_device *)dev_id;
1055 struct mv643xx_private *mp = netdev_priv(dev);
1056 u32 eth_int_cause, eth_int_cause_ext = 0;
1057 unsigned int port_num = mp->port_num;
1059 /* Read interrupt cause registers */
1060 eth_int_cause = rdl(mp, INTERRUPT_CAUSE_REG(port_num)) &
1062 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
1063 eth_int_cause_ext = rdl(mp,
1064 INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
1065 ETH_INT_UNMASK_ALL_EXT;
1066 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num),
1067 ~eth_int_cause_ext);
1070 /* PHY status changed */
1071 if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) {
1072 struct ethtool_cmd cmd;
1074 if (mii_link_ok(&mp->mii)) {
1075 mii_ethtool_gset(&mp->mii, &cmd);
1076 mv643xx_eth_update_pscr(dev, &cmd);
1077 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED);
1078 if (!netif_carrier_ok(dev)) {
1079 netif_carrier_on(dev);
1080 if (mp->tx_ring_size - mp->tx_desc_count >=
1082 netif_wake_queue(dev);
1084 } else if (netif_carrier_ok(dev)) {
1085 netif_stop_queue(dev);
1086 netif_carrier_off(dev);
1091 if (eth_int_cause & ETH_INT_CAUSE_RX) {
1092 /* schedule the NAPI poll routine to maintain port */
1093 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1095 /* wait for previous write to complete */
1096 rdl(mp, INTERRUPT_MASK_REG(port_num));
1098 netif_rx_schedule(dev, &mp->napi);
1101 if (eth_int_cause & ETH_INT_CAUSE_RX)
1102 mv643xx_eth_receive_queue(dev, INT_MAX);
1104 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
1105 mv643xx_eth_free_completed_tx_descs(dev);
1108 * If no real interrupt occured, exit.
1109 * This can happen when using gigE interrupt coalescing mechanism.
1111 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
1120 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
1123 * This routine sets the RX coalescing interrupt mechanism parameter.
1124 * This parameter is a timeout counter, that counts in 64 t_clk
1125 * chunks ; that when timeout event occurs a maskable interrupt
1127 * The parameter is calculated using the tClk of the MV-643xx chip
1128 * , and the required delay of the interrupt in usec.
1131 * struct mv643xx_private *mp Ethernet port
1132 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
1133 * unsigned int delay Delay in usec
1136 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1139 * The interrupt coalescing value set in the gigE port.
1142 static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp,
1143 unsigned int t_clk, unsigned int delay)
1145 unsigned int port_num = mp->port_num;
1146 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
1148 /* Set RX Coalescing mechanism */
1149 wrl(mp, SDMA_CONFIG_REG(port_num),
1150 ((coal & 0x3fff) << 8) |
1151 (rdl(mp, SDMA_CONFIG_REG(port_num))
1159 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
1162 * This routine sets the TX coalescing interrupt mechanism parameter.
1163 * This parameter is a timeout counter, that counts in 64 t_clk
1164 * chunks ; that when timeout event occurs a maskable interrupt
1166 * The parameter is calculated using the t_cLK frequency of the
1167 * MV-643xx chip and the required delay in the interrupt in uSec
1170 * struct mv643xx_private *mp Ethernet port
1171 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
1172 * unsigned int delay Delay in uSeconds
1175 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1178 * The interrupt coalescing value set in the gigE port.
1181 static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp,
1182 unsigned int t_clk, unsigned int delay)
1184 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
1186 /* Set TX Coalescing mechanism */
1187 wrl(mp, TX_FIFO_URGENT_THRESHOLD_REG(mp->port_num), coal << 4);
1193 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
1196 * This function prepares a Rx chained list of descriptors and packet
1197 * buffers in a form of a ring. The routine must be called after port
1198 * initialization routine and before port start routine.
1199 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1200 * devices in the system (i.e. DRAM). This function uses the ethernet
1201 * struct 'virtual to physical' routine (set by the user) to set the ring
1202 * with physical addresses.
1205 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1208 * The routine updates the Ethernet port control struct with information
1209 * regarding the Rx descriptors and buffers.
1214 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
1216 volatile struct eth_rx_desc *p_rx_desc;
1217 int rx_desc_num = mp->rx_ring_size;
1220 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1221 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
1222 for (i = 0; i < rx_desc_num; i++) {
1223 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
1224 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
1227 /* Save Rx desc pointer to driver struct. */
1228 mp->rx_curr_desc_q = 0;
1229 mp->rx_used_desc_q = 0;
1231 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
1235 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
1238 * This function prepares a Tx chained list of descriptors and packet
1239 * buffers in a form of a ring. The routine must be called after port
1240 * initialization routine and before port start routine.
1241 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1242 * devices in the system (i.e. DRAM). This function uses the ethernet
1243 * struct 'virtual to physical' routine (set by the user) to set the ring
1244 * with physical addresses.
1247 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1250 * The routine updates the Ethernet port control struct with information
1251 * regarding the Tx descriptors and buffers.
1256 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
1258 int tx_desc_num = mp->tx_ring_size;
1259 struct eth_tx_desc *p_tx_desc;
1262 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1263 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
1264 for (i = 0; i < tx_desc_num; i++) {
1265 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
1266 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
1269 mp->tx_curr_desc_q = 0;
1270 mp->tx_used_desc_q = 0;
1272 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
1275 static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1277 struct mv643xx_private *mp = netdev_priv(dev);
1280 spin_lock_irq(&mp->lock);
1281 err = mii_ethtool_sset(&mp->mii, cmd);
1282 spin_unlock_irq(&mp->lock);
1287 static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1289 struct mv643xx_private *mp = netdev_priv(dev);
1292 spin_lock_irq(&mp->lock);
1293 err = mii_ethtool_gset(&mp->mii, cmd);
1294 spin_unlock_irq(&mp->lock);
1296 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
1297 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1298 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1306 * This function is called when openning the network device. The function
1307 * should initialize all the hardware, initialize cyclic Rx/Tx
1308 * descriptors chain and buffers and allocate an IRQ to the network
1311 * Input : a pointer to the network device structure
1313 * Output : zero of success , nonzero if fails.
1316 static int mv643xx_eth_open(struct net_device *dev)
1318 struct mv643xx_private *mp = netdev_priv(dev);
1319 unsigned int port_num = mp->port_num;
1323 /* Clear any pending ethernet port interrupts */
1324 wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0);
1325 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1326 /* wait for previous write to complete */
1327 rdl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num));
1329 err = request_irq(dev->irq, mv643xx_eth_int_handler,
1330 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
1332 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
1338 memset(&mp->timeout, 0, sizeof(struct timer_list));
1339 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
1340 mp->timeout.data = (unsigned long)dev;
1342 /* Allocate RX and TX skb rings */
1343 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
1346 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
1350 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
1353 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
1355 goto out_free_rx_skb;
1358 /* Allocate TX ring */
1359 mp->tx_desc_count = 0;
1360 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
1361 mp->tx_desc_area_size = size;
1363 if (mp->tx_sram_size) {
1364 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
1366 mp->tx_desc_dma = mp->tx_sram_addr;
1368 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
1372 if (!mp->p_tx_desc_area) {
1373 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
1376 goto out_free_tx_skb;
1378 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
1379 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
1381 ether_init_tx_desc_ring(mp);
1383 /* Allocate RX ring */
1384 mp->rx_desc_count = 0;
1385 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
1386 mp->rx_desc_area_size = size;
1388 if (mp->rx_sram_size) {
1389 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
1391 mp->rx_desc_dma = mp->rx_sram_addr;
1393 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
1397 if (!mp->p_rx_desc_area) {
1398 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
1400 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
1402 if (mp->rx_sram_size)
1403 iounmap(mp->p_tx_desc_area);
1405 dma_free_coherent(NULL, mp->tx_desc_area_size,
1406 mp->p_tx_desc_area, mp->tx_desc_dma);
1408 goto out_free_tx_skb;
1410 memset((void *)mp->p_rx_desc_area, 0, size);
1412 ether_init_rx_desc_ring(mp);
1414 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1417 napi_enable(&mp->napi);
1420 eth_port_start(dev);
1422 /* Interrupt Coalescing */
1426 eth_port_set_rx_coal(mp, 133000000, MV643XX_RX_COAL);
1430 eth_port_set_tx_coal(mp, 133000000, MV643XX_TX_COAL);
1432 /* Unmask phy and link status changes interrupts */
1433 wrl(mp, INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT);
1435 /* Unmask RX buffer and TX end interrupt */
1436 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1445 free_irq(dev->irq, dev);
1450 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1452 struct mv643xx_private *mp = netdev_priv(dev);
1454 /* Stop Tx Queues */
1455 mv643xx_eth_port_disable_tx(mp);
1457 /* Free outstanding skb's on TX ring */
1458 mv643xx_eth_free_all_tx_descs(dev);
1460 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
1463 if (mp->tx_sram_size)
1464 iounmap(mp->p_tx_desc_area);
1466 dma_free_coherent(NULL, mp->tx_desc_area_size,
1467 mp->p_tx_desc_area, mp->tx_desc_dma);
1470 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
1472 struct mv643xx_private *mp = netdev_priv(dev);
1475 /* Stop RX Queues */
1476 mv643xx_eth_port_disable_rx(mp);
1478 /* Free preallocated skb's on RX rings */
1479 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1480 if (mp->rx_skb[curr]) {
1481 dev_kfree_skb(mp->rx_skb[curr]);
1482 mp->rx_desc_count--;
1486 if (mp->rx_desc_count)
1488 "%s: Error in freeing Rx Ring. %d skb's still"
1489 " stuck in RX Ring - ignoring them\n", dev->name,
1492 if (mp->rx_sram_size)
1493 iounmap(mp->p_rx_desc_area);
1495 dma_free_coherent(NULL, mp->rx_desc_area_size,
1496 mp->p_rx_desc_area, mp->rx_desc_dma);
1502 * This function is used when closing the network device.
1503 * It updates the hardware,
1504 * release all memory that holds buffers and descriptors and release the IRQ.
1505 * Input : a pointer to the device structure
1506 * Output : zero if success , nonzero if fails
1509 static int mv643xx_eth_stop(struct net_device *dev)
1511 struct mv643xx_private *mp = netdev_priv(dev);
1512 unsigned int port_num = mp->port_num;
1514 /* Mask all interrupts on ethernet port */
1515 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1516 /* wait for previous write to complete */
1517 rdl(mp, INTERRUPT_MASK_REG(port_num));
1520 napi_disable(&mp->napi);
1522 netif_carrier_off(dev);
1523 netif_stop_queue(dev);
1527 mv643xx_eth_free_tx_rings(dev);
1528 mv643xx_eth_free_rx_rings(dev);
1530 free_irq(dev->irq, dev);
1539 * This function is used in case of NAPI
1541 static int mv643xx_poll(struct napi_struct *napi, int budget)
1543 struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi);
1544 struct net_device *dev = mp->dev;
1545 unsigned int port_num = mp->port_num;
1548 #ifdef MV643XX_TX_FAST_REFILL
1549 if (++mp->tx_clean_threshold > 5) {
1550 mv643xx_eth_free_completed_tx_descs(dev);
1551 mp->tx_clean_threshold = 0;
1556 if ((rdl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1557 != (u32) mp->rx_used_desc_q)
1558 work_done = mv643xx_eth_receive_queue(dev, budget);
1560 if (work_done < budget) {
1561 netif_rx_complete(dev, napi);
1562 wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0);
1563 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1564 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1572 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1574 * Hardware can't handle unaligned fragments smaller than 9 bytes.
1575 * This helper function detects that case.
1578 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1583 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1584 fragp = &skb_shinfo(skb)->frags[frag];
1585 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1592 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1594 static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1598 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
1600 tx_desc_curr = mp->tx_curr_desc_q;
1601 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
1603 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
1605 return tx_desc_curr;
1609 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
1611 * Ensure the data for each fragment to be transmitted is mapped properly,
1612 * then fill in descriptors in the tx hw queue.
1614 static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
1615 struct sk_buff *skb)
1619 struct eth_tx_desc *desc;
1621 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1622 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1624 tx_index = eth_alloc_tx_desc_index(mp);
1625 desc = &mp->p_tx_desc_area[tx_index];
1627 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
1628 /* Last Frag enables interrupt and frees the skb */
1629 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1630 desc->cmd_sts |= ETH_ZERO_PADDING |
1632 ETH_TX_ENABLE_INTERRUPT;
1633 mp->tx_skb[tx_index] = skb;
1635 mp->tx_skb[tx_index] = NULL;
1637 desc = &mp->p_tx_desc_area[tx_index];
1639 desc->byte_cnt = this_frag->size;
1640 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1641 this_frag->page_offset,
1647 static inline __be16 sum16_as_be(__sum16 sum)
1649 return (__force __be16)sum;
1653 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1655 * Ensure the data for an skb to be transmitted is mapped properly,
1656 * then fill in descriptors in the tx hw queue and start the hardware.
1658 static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1659 struct sk_buff *skb)
1662 struct eth_tx_desc *desc;
1665 int nr_frags = skb_shinfo(skb)->nr_frags;
1667 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
1669 tx_index = eth_alloc_tx_desc_index(mp);
1670 desc = &mp->p_tx_desc_area[tx_index];
1673 eth_tx_fill_frag_descs(mp, skb);
1675 length = skb_headlen(skb);
1676 mp->tx_skb[tx_index] = NULL;
1678 cmd_sts |= ETH_ZERO_PADDING |
1680 ETH_TX_ENABLE_INTERRUPT;
1682 mp->tx_skb[tx_index] = skb;
1685 desc->byte_cnt = length;
1686 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1688 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1689 BUG_ON(skb->protocol != htons(ETH_P_IP));
1691 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
1692 ETH_GEN_IP_V_4_CHECKSUM |
1693 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT;
1695 switch (ip_hdr(skb)->protocol) {
1697 cmd_sts |= ETH_UDP_FRAME;
1698 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
1701 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
1707 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1708 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1712 /* ensure all other descriptors are written before first cmd_sts */
1714 desc->cmd_sts = cmd_sts;
1716 /* ensure all descriptors are written before poking hardware */
1718 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED);
1720 mp->tx_desc_count += nr_frags + 1;
1724 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1727 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1729 struct mv643xx_private *mp = netdev_priv(dev);
1730 struct net_device_stats *stats = &dev->stats;
1731 unsigned long flags;
1733 BUG_ON(netif_queue_stopped(dev));
1735 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1736 stats->tx_dropped++;
1737 printk(KERN_DEBUG "%s: failed to linearize tiny "
1738 "unaligned fragment\n", dev->name);
1739 return NETDEV_TX_BUSY;
1742 spin_lock_irqsave(&mp->lock, flags);
1744 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
1745 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
1746 netif_stop_queue(dev);
1747 spin_unlock_irqrestore(&mp->lock, flags);
1748 return NETDEV_TX_BUSY;
1751 eth_tx_submit_descs_for_skb(mp, skb);
1752 stats->tx_bytes += skb->len;
1753 stats->tx_packets++;
1754 dev->trans_start = jiffies;
1756 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1757 netif_stop_queue(dev);
1759 spin_unlock_irqrestore(&mp->lock, flags);
1761 return NETDEV_TX_OK;
1764 #ifdef CONFIG_NET_POLL_CONTROLLER
1765 static void mv643xx_netpoll(struct net_device *netdev)
1767 struct mv643xx_private *mp = netdev_priv(netdev);
1768 int port_num = mp->port_num;
1770 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1771 /* wait for previous write to complete */
1772 rdl(mp, INTERRUPT_MASK_REG(port_num));
1774 mv643xx_eth_int_handler(netdev->irq, netdev);
1776 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1780 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
1781 int speed, int duplex,
1782 struct ethtool_cmd *cmd)
1784 struct mv643xx_private *mp = netdev_priv(dev);
1786 memset(cmd, 0, sizeof(*cmd));
1788 cmd->port = PORT_MII;
1789 cmd->transceiver = XCVR_INTERNAL;
1790 cmd->phy_address = phy_address;
1793 cmd->autoneg = AUTONEG_ENABLE;
1794 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1795 cmd->speed = SPEED_100;
1796 cmd->advertising = ADVERTISED_10baseT_Half |
1797 ADVERTISED_10baseT_Full |
1798 ADVERTISED_100baseT_Half |
1799 ADVERTISED_100baseT_Full;
1800 if (mp->mii.supports_gmii)
1801 cmd->advertising |= ADVERTISED_1000baseT_Full;
1803 cmd->autoneg = AUTONEG_DISABLE;
1805 cmd->duplex = duplex;
1812 * First function called after registering the network device.
1813 * It's purpose is to initialize the device as an ethernet device,
1814 * fill the ethernet device structure with pointers * to functions,
1815 * and set the MAC address of the interface
1817 * Input : struct device *
1818 * Output : -ENOMEM if failed , 0 if success
1820 static int mv643xx_eth_probe(struct platform_device *pdev)
1822 struct mv643xx_eth_platform_data *pd;
1824 struct mv643xx_private *mp;
1825 struct net_device *dev;
1827 struct resource *res;
1829 struct ethtool_cmd cmd;
1830 int duplex = DUPLEX_HALF;
1831 int speed = 0; /* default to auto-negotiation */
1832 DECLARE_MAC_BUF(mac);
1834 pd = pdev->dev.platform_data;
1836 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
1840 if (pd->shared == NULL) {
1841 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
1845 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1849 platform_set_drvdata(pdev, dev);
1851 mp = netdev_priv(dev);
1854 netif_napi_add(dev, &mp->napi, mv643xx_poll, 64);
1857 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1859 dev->irq = res->start;
1861 dev->open = mv643xx_eth_open;
1862 dev->stop = mv643xx_eth_stop;
1863 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1864 dev->set_mac_address = mv643xx_eth_set_mac_address;
1865 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1867 /* No need to Tx Timeout */
1868 dev->tx_timeout = mv643xx_eth_tx_timeout;
1870 #ifdef CONFIG_NET_POLL_CONTROLLER
1871 dev->poll_controller = mv643xx_netpoll;
1874 dev->watchdog_timeo = 2 * HZ;
1876 dev->change_mtu = mv643xx_eth_change_mtu;
1877 dev->do_ioctl = mv643xx_eth_do_ioctl;
1878 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1880 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1881 #ifdef MAX_SKB_FRAGS
1883 * Zero copy can only work if we use Discovery II memory. Else, we will
1884 * have to map the buffers to ISA memory which is only 16 MB
1886 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1890 /* Configure the timeout task */
1891 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
1893 spin_lock_init(&mp->lock);
1895 mp->shared = platform_get_drvdata(pd->shared);
1896 port_num = mp->port_num = pd->port_number;
1898 if (mp->shared->win_protect)
1899 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
1901 /* set default config values */
1902 eth_port_uc_addr_get(mp, dev->dev_addr);
1903 mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1904 mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1906 if (is_valid_ether_addr(pd->mac_addr))
1907 memcpy(dev->dev_addr, pd->mac_addr, 6);
1909 if (pd->phy_addr || pd->force_phy_addr)
1910 ethernet_phy_set(mp, pd->phy_addr);
1912 if (pd->rx_queue_size)
1913 mp->rx_ring_size = pd->rx_queue_size;
1915 if (pd->tx_queue_size)
1916 mp->tx_ring_size = pd->tx_queue_size;
1918 if (pd->tx_sram_size) {
1919 mp->tx_sram_size = pd->tx_sram_size;
1920 mp->tx_sram_addr = pd->tx_sram_addr;
1923 if (pd->rx_sram_size) {
1924 mp->rx_sram_size = pd->rx_sram_size;
1925 mp->rx_sram_addr = pd->rx_sram_addr;
1928 duplex = pd->duplex;
1931 /* Hook up MII support for ethtool */
1933 mp->mii.mdio_read = mv643xx_mdio_read;
1934 mp->mii.mdio_write = mv643xx_mdio_write;
1935 mp->mii.phy_id = ethernet_phy_get(mp);
1936 mp->mii.phy_id_mask = 0x3f;
1937 mp->mii.reg_num_mask = 0x1f;
1939 err = ethernet_phy_detect(mp);
1941 pr_debug("%s: No PHY detected at addr %d\n",
1942 dev->name, ethernet_phy_get(mp));
1946 ethernet_phy_reset(mp);
1947 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
1948 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
1949 mv643xx_eth_update_pscr(dev, &cmd);
1950 mv643xx_set_settings(dev, &cmd);
1952 SET_NETDEV_DEV(dev, &pdev->dev);
1953 err = register_netdev(dev);
1959 "%s: port %d with MAC address %s\n",
1960 dev->name, port_num, print_mac(mac, p));
1962 if (dev->features & NETIF_F_SG)
1963 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1965 if (dev->features & NETIF_F_IP_CSUM)
1966 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1969 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1970 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1974 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1979 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1982 if (mp->tx_sram_size > 0)
1983 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1993 static int mv643xx_eth_remove(struct platform_device *pdev)
1995 struct net_device *dev = platform_get_drvdata(pdev);
1997 unregister_netdev(dev);
1998 flush_scheduled_work();
2001 platform_set_drvdata(pdev, NULL);
2005 static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp,
2006 struct mbus_dram_target_info *dram)
2008 void __iomem *base = msp->eth_base;
2013 for (i = 0; i < 6; i++) {
2014 writel(0, base + WINDOW_BASE(i));
2015 writel(0, base + WINDOW_SIZE(i));
2017 writel(0, base + WINDOW_REMAP_HIGH(i));
2023 for (i = 0; i < dram->num_cs; i++) {
2024 struct mbus_dram_window *cs = dram->cs + i;
2026 writel((cs->base & 0xffff0000) |
2027 (cs->mbus_attr << 8) |
2028 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2029 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2031 win_enable &= ~(1 << i);
2032 win_protect |= 3 << (2 * i);
2035 writel(win_enable, base + WINDOW_BAR_ENABLE);
2036 msp->win_protect = win_protect;
2039 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2041 static int mv643xx_version_printed = 0;
2042 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2043 struct mv643xx_shared_private *msp;
2044 struct resource *res;
2047 if (!mv643xx_version_printed++)
2048 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2051 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2056 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2059 memset(msp, 0, sizeof(*msp));
2061 msp->eth_base = ioremap(res->start, res->end - res->start + 1);
2062 if (msp->eth_base == NULL)
2065 spin_lock_init(&msp->phy_lock);
2067 platform_set_drvdata(pdev, msp);
2070 * (Re-)program MBUS remapping windows if we are asked to.
2072 if (pd != NULL && pd->dram != NULL)
2073 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2083 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2085 struct mv643xx_shared_private *msp = platform_get_drvdata(pdev);
2087 iounmap(msp->eth_base);
2093 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2095 struct net_device *dev = platform_get_drvdata(pdev);
2096 struct mv643xx_private *mp = netdev_priv(dev);
2097 unsigned int port_num = mp->port_num;
2099 /* Mask all interrupts on ethernet port */
2100 wrl(mp, INTERRUPT_MASK_REG(port_num), 0);
2101 rdl(mp, INTERRUPT_MASK_REG(port_num));
2106 static struct platform_driver mv643xx_eth_driver = {
2107 .probe = mv643xx_eth_probe,
2108 .remove = mv643xx_eth_remove,
2109 .shutdown = mv643xx_eth_shutdown,
2111 .name = MV643XX_ETH_NAME,
2112 .owner = THIS_MODULE,
2116 static struct platform_driver mv643xx_eth_shared_driver = {
2117 .probe = mv643xx_eth_shared_probe,
2118 .remove = mv643xx_eth_shared_remove,
2120 .name = MV643XX_ETH_SHARED_NAME,
2121 .owner = THIS_MODULE,
2126 * mv643xx_init_module
2128 * Registers the network drivers into the Linux kernel
2134 static int __init mv643xx_init_module(void)
2138 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2140 rc = platform_driver_register(&mv643xx_eth_driver);
2142 platform_driver_unregister(&mv643xx_eth_shared_driver);
2148 * mv643xx_cleanup_module
2150 * Registers the network drivers into the Linux kernel
2156 static void __exit mv643xx_cleanup_module(void)
2158 platform_driver_unregister(&mv643xx_eth_driver);
2159 platform_driver_unregister(&mv643xx_eth_shared_driver);
2162 module_init(mv643xx_init_module);
2163 module_exit(mv643xx_cleanup_module);
2165 MODULE_LICENSE("GPL");
2166 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
2167 " and Dale Farnsworth");
2168 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2169 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
2170 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2173 * The second part is the low level driver of the gigE ethernet ports.
2177 * Marvell's Gigabit Ethernet controller low level driver
2180 * This file introduce low level API to Marvell's Gigabit Ethernet
2181 * controller. This Gigabit Ethernet Controller driver API controls
2182 * 1) Operations (i.e. port init, start, reset etc').
2183 * 2) Data flow (i.e. port send, receive etc').
2184 * Each Gigabit Ethernet port is controlled via
2185 * struct mv643xx_private.
2186 * This struct includes user configuration information as well as
2187 * driver internal data needed for its operations.
2189 * Supported Features:
2190 * - This low level driver is OS independent. Allocating memory for
2191 * the descriptor rings and buffers are not within the scope of
2193 * - The user is free from Rx/Tx queue managing.
2194 * - This low level driver introduce functionality API that enable
2195 * the to operate Marvell's Gigabit Ethernet Controller in a
2197 * - Simple Gigabit Ethernet port operation API.
2198 * - Simple Gigabit Ethernet port data flow API.
2199 * - Data flow and operation API support per queue functionality.
2200 * - Support cached descriptors for better performance.
2201 * - Enable access to all four DRAM banks and internal SRAM memory
2203 * - PHY access and control API.
2204 * - Port control register configuration API.
2205 * - Full control over Unicast and Multicast MAC configurations.
2209 * Initialization phase
2210 * This phase complete the initialization of the the
2211 * mv643xx_private struct.
2212 * User information regarding port configuration has to be set
2213 * prior to calling the port initialization routine.
2215 * In this phase any port Tx/Rx activity is halted, MIB counters
2216 * are cleared, PHY address is set according to user parameter and
2217 * access to DRAM and internal SRAM memory spaces.
2219 * Driver ring initialization
2220 * Allocating memory for the descriptor rings and buffers is not
2221 * within the scope of this driver. Thus, the user is required to
2222 * allocate memory for the descriptors ring and buffers. Those
2223 * memory parameters are used by the Rx and Tx ring initialization
2224 * routines in order to curve the descriptor linked list in a form
2226 * Note: Pay special attention to alignment issues when using
2227 * cached descriptors/buffers. In this phase the driver store
2228 * information in the mv643xx_private struct regarding each queue
2232 * This phase prepares the Ethernet port for Rx and Tx activity.
2233 * It uses the information stored in the mv643xx_private struct to
2234 * initialize the various port registers.
2237 * All packet references to/from the driver are done using
2239 * This struct is a unified struct used with Rx and Tx operations.
2240 * This way the user is not required to be familiar with neither
2241 * Tx nor Rx descriptors structures.
2242 * The driver's descriptors rings are management by indexes.
2243 * Those indexes controls the ring resources and used to indicate
2244 * a SW resource error:
2246 * This index points to the current available resource for use. For
2247 * example in Rx process this index will point to the descriptor
2248 * that will be passed to the user upon calling the receive
2249 * routine. In Tx process, this index will point to the descriptor
2250 * that will be assigned with the user packet info and transmitted.
2252 * This index points to the descriptor that need to restore its
2253 * resources. For example in Rx process, using the Rx buffer return
2254 * API will attach the buffer returned in packet info to the
2255 * descriptor pointed by 'used'. In Tx process, using the Tx
2256 * descriptor return will merely return the user packet info with
2257 * the command status of the transmitted buffer pointed by the
2258 * 'used' index. Nevertheless, it is essential to use this routine
2259 * to update the 'used' index.
2261 * This index supports Tx Scatter-Gather. It points to the first
2262 * descriptor of a packet assembled of multiple buffers. For
2263 * example when in middle of Such packet we have a Tx resource
2264 * error the 'curr' index get the value of 'first' to indicate
2265 * that the ring returned to its state before trying to transmit
2268 * Receive operation:
2269 * The eth_port_receive API set the packet information struct,
2270 * passed by the caller, with received information from the
2271 * 'current' SDMA descriptor.
2272 * It is the user responsibility to return this resource back
2273 * to the Rx descriptor ring to enable the reuse of this source.
2274 * Return Rx resource is done using the eth_rx_return_buff API.
2276 * Prior to calling the initialization routine eth_port_init() the user
2277 * must set the following fields under mv643xx_private struct:
2278 * port_num User Ethernet port number.
2279 * port_config User port configuration value.
2280 * port_config_extend User port config extend value.
2281 * port_sdma_config User port SDMA config value.
2282 * port_serial_control User port serial control value.
2284 * This driver data flow is done using the struct pkt_info which
2285 * is a unified struct for Rx and Tx operations:
2287 * byte_cnt Tx/Rx descriptor buffer byte count.
2288 * l4i_chk CPU provided TCP Checksum. For Tx operation
2290 * cmd_sts Tx/Rx descriptor command status.
2291 * buf_ptr Tx/Rx descriptor buffer pointer.
2292 * return_info Tx/Rx user resource return information.
2295 /* Ethernet Port routines */
2296 static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
2297 int table, unsigned char entry);
2300 * eth_port_init - Initialize the Ethernet port driver
2303 * This function prepares the ethernet port to start its activity:
2304 * 1) Completes the ethernet port driver struct initialization toward port
2306 * 2) Resets the device to a quiescent state in case of warm reboot.
2307 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
2308 * 4) Clean MAC tables. The reset status of those tables is unknown.
2309 * 5) Set PHY address.
2310 * Note: Call this routine prior to eth_port_start routine and after
2311 * setting user values in the user fields of Ethernet port control
2315 * struct mv643xx_private *mp Ethernet port control struct
2323 static void eth_port_init(struct mv643xx_private *mp)
2325 mp->rx_resource_err = 0;
2329 eth_port_init_mac_tables(mp);
2333 * eth_port_start - Start the Ethernet port activity.
2336 * This routine prepares the Ethernet port for Rx and Tx activity:
2337 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
2338 * has been initialized a descriptor's ring (using
2339 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
2340 * 2. Initialize and enable the Ethernet configuration port by writing to
2341 * the port's configuration and command registers.
2342 * 3. Initialize and enable the SDMA by writing to the SDMA's
2343 * configuration and command registers. After completing these steps,
2344 * the ethernet port SDMA can starts to perform Rx and Tx activities.
2346 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
2347 * to calling this function (use ether_init_tx_desc_ring for Tx queues
2348 * and ether_init_rx_desc_ring for Rx queues).
2351 * dev - a pointer to the required interface
2354 * Ethernet port is ready to receive and transmit.
2359 static void eth_port_start(struct net_device *dev)
2361 struct mv643xx_private *mp = netdev_priv(dev);
2362 unsigned int port_num = mp->port_num;
2363 int tx_curr_desc, rx_curr_desc;
2365 struct ethtool_cmd ethtool_cmd;
2367 /* Assignment of Tx CTRP of given queue */
2368 tx_curr_desc = mp->tx_curr_desc_q;
2369 wrl(mp, TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2370 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
2372 /* Assignment of Rx CRDP of given queue */
2373 rx_curr_desc = mp->rx_curr_desc_q;
2374 wrl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2375 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
2377 /* Add the assigned Ethernet address to the port's address table */
2378 eth_port_uc_addr_set(mp, dev->dev_addr);
2380 /* Assign port configuration and command. */
2381 wrl(mp, PORT_CONFIG_REG(port_num),
2382 PORT_CONFIG_DEFAULT_VALUE);
2384 wrl(mp, PORT_CONFIG_EXTEND_REG(port_num),
2385 PORT_CONFIG_EXTEND_DEFAULT_VALUE);
2387 pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num));
2389 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
2390 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr);
2392 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
2393 DISABLE_AUTO_NEG_SPEED_GMII |
2394 DISABLE_AUTO_NEG_FOR_DUPLX |
2395 DO_NOT_FORCE_LINK_FAIL |
2396 SERIAL_PORT_CONTROL_RESERVED;
2398 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr);
2400 pscr |= SERIAL_PORT_ENABLE;
2401 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr);
2403 /* Assign port SDMA configuration */
2404 wrl(mp, SDMA_CONFIG_REG(port_num),
2405 PORT_SDMA_CONFIG_DEFAULT_VALUE);
2407 /* Enable port Rx. */
2408 mv643xx_eth_port_enable_rx(mp, ETH_RX_QUEUES_ENABLED);
2410 /* Disable port bandwidth limits by clearing MTU register */
2411 wrl(mp, MAXIMUM_TRANSMIT_UNIT(port_num), 0);
2413 /* save phy settings across reset */
2414 mv643xx_get_settings(dev, ðtool_cmd);
2415 ethernet_phy_reset(mp);
2416 mv643xx_set_settings(dev, ðtool_cmd);
2420 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
2422 static void eth_port_uc_addr_set(struct mv643xx_private *mp,
2423 unsigned char *p_addr)
2425 unsigned int port_num = mp->port_num;
2430 mac_l = (p_addr[4] << 8) | (p_addr[5]);
2431 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
2434 wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
2435 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
2437 /* Accept frames with this address */
2438 table = DA_FILTER_UNICAST_TABLE_BASE(port_num);
2439 eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f);
2443 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
2445 static void eth_port_uc_addr_get(struct mv643xx_private *mp,
2446 unsigned char *p_addr)
2448 unsigned int port_num = mp->port_num;
2452 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
2453 mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
2455 p_addr[0] = (mac_h >> 24) & 0xff;
2456 p_addr[1] = (mac_h >> 16) & 0xff;
2457 p_addr[2] = (mac_h >> 8) & 0xff;
2458 p_addr[3] = mac_h & 0xff;
2459 p_addr[4] = (mac_l >> 8) & 0xff;
2460 p_addr[5] = mac_l & 0xff;
2464 * The entries in each table are indexed by a hash of a packet's MAC
2465 * address. One bit in each entry determines whether the packet is
2466 * accepted. There are 4 entries (each 8 bits wide) in each register
2467 * of the table. The bits in each entry are defined as follows:
2468 * 0 Accept=1, Drop=0
2469 * 3-1 Queue (ETH_Q0=0)
2472 static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
2473 int table, unsigned char entry)
2475 unsigned int table_reg;
2476 unsigned int tbl_offset;
2477 unsigned int reg_offset;
2479 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
2480 reg_offset = entry % 4; /* Entry offset within the register */
2482 /* Set "accepts frame bit" at specified table entry */
2483 table_reg = rdl(mp, table + tbl_offset);
2484 table_reg |= 0x01 << (8 * reg_offset);
2485 wrl(mp, table + tbl_offset, table_reg);
2489 * eth_port_mc_addr - Multicast address settings.
2491 * The MV device supports multicast using two tables:
2492 * 1) Special Multicast Table for MAC addresses of the form
2493 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2494 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2495 * Table entries in the DA-Filter table.
2496 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2497 * is used as an index to the Other Multicast Table entries in the
2498 * DA-Filter table. This function calculates the CRC-8bit value.
2499 * In either case, eth_port_set_filter_table_entry() is then called
2500 * to set to set the actual table entry.
2502 static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr)
2504 unsigned int port_num = mp->port_num;
2507 unsigned char crc_result = 0;
2513 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
2514 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
2515 table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num);
2516 eth_port_set_filter_table_entry(mp, table, p_addr[5]);
2520 /* Calculate CRC-8 out of the given address */
2521 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2522 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2523 (p_addr[4] << 8) | (p_addr[5] << 0);
2525 for (i = 0; i < 32; i++)
2526 mac_array[i] = (mac_l >> i) & 0x1;
2527 for (i = 32; i < 48; i++)
2528 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2530 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2531 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2532 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2533 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2534 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2536 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2537 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2538 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2539 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2540 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2541 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2542 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2544 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2545 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2546 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2547 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2548 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2549 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2551 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2552 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2553 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2554 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2555 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2556 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2558 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2559 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2560 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2561 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2562 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2563 mac_array[3] ^ mac_array[2];
2565 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2566 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2567 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2568 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2569 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2570 mac_array[4] ^ mac_array[3];
2572 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2573 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2574 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2575 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2576 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2579 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2580 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2581 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2582 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2583 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2585 for (i = 0; i < 8; i++)
2586 crc_result = crc_result | (crc[i] << i);
2588 table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num);
2589 eth_port_set_filter_table_entry(mp, table, crc_result);
2593 * Set the entire multicast list based on dev->mc_list.
2595 static void eth_port_set_multicast_list(struct net_device *dev)
2598 struct dev_mc_list *mc_list;
2601 struct mv643xx_private *mp = netdev_priv(dev);
2602 unsigned int eth_port_num = mp->port_num;
2604 /* If the device is in promiscuous mode or in all multicast mode,
2605 * we will fully populate both multicast tables with accept.
2606 * This is guaranteed to yield a match on all multicast addresses...
2608 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2609 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2610 /* Set all entries in DA filter special multicast
2612 * Set for ETH_Q0 for now
2614 * 0 Accept=1, Drop=0
2615 * 3-1 Queue ETH_Q0=0
2618 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2620 /* Set all entries in DA filter other multicast
2622 * Set for ETH_Q0 for now
2624 * 0 Accept=1, Drop=0
2625 * 3-1 Queue ETH_Q0=0
2628 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2633 /* We will clear out multicast tables every time we get the list.
2634 * Then add the entire new list...
2636 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2637 /* Clear DA filter special multicast table (Ex_dFSMT) */
2638 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2639 (eth_port_num) + table_index, 0);
2641 /* Clear DA filter other multicast table (Ex_dFOMT) */
2642 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2643 (eth_port_num) + table_index, 0);
2646 /* Get pointer to net_device multicast list and add each one... */
2647 for (i = 0, mc_list = dev->mc_list;
2648 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2649 i++, mc_list = mc_list->next)
2650 if (mc_list->dmi_addrlen == 6)
2651 eth_port_mc_addr(mp, mc_list->dmi_addr);
2655 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2658 * Go through all the DA filter tables (Unicast, Special Multicast &
2659 * Other Multicast) and set each entry to 0.
2662 * struct mv643xx_private *mp Ethernet Port.
2665 * Multicast and Unicast packets are rejected.
2670 static void eth_port_init_mac_tables(struct mv643xx_private *mp)
2672 unsigned int port_num = mp->port_num;
2675 /* Clear DA filter unicast table (Ex_dFUT) */
2676 for (table_index = 0; table_index <= 0xC; table_index += 4)
2677 wrl(mp, DA_FILTER_UNICAST_TABLE_BASE(port_num) +
2680 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2681 /* Clear DA filter special multicast table (Ex_dFSMT) */
2682 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num) +
2684 /* Clear DA filter other multicast table (Ex_dFOMT) */
2685 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num) +
2691 * eth_clear_mib_counters - Clear all MIB counters
2694 * This function clears all MIB counters of a specific ethernet port.
2695 * A read from the MIB counter will reset the counter.
2698 * struct mv643xx_private *mp Ethernet Port.
2701 * After reading all MIB counters, the counters resets.
2704 * MIB counter value.
2707 static void eth_clear_mib_counters(struct mv643xx_private *mp)
2709 unsigned int port_num = mp->port_num;
2712 /* Perform dummy reads from MIB counters */
2713 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2715 rdl(mp, MIB_COUNTERS_BASE(port_num) + i);
2718 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2720 return rdl(mp, MIB_COUNTERS_BASE(mp->port_num) + offset);
2723 static void eth_update_mib_counters(struct mv643xx_private *mp)
2725 struct mv643xx_mib_counters *p = &mp->mib_counters;
2728 p->good_octets_received +=
2729 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2730 p->good_octets_received +=
2731 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2733 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2734 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2736 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
2738 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2739 p->good_octets_sent +=
2740 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2742 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2743 offset <= ETH_MIB_LATE_COLLISION;
2745 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
2749 * ethernet_phy_detect - Detect whether a phy is present
2752 * This function tests whether there is a PHY present on
2753 * the specified port.
2756 * struct mv643xx_private *mp Ethernet Port.
2763 * -ENODEV on failure
2766 static int ethernet_phy_detect(struct mv643xx_private *mp)
2768 unsigned int phy_reg_data0;
2771 eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
2772 auto_neg = phy_reg_data0 & 0x1000;
2773 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2774 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2776 eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
2777 if ((phy_reg_data0 & 0x1000) == auto_neg)
2778 return -ENODEV; /* change didn't take */
2780 phy_reg_data0 ^= 0x1000;
2781 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2786 * ethernet_phy_get - Get the ethernet port PHY address.
2789 * This routine returns the given ethernet port PHY address.
2792 * struct mv643xx_private *mp Ethernet Port.
2801 static int ethernet_phy_get(struct mv643xx_private *mp)
2803 unsigned int reg_data;
2805 reg_data = rdl(mp, PHY_ADDR_REG);
2807 return ((reg_data >> (5 * mp->port_num)) & 0x1f);
2811 * ethernet_phy_set - Set the ethernet port PHY address.
2814 * This routine sets the given ethernet port PHY address.
2817 * struct mv643xx_private *mp Ethernet Port.
2818 * int phy_addr PHY address.
2827 static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr)
2830 int addr_shift = 5 * mp->port_num;
2832 reg_data = rdl(mp, PHY_ADDR_REG);
2833 reg_data &= ~(0x1f << addr_shift);
2834 reg_data |= (phy_addr & 0x1f) << addr_shift;
2835 wrl(mp, PHY_ADDR_REG, reg_data);
2839 * ethernet_phy_reset - Reset Ethernet port PHY.
2842 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2845 * struct mv643xx_private *mp Ethernet Port.
2854 static void ethernet_phy_reset(struct mv643xx_private *mp)
2856 unsigned int phy_reg_data;
2859 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2860 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2861 eth_port_write_smi_reg(mp, 0, phy_reg_data);
2863 /* wait for PHY to come out of reset */
2866 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2867 } while (phy_reg_data & 0x8000);
2870 static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
2871 unsigned int queues)
2873 wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(mp->port_num), queues);
2876 static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
2877 unsigned int queues)
2879 wrl(mp, RECEIVE_QUEUE_COMMAND_REG(mp->port_num), queues);
2882 static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp)
2884 unsigned int port_num = mp->port_num;
2887 /* Stop Tx port activity. Check port Tx activity. */
2888 queues = rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF;
2890 /* Issue stop command for active queues only */
2891 wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8));
2893 /* Wait for all Tx activity to terminate. */
2894 /* Check port cause register that all Tx queues are stopped */
2895 while (rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2896 udelay(PHY_WAIT_MICRO_SECONDS);
2898 /* Wait for Tx FIFO to empty */
2899 while (rdl(mp, PORT_STATUS_REG(port_num)) &
2900 ETH_PORT_TX_FIFO_EMPTY)
2901 udelay(PHY_WAIT_MICRO_SECONDS);
2907 static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp)
2909 unsigned int port_num = mp->port_num;
2912 /* Stop Rx port activity. Check port Rx activity. */
2913 queues = rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF;
2915 /* Issue stop command for active queues only */
2916 wrl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8));
2918 /* Wait for all Rx activity to terminate. */
2919 /* Check port cause register that all Rx queues are stopped */
2920 while (rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2921 udelay(PHY_WAIT_MICRO_SECONDS);
2928 * eth_port_reset - Reset Ethernet port
2931 * This routine resets the chip by aborting any SDMA engine activity and
2932 * clearing the MIB counters. The Receiver and the Transmit unit are in
2933 * idle state after this command is performed and the port is disabled.
2936 * struct mv643xx_private *mp Ethernet Port.
2939 * Channel activity is halted.
2945 static void eth_port_reset(struct mv643xx_private *mp)
2947 unsigned int port_num = mp->port_num;
2948 unsigned int reg_data;
2950 mv643xx_eth_port_disable_tx(mp);
2951 mv643xx_eth_port_disable_rx(mp);
2953 /* Clear all MIB counters */
2954 eth_clear_mib_counters(mp);
2956 /* Reset the Enable bit in the Configuration Register */
2957 reg_data = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num));
2958 reg_data &= ~(SERIAL_PORT_ENABLE |
2959 DO_NOT_FORCE_LINK_FAIL |
2961 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2966 * eth_port_read_smi_reg - Read PHY registers
2969 * This routine utilize the SMI interface to interact with the PHY in
2970 * order to perform PHY register read.
2973 * struct mv643xx_private *mp Ethernet Port.
2974 * unsigned int phy_reg PHY register address offset.
2975 * unsigned int *value Register value buffer.
2978 * Write the value of a specified PHY register into given buffer.
2981 * false if the PHY is busy or read data is not in valid state.
2985 static void eth_port_read_smi_reg(struct mv643xx_private *mp,
2986 unsigned int phy_reg, unsigned int *value)
2988 int phy_addr = ethernet_phy_get(mp);
2989 unsigned long flags;
2992 /* the SMI register is a shared resource */
2993 spin_lock_irqsave(&mp->shared->phy_lock, flags);
2995 /* wait for the SMI register to become available */
2996 for (i = 0; rdl(mp, SMI_REG) & ETH_SMI_BUSY; i++) {
2997 if (i == PHY_WAIT_ITERATIONS) {
2998 printk("%s: PHY busy timeout\n", mp->dev->name);
3001 udelay(PHY_WAIT_MICRO_SECONDS);
3005 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
3007 /* now wait for the data to be valid */
3008 for (i = 0; !(rdl(mp, SMI_REG) & ETH_SMI_READ_VALID); i++) {
3009 if (i == PHY_WAIT_ITERATIONS) {
3010 printk("%s: PHY read timeout\n", mp->dev->name);
3013 udelay(PHY_WAIT_MICRO_SECONDS);
3016 *value = rdl(mp, SMI_REG) & 0xffff;
3018 spin_unlock_irqrestore(&mp->shared->phy_lock, flags);
3022 * eth_port_write_smi_reg - Write to PHY registers
3025 * This routine utilize the SMI interface to interact with the PHY in
3026 * order to perform writes to PHY registers.
3029 * struct mv643xx_private *mp Ethernet Port.
3030 * unsigned int phy_reg PHY register address offset.
3031 * unsigned int value Register value.
3034 * Write the given value to the specified PHY register.
3037 * false if the PHY is busy.
3041 static void eth_port_write_smi_reg(struct mv643xx_private *mp,
3042 unsigned int phy_reg, unsigned int value)
3046 unsigned long flags;
3048 phy_addr = ethernet_phy_get(mp);
3050 /* the SMI register is a shared resource */
3051 spin_lock_irqsave(&mp->shared->phy_lock, flags);
3053 /* wait for the SMI register to become available */
3054 for (i = 0; rdl(mp, SMI_REG) & ETH_SMI_BUSY; i++) {
3055 if (i == PHY_WAIT_ITERATIONS) {
3056 printk("%s: PHY busy timeout\n", mp->dev->name);
3059 udelay(PHY_WAIT_MICRO_SECONDS);
3062 wrl(mp, SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
3063 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
3065 spin_unlock_irqrestore(&mp->shared->phy_lock, flags);
3069 * Wrappers for MII support library.
3071 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
3073 struct mv643xx_private *mp = netdev_priv(dev);
3076 eth_port_read_smi_reg(mp, location, &val);
3080 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
3082 struct mv643xx_private *mp = netdev_priv(dev);
3083 eth_port_write_smi_reg(mp, location, val);
3087 * eth_port_receive - Get received information from Rx ring.
3090 * This routine returns the received data to the caller. There is no
3091 * data copying during routine operation. All information is returned
3092 * using pointer to packet information struct passed from the caller.
3093 * If the routine exhausts Rx ring resources then the resource error flag
3097 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3098 * struct pkt_info *p_pkt_info User packet buffer.
3101 * Rx ring current and used indexes are updated.
3104 * ETH_ERROR in case the routine can not access Rx desc ring.
3105 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
3106 * ETH_END_OF_JOB if there is no received data.
3109 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
3110 struct pkt_info *p_pkt_info)
3112 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
3113 volatile struct eth_rx_desc *p_rx_desc;
3114 unsigned int command_status;
3115 unsigned long flags;
3117 /* Do not process Rx ring in case of Rx ring resource error */
3118 if (mp->rx_resource_err)
3119 return ETH_QUEUE_FULL;
3121 spin_lock_irqsave(&mp->lock, flags);
3123 /* Get the Rx Desc ring 'curr and 'used' indexes */
3124 rx_curr_desc = mp->rx_curr_desc_q;
3125 rx_used_desc = mp->rx_used_desc_q;
3127 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
3129 /* The following parameters are used to save readings from memory */
3130 command_status = p_rx_desc->cmd_sts;
3133 /* Nothing to receive... */
3134 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
3135 spin_unlock_irqrestore(&mp->lock, flags);
3136 return ETH_END_OF_JOB;
3139 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
3140 p_pkt_info->cmd_sts = command_status;
3141 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
3142 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
3143 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
3146 * Clean the return info field to indicate that the
3147 * packet has been moved to the upper layers
3149 mp->rx_skb[rx_curr_desc] = NULL;
3151 /* Update current index in data structure */
3152 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
3153 mp->rx_curr_desc_q = rx_next_curr_desc;
3155 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
3156 if (rx_next_curr_desc == rx_used_desc)
3157 mp->rx_resource_err = 1;
3159 spin_unlock_irqrestore(&mp->lock, flags);
3165 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
3168 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
3169 * next 'used' descriptor and attached the returned buffer to it.
3170 * In case the Rx ring was in "resource error" condition, where there are
3171 * no available Rx resources, the function resets the resource error flag.
3174 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3175 * struct pkt_info *p_pkt_info Information on returned buffer.
3178 * New available Rx resource in Rx descriptor ring.
3181 * ETH_ERROR in case the routine can not access Rx desc ring.
3184 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
3185 struct pkt_info *p_pkt_info)
3187 int used_rx_desc; /* Where to return Rx resource */
3188 volatile struct eth_rx_desc *p_used_rx_desc;
3189 unsigned long flags;
3191 spin_lock_irqsave(&mp->lock, flags);
3193 /* Get 'used' Rx descriptor */
3194 used_rx_desc = mp->rx_used_desc_q;
3195 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
3197 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
3198 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
3199 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
3201 /* Flush the write pipe */
3203 /* Return the descriptor to DMA ownership */
3205 p_used_rx_desc->cmd_sts =
3206 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3209 /* Move the used descriptor pointer to the next descriptor */
3210 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
3212 /* Any Rx return cancels the Rx resource error status */
3213 mp->rx_resource_err = 0;
3215 spin_unlock_irqrestore(&mp->lock, flags);
3220 /************* Begin ethtool support *************************/
3222 struct mv643xx_stats {
3223 char stat_string[ETH_GSTRING_LEN];
3228 #define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \
3229 offsetof(struct mv643xx_private, m)
3231 static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
3232 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
3233 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
3234 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
3235 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
3236 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
3237 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
3238 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
3239 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
3240 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
3241 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
3242 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
3243 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
3244 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
3245 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
3246 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
3247 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
3248 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
3249 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
3250 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
3251 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
3252 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
3253 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
3254 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
3255 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
3256 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
3257 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
3258 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
3259 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
3260 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
3261 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
3262 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
3263 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
3264 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
3265 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
3266 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
3267 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
3268 { "collision", MV643XX_STAT(mib_counters.collision) },
3269 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
3272 #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats)
3274 static void mv643xx_get_drvinfo(struct net_device *netdev,
3275 struct ethtool_drvinfo *drvinfo)
3277 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3278 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3279 strncpy(drvinfo->fw_version, "N/A", 32);
3280 strncpy(drvinfo->bus_info, "mv643xx", 32);
3281 drvinfo->n_stats = MV643XX_STATS_LEN;
3284 static int mv643xx_get_sset_count(struct net_device *netdev, int sset)
3288 return MV643XX_STATS_LEN;
3294 static void mv643xx_get_ethtool_stats(struct net_device *netdev,
3295 struct ethtool_stats *stats, uint64_t *data)
3297 struct mv643xx_private *mp = netdev->priv;
3300 eth_update_mib_counters(mp);
3302 for (i = 0; i < MV643XX_STATS_LEN; i++) {
3303 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
3304 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
3305 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3309 static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
3316 for (i=0; i < MV643XX_STATS_LEN; i++) {
3317 memcpy(data + i * ETH_GSTRING_LEN,
3318 mv643xx_gstrings_stats[i].stat_string,
3325 static u32 mv643xx_eth_get_link(struct net_device *dev)
3327 struct mv643xx_private *mp = netdev_priv(dev);
3329 return mii_link_ok(&mp->mii);
3332 static int mv643xx_eth_nway_restart(struct net_device *dev)
3334 struct mv643xx_private *mp = netdev_priv(dev);
3336 return mii_nway_restart(&mp->mii);
3339 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3341 struct mv643xx_private *mp = netdev_priv(dev);
3343 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
3346 static const struct ethtool_ops mv643xx_ethtool_ops = {
3347 .get_settings = mv643xx_get_settings,
3348 .set_settings = mv643xx_set_settings,
3349 .get_drvinfo = mv643xx_get_drvinfo,
3350 .get_link = mv643xx_eth_get_link,
3351 .set_sg = ethtool_op_set_sg,
3352 .get_sset_count = mv643xx_get_sset_count,
3353 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3354 .get_strings = mv643xx_get_strings,
3355 .nway_reset = mv643xx_eth_nway_restart,
3358 /************* End ethtool support *************************/