2 * Copyright (C) 1995 Linus Torvalds
6 * This file handles the architecture-dependent parts of initialization
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/a.out.h>
19 #include <linux/screen_info.h>
20 #include <linux/ioport.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/initrd.h>
24 #include <linux/highmem.h>
25 #include <linux/bootmem.h>
26 #include <linux/module.h>
27 #include <asm/processor.h>
28 #include <linux/console.h>
29 #include <linux/seq_file.h>
30 #include <linux/crash_dump.h>
31 #include <linux/root_dev.h>
32 #include <linux/pci.h>
33 #include <linux/acpi.h>
34 #include <linux/kallsyms.h>
35 #include <linux/edd.h>
36 #include <linux/mmzone.h>
37 #include <linux/kexec.h>
38 #include <linux/cpufreq.h>
39 #include <linux/dmi.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/ctype.h>
44 #include <asm/uaccess.h>
45 #include <asm/system.h>
50 #include <video/edid.h>
53 #include <asm/mpspec.h>
54 #include <asm/mmu_context.h>
55 #include <asm/bootsetup.h>
56 #include <asm/proto.h>
57 #include <asm/setup.h>
58 #include <asm/mach_apic.h>
60 #include <asm/sections.h>
67 struct cpuinfo_x86 boot_cpu_data __read_mostly;
68 EXPORT_SYMBOL(boot_cpu_data);
70 unsigned long mmu_cr4_features;
72 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
75 unsigned long saved_video_mode;
77 int force_mwait __cpuinitdata;
83 char dmi_alloc_data[DMI_MAX_DATA];
88 struct screen_info screen_info;
89 EXPORT_SYMBOL(screen_info);
90 struct sys_desc_table_struct {
91 unsigned short length;
92 unsigned char table[0];
95 struct edid_info edid_info;
96 EXPORT_SYMBOL_GPL(edid_info);
98 extern int root_mountflags;
100 char __initdata command_line[COMMAND_LINE_SIZE];
102 struct resource standard_io_resources[] = {
103 { .name = "dma1", .start = 0x00, .end = 0x1f,
104 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
105 { .name = "pic1", .start = 0x20, .end = 0x21,
106 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
107 { .name = "timer0", .start = 0x40, .end = 0x43,
108 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
109 { .name = "timer1", .start = 0x50, .end = 0x53,
110 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
111 { .name = "keyboard", .start = 0x60, .end = 0x6f,
112 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
113 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
114 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
115 { .name = "pic2", .start = 0xa0, .end = 0xa1,
116 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
117 { .name = "dma2", .start = 0xc0, .end = 0xdf,
118 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
119 { .name = "fpu", .start = 0xf0, .end = 0xff,
120 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
123 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
125 struct resource data_resource = {
126 .name = "Kernel data",
129 .flags = IORESOURCE_RAM,
131 struct resource code_resource = {
132 .name = "Kernel code",
135 .flags = IORESOURCE_RAM,
138 #ifdef CONFIG_PROC_VMCORE
139 /* elfcorehdr= specifies the location of elf core header
140 * stored by the crashed kernel. This option will be passed
141 * by kexec loader to the capture kernel.
143 static int __init setup_elfcorehdr(char *arg)
148 elfcorehdr_addr = memparse(arg, &end);
149 return end > arg ? 0 : -EINVAL;
151 early_param("elfcorehdr", setup_elfcorehdr);
156 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
158 unsigned long bootmap_size, bootmap;
160 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
161 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
163 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
164 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
165 e820_register_active_regions(0, start_pfn, end_pfn);
166 free_bootmem_with_active_regions(0, end_pfn);
167 reserve_bootmem(bootmap, bootmap_size);
171 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
173 #ifdef CONFIG_EDD_MODULE
177 * copy_edd() - Copy the BIOS EDD information
178 * from boot_params into a safe place.
181 static inline void copy_edd(void)
183 memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
184 memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
185 edd.mbr_signature_nr = EDD_MBR_SIG_NR;
186 edd.edd_info_nr = EDD_NR;
189 static inline void copy_edd(void)
194 #define EBDA_ADDR_POINTER 0x40E
196 unsigned __initdata ebda_addr;
197 unsigned __initdata ebda_size;
199 static void discover_ebda(void)
202 * there is a real-mode segmented pointer pointing to the
203 * 4K EBDA area at 0x40E
205 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
208 ebda_size = *(unsigned short *)__va(ebda_addr);
210 /* Round EBDA up to pages */
214 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
215 if (ebda_size > 64*1024)
219 void __init setup_arch(char **cmdline_p)
221 printk(KERN_INFO "Command line: %s\n", boot_command_line);
223 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
224 screen_info = SCREEN_INFO;
225 edid_info = EDID_INFO;
226 saved_video_mode = SAVED_VIDEO_MODE;
227 bootloader_type = LOADER_TYPE;
229 #ifdef CONFIG_BLK_DEV_RAM
230 rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
231 rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
232 rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
234 setup_memory_region();
237 if (!MOUNT_ROOT_RDONLY)
238 root_mountflags &= ~MS_RDONLY;
239 init_mm.start_code = (unsigned long) &_text;
240 init_mm.end_code = (unsigned long) &_etext;
241 init_mm.end_data = (unsigned long) &_edata;
242 init_mm.brk = (unsigned long) &_end;
244 code_resource.start = virt_to_phys(&_text);
245 code_resource.end = virt_to_phys(&_etext)-1;
246 data_resource.start = virt_to_phys(&_etext);
247 data_resource.end = virt_to_phys(&_edata)-1;
249 early_identify_cpu(&boot_cpu_data);
251 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
252 *cmdline_p = command_line;
256 finish_e820_parsing();
258 e820_register_active_regions(0, 0, -1UL);
260 * partially used pages are not usable - thus
261 * we are rounding upwards:
263 end_pfn = e820_end_of_ram();
264 num_physpages = end_pfn;
270 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
276 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
277 * Call this early for SRAT node setup.
279 acpi_boot_table_init();
282 /* How many end-of-memory variables you have, grandma! */
283 max_low_pfn = end_pfn;
285 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
287 /* Remove active ranges so rediscovery with NUMA-awareness happens */
288 remove_all_active_ranges();
290 #ifdef CONFIG_ACPI_NUMA
292 * Parse SRAT to discover nodes.
298 numa_initmem_init(0, end_pfn);
300 contig_initmem_init(0, end_pfn);
303 /* Reserve direct mapping */
304 reserve_bootmem_generic(table_start << PAGE_SHIFT,
305 (table_end - table_start) << PAGE_SHIFT);
308 reserve_bootmem_generic(__pa_symbol(&_text),
309 __pa_symbol(&_end) - __pa_symbol(&_text));
312 * reserve physical page 0 - it's a special BIOS page on many boxes,
313 * enabling clean reboots, SMP operation, laptop functions.
315 reserve_bootmem_generic(0, PAGE_SIZE);
317 /* reserve ebda region */
319 reserve_bootmem_generic(ebda_addr, ebda_size);
321 /* reserve nodemap region */
323 reserve_bootmem_generic(nodemap_addr, nodemap_size);
327 /* Reserve SMP trampoline */
328 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
331 #ifdef CONFIG_ACPI_SLEEP
333 * Reserve low memory region for sleep support.
335 acpi_reserve_bootmem();
338 * Find and reserve possible boot-time SMP configuration:
341 #ifdef CONFIG_BLK_DEV_INITRD
342 if (LOADER_TYPE && INITRD_START) {
343 if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
344 reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
345 initrd_start = INITRD_START + PAGE_OFFSET;
346 initrd_end = initrd_start+INITRD_SIZE;
349 printk(KERN_ERR "initrd extends beyond end of memory "
350 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
351 (unsigned long)(INITRD_START + INITRD_SIZE),
352 (unsigned long)(end_pfn << PAGE_SHIFT));
358 if (crashk_res.start != crashk_res.end) {
359 reserve_bootmem_generic(crashk_res.start,
360 crashk_res.end - crashk_res.start + 1);
371 * set this early, so we dont allocate cpu0
372 * if MADT list doesnt list BSP first
373 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
375 cpu_set(0, cpu_present_map);
378 * Read APIC and some other early information from ACPI tables.
386 * get boot-time SMP configuration:
388 if (smp_found_config)
390 init_apic_mappings();
393 * We trust e820 completely. No explicit ROM probing in memory.
395 e820_reserve_resources();
396 e820_mark_nosave_regions();
400 /* request I/O space for devices used on all i[345]86 PCs */
401 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
402 request_resource(&ioport_resource, &standard_io_resources[i]);
408 #if defined(CONFIG_VGA_CONSOLE)
409 conswitchp = &vga_con;
410 #elif defined(CONFIG_DUMMY_CONSOLE)
411 conswitchp = &dummy_con;
416 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
420 if (c->extended_cpuid_level < 0x80000004)
423 v = (unsigned int *) c->x86_model_id;
424 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
425 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
426 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
427 c->x86_model_id[48] = 0;
432 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
434 unsigned int n, dummy, eax, ebx, ecx, edx;
436 n = c->extended_cpuid_level;
438 if (n >= 0x80000005) {
439 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
440 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
441 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
442 c->x86_cache_size=(ecx>>24)+(edx>>24);
443 /* On K8 L1 TLB is inclusive, so don't count it */
447 if (n >= 0x80000006) {
448 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
449 ecx = cpuid_ecx(0x80000006);
450 c->x86_cache_size = ecx >> 16;
451 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
453 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
454 c->x86_cache_size, ecx & 0xFF);
458 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
459 if (n >= 0x80000008) {
460 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
461 c->x86_virt_bits = (eax >> 8) & 0xff;
462 c->x86_phys_bits = eax & 0xff;
467 static int nearby_node(int apicid)
470 for (i = apicid - 1; i >= 0; i--) {
471 int node = apicid_to_node[i];
472 if (node != NUMA_NO_NODE && node_online(node))
475 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
476 int node = apicid_to_node[i];
477 if (node != NUMA_NO_NODE && node_online(node))
480 return first_node(node_online_map); /* Shouldn't happen */
485 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
486 * Assumes number of cores is a power of two.
488 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
493 int cpu = smp_processor_id();
495 unsigned apicid = hard_smp_processor_id();
497 unsigned ecx = cpuid_ecx(0x80000008);
499 c->x86_max_cores = (ecx & 0xff) + 1;
501 /* CPU telling us the core id bits shift? */
502 bits = (ecx >> 12) & 0xF;
504 /* Otherwise recompute */
506 while ((1 << bits) < c->x86_max_cores)
510 /* Low order bits define the core id (index of core in socket) */
511 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
512 /* Convert the APIC ID into the socket ID */
513 c->phys_proc_id = phys_pkg_id(bits);
516 node = c->phys_proc_id;
517 if (apicid_to_node[apicid] != NUMA_NO_NODE)
518 node = apicid_to_node[apicid];
519 if (!node_online(node)) {
520 /* Two possibilities here:
521 - The CPU is missing memory and no node was created.
522 In that case try picking one from a nearby CPU
523 - The APIC IDs differ from the HyperTransport node IDs
524 which the K8 northbridge parsing fills in.
525 Assume they are all increased by a constant offset,
526 but in the same order as the HT nodeids.
527 If that doesn't result in a usable node fall back to the
528 path for the previous case. */
529 int ht_nodeid = apicid - (cpu_data[0].phys_proc_id << bits);
530 if (ht_nodeid >= 0 &&
531 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
532 node = apicid_to_node[ht_nodeid];
533 /* Pick a nearby node */
534 if (!node_online(node))
535 node = nearby_node(apicid);
537 numa_set_node(cpu, node);
539 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
544 #define ENABLE_C1E_MASK 0x18000000
545 #define CPUID_PROCESSOR_SIGNATURE 1
546 #define CPUID_XFAM 0x0ff00000
547 #define CPUID_XFAM_K8 0x00000000
548 #define CPUID_XFAM_10H 0x00100000
549 #define CPUID_XFAM_11H 0x00200000
550 #define CPUID_XMOD 0x000f0000
551 #define CPUID_XMOD_REV_F 0x00040000
553 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
554 static __cpuinit int amd_apic_timer_broken(void)
557 u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
558 switch (eax & CPUID_XFAM) {
560 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
564 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
565 if (lo & ENABLE_C1E_MASK)
569 /* err on the side of caution */
575 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
583 * Disable TLB flush filter by setting HWCR.FFDIS on K8
584 * bit 6 of msr C001_0015
586 * Errata 63 for SH-B3 steppings
587 * Errata 122 for all steppings (F+ have it disabled by default)
590 rdmsrl(MSR_K8_HWCR, value);
592 wrmsrl(MSR_K8_HWCR, value);
596 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
597 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
598 clear_bit(0*32+31, &c->x86_capability);
600 /* On C+ stepping K8 rep microcode works well for copy/memset */
601 level = cpuid_eax(1);
602 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
603 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
605 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
607 /* Enable workaround for FXSAVE leak */
609 set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
611 level = get_model_name(c);
615 /* Should distinguish Models here, but this is only
616 a fallback anyways. */
617 strcpy(c->x86_model_id, "Hammer");
621 display_cacheinfo(c);
623 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
624 if (c->x86_power & (1<<8))
625 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
627 /* Multi core CPU? */
628 if (c->extended_cpuid_level >= 0x80000008)
631 if (c->extended_cpuid_level >= 0x80000006 &&
632 (cpuid_edx(0x80000006) & 0xf000))
633 num_cache_leaves = 4;
635 num_cache_leaves = 3;
637 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
638 set_bit(X86_FEATURE_K8, &c->x86_capability);
640 /* RDTSC can be speculated around */
641 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
643 /* Family 10 doesn't support C states in MWAIT so don't use it */
644 if (c->x86 == 0x10 && !force_mwait)
645 clear_bit(X86_FEATURE_MWAIT, &c->x86_capability);
647 if (amd_apic_timer_broken())
648 disable_apic_timer = 1;
651 static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
654 u32 eax, ebx, ecx, edx;
655 int index_msb, core_bits;
657 cpuid(1, &eax, &ebx, &ecx, &edx);
660 if (!cpu_has(c, X86_FEATURE_HT))
662 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
665 smp_num_siblings = (ebx & 0xff0000) >> 16;
667 if (smp_num_siblings == 1) {
668 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
669 } else if (smp_num_siblings > 1 ) {
671 if (smp_num_siblings > NR_CPUS) {
672 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
673 smp_num_siblings = 1;
677 index_msb = get_count_order(smp_num_siblings);
678 c->phys_proc_id = phys_pkg_id(index_msb);
680 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
682 index_msb = get_count_order(smp_num_siblings) ;
684 core_bits = get_count_order(c->x86_max_cores);
686 c->cpu_core_id = phys_pkg_id(index_msb) &
687 ((1 << core_bits) - 1);
690 if ((c->x86_max_cores * smp_num_siblings) > 1) {
691 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
692 printk(KERN_INFO "CPU: Processor Core ID: %d\n", c->cpu_core_id);
699 * find out the number of processor cores on the die
701 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
705 if (c->cpuid_level < 4)
708 cpuid_count(4, 0, &eax, &t, &t, &t);
711 return ((eax >> 26) + 1);
716 static void srat_detect_node(void)
720 int cpu = smp_processor_id();
721 int apicid = hard_smp_processor_id();
723 /* Don't do the funky fallback heuristics the AMD version employs
725 node = apicid_to_node[apicid];
726 if (node == NUMA_NO_NODE)
727 node = first_node(node_online_map);
728 numa_set_node(cpu, node);
730 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
734 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
739 init_intel_cacheinfo(c);
740 if (c->cpuid_level > 9 ) {
741 unsigned eax = cpuid_eax(10);
742 /* Check for version and the number of counters */
743 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
744 set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
749 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
751 set_bit(X86_FEATURE_BTS, c->x86_capability);
753 set_bit(X86_FEATURE_PEBS, c->x86_capability);
756 n = c->extended_cpuid_level;
757 if (n >= 0x80000008) {
758 unsigned eax = cpuid_eax(0x80000008);
759 c->x86_virt_bits = (eax >> 8) & 0xff;
760 c->x86_phys_bits = eax & 0xff;
761 /* CPUID workaround for Intel 0F34 CPU */
762 if (c->x86_vendor == X86_VENDOR_INTEL &&
763 c->x86 == 0xF && c->x86_model == 0x3 &&
765 c->x86_phys_bits = 36;
769 c->x86_cache_alignment = c->x86_clflush_size * 2;
770 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
771 (c->x86 == 0x6 && c->x86_model >= 0x0e))
772 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
774 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
776 set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
778 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
779 c->x86_max_cores = intel_num_cpu_cores(c);
784 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
786 char *v = c->x86_vendor_id;
788 if (!strcmp(v, "AuthenticAMD"))
789 c->x86_vendor = X86_VENDOR_AMD;
790 else if (!strcmp(v, "GenuineIntel"))
791 c->x86_vendor = X86_VENDOR_INTEL;
793 c->x86_vendor = X86_VENDOR_UNKNOWN;
796 struct cpu_model_info {
799 char *model_names[16];
802 /* Do some early cpuid on the boot CPU to get some parameter that are
803 needed before check_bugs. Everything advanced is in identify_cpu
805 void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
809 c->loops_per_jiffy = loops_per_jiffy;
810 c->x86_cache_size = -1;
811 c->x86_vendor = X86_VENDOR_UNKNOWN;
812 c->x86_model = c->x86_mask = 0; /* So far unknown... */
813 c->x86_vendor_id[0] = '\0'; /* Unset */
814 c->x86_model_id[0] = '\0'; /* Unset */
815 c->x86_clflush_size = 64;
816 c->x86_cache_alignment = c->x86_clflush_size;
817 c->x86_max_cores = 1;
818 c->extended_cpuid_level = 0;
819 memset(&c->x86_capability, 0, sizeof c->x86_capability);
821 /* Get vendor name */
822 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
823 (unsigned int *)&c->x86_vendor_id[0],
824 (unsigned int *)&c->x86_vendor_id[8],
825 (unsigned int *)&c->x86_vendor_id[4]);
829 /* Initialize the standard set of capabilities */
830 /* Note that the vendor-specific code below might override */
832 /* Intel-defined flags: level 0x00000001 */
833 if (c->cpuid_level >= 0x00000001) {
835 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
836 &c->x86_capability[0]);
837 c->x86 = (tfms >> 8) & 0xf;
838 c->x86_model = (tfms >> 4) & 0xf;
839 c->x86_mask = tfms & 0xf;
841 c->x86 += (tfms >> 20) & 0xff;
843 c->x86_model += ((tfms >> 16) & 0xF) << 4;
844 if (c->x86_capability[0] & (1<<19))
845 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
847 /* Have CPUID level 0 only - unheard of */
852 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
857 * This does the hard work of actually picking apart the CPU stuff...
859 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
864 early_identify_cpu(c);
866 /* AMD-defined flags: level 0x80000001 */
867 xlvl = cpuid_eax(0x80000000);
868 c->extended_cpuid_level = xlvl;
869 if ((xlvl & 0xffff0000) == 0x80000000) {
870 if (xlvl >= 0x80000001) {
871 c->x86_capability[1] = cpuid_edx(0x80000001);
872 c->x86_capability[6] = cpuid_ecx(0x80000001);
874 if (xlvl >= 0x80000004)
875 get_model_name(c); /* Default name */
878 /* Transmeta-defined flags: level 0x80860001 */
879 xlvl = cpuid_eax(0x80860000);
880 if ((xlvl & 0xffff0000) == 0x80860000) {
881 /* Don't set x86_cpuid_level here for now to not confuse. */
882 if (xlvl >= 0x80860001)
883 c->x86_capability[2] = cpuid_edx(0x80860001);
886 init_scattered_cpuid_features(c);
888 c->apicid = phys_pkg_id(0);
891 * Vendor-specific initialization. In this section we
892 * canonicalize the feature flags, meaning if there are
893 * features a certain CPU supports which CPUID doesn't
894 * tell us, CPUID claiming incorrect flags, or other bugs,
895 * we handle them here.
897 * At the end of this section, c->x86_capability better
898 * indicate the features this CPU genuinely supports!
900 switch (c->x86_vendor) {
905 case X86_VENDOR_INTEL:
909 case X86_VENDOR_UNKNOWN:
911 display_cacheinfo(c);
915 select_idle_routine(c);
919 * On SMP, boot_cpu_data holds the common feature set between
920 * all CPUs; so make sure that we indicate which features are
921 * common between the CPUs. The first time this routine gets
922 * executed, c == &boot_cpu_data.
924 if (c != &boot_cpu_data) {
925 /* AND the already accumulated flags with these */
926 for (i = 0 ; i < NCAPINTS ; i++)
927 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
930 #ifdef CONFIG_X86_MCE
933 if (c != &boot_cpu_data)
936 numa_add_cpu(smp_processor_id());
941 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
943 if (c->x86_model_id[0])
944 printk("%s", c->x86_model_id);
946 if (c->x86_mask || c->cpuid_level >= 0)
947 printk(" stepping %02x\n", c->x86_mask);
953 * Get CPU information for use by the procfs.
956 static int show_cpuinfo(struct seq_file *m, void *v)
958 struct cpuinfo_x86 *c = v;
961 * These flag bits must match the definitions in <asm/cpufeature.h>.
962 * NULL means this bit is undefined or reserved; either way it doesn't
963 * have meaning as far as Linux is concerned. Note that it's important
964 * to realize there is a difference between this table and CPUID -- if
965 * applications want to get the raw CPUID data, they should access
966 * /dev/cpu/<cpu_nr>/cpuid instead.
968 static char *x86_cap_flags[] = {
970 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
971 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
972 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
973 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
976 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
977 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
978 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
979 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
982 /* Transmeta-defined */
983 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
984 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
985 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
986 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
988 /* Other (Linux-defined) */
989 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
990 NULL, NULL, NULL, NULL,
991 "constant_tsc", "up", NULL, "arch_perfmon",
992 "pebs", "bts", NULL, "sync_rdtsc",
993 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
994 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
996 /* Intel-defined (#2) */
997 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
998 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
999 NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
1000 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1002 /* VIA/Cyrix/Centaur-defined */
1003 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1004 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
1005 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1006 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1008 /* AMD-defined (#2) */
1009 "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",
1010 "altmovcr8", "abm", "sse4a",
1011 "misalignsse", "3dnowprefetch",
1012 "osvw", "ibs", NULL, NULL, NULL, NULL,
1013 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1016 /* Auxiliary (Linux-defined) */
1017 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1018 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1019 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1020 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1022 static char *x86_power_flags[] = {
1023 "ts", /* temperature sensor */
1024 "fid", /* frequency id control */
1025 "vid", /* voltage id control */
1026 "ttp", /* thermal trip */
1031 "", /* tsc invariant mapped to constant_tsc */
1037 if (!cpu_online(c-cpu_data))
1041 seq_printf(m,"processor\t: %u\n"
1043 "cpu family\t: %d\n"
1045 "model name\t: %s\n",
1046 (unsigned)(c-cpu_data),
1047 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1050 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1052 if (c->x86_mask || c->cpuid_level >= 0)
1053 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1055 seq_printf(m, "stepping\t: unknown\n");
1057 if (cpu_has(c,X86_FEATURE_TSC)) {
1058 unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
1061 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1062 freq / 1000, (freq % 1000));
1066 if (c->x86_cache_size >= 0)
1067 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1070 if (smp_num_siblings * c->x86_max_cores > 1) {
1071 int cpu = c - cpu_data;
1072 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1073 seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
1074 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1075 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1081 "fpu_exception\t: yes\n"
1082 "cpuid level\t: %d\n"
1089 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
1090 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1091 seq_printf(m, " %s", x86_cap_flags[i]);
1094 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1095 c->loops_per_jiffy/(500000/HZ),
1096 (c->loops_per_jiffy/(5000/HZ)) % 100);
1098 if (c->x86_tlbsize > 0)
1099 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1100 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1101 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1103 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1104 c->x86_phys_bits, c->x86_virt_bits);
1106 seq_printf(m, "power management:");
1109 for (i = 0; i < 32; i++)
1110 if (c->x86_power & (1 << i)) {
1111 if (i < ARRAY_SIZE(x86_power_flags) &&
1113 seq_printf(m, "%s%s",
1114 x86_power_flags[i][0]?" ":"",
1115 x86_power_flags[i]);
1117 seq_printf(m, " [%d]", i);
1121 seq_printf(m, "\n\n");
1126 static void *c_start(struct seq_file *m, loff_t *pos)
1128 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1131 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1134 return c_start(m, pos);
1137 static void c_stop(struct seq_file *m, void *v)
1141 struct seq_operations cpuinfo_op = {
1145 .show = show_cpuinfo,