git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/b43/main.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   Some parts of the code in this file are derived from the ipw2200
  12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  13
  14   This program is free software; you can redistribute it and/or modify
  15   it under the terms of the GNU General Public License as published by
  16   the Free Software Foundation; either version 2 of the License, or
  17   (at your option) any later version.
  18
  19   This program is distributed in the hope that it will be useful,
  20   but WITHOUT ANY WARRANTY; without even the implied warranty of
  21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22   GNU General Public License for more details.
  23
  24   You should have received a copy of the GNU General Public License
  25   along with this program; see the file COPYING.  If not, write to
  26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27   Boston, MA 02110-1301, USA.
  28
  29 */
  30
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/if_arp.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/version.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <asm/unaligned.h>
  43
  44 #include "b43.h"
  45 #include "main.h"
  46 #include "debugfs.h"
  47 #include "phy.h"
  48 #include "dma.h"
  49 #include "pio.h"
  50 #include "sysfs.h"
  51 #include "xmit.h"
  52 #include "lo.h"
  53 #include "pcmcia.h"
  54
  55 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  56 MODULE_AUTHOR("Martin Langer");
  57 MODULE_AUTHOR("Stefano Brivio");
  58 MODULE_AUTHOR("Michael Buesch");
  59 MODULE_LICENSE("GPL");
  60
  61 extern char *nvram_get(char *name);
  62
  63 #if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
  64 static int modparam_pio;
  65 module_param_named(pio, modparam_pio, int, 0444);
  66 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  67 #elif defined(CONFIG_B43_DMA)
  68 # define modparam_pio   0
  69 #elif defined(CONFIG_B43_PIO)
  70 # define modparam_pio   1
  71 #endif
  72
  73 static int modparam_bad_frames_preempt;
  74 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  75 MODULE_PARM_DESC(bad_frames_preempt,
  76                  "enable(1) / disable(0) Bad Frames Preemption");
  77
  78 static char modparam_fwpostfix[16];
  79 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  80 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  81
  82 static int modparam_hwpctl;
  83 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  84 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  85
  86 static int modparam_nohwcrypt;
  87 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  88 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  89
  90 static const struct ssb_device_id b43_ssb_tbl[] = {
  91         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
  92         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
  93         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
  94         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
  95         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
  96         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
  97         SSB_DEVTABLE_END
  98 };
  99
 100 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
 101
 102 /* Channel and ratetables are shared for all devices.
 103  * They can't be const, because ieee80211 puts some precalculated
 104  * data in there. This data is the same for all devices, so we don't
 105  * get concurrency issues */
 106 #define RATETAB_ENT(_rateid, _flags) \
 107         {                                                       \
 108                 .rate   = B43_RATE_TO_BASE100KBPS(_rateid),     \
 109                 .val    = (_rateid),                            \
 110                 .val2   = (_rateid),                            \
 111                 .flags  = (_flags),                             \
 112         }
 113 static struct ieee80211_rate __b43_ratetable[] = {
 114         RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
 115         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
 116         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
 117         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
 118         RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
 119         RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
 120         RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
 121         RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
 122         RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
 123         RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
 124         RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
 125         RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
 126 };
 127
 128 #define b43_a_ratetable         (__b43_ratetable + 4)
 129 #define b43_a_ratetable_size    8
 130 #define b43_b_ratetable         (__b43_ratetable + 0)
 131 #define b43_b_ratetable_size    4
 132 #define b43_g_ratetable         (__b43_ratetable + 0)
 133 #define b43_g_ratetable_size    12
 134
 135 #define CHANTAB_ENT(_chanid, _freq) \
 136         {                                                       \
 137                 .chan   = (_chanid),                            \
 138                 .freq   = (_freq),                              \
 139                 .val    = (_chanid),                            \
 140                 .flag   = IEEE80211_CHAN_W_SCAN |               \
 141                           IEEE80211_CHAN_W_ACTIVE_SCAN |        \
 142                           IEEE80211_CHAN_W_IBSS,                \
 143                 .power_level    = 0xFF,                         \
 144                 .antenna_max    = 0xFF,                         \
 145         }
 146 static struct ieee80211_channel b43_bg_chantable[] = {
 147         CHANTAB_ENT(1, 2412),
 148         CHANTAB_ENT(2, 2417),
 149         CHANTAB_ENT(3, 2422),
 150         CHANTAB_ENT(4, 2427),
 151         CHANTAB_ENT(5, 2432),
 152         CHANTAB_ENT(6, 2437),
 153         CHANTAB_ENT(7, 2442),
 154         CHANTAB_ENT(8, 2447),
 155         CHANTAB_ENT(9, 2452),
 156         CHANTAB_ENT(10, 2457),
 157         CHANTAB_ENT(11, 2462),
 158         CHANTAB_ENT(12, 2467),
 159         CHANTAB_ENT(13, 2472),
 160         CHANTAB_ENT(14, 2484),
 161 };
 162
 163 #define b43_bg_chantable_size   ARRAY_SIZE(b43_bg_chantable)
 164 static struct ieee80211_channel b43_a_chantable[] = {
 165         CHANTAB_ENT(36, 5180),
 166         CHANTAB_ENT(40, 5200),
 167         CHANTAB_ENT(44, 5220),
 168         CHANTAB_ENT(48, 5240),
 169         CHANTAB_ENT(52, 5260),
 170         CHANTAB_ENT(56, 5280),
 171         CHANTAB_ENT(60, 5300),
 172         CHANTAB_ENT(64, 5320),
 173         CHANTAB_ENT(149, 5745),
 174         CHANTAB_ENT(153, 5765),
 175         CHANTAB_ENT(157, 5785),
 176         CHANTAB_ENT(161, 5805),
 177         CHANTAB_ENT(165, 5825),
 178 };
 179
 180 #define b43_a_chantable_size    ARRAY_SIZE(b43_a_chantable)
 181
 182 static void b43_wireless_core_exit(struct b43_wldev *dev);
 183 static int b43_wireless_core_init(struct b43_wldev *dev);
 184 static void b43_wireless_core_stop(struct b43_wldev *dev);
 185 static int b43_wireless_core_start(struct b43_wldev *dev);
 186
 187 static int b43_ratelimit(struct b43_wl *wl)
 188 {
 189         if (!wl || !wl->current_dev)
 190                 return 1;
 191         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
 192                 return 1;
 193         /* We are up and running.
 194          * Ratelimit the messages to avoid DoS over the net. */
 195         return net_ratelimit();
 196 }
 197
 198 void b43info(struct b43_wl *wl, const char *fmt, ...)
 199 {
 200         va_list args;
 201
 202         if (!b43_ratelimit(wl))
 203                 return;
 204         va_start(args, fmt);
 205         printk(KERN_INFO "b43-%s: ",
 206                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 207         vprintk(fmt, args);
 208         va_end(args);
 209 }
 210
 211 void b43err(struct b43_wl *wl, const char *fmt, ...)
 212 {
 213         va_list args;
 214
 215         if (!b43_ratelimit(wl))
 216                 return;
 217         va_start(args, fmt);
 218         printk(KERN_ERR "b43-%s ERROR: ",
 219                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 220         vprintk(fmt, args);
 221         va_end(args);
 222 }
 223
 224 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 225 {
 226         va_list args;
 227
 228         if (!b43_ratelimit(wl))
 229                 return;
 230         va_start(args, fmt);
 231         printk(KERN_WARNING "b43-%s warning: ",
 232                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 233         vprintk(fmt, args);
 234         va_end(args);
 235 }
 236
 237 #if B43_DEBUG
 238 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 239 {
 240         va_list args;
 241
 242         va_start(args, fmt);
 243         printk(KERN_DEBUG "b43-%s debug: ",
 244                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 245         vprintk(fmt, args);
 246         va_end(args);
 247 }
 248 #endif /* DEBUG */
 249
 250 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
 251 {
 252         u32 macctl;
 253
 254         B43_WARN_ON(offset % 4 != 0);
 255
 256         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 257         if (macctl & B43_MACCTL_BE)
 258                 val = swab32(val);
 259
 260         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
 261         mmiowb();
 262         b43_write32(dev, B43_MMIO_RAM_DATA, val);
 263 }
 264
 265 static inline
 266     void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
 267 {
 268         u32 control;
 269
 270         /* "offset" is the WORD offset. */
 271
 272         control = routing;
 273         control <<= 16;
 274         control |= offset;
 275         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
 276 }
 277
 278 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
 279 {
 280         u32 ret;
 281
 282         if (routing == B43_SHM_SHARED) {
 283                 B43_WARN_ON(offset & 0x0001);
 284                 if (offset & 0x0003) {
 285                         /* Unaligned access */
 286                         b43_shm_control_word(dev, routing, offset >> 2);
 287                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 288                         ret <<= 16;
 289                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 290                         ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
 291
 292                         return ret;
 293                 }
 294                 offset >>= 2;
 295         }
 296         b43_shm_control_word(dev, routing, offset);
 297         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
 298
 299         return ret;
 300 }
 301
 302 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
 303 {
 304         u16 ret;
 305
 306         if (routing == B43_SHM_SHARED) {
 307                 B43_WARN_ON(offset & 0x0001);
 308                 if (offset & 0x0003) {
 309                         /* Unaligned access */
 310                         b43_shm_control_word(dev, routing, offset >> 2);
 311                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 312
 313                         return ret;
 314                 }
 315                 offset >>= 2;
 316         }
 317         b43_shm_control_word(dev, routing, offset);
 318         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
 319
 320         return ret;
 321 }
 322
 323 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
 324 {
 325         if (routing == B43_SHM_SHARED) {
 326                 B43_WARN_ON(offset & 0x0001);
 327                 if (offset & 0x0003) {
 328                         /* Unaligned access */
 329                         b43_shm_control_word(dev, routing, offset >> 2);
 330                         mmiowb();
 331                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
 332                                     (value >> 16) & 0xffff);
 333                         mmiowb();
 334                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 335                         mmiowb();
 336                         b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
 337                         return;
 338                 }
 339                 offset >>= 2;
 340         }
 341         b43_shm_control_word(dev, routing, offset);
 342         mmiowb();
 343         b43_write32(dev, B43_MMIO_SHM_DATA, value);
 344 }
 345
 346 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
 347 {
 348         if (routing == B43_SHM_SHARED) {
 349                 B43_WARN_ON(offset & 0x0001);
 350                 if (offset & 0x0003) {
 351                         /* Unaligned access */
 352                         b43_shm_control_word(dev, routing, offset >> 2);
 353                         mmiowb();
 354                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
 355                         return;
 356                 }
 357                 offset >>= 2;
 358         }
 359         b43_shm_control_word(dev, routing, offset);
 360         mmiowb();
 361         b43_write16(dev, B43_MMIO_SHM_DATA, value);
 362 }
 363
 364 /* Read HostFlags */
 365 u32 b43_hf_read(struct b43_wldev * dev)
 366 {
 367         u32 ret;
 368
 369         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
 370         ret <<= 16;
 371         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
 372
 373         return ret;
 374 }
 375
 376 /* Write HostFlags */
 377 void b43_hf_write(struct b43_wldev *dev, u32 value)
 378 {
 379         b43_shm_write16(dev, B43_SHM_SHARED,
 380                         B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
 381         b43_shm_write16(dev, B43_SHM_SHARED,
 382                         B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
 383 }
 384
 385 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
 386 {
 387         /* We need to be careful. As we read the TSF from multiple
 388          * registers, we should take care of register overflows.
 389          * In theory, the whole tsf read process should be atomic.
 390          * We try to be atomic here, by restaring the read process,
 391          * if any of the high registers changed (overflew).
 392          */
 393         if (dev->dev->id.revision >= 3) {
 394                 u32 low, high, high2;
 395
 396                 do {
 397                         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 398                         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
 399                         high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 400                 } while (unlikely(high != high2));
 401
 402                 *tsf = high;
 403                 *tsf <<= 32;
 404                 *tsf |= low;
 405         } else {
 406                 u64 tmp;
 407                 u16 v0, v1, v2, v3;
 408                 u16 test1, test2, test3;
 409
 410                 do {
 411                         v3 = b43_read16(dev, B43_MMIO_TSF_3);
 412                         v2 = b43_read16(dev, B43_MMIO_TSF_2);
 413                         v1 = b43_read16(dev, B43_MMIO_TSF_1);
 414                         v0 = b43_read16(dev, B43_MMIO_TSF_0);
 415
 416                         test3 = b43_read16(dev, B43_MMIO_TSF_3);
 417                         test2 = b43_read16(dev, B43_MMIO_TSF_2);
 418                         test1 = b43_read16(dev, B43_MMIO_TSF_1);
 419                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 420
 421                 *tsf = v3;
 422                 *tsf <<= 48;
 423                 tmp = v2;
 424                 tmp <<= 32;
 425                 *tsf |= tmp;
 426                 tmp = v1;
 427                 tmp <<= 16;
 428                 *tsf |= tmp;
 429                 *tsf |= v0;
 430         }
 431 }
 432
 433 static void b43_time_lock(struct b43_wldev *dev)
 434 {
 435         u32 macctl;
 436
 437         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 438         macctl |= B43_MACCTL_TBTTHOLD;
 439         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 440         /* Commit the write */
 441         b43_read32(dev, B43_MMIO_MACCTL);
 442 }
 443
 444 static void b43_time_unlock(struct b43_wldev *dev)
 445 {
 446         u32 macctl;
 447
 448         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 449         macctl &= ~B43_MACCTL_TBTTHOLD;
 450         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 451         /* Commit the write */
 452         b43_read32(dev, B43_MMIO_MACCTL);
 453 }
 454
 455 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
 456 {
 457         /* Be careful with the in-progress timer.
 458          * First zero out the low register, so we have a full
 459          * register-overflow duration to complete the operation.
 460          */
 461         if (dev->dev->id.revision >= 3) {
 462                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 463                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 464
 465                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
 466                 mmiowb();
 467                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
 468                 mmiowb();
 469                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
 470         } else {
 471                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 472                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 473                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 474                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 475
 476                 b43_write16(dev, B43_MMIO_TSF_0, 0);
 477                 mmiowb();
 478                 b43_write16(dev, B43_MMIO_TSF_3, v3);
 479                 mmiowb();
 480                 b43_write16(dev, B43_MMIO_TSF_2, v2);
 481                 mmiowb();
 482                 b43_write16(dev, B43_MMIO_TSF_1, v1);
 483                 mmiowb();
 484                 b43_write16(dev, B43_MMIO_TSF_0, v0);
 485         }
 486 }
 487
 488 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
 489 {
 490         b43_time_lock(dev);
 491         b43_tsf_write_locked(dev, tsf);
 492         b43_time_unlock(dev);
 493 }
 494
 495 static
 496 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
 497 {
 498         static const u8 zero_addr[ETH_ALEN] = { 0 };
 499         u16 data;
 500
 501         if (!mac)
 502                 mac = zero_addr;
 503
 504         offset |= 0x0020;
 505         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
 506
 507         data = mac[0];
 508         data |= mac[1] << 8;
 509         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 510         data = mac[2];
 511         data |= mac[3] << 8;
 512         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 513         data = mac[4];
 514         data |= mac[5] << 8;
 515         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 516 }
 517
 518 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
 519 {
 520         const u8 *mac;
 521         const u8 *bssid;
 522         u8 mac_bssid[ETH_ALEN * 2];
 523         int i;
 524         u32 tmp;
 525
 526         bssid = dev->wl->bssid;
 527         mac = dev->wl->mac_addr;
 528
 529         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
 530
 531         memcpy(mac_bssid, mac, ETH_ALEN);
 532         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 533
 534         /* Write our MAC address and BSSID to template ram */
 535         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 536                 tmp = (u32) (mac_bssid[i + 0]);
 537                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
 538                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
 539                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
 540                 b43_ram_write(dev, 0x20 + i, tmp);
 541         }
 542 }
 543
 544 static void b43_upload_card_macaddress(struct b43_wldev *dev)
 545 {
 546         b43_write_mac_bssid_templates(dev);
 547         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
 548 }
 549
 550 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 551 {
 552         /* slot_time is in usec. */
 553         if (dev->phy.type != B43_PHYTYPE_G)
 554                 return;
 555         b43_write16(dev, 0x684, 510 + slot_time);
 556         b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
 557 }
 558
 559 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
 560 {
 561         b43_set_slot_time(dev, 9);
 562         dev->short_slot = 1;
 563 }
 564
 565 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
 566 {
 567         b43_set_slot_time(dev, 20);
 568         dev->short_slot = 0;
 569 }
 570
 571 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
 572  * Returns the _previously_ enabled IRQ mask.
 573  */
 574 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
 575 {
 576         u32 old_mask;
 577
 578         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 579         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
 580
 581         return old_mask;
 582 }
 583
 584 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
 585  * Returns the _previously_ enabled IRQ mask.
 586  */
 587 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
 588 {
 589         u32 old_mask;
 590
 591         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 592         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
 593
 594         return old_mask;
 595 }
 596
 597 /* Synchronize IRQ top- and bottom-half.
 598  * IRQs must be masked before calling this.
 599  * This must not be called with the irq_lock held.
 600  */
 601 static void b43_synchronize_irq(struct b43_wldev *dev)
 602 {
 603         synchronize_irq(dev->dev->irq);
 604         tasklet_kill(&dev->isr_tasklet);
 605 }
 606
 607 /* DummyTransmission function, as documented on
 608  * http://bcm-specs.sipsolutions.net/DummyTransmission
 609  */
 610 void b43_dummy_transmission(struct b43_wldev *dev)
 611 {
 612         struct b43_phy *phy = &dev->phy;
 613         unsigned int i, max_loop;
 614         u16 value;
 615         u32 buffer[5] = {
 616                 0x00000000,
 617                 0x00D40000,
 618                 0x00000000,
 619                 0x01000000,
 620                 0x00000000,
 621         };
 622
 623         switch (phy->type) {
 624         case B43_PHYTYPE_A:
 625                 max_loop = 0x1E;
 626                 buffer[0] = 0x000201CC;
 627                 break;
 628         case B43_PHYTYPE_B:
 629         case B43_PHYTYPE_G:
 630                 max_loop = 0xFA;
 631                 buffer[0] = 0x000B846E;
 632                 break;
 633         default:
 634                 B43_WARN_ON(1);
 635                 return;
 636         }
 637
 638         for (i = 0; i < 5; i++)
 639                 b43_ram_write(dev, i * 4, buffer[i]);
 640
 641         /* Commit writes */
 642         b43_read32(dev, B43_MMIO_MACCTL);
 643
 644         b43_write16(dev, 0x0568, 0x0000);
 645         b43_write16(dev, 0x07C0, 0x0000);
 646         value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
 647         b43_write16(dev, 0x050C, value);
 648         b43_write16(dev, 0x0508, 0x0000);
 649         b43_write16(dev, 0x050A, 0x0000);
 650         b43_write16(dev, 0x054C, 0x0000);
 651         b43_write16(dev, 0x056A, 0x0014);
 652         b43_write16(dev, 0x0568, 0x0826);
 653         b43_write16(dev, 0x0500, 0x0000);
 654         b43_write16(dev, 0x0502, 0x0030);
 655
 656         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 657                 b43_radio_write16(dev, 0x0051, 0x0017);
 658         for (i = 0x00; i < max_loop; i++) {
 659                 value = b43_read16(dev, 0x050E);
 660                 if (value & 0x0080)
 661                         break;
 662                 udelay(10);
 663         }
 664         for (i = 0x00; i < 0x0A; i++) {
 665                 value = b43_read16(dev, 0x050E);
 666                 if (value & 0x0400)
 667                         break;
 668                 udelay(10);
 669         }
 670         for (i = 0x00; i < 0x0A; i++) {
 671                 value = b43_read16(dev, 0x0690);
 672                 if (!(value & 0x0100))
 673                         break;
 674                 udelay(10);
 675         }
 676         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 677                 b43_radio_write16(dev, 0x0051, 0x0037);
 678 }
 679
 680 static void key_write(struct b43_wldev *dev,
 681                       u8 index, u8 algorithm, const u8 * key)
 682 {
 683         unsigned int i;
 684         u32 offset;
 685         u16 value;
 686         u16 kidx;
 687
 688         /* Key index/algo block */
 689         kidx = b43_kidx_to_fw(dev, index);
 690         value = ((kidx << 4) | algorithm);
 691         b43_shm_write16(dev, B43_SHM_SHARED,
 692                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
 693
 694         /* Write the key to the Key Table Pointer offset */
 695         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
 696         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
 697                 value = key[i];
 698                 value |= (u16) (key[i + 1]) << 8;
 699                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
 700         }
 701 }
 702
 703 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
 704 {
 705         u32 addrtmp[2] = { 0, 0, };
 706         u8 per_sta_keys_start = 8;
 707
 708         if (b43_new_kidx_api(dev))
 709                 per_sta_keys_start = 4;
 710
 711         B43_WARN_ON(index < per_sta_keys_start);
 712         /* We have two default TX keys and possibly two default RX keys.
 713          * Physical mac 0 is mapped to physical key 4 or 8, depending
 714          * on the firmware version.
 715          * So we must adjust the index here.
 716          */
 717         index -= per_sta_keys_start;
 718
 719         if (addr) {
 720                 addrtmp[0] = addr[0];
 721                 addrtmp[0] |= ((u32) (addr[1]) << 8);
 722                 addrtmp[0] |= ((u32) (addr[2]) << 16);
 723                 addrtmp[0] |= ((u32) (addr[3]) << 24);
 724                 addrtmp[1] = addr[4];
 725                 addrtmp[1] |= ((u32) (addr[5]) << 8);
 726         }
 727
 728         if (dev->dev->id.revision >= 5) {
 729                 /* Receive match transmitter address mechanism */
 730                 b43_shm_write32(dev, B43_SHM_RCMTA,
 731                                 (index * 2) + 0, addrtmp[0]);
 732                 b43_shm_write16(dev, B43_SHM_RCMTA,
 733                                 (index * 2) + 1, addrtmp[1]);
 734         } else {
 735                 /* RXE (Receive Engine) and
 736                  * PSM (Programmable State Machine) mechanism
 737                  */
 738                 if (index < 8) {
 739                         /* TODO write to RCM 16, 19, 22 and 25 */
 740                 } else {
 741                         b43_shm_write32(dev, B43_SHM_SHARED,
 742                                         B43_SHM_SH_PSM + (index * 6) + 0,
 743                                         addrtmp[0]);
 744                         b43_shm_write16(dev, B43_SHM_SHARED,
 745                                         B43_SHM_SH_PSM + (index * 6) + 4,
 746                                         addrtmp[1]);
 747                 }
 748         }
 749 }
 750
 751 static void do_key_write(struct b43_wldev *dev,
 752                          u8 index, u8 algorithm,
 753                          const u8 * key, size_t key_len, const u8 * mac_addr)
 754 {
 755         u8 buf[B43_SEC_KEYSIZE] = { 0, };
 756         u8 per_sta_keys_start = 8;
 757
 758         if (b43_new_kidx_api(dev))
 759                 per_sta_keys_start = 4;
 760
 761         B43_WARN_ON(index >= dev->max_nr_keys);
 762         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
 763
 764         if (index >= per_sta_keys_start)
 765                 keymac_write(dev, index, NULL); /* First zero out mac. */
 766         if (key)
 767                 memcpy(buf, key, key_len);
 768         key_write(dev, index, algorithm, buf);
 769         if (index >= per_sta_keys_start)
 770                 keymac_write(dev, index, mac_addr);
 771
 772         dev->key[index].algorithm = algorithm;
 773 }
 774
 775 static int b43_key_write(struct b43_wldev *dev,
 776                          int index, u8 algorithm,
 777                          const u8 * key, size_t key_len,
 778                          const u8 * mac_addr,
 779                          struct ieee80211_key_conf *keyconf)
 780 {
 781         int i;
 782         int sta_keys_start;
 783
 784         if (key_len > B43_SEC_KEYSIZE)
 785                 return -EINVAL;
 786         for (i = 0; i < dev->max_nr_keys; i++) {
 787                 /* Check that we don't already have this key. */
 788                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
 789         }
 790         if (index < 0) {
 791                 /* Either pairwise key or address is 00:00:00:00:00:00
 792                  * for transmit-only keys. Search the index. */
 793                 if (b43_new_kidx_api(dev))
 794                         sta_keys_start = 4;
 795                 else
 796                         sta_keys_start = 8;
 797                 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
 798                         if (!dev->key[i].keyconf) {
 799                                 /* found empty */
 800                                 index = i;
 801                                 break;
 802                         }
 803                 }
 804                 if (index < 0) {
 805                         b43err(dev->wl, "Out of hardware key memory\n");
 806                         return -ENOSPC;
 807                 }
 808         } else
 809                 B43_WARN_ON(index > 3);
 810
 811         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
 812         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 813                 /* Default RX key */
 814                 B43_WARN_ON(mac_addr);
 815                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
 816         }
 817         keyconf->hw_key_idx = index;
 818         dev->key[index].keyconf = keyconf;
 819
 820         return 0;
 821 }
 822
 823 static int b43_key_clear(struct b43_wldev *dev, int index)
 824 {
 825         if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
 826                 return -EINVAL;
 827         do_key_write(dev, index, B43_SEC_ALGO_NONE,
 828                      NULL, B43_SEC_KEYSIZE, NULL);
 829         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 830                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
 831                              NULL, B43_SEC_KEYSIZE, NULL);
 832         }
 833         dev->key[index].keyconf = NULL;
 834
 835         return 0;
 836 }
 837
 838 static void b43_clear_keys(struct b43_wldev *dev)
 839 {
 840         int i;
 841
 842         for (i = 0; i < dev->max_nr_keys; i++)
 843                 b43_key_clear(dev, i);
 844 }
 845
 846 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
 847 {
 848         u32 macctl;
 849         u16 ucstat;
 850         bool hwps;
 851         bool awake;
 852         int i;
 853
 854         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
 855                     (ps_flags & B43_PS_DISABLED));
 856         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
 857
 858         if (ps_flags & B43_PS_ENABLED) {
 859                 hwps = 1;
 860         } else if (ps_flags & B43_PS_DISABLED) {
 861                 hwps = 0;
 862         } else {
 863                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
 864                 //      and thus is not an AP and we are associated, set bit 25
 865         }
 866         if (ps_flags & B43_PS_AWAKE) {
 867                 awake = 1;
 868         } else if (ps_flags & B43_PS_ASLEEP) {
 869                 awake = 0;
 870         } else {
 871                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
 872                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
 873                 //      successful, set bit26
 874         }
 875
 876 /* FIXME: For now we force awake-on and hwps-off */
 877         hwps = 0;
 878         awake = 1;
 879
 880         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 881         if (hwps)
 882                 macctl |= B43_MACCTL_HWPS;
 883         else
 884                 macctl &= ~B43_MACCTL_HWPS;
 885         if (awake)
 886                 macctl |= B43_MACCTL_AWAKE;
 887         else
 888                 macctl &= ~B43_MACCTL_AWAKE;
 889         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 890         /* Commit write */
 891         b43_read32(dev, B43_MMIO_MACCTL);
 892         if (awake && dev->dev->id.revision >= 5) {
 893                 /* Wait for the microcode to wake up. */
 894                 for (i = 0; i < 100; i++) {
 895                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
 896                                                 B43_SHM_SH_UCODESTAT);
 897                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
 898                                 break;
 899                         udelay(10);
 900                 }
 901         }
 902 }
 903
 904 /* Turn the Analog ON/OFF */
 905 static void b43_switch_analog(struct b43_wldev *dev, int on)
 906 {
 907         b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
 908 }
 909
 910 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
 911 {
 912         u32 tmslow;
 913         u32 macctl;
 914
 915         flags |= B43_TMSLOW_PHYCLKEN;
 916         flags |= B43_TMSLOW_PHYRESET;
 917         ssb_device_enable(dev->dev, flags);
 918         msleep(2);              /* Wait for the PLL to turn on. */
 919
 920         /* Now take the PHY out of Reset again */
 921         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 922         tmslow |= SSB_TMSLOW_FGC;
 923         tmslow &= ~B43_TMSLOW_PHYRESET;
 924         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 925         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 926         msleep(1);
 927         tmslow &= ~SSB_TMSLOW_FGC;
 928         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 929         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 930         msleep(1);
 931
 932         /* Turn Analog ON */
 933         b43_switch_analog(dev, 1);
 934
 935         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 936         macctl &= ~B43_MACCTL_GMODE;
 937         if (flags & B43_TMSLOW_GMODE)
 938                 macctl |= B43_MACCTL_GMODE;
 939         macctl |= B43_MACCTL_IHR_ENABLED;
 940         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 941 }
 942
 943 static void handle_irq_transmit_status(struct b43_wldev *dev)
 944 {
 945         u32 v0, v1;
 946         u16 tmp;
 947         struct b43_txstatus stat;
 948
 949         while (1) {
 950                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 951                 if (!(v0 & 0x00000001))
 952                         break;
 953                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 954
 955                 stat.cookie = (v0 >> 16);
 956                 stat.seq = (v1 & 0x0000FFFF);
 957                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 958                 tmp = (v0 & 0x0000FFFF);
 959                 stat.frame_count = ((tmp & 0xF000) >> 12);
 960                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 961                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 962                 stat.pm_indicated = !!(tmp & 0x0080);
 963                 stat.intermediate = !!(tmp & 0x0040);
 964                 stat.for_ampdu = !!(tmp & 0x0020);
 965                 stat.acked = !!(tmp & 0x0002);
 966
 967                 b43_handle_txstatus(dev, &stat);
 968         }
 969 }
 970
 971 static void drain_txstatus_queue(struct b43_wldev *dev)
 972 {
 973         u32 dummy;
 974
 975         if (dev->dev->id.revision < 5)
 976                 return;
 977         /* Read all entries from the microcode TXstatus FIFO
 978          * and throw them away.
 979          */
 980         while (1) {
 981                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 982                 if (!(dummy & 0x00000001))
 983                         break;
 984                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 985         }
 986 }
 987
 988 static u32 b43_jssi_read(struct b43_wldev *dev)
 989 {
 990         u32 val = 0;
 991
 992         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
 993         val <<= 16;
 994         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
 995
 996         return val;
 997 }
 998
 999 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1000 {
1001         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1002         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1003 }
1004
1005 static void b43_generate_noise_sample(struct b43_wldev *dev)
1006 {
1007         b43_jssi_write(dev, 0x7F7F7F7F);
1008         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1009                     b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1010                     | (1 << 4));
1011         B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1012 }
1013
1014 static void b43_calculate_link_quality(struct b43_wldev *dev)
1015 {
1016         /* Top half of Link Quality calculation. */
1017
1018         if (dev->noisecalc.calculation_running)
1019                 return;
1020         dev->noisecalc.channel_at_start = dev->phy.channel;
1021         dev->noisecalc.calculation_running = 1;
1022         dev->noisecalc.nr_samples = 0;
1023
1024         b43_generate_noise_sample(dev);
1025 }
1026
1027 static void handle_irq_noise(struct b43_wldev *dev)
1028 {
1029         struct b43_phy *phy = &dev->phy;
1030         u16 tmp;
1031         u8 noise[4];
1032         u8 i, j;
1033         s32 average;
1034
1035         /* Bottom half of Link Quality calculation. */
1036
1037         B43_WARN_ON(!dev->noisecalc.calculation_running);
1038         if (dev->noisecalc.channel_at_start != phy->channel)
1039                 goto drop_calculation;
1040         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1041         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1042             noise[2] == 0x7F || noise[3] == 0x7F)
1043                 goto generate_new;
1044
1045         /* Get the noise samples. */
1046         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1047         i = dev->noisecalc.nr_samples;
1048         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1049         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1050         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1051         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1052         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1053         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1054         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1055         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1056         dev->noisecalc.nr_samples++;
1057         if (dev->noisecalc.nr_samples == 8) {
1058                 /* Calculate the Link Quality by the noise samples. */
1059                 average = 0;
1060                 for (i = 0; i < 8; i++) {
1061                         for (j = 0; j < 4; j++)
1062                                 average += dev->noisecalc.samples[i][j];
1063                 }
1064                 average /= (8 * 4);
1065                 average *= 125;
1066                 average += 64;
1067                 average /= 128;
1068                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1069                 tmp = (tmp / 128) & 0x1F;
1070                 if (tmp >= 8)
1071                         average += 2;
1072                 else
1073                         average -= 25;
1074                 if (tmp == 8)
1075                         average -= 72;
1076                 else
1077                         average -= 48;
1078
1079                 dev->stats.link_noise = average;
1080               drop_calculation:
1081                 dev->noisecalc.calculation_running = 0;
1082                 return;
1083         }
1084       generate_new:
1085         b43_generate_noise_sample(dev);
1086 }
1087
1088 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1089 {
1090         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1091                 ///TODO: PS TBTT
1092         } else {
1093                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1094                         b43_power_saving_ctl_bits(dev, 0);
1095         }
1096         dev->reg124_set_0x4 = 0;
1097         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1098                 dev->reg124_set_0x4 = 1;
1099 }
1100
1101 static void handle_irq_atim_end(struct b43_wldev *dev)
1102 {
1103         if (!dev->reg124_set_0x4 /*FIXME rename this variable */ )
1104                 return;
1105         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1106                     b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1107                     | 0x4);
1108 }
1109
1110 static void handle_irq_pmq(struct b43_wldev *dev)
1111 {
1112         u32 tmp;
1113
1114         //TODO: AP mode.
1115
1116         while (1) {
1117                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1118                 if (!(tmp & 0x00000008))
1119                         break;
1120         }
1121         /* 16bit write is odd, but correct. */
1122         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1123 }
1124
1125 static void b43_write_template_common(struct b43_wldev *dev,
1126                                       const u8 * data, u16 size,
1127                                       u16 ram_offset,
1128                                       u16 shm_size_offset, u8 rate)
1129 {
1130         u32 i, tmp;
1131         struct b43_plcp_hdr4 plcp;
1132
1133         plcp.data = 0;
1134         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1135         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1136         ram_offset += sizeof(u32);
1137         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1138          * So leave the first two bytes of the next write blank.
1139          */
1140         tmp = (u32) (data[0]) << 16;
1141         tmp |= (u32) (data[1]) << 24;
1142         b43_ram_write(dev, ram_offset, tmp);
1143         ram_offset += sizeof(u32);
1144         for (i = 2; i < size; i += sizeof(u32)) {
1145                 tmp = (u32) (data[i + 0]);
1146                 if (i + 1 < size)
1147                         tmp |= (u32) (data[i + 1]) << 8;
1148                 if (i + 2 < size)
1149                         tmp |= (u32) (data[i + 2]) << 16;
1150                 if (i + 3 < size)
1151                         tmp |= (u32) (data[i + 3]) << 24;
1152                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1153         }
1154         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1155                         size + sizeof(struct b43_plcp_hdr6));
1156 }
1157
1158 static void b43_write_beacon_template(struct b43_wldev *dev,
1159                                       u16 ram_offset,
1160                                       u16 shm_size_offset, u8 rate)
1161 {
1162         int len;
1163         const u8 *data;
1164
1165         B43_WARN_ON(!dev->cached_beacon);
1166         len = min((size_t) dev->cached_beacon->len,
1167                   0x200 - sizeof(struct b43_plcp_hdr6));
1168         data = (const u8 *)(dev->cached_beacon->data);
1169         b43_write_template_common(dev, data,
1170                                   len, ram_offset, shm_size_offset, rate);
1171 }
1172
1173 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1174                                       u16 shm_offset, u16 size, u8 rate)
1175 {
1176         struct b43_plcp_hdr4 plcp;
1177         u32 tmp;
1178         __le16 dur;
1179
1180         plcp.data = 0;
1181         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1182         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1183                                                dev->wl->if_id, size,
1184                                                B43_RATE_TO_BASE100KBPS(rate));
1185         /* Write PLCP in two parts and timing for packet transfer */
1186         tmp = le32_to_cpu(plcp.data);
1187         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1188         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1189         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1190 }
1191
1192 /* Instead of using custom probe response template, this function
1193  * just patches custom beacon template by:
1194  * 1) Changing packet type
1195  * 2) Patching duration field
1196  * 3) Stripping TIM
1197  */
1198 static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1199                                    u16 * dest_size, u8 rate)
1200 {
1201         const u8 *src_data;
1202         u8 *dest_data;
1203         u16 src_size, elem_size, src_pos, dest_pos;
1204         __le16 dur;
1205         struct ieee80211_hdr *hdr;
1206
1207         B43_WARN_ON(!dev->cached_beacon);
1208         src_size = dev->cached_beacon->len;
1209         src_data = (const u8 *)dev->cached_beacon->data;
1210
1211         if (unlikely(src_size < 0x24)) {
1212                 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1213                 return NULL;
1214         }
1215
1216         dest_data = kmalloc(src_size, GFP_ATOMIC);
1217         if (unlikely(!dest_data))
1218                 return NULL;
1219
1220         /* 0x24 is offset of first variable-len Information-Element
1221          * in beacon frame.
1222          */
1223         memcpy(dest_data, src_data, 0x24);
1224         src_pos = dest_pos = 0x24;
1225         for (; src_pos < src_size - 2; src_pos += elem_size) {
1226                 elem_size = src_data[src_pos + 1] + 2;
1227                 if (src_data[src_pos] != 0x05) {        /* TIM */
1228                         memcpy(dest_data + dest_pos, src_data + src_pos,
1229                                elem_size);
1230                         dest_pos += elem_size;
1231                 }
1232         }
1233         *dest_size = dest_pos;
1234         hdr = (struct ieee80211_hdr *)dest_data;
1235
1236         /* Set the frame control. */
1237         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1238                                          IEEE80211_STYPE_PROBE_RESP);
1239         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1240                                                dev->wl->if_id, *dest_size,
1241                                                B43_RATE_TO_BASE100KBPS(rate));
1242         hdr->duration_id = dur;
1243
1244         return dest_data;
1245 }
1246
1247 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1248                                           u16 ram_offset,
1249                                           u16 shm_size_offset, u8 rate)
1250 {
1251         u8 *probe_resp_data;
1252         u16 size;
1253
1254         B43_WARN_ON(!dev->cached_beacon);
1255         size = dev->cached_beacon->len;
1256         probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1257         if (unlikely(!probe_resp_data))
1258                 return;
1259
1260         /* Looks like PLCP headers plus packet timings are stored for
1261          * all possible basic rates
1262          */
1263         b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1264         b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1265         b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1266         b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1267
1268         size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1269         b43_write_template_common(dev, probe_resp_data,
1270                                   size, ram_offset, shm_size_offset, rate);
1271         kfree(probe_resp_data);
1272 }
1273
1274 static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1275                                      struct sk_buff *beacon)
1276 {
1277         if (dev->cached_beacon)
1278                 kfree_skb(dev->cached_beacon);
1279         dev->cached_beacon = beacon;
1280
1281         return 0;
1282 }
1283
1284 static void b43_update_templates(struct b43_wldev *dev)
1285 {
1286         u32 status;
1287
1288         B43_WARN_ON(!dev->cached_beacon);
1289
1290         b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1291         b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1292         b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1293
1294         status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1295         status |= 0x03;
1296         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1297 }
1298
1299 static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1300 {
1301         int err;
1302
1303         err = b43_refresh_cached_beacon(dev, beacon);
1304         if (unlikely(err))
1305                 return;
1306         b43_update_templates(dev);
1307 }
1308
1309 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1310 {
1311         u32 tmp;
1312         u16 i, len;
1313
1314         len = min((u16) ssid_len, (u16) 0x100);
1315         for (i = 0; i < len; i += sizeof(u32)) {
1316                 tmp = (u32) (ssid[i + 0]);
1317                 if (i + 1 < len)
1318                         tmp |= (u32) (ssid[i + 1]) << 8;
1319                 if (i + 2 < len)
1320                         tmp |= (u32) (ssid[i + 2]) << 16;
1321                 if (i + 3 < len)
1322                         tmp |= (u32) (ssid[i + 3]) << 24;
1323                 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1324         }
1325         b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1326 }
1327
1328 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1329 {
1330         b43_time_lock(dev);
1331         if (dev->dev->id.revision >= 3) {
1332                 b43_write32(dev, 0x188, (beacon_int << 16));
1333         } else {
1334                 b43_write16(dev, 0x606, (beacon_int >> 6));
1335                 b43_write16(dev, 0x610, beacon_int);
1336         }
1337         b43_time_unlock(dev);
1338 }
1339
1340 static void handle_irq_beacon(struct b43_wldev *dev)
1341 {
1342         u32 status;
1343
1344         if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1345                 return;
1346
1347         dev->irq_savedstate &= ~B43_IRQ_BEACON;
1348         status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1349
1350         if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1351                 /* ACK beacon IRQ. */
1352                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1353                 dev->irq_savedstate |= B43_IRQ_BEACON;
1354                 if (dev->cached_beacon)
1355                         kfree_skb(dev->cached_beacon);
1356                 dev->cached_beacon = NULL;
1357                 return;
1358         }
1359         if (!(status & 0x1)) {
1360                 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1361                 status |= 0x1;
1362                 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1363         }
1364         if (!(status & 0x2)) {
1365                 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1366                 status |= 0x2;
1367                 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1368         }
1369 }
1370
1371 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1372 {
1373         //TODO
1374 }
1375
1376 /* Interrupt handler bottom-half */
1377 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1378 {
1379         u32 reason;
1380         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1381         u32 merged_dma_reason = 0;
1382         int i;
1383         unsigned long flags;
1384
1385         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1386
1387         B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1388
1389         reason = dev->irq_reason;
1390         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1391                 dma_reason[i] = dev->dma_reason[i];
1392                 merged_dma_reason |= dma_reason[i];
1393         }
1394
1395         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1396                 b43err(dev->wl, "MAC transmission error\n");
1397
1398         if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1399                 b43err(dev->wl, "PHY transmission error\n");
1400                 rmb();
1401                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1402                         atomic_set(&dev->phy.txerr_cnt,
1403                                    B43_PHY_TX_BADNESS_LIMIT);
1404                         b43err(dev->wl, "Too many PHY TX errors, "
1405                                         "restarting the controller\n");
1406                         b43_controller_restart(dev, "PHY TX errors");
1407                 }
1408         }
1409
1410         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1411                                           B43_DMAIRQ_NONFATALMASK))) {
1412                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1413                         b43err(dev->wl, "Fatal DMA error: "
1414                                "0x%08X, 0x%08X, 0x%08X, "
1415                                "0x%08X, 0x%08X, 0x%08X\n",
1416                                dma_reason[0], dma_reason[1],
1417                                dma_reason[2], dma_reason[3],
1418                                dma_reason[4], dma_reason[5]);
1419                         b43_controller_restart(dev, "DMA error");
1420                         mmiowb();
1421                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1422                         return;
1423                 }
1424                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1425                         b43err(dev->wl, "DMA error: "
1426                                "0x%08X, 0x%08X, 0x%08X, "
1427                                "0x%08X, 0x%08X, 0x%08X\n",
1428                                dma_reason[0], dma_reason[1],
1429                                dma_reason[2], dma_reason[3],
1430                                dma_reason[4], dma_reason[5]);
1431                 }
1432         }
1433
1434         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1435                 handle_irq_ucode_debug(dev);
1436         if (reason & B43_IRQ_TBTT_INDI)
1437                 handle_irq_tbtt_indication(dev);
1438         if (reason & B43_IRQ_ATIM_END)
1439                 handle_irq_atim_end(dev);
1440         if (reason & B43_IRQ_BEACON)
1441                 handle_irq_beacon(dev);
1442         if (reason & B43_IRQ_PMQ)
1443                 handle_irq_pmq(dev);
1444         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1445                 ;/* TODO */
1446         if (reason & B43_IRQ_NOISESAMPLE_OK)
1447                 handle_irq_noise(dev);
1448
1449         /* Check the DMA reason registers for received data. */
1450         if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1451                 if (b43_using_pio(dev))
1452                         b43_pio_rx(dev->pio.queue0);
1453                 else
1454                         b43_dma_rx(dev->dma.rx_ring0);
1455         }
1456         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1457         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1458         if (dma_reason[3] & B43_DMAIRQ_RX_DONE) {
1459                 if (b43_using_pio(dev))
1460                         b43_pio_rx(dev->pio.queue3);
1461                 else
1462                         b43_dma_rx(dev->dma.rx_ring3);
1463         }
1464         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1465         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1466
1467         if (reason & B43_IRQ_TX_OK)
1468                 handle_irq_transmit_status(dev);
1469
1470         b43_interrupt_enable(dev, dev->irq_savedstate);
1471         mmiowb();
1472         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1473 }
1474
1475 static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx)
1476 {
1477         u16 rxctl;
1478
1479         rxctl = b43_read16(dev, base + B43_PIO_RXCTL);
1480         if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE)
1481                 dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE;
1482         else
1483                 dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE;
1484 }
1485
1486 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1487 {
1488         if (b43_using_pio(dev) &&
1489             (dev->dev->id.revision < 3) &&
1490             (!(reason & B43_IRQ_PIO_WORKAROUND))) {
1491                 /* Apply a PIO specific workaround to the dma_reasons */
1492                 pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0);
1493                 pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1);
1494                 pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2);
1495                 pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3);
1496         }
1497
1498         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1499
1500         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1501         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1502         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1503         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1504         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1505         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1506 }
1507
1508 /* Interrupt handler top-half */
1509 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1510 {
1511         irqreturn_t ret = IRQ_NONE;
1512         struct b43_wldev *dev = dev_id;
1513         u32 reason;
1514
1515         if (!dev)
1516                 return IRQ_NONE;
1517
1518         spin_lock(&dev->wl->irq_lock);
1519
1520         if (b43_status(dev) < B43_STAT_STARTED)
1521                 goto out;
1522         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1523         if (reason == 0xffffffff)       /* shared IRQ */
1524                 goto out;
1525         ret = IRQ_HANDLED;
1526         reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1527         if (!reason)
1528                 goto out;
1529
1530         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1531             & 0x0001DC00;
1532         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1533             & 0x0000DC00;
1534         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1535             & 0x0000DC00;
1536         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1537             & 0x0001DC00;
1538         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1539             & 0x0000DC00;
1540         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1541             & 0x0000DC00;
1542
1543         b43_interrupt_ack(dev, reason);
1544         /* disable all IRQs. They are enabled again in the bottom half. */
1545         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1546         /* save the reason code and call our bottom half. */
1547         dev->irq_reason = reason;
1548         tasklet_schedule(&dev->isr_tasklet);
1549       out:
1550         mmiowb();
1551         spin_unlock(&dev->wl->irq_lock);
1552
1553         return ret;
1554 }
1555
1556 static void b43_release_firmware(struct b43_wldev *dev)
1557 {
1558         release_firmware(dev->fw.ucode);
1559         dev->fw.ucode = NULL;
1560         release_firmware(dev->fw.pcm);
1561         dev->fw.pcm = NULL;
1562         release_firmware(dev->fw.initvals);
1563         dev->fw.initvals = NULL;
1564         release_firmware(dev->fw.initvals_band);
1565         dev->fw.initvals_band = NULL;
1566 }
1567
1568 static void b43_print_fw_helptext(struct b43_wl *wl)
1569 {
1570         b43err(wl, "You must go to "
1571                "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1572                "and download the correct firmware (version 4).\n");
1573 }
1574
1575 static int do_request_fw(struct b43_wldev *dev,
1576                          const char *name,
1577                          const struct firmware **fw)
1578 {
1579         char path[sizeof(modparam_fwpostfix) + 32];
1580         struct b43_fw_header *hdr;
1581         u32 size;
1582         int err;
1583
1584         if (!name)
1585                 return 0;
1586
1587         snprintf(path, ARRAY_SIZE(path),
1588                  "b43%s/%s.fw",
1589                  modparam_fwpostfix, name);
1590         err = request_firmware(fw, path, dev->dev->dev);
1591         if (err) {
1592                 b43err(dev->wl, "Firmware file \"%s\" not found "
1593                        "or load failed.\n", path);
1594                 return err;
1595         }
1596         if ((*fw)->size < sizeof(struct b43_fw_header))
1597                 goto err_format;
1598         hdr = (struct b43_fw_header *)((*fw)->data);
1599         switch (hdr->type) {
1600         case B43_FW_TYPE_UCODE:
1601         case B43_FW_TYPE_PCM:
1602                 size = be32_to_cpu(hdr->size);
1603                 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1604                         goto err_format;
1605                 /* fallthrough */
1606         case B43_FW_TYPE_IV:
1607                 if (hdr->ver != 1)
1608                         goto err_format;
1609                 break;
1610         default:
1611                 goto err_format;
1612         }
1613
1614         return err;
1615
1616 err_format:
1617         b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1618         return -EPROTO;
1619 }
1620
1621 static int b43_request_firmware(struct b43_wldev *dev)
1622 {
1623         struct b43_firmware *fw = &dev->fw;
1624         const u8 rev = dev->dev->id.revision;
1625         const char *filename;
1626         u32 tmshigh;
1627         int err;
1628
1629         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1630         if (!fw->ucode) {
1631                 if ((rev >= 5) && (rev <= 10))
1632                         filename = "ucode5";
1633                 else if ((rev >= 11) && (rev <= 12))
1634                         filename = "ucode11";
1635                 else if (rev >= 13)
1636                         filename = "ucode13";
1637                 else
1638                         goto err_no_ucode;
1639                 err = do_request_fw(dev, filename, &fw->ucode);
1640                 if (err)
1641                         goto err_load;
1642         }
1643         if (!fw->pcm) {
1644                 if ((rev >= 5) && (rev <= 10))
1645                         filename = "pcm5";
1646                 else if (rev >= 11)
1647                         filename = NULL;
1648                 else
1649                         goto err_no_pcm;
1650                 err = do_request_fw(dev, filename, &fw->pcm);
1651                 if (err)
1652                         goto err_load;
1653         }
1654         if (!fw->initvals) {
1655                 switch (dev->phy.type) {
1656                 case B43_PHYTYPE_A:
1657                         if ((rev >= 5) && (rev <= 10)) {
1658                                 if (tmshigh & B43_TMSHIGH_GPHY)
1659                                         filename = "a0g1initvals5";
1660                                 else
1661                                         filename = "a0g0initvals5";
1662                         } else
1663                                 goto err_no_initvals;
1664                         break;
1665                 case B43_PHYTYPE_G:
1666                         if ((rev >= 5) && (rev <= 10))
1667                                 filename = "b0g0initvals5";
1668                         else if (rev >= 13)
1669                                 filename = "lp0initvals13";
1670                         else
1671                                 goto err_no_initvals;
1672                         break;
1673                 default:
1674                         goto err_no_initvals;
1675                 }
1676                 err = do_request_fw(dev, filename, &fw->initvals);
1677                 if (err)
1678                         goto err_load;
1679         }
1680         if (!fw->initvals_band) {
1681                 switch (dev->phy.type) {
1682                 case B43_PHYTYPE_A:
1683                         if ((rev >= 5) && (rev <= 10)) {
1684                                 if (tmshigh & B43_TMSHIGH_GPHY)
1685                                         filename = "a0g1bsinitvals5";
1686                                 else
1687                                         filename = "a0g0bsinitvals5";
1688                         } else if (rev >= 11)
1689                                 filename = NULL;
1690                         else
1691                                 goto err_no_initvals;
1692                         break;
1693                 case B43_PHYTYPE_G:
1694                         if ((rev >= 5) && (rev <= 10))
1695                                 filename = "b0g0bsinitvals5";
1696                         else if (rev >= 11)
1697                                 filename = NULL;
1698                         else
1699                                 goto err_no_initvals;
1700                         break;
1701                 default:
1702                         goto err_no_initvals;
1703                 }
1704                 err = do_request_fw(dev, filename, &fw->initvals_band);
1705                 if (err)
1706                         goto err_load;
1707         }
1708
1709         return 0;
1710
1711 err_load:
1712         b43_print_fw_helptext(dev->wl);
1713         goto error;
1714
1715 err_no_ucode:
1716         err = -ENODEV;
1717         b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1718         goto error;
1719
1720 err_no_pcm:
1721         err = -ENODEV;
1722         b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1723         goto error;
1724
1725 err_no_initvals:
1726         err = -ENODEV;
1727         b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1728                "core rev %u\n", dev->phy.type, rev);
1729         goto error;
1730
1731 error:
1732         b43_release_firmware(dev);
1733         return err;
1734 }
1735
1736 static int b43_upload_microcode(struct b43_wldev *dev)
1737 {
1738         const size_t hdr_len = sizeof(struct b43_fw_header);
1739         const __be32 *data;
1740         unsigned int i, len;
1741         u16 fwrev, fwpatch, fwdate, fwtime;
1742         u32 tmp;
1743         int err = 0;
1744
1745         /* Upload Microcode. */
1746         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1747         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1748         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1749         for (i = 0; i < len; i++) {
1750                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1751                 udelay(10);
1752         }
1753
1754         if (dev->fw.pcm) {
1755                 /* Upload PCM data. */
1756                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1757                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1758                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1759                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1760                 /* No need for autoinc bit in SHM_HW */
1761                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1762                 for (i = 0; i < len; i++) {
1763                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1764                         udelay(10);
1765                 }
1766         }
1767
1768         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1769         b43_write32(dev, B43_MMIO_MACCTL,
1770                     B43_MACCTL_PSM_RUN |
1771                     B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1772
1773         /* Wait for the microcode to load and respond */
1774         i = 0;
1775         while (1) {
1776                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1777                 if (tmp == B43_IRQ_MAC_SUSPENDED)
1778                         break;
1779                 i++;
1780                 if (i >= 50) {
1781                         b43err(dev->wl, "Microcode not responding\n");
1782                         b43_print_fw_helptext(dev->wl);
1783                         err = -ENODEV;
1784                         goto out;
1785                 }
1786                 udelay(10);
1787         }
1788         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
1789
1790         /* Get and check the revisions. */
1791         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1792         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1793         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1794         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1795
1796         if (fwrev <= 0x128) {
1797                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1798                        "binary drivers older than version 4.x is unsupported. "
1799                        "You must upgrade your firmware files.\n");
1800                 b43_print_fw_helptext(dev->wl);
1801                 b43_write32(dev, B43_MMIO_MACCTL, 0);
1802                 err = -EOPNOTSUPP;
1803                 goto out;
1804         }
1805         b43dbg(dev->wl, "Loading firmware version %u.%u "
1806                "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1807                fwrev, fwpatch,
1808                (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1809                (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1810
1811         dev->fw.rev = fwrev;
1812         dev->fw.patch = fwpatch;
1813
1814       out:
1815         return err;
1816 }
1817
1818 static int b43_write_initvals(struct b43_wldev *dev,
1819                               const struct b43_iv *ivals,
1820                               size_t count,
1821                               size_t array_size)
1822 {
1823         const struct b43_iv *iv;
1824         u16 offset;
1825         size_t i;
1826         bool bit32;
1827
1828         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1829         iv = ivals;
1830         for (i = 0; i < count; i++) {
1831                 if (array_size < sizeof(iv->offset_size))
1832                         goto err_format;
1833                 array_size -= sizeof(iv->offset_size);
1834                 offset = be16_to_cpu(iv->offset_size);
1835                 bit32 = !!(offset & B43_IV_32BIT);
1836                 offset &= B43_IV_OFFSET_MASK;
1837                 if (offset >= 0x1000)
1838                         goto err_format;
1839                 if (bit32) {
1840                         u32 value;
1841
1842                         if (array_size < sizeof(iv->data.d32))
1843                                 goto err_format;
1844                         array_size -= sizeof(iv->data.d32);
1845
1846                         value = be32_to_cpu(get_unaligned(&iv->data.d32));
1847                         b43_write32(dev, offset, value);
1848
1849                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1850                                                         sizeof(__be16) +
1851                                                         sizeof(__be32));
1852                 } else {
1853                         u16 value;
1854
1855                         if (array_size < sizeof(iv->data.d16))
1856                                 goto err_format;
1857                         array_size -= sizeof(iv->data.d16);
1858
1859                         value = be16_to_cpu(iv->data.d16);
1860                         b43_write16(dev, offset, value);
1861
1862                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1863                                                         sizeof(__be16) +
1864                                                         sizeof(__be16));
1865                 }
1866         }
1867         if (array_size)
1868                 goto err_format;
1869
1870         return 0;
1871
1872 err_format:
1873         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1874         b43_print_fw_helptext(dev->wl);
1875
1876         return -EPROTO;
1877 }
1878
1879 static int b43_upload_initvals(struct b43_wldev *dev)
1880 {
1881         const size_t hdr_len = sizeof(struct b43_fw_header);
1882         const struct b43_fw_header *hdr;
1883         struct b43_firmware *fw = &dev->fw;
1884         const struct b43_iv *ivals;
1885         size_t count;
1886         int err;
1887
1888         hdr = (const struct b43_fw_header *)(fw->initvals->data);
1889         ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1890         count = be32_to_cpu(hdr->size);
1891         err = b43_write_initvals(dev, ivals, count,
1892                                  fw->initvals->size - hdr_len);
1893         if (err)
1894                 goto out;
1895         if (fw->initvals_band) {
1896                 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1897                 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1898                 count = be32_to_cpu(hdr->size);
1899                 err = b43_write_initvals(dev, ivals, count,
1900                                          fw->initvals_band->size - hdr_len);
1901                 if (err)
1902                         goto out;
1903         }
1904 out:
1905
1906         return err;
1907 }
1908
1909 /* Initialize the GPIOs
1910  * http://bcm-specs.sipsolutions.net/GPIO
1911  */
1912 static int b43_gpio_init(struct b43_wldev *dev)
1913 {
1914         struct ssb_bus *bus = dev->dev->bus;
1915         struct ssb_device *gpiodev, *pcidev = NULL;
1916         u32 mask, set;
1917
1918         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1919                     & ~B43_MACCTL_GPOUTSMSK);
1920
1921         b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1922                     | 0x000F);
1923
1924         mask = 0x0000001F;
1925         set = 0x0000000F;
1926         if (dev->dev->bus->chip_id == 0x4301) {
1927                 mask |= 0x0060;
1928                 set |= 0x0060;
1929         }
1930         if (0 /* FIXME: conditional unknown */ ) {
1931                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1932                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1933                             | 0x0100);
1934                 mask |= 0x0180;
1935                 set |= 0x0180;
1936         }
1937         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
1938                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1939                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1940                             | 0x0200);
1941                 mask |= 0x0200;
1942                 set |= 0x0200;
1943         }
1944         if (dev->dev->id.revision >= 2)
1945                 mask |= 0x0010; /* FIXME: This is redundant. */
1946
1947 #ifdef CONFIG_SSB_DRIVER_PCICORE
1948         pcidev = bus->pcicore.dev;
1949 #endif
1950         gpiodev = bus->chipco.dev ? : pcidev;
1951         if (!gpiodev)
1952                 return 0;
1953         ssb_write32(gpiodev, B43_GPIO_CONTROL,
1954                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1955                      & mask) | set);
1956
1957         return 0;
1958 }
1959
1960 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1961 static void b43_gpio_cleanup(struct b43_wldev *dev)
1962 {
1963         struct ssb_bus *bus = dev->dev->bus;
1964         struct ssb_device *gpiodev, *pcidev = NULL;
1965
1966 #ifdef CONFIG_SSB_DRIVER_PCICORE
1967         pcidev = bus->pcicore.dev;
1968 #endif
1969         gpiodev = bus->chipco.dev ? : pcidev;
1970         if (!gpiodev)
1971                 return;
1972         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1973 }
1974
1975 /* http://bcm-specs.sipsolutions.net/EnableMac */
1976 void b43_mac_enable(struct b43_wldev *dev)
1977 {
1978         dev->mac_suspended--;
1979         B43_WARN_ON(dev->mac_suspended < 0);
1980         B43_WARN_ON(irqs_disabled());
1981         if (dev->mac_suspended == 0) {
1982                 b43_write32(dev, B43_MMIO_MACCTL,
1983                             b43_read32(dev, B43_MMIO_MACCTL)
1984                             | B43_MACCTL_ENABLED);
1985                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1986                             B43_IRQ_MAC_SUSPENDED);
1987                 /* Commit writes */
1988                 b43_read32(dev, B43_MMIO_MACCTL);
1989                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1990                 b43_power_saving_ctl_bits(dev, 0);
1991
1992                 /* Re-enable IRQs. */
1993                 spin_lock_irq(&dev->wl->irq_lock);
1994                 b43_interrupt_enable(dev, dev->irq_savedstate);
1995                 spin_unlock_irq(&dev->wl->irq_lock);
1996         }
1997 }
1998
1999 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2000 void b43_mac_suspend(struct b43_wldev *dev)
2001 {
2002         int i;
2003         u32 tmp;
2004
2005         might_sleep();
2006         B43_WARN_ON(irqs_disabled());
2007         B43_WARN_ON(dev->mac_suspended < 0);
2008
2009         if (dev->mac_suspended == 0) {
2010                 /* Mask IRQs before suspending MAC. Otherwise
2011                  * the MAC stays busy and won't suspend. */
2012                 spin_lock_irq(&dev->wl->irq_lock);
2013                 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2014                 spin_unlock_irq(&dev->wl->irq_lock);
2015                 b43_synchronize_irq(dev);
2016                 dev->irq_savedstate = tmp;
2017
2018                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2019                 b43_write32(dev, B43_MMIO_MACCTL,
2020                             b43_read32(dev, B43_MMIO_MACCTL)
2021                             & ~B43_MACCTL_ENABLED);
2022                 /* force pci to flush the write */
2023                 b43_read32(dev, B43_MMIO_MACCTL);
2024                 for (i = 40; i; i--) {
2025                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2026                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2027                                 goto out;
2028                         msleep(1);
2029                 }
2030                 b43err(dev->wl, "MAC suspend failed\n");
2031         }
2032 out:
2033         dev->mac_suspended++;
2034 }
2035
2036 static void b43_adjust_opmode(struct b43_wldev *dev)
2037 {
2038         struct b43_wl *wl = dev->wl;
2039         u32 ctl;
2040         u16 cfp_pretbtt;
2041
2042         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2043         /* Reset status to STA infrastructure mode. */
2044         ctl &= ~B43_MACCTL_AP;
2045         ctl &= ~B43_MACCTL_KEEP_CTL;
2046         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2047         ctl &= ~B43_MACCTL_KEEP_BAD;
2048         ctl &= ~B43_MACCTL_PROMISC;
2049         ctl &= ~B43_MACCTL_BEACPROMISC;
2050         ctl |= B43_MACCTL_INFRA;
2051
2052         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2053                 ctl |= B43_MACCTL_AP;
2054         else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2055                 ctl &= ~B43_MACCTL_INFRA;
2056
2057         if (wl->filter_flags & FIF_CONTROL)
2058                 ctl |= B43_MACCTL_KEEP_CTL;
2059         if (wl->filter_flags & FIF_FCSFAIL)
2060                 ctl |= B43_MACCTL_KEEP_BAD;
2061         if (wl->filter_flags & FIF_PLCPFAIL)
2062                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2063         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2064                 ctl |= B43_MACCTL_PROMISC;
2065         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2066                 ctl |= B43_MACCTL_BEACPROMISC;
2067
2068         /* Workaround: On old hardware the HW-MAC-address-filter
2069          * doesn't work properly, so always run promisc in filter
2070          * it in software. */
2071         if (dev->dev->id.revision <= 4)
2072                 ctl |= B43_MACCTL_PROMISC;
2073
2074         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2075
2076         cfp_pretbtt = 2;
2077         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2078                 if (dev->dev->bus->chip_id == 0x4306 &&
2079                     dev->dev->bus->chip_rev == 3)
2080                         cfp_pretbtt = 100;
2081                 else
2082                         cfp_pretbtt = 50;
2083         }
2084         b43_write16(dev, 0x612, cfp_pretbtt);
2085 }
2086
2087 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2088 {
2089         u16 offset;
2090
2091         if (is_ofdm) {
2092                 offset = 0x480;
2093                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2094         } else {
2095                 offset = 0x4C0;
2096                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2097         }
2098         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2099                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2100 }
2101
2102 static void b43_rate_memory_init(struct b43_wldev *dev)
2103 {
2104         switch (dev->phy.type) {
2105         case B43_PHYTYPE_A:
2106         case B43_PHYTYPE_G:
2107                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2108                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2109                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2110                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2111                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2112                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2113                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2114                 if (dev->phy.type == B43_PHYTYPE_A)
2115                         break;
2116                 /* fallthrough */
2117         case B43_PHYTYPE_B:
2118                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2119                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2120                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2121                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2122                 break;
2123         default:
2124                 B43_WARN_ON(1);
2125         }
2126 }
2127
2128 /* Set the TX-Antenna for management frames sent by firmware. */
2129 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2130 {
2131         u16 ant = 0;
2132         u16 tmp;
2133
2134         switch (antenna) {
2135         case B43_ANTENNA0:
2136                 ant |= B43_TX4_PHY_ANT0;
2137                 break;
2138         case B43_ANTENNA1:
2139                 ant |= B43_TX4_PHY_ANT1;
2140                 break;
2141         case B43_ANTENNA_AUTO:
2142                 ant |= B43_TX4_PHY_ANTLAST;
2143                 break;
2144         default:
2145                 B43_WARN_ON(1);
2146         }
2147
2148         /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2149
2150         /* For Beacons */
2151         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2152         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2153         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2154         /* For ACK/CTS */
2155         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2156         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2157         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2158         /* For Probe Resposes */
2159         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2160         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2161         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2162 }
2163
2164 /* This is the opposite of b43_chip_init() */
2165 static void b43_chip_exit(struct b43_wldev *dev)
2166 {
2167         b43_radio_turn_off(dev, 1);
2168         b43_gpio_cleanup(dev);
2169         /* firmware is released later */
2170 }
2171
2172 /* Initialize the chip
2173  * http://bcm-specs.sipsolutions.net/ChipInit
2174  */
2175 static int b43_chip_init(struct b43_wldev *dev)
2176 {
2177         struct b43_phy *phy = &dev->phy;
2178         int err, tmp;
2179         u32 value32;
2180         u16 value16;
2181
2182         b43_write32(dev, B43_MMIO_MACCTL,
2183                     B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2184
2185         err = b43_request_firmware(dev);
2186         if (err)
2187                 goto out;
2188         err = b43_upload_microcode(dev);
2189         if (err)
2190                 goto out;       /* firmware is released later */
2191
2192         err = b43_gpio_init(dev);
2193         if (err)
2194                 goto out;       /* firmware is released later */
2195
2196         err = b43_upload_initvals(dev);
2197         if (err)
2198                 goto err_gpio_clean;
2199         b43_radio_turn_on(dev);
2200
2201         b43_write16(dev, 0x03E6, 0x0000);
2202         err = b43_phy_init(dev);
2203         if (err)
2204                 goto err_radio_off;
2205
2206         /* Select initial Interference Mitigation. */
2207         tmp = phy->interfmode;
2208         phy->interfmode = B43_INTERFMODE_NONE;
2209         b43_radio_set_interference_mitigation(dev, tmp);
2210
2211         b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2212         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2213
2214         if (phy->type == B43_PHYTYPE_B) {
2215                 value16 = b43_read16(dev, 0x005E);
2216                 value16 |= 0x0004;
2217                 b43_write16(dev, 0x005E, value16);
2218         }
2219         b43_write32(dev, 0x0100, 0x01000000);
2220         if (dev->dev->id.revision < 5)
2221                 b43_write32(dev, 0x010C, 0x01000000);
2222
2223         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2224                     & ~B43_MACCTL_INFRA);
2225         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2226                     | B43_MACCTL_INFRA);
2227
2228         if (b43_using_pio(dev)) {
2229                 b43_write32(dev, 0x0210, 0x00000100);
2230                 b43_write32(dev, 0x0230, 0x00000100);
2231                 b43_write32(dev, 0x0250, 0x00000100);
2232                 b43_write32(dev, 0x0270, 0x00000100);
2233                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000);
2234         }
2235
2236         /* Probe Response Timeout value */
2237         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2238         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2239
2240         /* Initially set the wireless operation mode. */
2241         b43_adjust_opmode(dev);
2242
2243         if (dev->dev->id.revision < 3) {
2244                 b43_write16(dev, 0x060E, 0x0000);
2245                 b43_write16(dev, 0x0610, 0x8000);
2246                 b43_write16(dev, 0x0604, 0x0000);
2247                 b43_write16(dev, 0x0606, 0x0200);
2248         } else {
2249                 b43_write32(dev, 0x0188, 0x80000000);
2250                 b43_write32(dev, 0x018C, 0x02000000);
2251         }
2252         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2253         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2254         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2255         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2256         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2257         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2258         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2259
2260         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2261         value32 |= 0x00100000;
2262         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2263
2264         b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2265                     dev->dev->bus->chipco.fast_pwrup_delay);
2266
2267         err = 0;
2268         b43dbg(dev->wl, "Chip initialized\n");
2269 out:
2270         return err;
2271
2272 err_radio_off:
2273         b43_radio_turn_off(dev, 1);
2274 err_gpio_clean:
2275         b43_gpio_cleanup(dev);
2276         return err;
2277 }
2278
2279 static void b43_periodic_every120sec(struct b43_wldev *dev)
2280 {
2281         struct b43_phy *phy = &dev->phy;
2282
2283         if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2284                 return;
2285
2286         b43_mac_suspend(dev);
2287         b43_lo_g_measure(dev);
2288         b43_mac_enable(dev);
2289         if (b43_has_hardware_pctl(phy))
2290                 b43_lo_g_ctl_mark_all_unused(dev);
2291 }
2292
2293 static void b43_periodic_every60sec(struct b43_wldev *dev)
2294 {
2295         struct b43_phy *phy = &dev->phy;
2296
2297         if (!b43_has_hardware_pctl(phy))
2298                 b43_lo_g_ctl_mark_all_unused(dev);
2299         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2300                 b43_mac_suspend(dev);
2301                 b43_calc_nrssi_slope(dev);
2302                 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2303                         u8 old_chan = phy->channel;
2304
2305                         /* VCO Calibration */
2306                         if (old_chan >= 8)
2307                                 b43_radio_selectchannel(dev, 1, 0);
2308                         else
2309                                 b43_radio_selectchannel(dev, 13, 0);
2310                         b43_radio_selectchannel(dev, old_chan, 0);
2311                 }
2312                 b43_mac_enable(dev);
2313         }
2314 }
2315
2316 static void b43_periodic_every30sec(struct b43_wldev *dev)
2317 {
2318         /* Update device statistics. */
2319         b43_calculate_link_quality(dev);
2320 }
2321
2322 static void b43_periodic_every15sec(struct b43_wldev *dev)
2323 {
2324         struct b43_phy *phy = &dev->phy;
2325
2326         if (phy->type == B43_PHYTYPE_G) {
2327                 //TODO: update_aci_moving_average
2328                 if (phy->aci_enable && phy->aci_wlan_automatic) {
2329                         b43_mac_suspend(dev);
2330                         if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2331                                 if (0 /*TODO: bunch of conditions */ ) {
2332                                         b43_radio_set_interference_mitigation
2333                                             (dev, B43_INTERFMODE_MANUALWLAN);
2334                                 }
2335                         } else if (1 /*TODO*/) {
2336                                 /*
2337                                    if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2338                                    b43_radio_set_interference_mitigation(dev,
2339                                    B43_INTERFMODE_NONE);
2340                                    }
2341                                  */
2342                         }
2343                         b43_mac_enable(dev);
2344                 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2345                            phy->rev == 1) {
2346                         //TODO: implement rev1 workaround
2347                 }
2348         }
2349         b43_phy_xmitpower(dev); //FIXME: unless scanning?
2350         //TODO for APHY (temperature?)
2351
2352         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2353         wmb();
2354 }
2355
2356 static void do_periodic_work(struct b43_wldev *dev)
2357 {
2358         unsigned int state;
2359
2360         state = dev->periodic_state;
2361         if (state % 8 == 0)
2362                 b43_periodic_every120sec(dev);
2363         if (state % 4 == 0)
2364                 b43_periodic_every60sec(dev);
2365         if (state % 2 == 0)
2366                 b43_periodic_every30sec(dev);
2367         b43_periodic_every15sec(dev);
2368 }
2369
2370 /* Periodic work locking policy:
2371  *      The whole periodic work handler is protected by
2372  *      wl->mutex. If another lock is needed somewhere in the
2373  *      pwork callchain, it's aquired in-place, where it's needed.
2374  */
2375 static void b43_periodic_work_handler(struct work_struct *work)
2376 {
2377         struct b43_wldev *dev = container_of(work, struct b43_wldev,
2378                                              periodic_work.work);
2379         struct b43_wl *wl = dev->wl;
2380         unsigned long delay;
2381
2382         mutex_lock(&wl->mutex);
2383
2384         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2385                 goto out;
2386         if (b43_debug(dev, B43_DBG_PWORK_STOP))
2387                 goto out_requeue;
2388
2389         do_periodic_work(dev);
2390
2391         dev->periodic_state++;
2392 out_requeue:
2393         if (b43_debug(dev, B43_DBG_PWORK_FAST))
2394                 delay = msecs_to_jiffies(50);
2395         else
2396                 delay = round_jiffies_relative(HZ * 15);
2397         queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2398 out:
2399         mutex_unlock(&wl->mutex);
2400 }
2401
2402 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2403 {
2404         struct delayed_work *work = &dev->periodic_work;
2405
2406         dev->periodic_state = 0;
2407         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2408         queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2409 }
2410
2411 /* Check if communication with the device works correctly. */
2412 static int b43_validate_chipaccess(struct b43_wldev *dev)
2413 {
2414         u32 v, backup;
2415
2416         backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2417
2418         /* Check for read/write and endianness problems. */
2419         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2420         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2421                 goto error;
2422         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2423         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2424                 goto error;
2425
2426         b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2427
2428         if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2429                 /* The 32bit register shadows the two 16bit registers
2430                  * with update sideeffects. Validate this. */
2431                 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2432                 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2433                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2434                         goto error;
2435                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2436                         goto error;
2437         }
2438         b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2439
2440         v = b43_read32(dev, B43_MMIO_MACCTL);
2441         v |= B43_MACCTL_GMODE;
2442         if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2443                 goto error;
2444
2445         return 0;
2446 error:
2447         b43err(dev->wl, "Failed to validate the chipaccess\n");
2448         return -ENODEV;
2449 }
2450
2451 static void b43_security_init(struct b43_wldev *dev)
2452 {
2453         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2454         B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2455         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2456         /* KTP is a word address, but we address SHM bytewise.
2457          * So multiply by two.
2458          */
2459         dev->ktp *= 2;
2460         if (dev->dev->id.revision >= 5) {
2461                 /* Number of RCMTA address slots */
2462                 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2463         }
2464         b43_clear_keys(dev);
2465 }
2466
2467 static int b43_rng_read(struct hwrng *rng, u32 * data)
2468 {
2469         struct b43_wl *wl = (struct b43_wl *)rng->priv;
2470         unsigned long flags;
2471
2472         /* Don't take wl->mutex here, as it could deadlock with
2473          * hwrng internal locking. It's not needed to take
2474          * wl->mutex here, anyway. */
2475
2476         spin_lock_irqsave(&wl->irq_lock, flags);
2477         *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2478         spin_unlock_irqrestore(&wl->irq_lock, flags);
2479
2480         return (sizeof(u16));
2481 }
2482
2483 static void b43_rng_exit(struct b43_wl *wl)
2484 {
2485         if (wl->rng_initialized)
2486                 hwrng_unregister(&wl->rng);
2487 }
2488
2489 static int b43_rng_init(struct b43_wl *wl)
2490 {
2491         int err;
2492
2493         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2494                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2495         wl->rng.name = wl->rng_name;
2496         wl->rng.data_read = b43_rng_read;
2497         wl->rng.priv = (unsigned long)wl;
2498         wl->rng_initialized = 1;
2499         err = hwrng_register(&wl->rng);
2500         if (err) {
2501                 wl->rng_initialized = 0;
2502                 b43err(wl, "Failed to register the random "
2503                        "number generator (%d)\n", err);
2504         }
2505
2506         return err;
2507 }
2508
2509 static int b43_op_tx(struct ieee80211_hw *hw,
2510                      struct sk_buff *skb,
2511                      struct ieee80211_tx_control *ctl)
2512 {
2513         struct b43_wl *wl = hw_to_b43_wl(hw);
2514         struct b43_wldev *dev = wl->current_dev;
2515         int err = -ENODEV;
2516         unsigned long flags;
2517
2518         if (unlikely(!dev))
2519                 goto out;
2520         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2521                 goto out;
2522         /* DMA-TX is done without a global lock. */
2523         if (b43_using_pio(dev)) {
2524                 spin_lock_irqsave(&wl->irq_lock, flags);
2525                 err = b43_pio_tx(dev, skb, ctl);
2526                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2527         } else
2528                 err = b43_dma_tx(dev, skb, ctl);
2529 out:
2530         if (unlikely(err))
2531                 return NETDEV_TX_BUSY;
2532         return NETDEV_TX_OK;
2533 }
2534
2535 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2536                           int queue,
2537                           const struct ieee80211_tx_queue_params *params)
2538 {
2539         return 0;
2540 }
2541
2542 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2543                                struct ieee80211_tx_queue_stats *stats)
2544 {
2545         struct b43_wl *wl = hw_to_b43_wl(hw);
2546         struct b43_wldev *dev = wl->current_dev;
2547         unsigned long flags;
2548         int err = -ENODEV;
2549
2550         if (!dev)
2551                 goto out;
2552         spin_lock_irqsave(&wl->irq_lock, flags);
2553         if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2554                 if (b43_using_pio(dev))
2555                         b43_pio_get_tx_stats(dev, stats);
2556                 else
2557                         b43_dma_get_tx_stats(dev, stats);
2558                 err = 0;
2559         }
2560         spin_unlock_irqrestore(&wl->irq_lock, flags);
2561 out:
2562         return err;
2563 }
2564
2565 static int b43_op_get_stats(struct ieee80211_hw *hw,
2566                             struct ieee80211_low_level_stats *stats)
2567 {
2568         struct b43_wl *wl = hw_to_b43_wl(hw);
2569         unsigned long flags;
2570
2571         spin_lock_irqsave(&wl->irq_lock, flags);
2572         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2573         spin_unlock_irqrestore(&wl->irq_lock, flags);
2574
2575         return 0;
2576 }
2577
2578 static const char *phymode_to_string(unsigned int phymode)
2579 {
2580         switch (phymode) {
2581         case B43_PHYMODE_A:
2582                 return "A";
2583         case B43_PHYMODE_B:
2584                 return "B";
2585         case B43_PHYMODE_G:
2586                 return "G";
2587         default:
2588                 B43_WARN_ON(1);
2589         }
2590         return "";
2591 }
2592
2593 static int find_wldev_for_phymode(struct b43_wl *wl,
2594                                   unsigned int phymode,
2595                                   struct b43_wldev **dev, bool * gmode)
2596 {
2597         struct b43_wldev *d;
2598
2599         list_for_each_entry(d, &wl->devlist, list) {
2600                 if (d->phy.possible_phymodes & phymode) {
2601                         /* Ok, this device supports the PHY-mode.
2602                          * Now figure out how the gmode bit has to be
2603                          * set to support it. */
2604                         if (phymode == B43_PHYMODE_A)
2605                                 *gmode = 0;
2606                         else
2607                                 *gmode = 1;
2608                         *dev = d;
2609
2610                         return 0;
2611                 }
2612         }
2613
2614         return -ESRCH;
2615 }
2616
2617 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2618 {
2619         struct ssb_device *sdev = dev->dev;
2620         u32 tmslow;
2621
2622         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2623         tmslow &= ~B43_TMSLOW_GMODE;
2624         tmslow |= B43_TMSLOW_PHYRESET;
2625         tmslow |= SSB_TMSLOW_FGC;
2626         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2627         msleep(1);
2628
2629         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2630         tmslow &= ~SSB_TMSLOW_FGC;
2631         tmslow |= B43_TMSLOW_PHYRESET;
2632         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2633         msleep(1);
2634 }
2635
2636 /* Expects wl->mutex locked */
2637 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2638 {
2639         struct b43_wldev *up_dev;
2640         struct b43_wldev *down_dev;
2641         int err;
2642         bool gmode = 0;
2643         int prev_status;
2644
2645         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2646         if (err) {
2647                 b43err(wl, "Could not find a device for %s-PHY mode\n",
2648                        phymode_to_string(new_mode));
2649                 return err;
2650         }
2651         if ((up_dev == wl->current_dev) &&
2652             (!!wl->current_dev->phy.gmode == !!gmode)) {
2653                 /* This device is already running. */
2654                 return 0;
2655         }
2656         b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2657                phymode_to_string(new_mode));
2658         down_dev = wl->current_dev;
2659
2660         prev_status = b43_status(down_dev);
2661         /* Shutdown the currently running core. */
2662         if (prev_status >= B43_STAT_STARTED)
2663                 b43_wireless_core_stop(down_dev);
2664         if (prev_status >= B43_STAT_INITIALIZED)
2665                 b43_wireless_core_exit(down_dev);
2666
2667         if (down_dev != up_dev) {
2668                 /* We switch to a different core, so we put PHY into
2669                  * RESET on the old core. */
2670                 b43_put_phy_into_reset(down_dev);
2671         }
2672
2673         /* Now start the new core. */
2674         up_dev->phy.gmode = gmode;
2675         if (prev_status >= B43_STAT_INITIALIZED) {
2676                 err = b43_wireless_core_init(up_dev);
2677                 if (err) {
2678                         b43err(wl, "Fatal: Could not initialize device for "
2679                                "newly selected %s-PHY mode\n",
2680                                phymode_to_string(new_mode));
2681                         goto init_failure;
2682                 }
2683         }
2684         if (prev_status >= B43_STAT_STARTED) {
2685                 err = b43_wireless_core_start(up_dev);
2686                 if (err) {
2687                         b43err(wl, "Fatal: Coult not start device for "
2688                                "newly selected %s-PHY mode\n",
2689                                phymode_to_string(new_mode));
2690                         b43_wireless_core_exit(up_dev);
2691                         goto init_failure;
2692                 }
2693         }
2694         B43_WARN_ON(b43_status(up_dev) != prev_status);
2695
2696         wl->current_dev = up_dev;
2697
2698         return 0;
2699       init_failure:
2700         /* Whoops, failed to init the new core. No core is operating now. */
2701         wl->current_dev = NULL;
2702         return err;
2703 }
2704
2705 /* Check if the use of the antenna that ieee80211 told us to
2706  * use is possible. This will fall back to DEFAULT.
2707  * "antenna_nr" is the antenna identifier we got from ieee80211. */
2708 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2709                                   u8 antenna_nr)
2710 {
2711         u8 antenna_mask;
2712
2713         if (antenna_nr == 0) {
2714                 /* Zero means "use default antenna". That's always OK. */
2715                 return 0;
2716         }
2717
2718         /* Get the mask of available antennas. */
2719         if (dev->phy.gmode)
2720                 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2721         else
2722                 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2723
2724         if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2725                 /* This antenna is not available. Fall back to default. */
2726                 return 0;
2727         }
2728
2729         return antenna_nr;
2730 }
2731
2732 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2733 {
2734         antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2735         switch (antenna) {
2736         case 0:         /* default/diversity */
2737                 return B43_ANTENNA_DEFAULT;
2738         case 1:         /* Antenna 0 */
2739                 return B43_ANTENNA0;
2740         case 2:         /* Antenna 1 */
2741                 return B43_ANTENNA1;
2742         default:
2743                 return B43_ANTENNA_DEFAULT;
2744         }
2745 }
2746
2747 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2748 {
2749         struct b43_wl *wl = hw_to_b43_wl(hw);
2750         struct b43_wldev *dev;
2751         struct b43_phy *phy;
2752         unsigned long flags;
2753         unsigned int new_phymode = 0xFFFF;
2754         int antenna;
2755         int err = 0;
2756         u32 savedirqs;
2757
2758         mutex_lock(&wl->mutex);
2759
2760         /* Switch the PHY mode (if necessary). */
2761         switch (conf->phymode) {
2762         case MODE_IEEE80211A:
2763                 new_phymode = B43_PHYMODE_A;
2764                 break;
2765         case MODE_IEEE80211B:
2766                 new_phymode = B43_PHYMODE_B;
2767                 break;
2768         case MODE_IEEE80211G:
2769                 new_phymode = B43_PHYMODE_G;
2770                 break;
2771         default:
2772                 B43_WARN_ON(1);
2773         }
2774         err = b43_switch_phymode(wl, new_phymode);
2775         if (err)
2776                 goto out_unlock_mutex;
2777         dev = wl->current_dev;
2778         phy = &dev->phy;
2779
2780         /* Disable IRQs while reconfiguring the device.
2781          * This makes it possible to drop the spinlock throughout
2782          * the reconfiguration process. */
2783         spin_lock_irqsave(&wl->irq_lock, flags);
2784         if (b43_status(dev) < B43_STAT_STARTED) {
2785                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2786                 goto out_unlock_mutex;
2787         }
2788         savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2789         spin_unlock_irqrestore(&wl->irq_lock, flags);
2790         b43_synchronize_irq(dev);
2791
2792         /* Switch to the requested channel.
2793          * The firmware takes care of races with the TX handler. */
2794         if (conf->channel_val != phy->channel)
2795                 b43_radio_selectchannel(dev, conf->channel_val, 0);
2796
2797         /* Enable/Disable ShortSlot timing. */
2798         if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2799             dev->short_slot) {
2800                 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2801                 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2802                         b43_short_slot_timing_enable(dev);
2803                 else
2804                         b43_short_slot_timing_disable(dev);
2805         }
2806
2807         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2808
2809         /* Adjust the desired TX power level. */
2810         if (conf->power_level != 0) {
2811                 if (conf->power_level != phy->power_level) {
2812                         phy->power_level = conf->power_level;
2813                         b43_phy_xmitpower(dev);
2814                 }
2815         }
2816
2817         /* Antennas for RX and management frame TX. */
2818         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2819         b43_mgmtframe_txantenna(dev, antenna);
2820         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2821         b43_set_rx_antenna(dev, antenna);
2822
2823         /* Update templates for AP mode. */
2824         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2825                 b43_set_beacon_int(dev, conf->beacon_int);
2826
2827         if (!!conf->radio_enabled != phy->radio_on) {
2828                 if (conf->radio_enabled) {
2829                         b43_radio_turn_on(dev);
2830                         b43info(dev->wl, "Radio turned on by software\n");
2831                         if (!dev->radio_hw_enable) {
2832                                 b43info(dev->wl, "The hardware RF-kill button "
2833                                         "still turns the radio physically off. "
2834                                         "Press the button to turn it on.\n");
2835                         }
2836                 } else {
2837                         b43_radio_turn_off(dev, 0);
2838                         b43info(dev->wl, "Radio turned off by software\n");
2839                 }
2840         }
2841
2842         spin_lock_irqsave(&wl->irq_lock, flags);
2843         b43_interrupt_enable(dev, savedirqs);
2844         mmiowb();
2845         spin_unlock_irqrestore(&wl->irq_lock, flags);
2846       out_unlock_mutex:
2847         mutex_unlock(&wl->mutex);
2848
2849         return err;
2850 }
2851
2852 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2853                            const u8 *local_addr, const u8 *addr,
2854                            struct ieee80211_key_conf *key)
2855 {
2856         struct b43_wl *wl = hw_to_b43_wl(hw);
2857         struct b43_wldev *dev;
2858         unsigned long flags;
2859         u8 algorithm;
2860         u8 index;
2861         int err;
2862         DECLARE_MAC_BUF(mac);
2863
2864         if (modparam_nohwcrypt)
2865                 return -ENOSPC; /* User disabled HW-crypto */
2866
2867         mutex_lock(&wl->mutex);
2868         spin_lock_irqsave(&wl->irq_lock, flags);
2869
2870         dev = wl->current_dev;
2871         err = -ENODEV;
2872         if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2873                 goto out_unlock;
2874
2875         err = -EINVAL;
2876         switch (key->alg) {
2877         case ALG_WEP:
2878                 if (key->keylen == 5)
2879                         algorithm = B43_SEC_ALGO_WEP40;
2880                 else
2881                         algorithm = B43_SEC_ALGO_WEP104;
2882                 break;
2883         case ALG_TKIP:
2884                 algorithm = B43_SEC_ALGO_TKIP;
2885                 break;
2886         case ALG_CCMP:
2887                 algorithm = B43_SEC_ALGO_AES;
2888                 break;
2889         default:
2890                 B43_WARN_ON(1);
2891                 goto out_unlock;
2892         }
2893         index = (u8) (key->keyidx);
2894         if (index > 3)
2895                 goto out_unlock;
2896
2897         switch (cmd) {
2898         case SET_KEY:
2899                 if (algorithm == B43_SEC_ALGO_TKIP) {
2900                         /* FIXME: No TKIP hardware encryption for now. */
2901                         err = -EOPNOTSUPP;
2902                         goto out_unlock;
2903                 }
2904
2905                 if (is_broadcast_ether_addr(addr)) {
2906                         /* addr is FF:FF:FF:FF:FF:FF for default keys */
2907                         err = b43_key_write(dev, index, algorithm,
2908                                             key->key, key->keylen, NULL, key);
2909                 } else {
2910                         /*
2911                          * either pairwise key or address is 00:00:00:00:00:00
2912                          * for transmit-only keys
2913                          */
2914                         err = b43_key_write(dev, -1, algorithm,
2915                                             key->key, key->keylen, addr, key);
2916                 }
2917                 if (err)
2918                         goto out_unlock;
2919
2920                 if (algorithm == B43_SEC_ALGO_WEP40 ||
2921                     algorithm == B43_SEC_ALGO_WEP104) {
2922                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2923                 } else {
2924                         b43_hf_write(dev,
2925                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2926                 }
2927                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2928                 break;
2929         case DISABLE_KEY: {
2930                 err = b43_key_clear(dev, key->hw_key_idx);
2931                 if (err)
2932                         goto out_unlock;
2933                 break;
2934         }
2935         default:
2936                 B43_WARN_ON(1);
2937         }
2938 out_unlock:
2939         spin_unlock_irqrestore(&wl->irq_lock, flags);
2940         mutex_unlock(&wl->mutex);
2941         if (!err) {
2942                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2943                        "mac: %s\n",
2944                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2945                        print_mac(mac, addr));
2946         }
2947         return err;
2948 }
2949
2950 static void b43_op_configure_filter(struct ieee80211_hw *hw,
2951                                     unsigned int changed, unsigned int *fflags,
2952                                     int mc_count, struct dev_addr_list *mc_list)
2953 {
2954         struct b43_wl *wl = hw_to_b43_wl(hw);
2955         struct b43_wldev *dev = wl->current_dev;
2956         unsigned long flags;
2957
2958         if (!dev) {
2959                 *fflags = 0;
2960                 return;
2961         }
2962
2963         spin_lock_irqsave(&wl->irq_lock, flags);
2964         *fflags &= FIF_PROMISC_IN_BSS |
2965                   FIF_ALLMULTI |
2966                   FIF_FCSFAIL |
2967                   FIF_PLCPFAIL |
2968                   FIF_CONTROL |
2969                   FIF_OTHER_BSS |
2970                   FIF_BCN_PRBRESP_PROMISC;
2971
2972         changed &= FIF_PROMISC_IN_BSS |
2973                    FIF_ALLMULTI |
2974                    FIF_FCSFAIL |
2975                    FIF_PLCPFAIL |
2976                    FIF_CONTROL |
2977                    FIF_OTHER_BSS |
2978                    FIF_BCN_PRBRESP_PROMISC;
2979
2980         wl->filter_flags = *fflags;
2981
2982         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2983                 b43_adjust_opmode(dev);
2984         spin_unlock_irqrestore(&wl->irq_lock, flags);
2985 }
2986
2987 static int b43_op_config_interface(struct ieee80211_hw *hw,
2988                                    int if_id,
2989                                    struct ieee80211_if_conf *conf)
2990 {
2991         struct b43_wl *wl = hw_to_b43_wl(hw);
2992         struct b43_wldev *dev = wl->current_dev;
2993         unsigned long flags;
2994
2995         if (!dev)
2996                 return -ENODEV;
2997         mutex_lock(&wl->mutex);
2998         spin_lock_irqsave(&wl->irq_lock, flags);
2999         B43_WARN_ON(wl->if_id != if_id);
3000         if (conf->bssid)
3001                 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3002         else
3003                 memset(wl->bssid, 0, ETH_ALEN);
3004         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3005                 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3006                         B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3007                         b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3008                         if (conf->beacon)
3009                                 b43_refresh_templates(dev, conf->beacon);
3010                 }
3011                 b43_write_mac_bssid_templates(dev);
3012         }
3013         spin_unlock_irqrestore(&wl->irq_lock, flags);
3014         mutex_unlock(&wl->mutex);
3015
3016         return 0;
3017 }
3018
3019 /* Locking: wl->mutex */
3020 static void b43_wireless_core_stop(struct b43_wldev *dev)
3021 {
3022         struct b43_wl *wl = dev->wl;
3023         unsigned long flags;
3024
3025         if (b43_status(dev) < B43_STAT_STARTED)
3026                 return;
3027
3028         /* Disable and sync interrupts. We must do this before than
3029          * setting the status to INITIALIZED, as the interrupt handler
3030          * won't care about IRQs then. */
3031         spin_lock_irqsave(&wl->irq_lock, flags);
3032         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3033         b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3034         spin_unlock_irqrestore(&wl->irq_lock, flags);
3035         b43_synchronize_irq(dev);
3036
3037         b43_set_status(dev, B43_STAT_INITIALIZED);
3038
3039         mutex_unlock(&wl->mutex);
3040         /* Must unlock as it would otherwise deadlock. No races here.
3041          * Cancel the possibly running self-rearming periodic work. */
3042         cancel_delayed_work_sync(&dev->periodic_work);
3043         mutex_lock(&wl->mutex);
3044
3045         ieee80211_stop_queues(wl->hw);  //FIXME this could cause a deadlock, as mac80211 seems buggy.
3046
3047         b43_mac_suspend(dev);
3048         free_irq(dev->dev->irq, dev);
3049         b43dbg(wl, "Wireless interface stopped\n");
3050 }
3051
3052 /* Locking: wl->mutex */
3053 static int b43_wireless_core_start(struct b43_wldev *dev)
3054 {
3055         int err;
3056
3057         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3058
3059         drain_txstatus_queue(dev);
3060         err = request_irq(dev->dev->irq, b43_interrupt_handler,
3061                           IRQF_SHARED, KBUILD_MODNAME, dev);
3062         if (err) {
3063                 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3064                 goto out;
3065         }
3066
3067         /* We are ready to run. */
3068         b43_set_status(dev, B43_STAT_STARTED);
3069
3070         /* Start data flow (TX/RX). */
3071         b43_mac_enable(dev);
3072         b43_interrupt_enable(dev, dev->irq_savedstate);
3073         ieee80211_start_queues(dev->wl->hw);
3074
3075         /* Start maintainance work */
3076         b43_periodic_tasks_setup(dev);
3077
3078         b43dbg(dev->wl, "Wireless interface started\n");
3079       out:
3080         return err;
3081 }
3082
3083 /* Get PHY and RADIO versioning numbers */
3084 static int b43_phy_versioning(struct b43_wldev *dev)
3085 {
3086         struct b43_phy *phy = &dev->phy;
3087         u32 tmp;
3088         u8 analog_type;
3089         u8 phy_type;
3090         u8 phy_rev;
3091         u16 radio_manuf;
3092         u16 radio_ver;
3093         u16 radio_rev;
3094         int unsupported = 0;
3095
3096         /* Get PHY versioning */
3097         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3098         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3099         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3100         phy_rev = (tmp & B43_PHYVER_VERSION);
3101         switch (phy_type) {
3102         case B43_PHYTYPE_A:
3103                 if (phy_rev >= 4)
3104                         unsupported = 1;
3105                 break;
3106         case B43_PHYTYPE_B:
3107                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3108                     && phy_rev != 7)
3109                         unsupported = 1;
3110                 break;
3111         case B43_PHYTYPE_G:
3112                 if (phy_rev > 9)
3113                         unsupported = 1;
3114                 break;
3115         default:
3116                 unsupported = 1;
3117         };
3118         if (unsupported) {
3119                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3120                        "(Analog %u, Type %u, Revision %u)\n",
3121                        analog_type, phy_type, phy_rev);
3122                 return -EOPNOTSUPP;
3123         }
3124         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3125                analog_type, phy_type, phy_rev);
3126
3127         /* Get RADIO versioning */
3128         if (dev->dev->bus->chip_id == 0x4317) {
3129                 if (dev->dev->bus->chip_rev == 0)
3130                         tmp = 0x3205017F;
3131                 else if (dev->dev->bus->chip_rev == 1)
3132                         tmp = 0x4205017F;
3133                 else
3134                         tmp = 0x5205017F;
3135         } else {
3136                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3137                 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3138                 tmp <<= 16;
3139                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3140                 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3141         }
3142         radio_manuf = (tmp & 0x00000FFF);
3143         radio_ver = (tmp & 0x0FFFF000) >> 12;
3144         radio_rev = (tmp & 0xF0000000) >> 28;
3145         switch (phy_type) {
3146         case B43_PHYTYPE_A:
3147                 if (radio_ver != 0x2060)
3148                         unsupported = 1;
3149                 if (radio_rev != 1)
3150                         unsupported = 1;
3151                 if (radio_manuf != 0x17F)
3152                         unsupported = 1;
3153                 break;
3154         case B43_PHYTYPE_B:
3155                 if ((radio_ver & 0xFFF0) != 0x2050)
3156                         unsupported = 1;
3157                 break;
3158         case B43_PHYTYPE_G:
3159                 if (radio_ver != 0x2050)
3160                         unsupported = 1;
3161                 break;
3162         default:
3163                 B43_WARN_ON(1);
3164         }
3165         if (unsupported) {
3166                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3167                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3168                        radio_manuf, radio_ver, radio_rev);
3169                 return -EOPNOTSUPP;
3170         }
3171         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3172                radio_manuf, radio_ver, radio_rev);
3173
3174         phy->radio_manuf = radio_manuf;
3175         phy->radio_ver = radio_ver;
3176         phy->radio_rev = radio_rev;
3177
3178         phy->analog = analog_type;
3179         phy->type = phy_type;
3180         phy->rev = phy_rev;
3181
3182         return 0;
3183 }
3184
3185 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3186                                       struct b43_phy *phy)
3187 {
3188         struct b43_txpower_lo_control *lo;
3189         int i;
3190
3191         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3192         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3193
3194         /* Flags */
3195         phy->locked = 0;
3196
3197         phy->aci_enable = 0;
3198         phy->aci_wlan_automatic = 0;
3199         phy->aci_hw_rssi = 0;
3200
3201         phy->radio_off_context.valid = 0;
3202
3203         lo = phy->lo_control;
3204         if (lo) {
3205                 memset(lo, 0, sizeof(*(phy->lo_control)));
3206                 lo->rebuild = 1;
3207                 lo->tx_bias = 0xFF;
3208         }
3209         phy->max_lb_gain = 0;
3210         phy->trsw_rx_gain = 0;
3211         phy->txpwr_offset = 0;
3212
3213         /* NRSSI */
3214         phy->nrssislope = 0;
3215         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3216                 phy->nrssi[i] = -1000;
3217         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3218                 phy->nrssi_lt[i] = i;
3219
3220         phy->lofcal = 0xFFFF;
3221         phy->initval = 0xFFFF;
3222
3223         spin_lock_init(&phy->lock);
3224         phy->interfmode = B43_INTERFMODE_NONE;
3225         phy->channel = 0xFF;
3226
3227         phy->hardware_power_control = !!modparam_hwpctl;
3228
3229         /* PHY TX errors counter. */
3230         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3231
3232         /* OFDM-table address caching. */
3233         phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3234 }
3235
3236 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3237 {
3238         /* Flags */
3239         dev->reg124_set_0x4 = 0;
3240         /* Assume the radio is enabled. If it's not enabled, the state will
3241          * immediately get fixed on the first periodic work run. */
3242         dev->radio_hw_enable = 1;
3243
3244         /* Stats */
3245         memset(&dev->stats, 0, sizeof(dev->stats));
3246
3247         setup_struct_phy_for_init(dev, &dev->phy);
3248
3249         /* IRQ related flags */
3250         dev->irq_reason = 0;
3251         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3252         dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3253
3254         dev->mac_suspended = 1;
3255
3256         /* Noise calculation context */
3257         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3258 }
3259
3260 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3261 {
3262         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3263         u32 hf;
3264
3265         if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3266                 return;
3267         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3268                 return;
3269
3270         hf = b43_hf_read(dev);
3271         if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3272                 hf |= B43_HF_BTCOEXALT;
3273         else
3274                 hf |= B43_HF_BTCOEX;
3275         b43_hf_write(dev, hf);
3276         //TODO
3277 }
3278
3279 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3280 {                               //TODO
3281 }
3282
3283 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3284 {
3285 #ifdef CONFIG_SSB_DRIVER_PCICORE
3286         struct ssb_bus *bus = dev->dev->bus;
3287         u32 tmp;
3288
3289         if (bus->pcicore.dev &&
3290             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3291             bus->pcicore.dev->id.revision <= 5) {
3292                 /* IMCFGLO timeouts workaround. */
3293                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3294                 tmp &= ~SSB_IMCFGLO_REQTO;
3295                 tmp &= ~SSB_IMCFGLO_SERTO;
3296                 switch (bus->bustype) {
3297                 case SSB_BUSTYPE_PCI:
3298                 case SSB_BUSTYPE_PCMCIA:
3299                         tmp |= 0x32;
3300                         break;
3301                 case SSB_BUSTYPE_SSB:
3302                         tmp |= 0x53;
3303                         break;
3304                 }
3305                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3306         }
3307 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3308 }
3309
3310 /* Write the short and long frame retry limit values. */
3311 static void b43_set_retry_limits(struct b43_wldev *dev,
3312                                  unsigned int short_retry,
3313                                  unsigned int long_retry)
3314 {
3315         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3316          * the chip-internal counter. */
3317         short_retry = min(short_retry, (unsigned int)0xF);
3318         long_retry = min(long_retry, (unsigned int)0xF);
3319
3320         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3321                         short_retry);
3322         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3323                         long_retry);
3324 }
3325
3326 /* Shutdown a wireless core */
3327 /* Locking: wl->mutex */
3328 static void b43_wireless_core_exit(struct b43_wldev *dev)
3329 {
3330         struct b43_phy *phy = &dev->phy;
3331
3332         B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3333         if (b43_status(dev) != B43_STAT_INITIALIZED)
3334                 return;
3335         b43_set_status(dev, B43_STAT_UNINIT);
3336
3337         b43_leds_exit(dev);
3338         b43_rng_exit(dev->wl);
3339         b43_pio_free(dev);
3340         b43_dma_free(dev);
3341         b43_chip_exit(dev);
3342         b43_radio_turn_off(dev, 1);
3343         b43_switch_analog(dev, 0);
3344         if (phy->dyn_tssi_tbl)
3345                 kfree(phy->tssi2dbm);
3346         kfree(phy->lo_control);
3347         phy->lo_control = NULL;
3348         ssb_device_disable(dev->dev, 0);
3349         ssb_bus_may_powerdown(dev->dev->bus);
3350 }
3351
3352 /* Initialize a wireless core */
3353 static int b43_wireless_core_init(struct b43_wldev *dev)
3354 {
3355         struct b43_wl *wl = dev->wl;
3356         struct ssb_bus *bus = dev->dev->bus;
3357         struct ssb_sprom *sprom = &bus->sprom;
3358         struct b43_phy *phy = &dev->phy;
3359         int err;
3360         u32 hf, tmp;
3361
3362         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3363
3364         err = ssb_bus_powerup(bus, 0);
3365         if (err)
3366                 goto out;
3367         if (!ssb_device_is_enabled(dev->dev)) {
3368                 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3369                 b43_wireless_core_reset(dev, tmp);
3370         }
3371
3372         if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3373                 phy->lo_control =
3374                     kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3375                 if (!phy->lo_control) {
3376                         err = -ENOMEM;
3377                         goto err_busdown;
3378                 }
3379         }
3380         setup_struct_wldev_for_init(dev);
3381
3382         err = b43_phy_init_tssi2dbm_table(dev);
3383         if (err)
3384                 goto err_kfree_lo_control;
3385
3386         /* Enable IRQ routing to this device. */
3387         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3388
3389         b43_imcfglo_timeouts_workaround(dev);
3390         b43_bluetooth_coext_disable(dev);
3391         b43_phy_early_init(dev);
3392         err = b43_chip_init(dev);
3393         if (err)
3394                 goto err_kfree_tssitbl;
3395         b43_shm_write16(dev, B43_SHM_SHARED,
3396                         B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3397         hf = b43_hf_read(dev);
3398         if (phy->type == B43_PHYTYPE_G) {
3399                 hf |= B43_HF_SYMW;
3400                 if (phy->rev == 1)
3401                         hf |= B43_HF_GDCW;
3402                 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3403                         hf |= B43_HF_OFDMPABOOST;
3404         } else if (phy->type == B43_PHYTYPE_B) {
3405                 hf |= B43_HF_SYMW;
3406                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3407                         hf &= ~B43_HF_GDCW;
3408         }
3409         b43_hf_write(dev, hf);
3410
3411         b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3412                              B43_DEFAULT_LONG_RETRY_LIMIT);
3413         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3414         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3415
3416         /* Disable sending probe responses from firmware.
3417          * Setting the MaxTime to one usec will always trigger
3418          * a timeout, so we never send any probe resp.
3419          * A timeout of zero is infinite. */
3420         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3421
3422         b43_rate_memory_init(dev);
3423
3424         /* Minimum Contention Window */
3425         if (phy->type == B43_PHYTYPE_B) {
3426                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3427         } else {
3428                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3429         }
3430         /* Maximum Contention Window */
3431         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3432
3433         do {
3434                 if (b43_using_pio(dev)) {
3435                         err = b43_pio_init(dev);
3436                 } else {
3437                         err = b43_dma_init(dev);
3438                         if (!err)
3439                                 b43_qos_init(dev);
3440                 }
3441         } while (err == -EAGAIN);
3442         if (err)
3443                 goto err_chip_exit;
3444
3445 //FIXME
3446 #if 1
3447         b43_write16(dev, 0x0612, 0x0050);
3448         b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3449         b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3450 #endif
3451
3452         b43_bluetooth_coext_enable(dev);
3453
3454         ssb_bus_powerup(bus, 1);        /* Enable dynamic PCTL */
3455         memset(wl->bssid, 0, ETH_ALEN);
3456         memset(wl->mac_addr, 0, ETH_ALEN);
3457         b43_upload_card_macaddress(dev);
3458         b43_security_init(dev);
3459         b43_rng_init(wl);
3460
3461         b43_set_status(dev, B43_STAT_INITIALIZED);
3462
3463         b43_leds_init(dev);
3464 out:
3465         return err;
3466
3467       err_chip_exit:
3468         b43_chip_exit(dev);
3469       err_kfree_tssitbl:
3470         if (phy->dyn_tssi_tbl)
3471                 kfree(phy->tssi2dbm);
3472       err_kfree_lo_control:
3473         kfree(phy->lo_control);
3474         phy->lo_control = NULL;
3475       err_busdown:
3476         ssb_bus_may_powerdown(bus);
3477         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3478         return err;
3479 }
3480
3481 static int b43_op_add_interface(struct ieee80211_hw *hw,
3482                                 struct ieee80211_if_init_conf *conf)
3483 {
3484         struct b43_wl *wl = hw_to_b43_wl(hw);
3485         struct b43_wldev *dev;
3486         unsigned long flags;
3487         int err = -EOPNOTSUPP;
3488
3489         /* TODO: allow WDS/AP devices to coexist */
3490
3491         if (conf->type != IEEE80211_IF_TYPE_AP &&
3492             conf->type != IEEE80211_IF_TYPE_STA &&
3493             conf->type != IEEE80211_IF_TYPE_WDS &&
3494             conf->type != IEEE80211_IF_TYPE_IBSS)
3495                 return -EOPNOTSUPP;
3496
3497         mutex_lock(&wl->mutex);
3498         if (wl->operating)
3499                 goto out_mutex_unlock;
3500
3501         b43dbg(wl, "Adding Interface type %d\n", conf->type);
3502
3503         dev = wl->current_dev;
3504         wl->operating = 1;
3505         wl->if_id = conf->if_id;
3506         wl->if_type = conf->type;
3507         memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3508
3509         spin_lock_irqsave(&wl->irq_lock, flags);
3510         b43_adjust_opmode(dev);
3511         b43_upload_card_macaddress(dev);
3512         spin_unlock_irqrestore(&wl->irq_lock, flags);
3513
3514         err = 0;
3515  out_mutex_unlock:
3516         mutex_unlock(&wl->mutex);
3517
3518         return err;
3519 }
3520
3521 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3522                                     struct ieee80211_if_init_conf *conf)
3523 {
3524         struct b43_wl *wl = hw_to_b43_wl(hw);
3525         struct b43_wldev *dev = wl->current_dev;
3526         unsigned long flags;
3527
3528         b43dbg(wl, "Removing Interface type %d\n", conf->type);
3529
3530         mutex_lock(&wl->mutex);
3531
3532         B43_WARN_ON(!wl->operating);
3533         B43_WARN_ON(wl->if_id != conf->if_id);
3534
3535         wl->operating = 0;
3536
3537         spin_lock_irqsave(&wl->irq_lock, flags);
3538         b43_adjust_opmode(dev);
3539         memset(wl->mac_addr, 0, ETH_ALEN);
3540         b43_upload_card_macaddress(dev);
3541         spin_unlock_irqrestore(&wl->irq_lock, flags);
3542
3543         mutex_unlock(&wl->mutex);
3544 }
3545
3546 static int b43_op_start(struct ieee80211_hw *hw)
3547 {
3548         struct b43_wl *wl = hw_to_b43_wl(hw);
3549         struct b43_wldev *dev = wl->current_dev;
3550         int did_init = 0;
3551         int err = 0;
3552
3553         /* First register RFkill.
3554          * LEDs that are registered later depend on it. */
3555         b43_rfkill_init(dev);
3556
3557         mutex_lock(&wl->mutex);
3558
3559         if (b43_status(dev) < B43_STAT_INITIALIZED) {
3560                 err = b43_wireless_core_init(dev);
3561                 if (err)
3562                         goto out_mutex_unlock;
3563                 did_init = 1;
3564         }
3565
3566         if (b43_status(dev) < B43_STAT_STARTED) {
3567                 err = b43_wireless_core_start(dev);
3568                 if (err) {
3569                         if (did_init)
3570                                 b43_wireless_core_exit(dev);
3571                         goto out_mutex_unlock;
3572                 }
3573         }
3574
3575  out_mutex_unlock:
3576         mutex_unlock(&wl->mutex);
3577
3578         return err;
3579 }
3580
3581 static void b43_op_stop(struct ieee80211_hw *hw)
3582 {
3583         struct b43_wl *wl = hw_to_b43_wl(hw);
3584         struct b43_wldev *dev = wl->current_dev;
3585
3586         b43_rfkill_exit(dev);
3587
3588         mutex_lock(&wl->mutex);
3589         if (b43_status(dev) >= B43_STAT_STARTED)
3590                 b43_wireless_core_stop(dev);
3591         b43_wireless_core_exit(dev);
3592         mutex_unlock(&wl->mutex);
3593 }
3594
3595 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3596                                   u32 short_retry_limit, u32 long_retry_limit)
3597 {
3598         struct b43_wl *wl = hw_to_b43_wl(hw);
3599         struct b43_wldev *dev;
3600         int err = 0;
3601
3602         mutex_lock(&wl->mutex);
3603         dev = wl->current_dev;
3604         if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3605                 err = -ENODEV;
3606                 goto out_unlock;
3607         }
3608         b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3609 out_unlock:
3610         mutex_unlock(&wl->mutex);
3611
3612         return err;
3613 }
3614
3615 static const struct ieee80211_ops b43_hw_ops = {
3616         .tx                     = b43_op_tx,
3617         .conf_tx                = b43_op_conf_tx,
3618         .add_interface          = b43_op_add_interface,
3619         .remove_interface       = b43_op_remove_interface,
3620         .config                 = b43_op_config,
3621         .config_interface       = b43_op_config_interface,
3622         .configure_filter       = b43_op_configure_filter,
3623         .set_key                = b43_op_set_key,
3624         .get_stats              = b43_op_get_stats,
3625         .get_tx_stats           = b43_op_get_tx_stats,
3626         .start                  = b43_op_start,
3627         .stop                   = b43_op_stop,
3628         .set_retry_limit        = b43_op_set_retry_limit,
3629 };
3630
3631 /* Hard-reset the chip. Do not call this directly.
3632  * Use b43_controller_restart()
3633  */
3634 static void b43_chip_reset(struct work_struct *work)
3635 {
3636         struct b43_wldev *dev =
3637             container_of(work, struct b43_wldev, restart_work);
3638         struct b43_wl *wl = dev->wl;
3639         int err = 0;
3640         int prev_status;
3641
3642         mutex_lock(&wl->mutex);
3643
3644         prev_status = b43_status(dev);
3645         /* Bring the device down... */
3646         if (prev_status >= B43_STAT_STARTED)
3647                 b43_wireless_core_stop(dev);
3648         if (prev_status >= B43_STAT_INITIALIZED)
3649                 b43_wireless_core_exit(dev);
3650
3651         /* ...and up again. */
3652         if (prev_status >= B43_STAT_INITIALIZED) {
3653                 err = b43_wireless_core_init(dev);
3654                 if (err)
3655                         goto out;
3656         }
3657         if (prev_status >= B43_STAT_STARTED) {
3658                 err = b43_wireless_core_start(dev);
3659                 if (err) {
3660                         b43_wireless_core_exit(dev);
3661                         goto out;
3662                 }
3663         }
3664       out:
3665         mutex_unlock(&wl->mutex);
3666         if (err)
3667                 b43err(wl, "Controller restart FAILED\n");
3668         else
3669                 b43info(wl, "Controller restarted\n");
3670 }
3671
3672 static int b43_setup_modes(struct b43_wldev *dev,
3673                            int have_aphy, int have_bphy, int have_gphy)
3674 {
3675         struct ieee80211_hw *hw = dev->wl->hw;
3676         struct ieee80211_hw_mode *mode;
3677         struct b43_phy *phy = &dev->phy;
3678         int cnt = 0;
3679         int err;
3680
3681 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3682         have_aphy = 0;
3683
3684         phy->possible_phymodes = 0;
3685         for (; 1; cnt++) {
3686                 if (have_aphy) {
3687                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3688                         mode = &phy->hwmodes[cnt];
3689
3690                         mode->mode = MODE_IEEE80211A;
3691                         mode->num_channels = b43_a_chantable_size;
3692                         mode->channels = b43_a_chantable;
3693                         mode->num_rates = b43_a_ratetable_size;
3694                         mode->rates = b43_a_ratetable;
3695                         err = ieee80211_register_hwmode(hw, mode);
3696                         if (err)
3697                                 return err;
3698
3699                         phy->possible_phymodes |= B43_PHYMODE_A;
3700                         have_aphy = 0;
3701                         continue;
3702                 }
3703                 if (have_bphy) {
3704                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3705                         mode = &phy->hwmodes[cnt];
3706
3707                         mode->mode = MODE_IEEE80211B;
3708                         mode->num_channels = b43_bg_chantable_size;
3709                         mode->channels = b43_bg_chantable;
3710                         mode->num_rates = b43_b_ratetable_size;
3711                         mode->rates = b43_b_ratetable;
3712                         err = ieee80211_register_hwmode(hw, mode);
3713                         if (err)
3714                                 return err;
3715
3716                         phy->possible_phymodes |= B43_PHYMODE_B;
3717                         have_bphy = 0;
3718                         continue;
3719                 }
3720                 if (have_gphy) {
3721                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3722                         mode = &phy->hwmodes[cnt];
3723
3724                         mode->mode = MODE_IEEE80211G;
3725                         mode->num_channels = b43_bg_chantable_size;
3726                         mode->channels = b43_bg_chantable;
3727                         mode->num_rates = b43_g_ratetable_size;
3728                         mode->rates = b43_g_ratetable;
3729                         err = ieee80211_register_hwmode(hw, mode);
3730                         if (err)
3731                                 return err;
3732
3733                         phy->possible_phymodes |= B43_PHYMODE_G;
3734                         have_gphy = 0;
3735                         continue;
3736                 }
3737                 break;
3738         }
3739
3740         return 0;
3741 }
3742
3743 static void b43_wireless_core_detach(struct b43_wldev *dev)
3744 {
3745         /* We release firmware that late to not be required to re-request
3746          * is all the time when we reinit the core. */
3747         b43_release_firmware(dev);
3748 }
3749
3750 static int b43_wireless_core_attach(struct b43_wldev *dev)
3751 {
3752         struct b43_wl *wl = dev->wl;
3753         struct ssb_bus *bus = dev->dev->bus;
3754         struct pci_dev *pdev = bus->host_pci;
3755         int err;
3756         int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3757         u32 tmp;
3758
3759         /* Do NOT do any device initialization here.
3760          * Do it in wireless_core_init() instead.
3761          * This function is for gathering basic information about the HW, only.
3762          * Also some structs may be set up here. But most likely you want to have
3763          * that in core_init(), too.
3764          */
3765
3766         err = ssb_bus_powerup(bus, 0);
3767         if (err) {
3768                 b43err(wl, "Bus powerup failed\n");
3769                 goto out;
3770         }
3771         /* Get the PHY type. */
3772         if (dev->dev->id.revision >= 5) {
3773                 u32 tmshigh;
3774
3775                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3776                 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
3777                 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
3778                 if (!have_aphy && !have_gphy)
3779                         have_bphy = 1;
3780         } else if (dev->dev->id.revision == 4) {
3781                 have_gphy = 1;
3782                 have_aphy = 1;
3783         } else
3784                 have_bphy = 1;
3785
3786         dev->phy.gmode = (have_gphy || have_bphy);
3787         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3788         b43_wireless_core_reset(dev, tmp);
3789
3790         err = b43_phy_versioning(dev);
3791         if (err)
3792                 goto err_powerdown;
3793         /* Check if this device supports multiband. */
3794         if (!pdev ||
3795             (pdev->device != 0x4312 &&
3796              pdev->device != 0x4319 && pdev->device != 0x4324)) {
3797                 /* No multiband support. */
3798                 have_aphy = 0;
3799                 have_bphy = 0;
3800                 have_gphy = 0;
3801                 switch (dev->phy.type) {
3802                 case B43_PHYTYPE_A:
3803                         have_aphy = 1;
3804                         break;
3805                 case B43_PHYTYPE_B:
3806                         have_bphy = 1;
3807                         break;
3808                 case B43_PHYTYPE_G:
3809                         have_gphy = 1;
3810                         break;
3811                 default:
3812                         B43_WARN_ON(1);
3813                 }
3814         }
3815         dev->phy.gmode = (have_gphy || have_bphy);
3816         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3817         b43_wireless_core_reset(dev, tmp);
3818
3819         err = b43_validate_chipaccess(dev);
3820         if (err)
3821                 goto err_powerdown;
3822         err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
3823         if (err)
3824                 goto err_powerdown;
3825
3826         /* Now set some default "current_dev" */
3827         if (!wl->current_dev)
3828                 wl->current_dev = dev;
3829         INIT_WORK(&dev->restart_work, b43_chip_reset);
3830
3831         b43_radio_turn_off(dev, 1);
3832         b43_switch_analog(dev, 0);
3833         ssb_device_disable(dev->dev, 0);
3834         ssb_bus_may_powerdown(bus);
3835
3836 out:
3837         return err;
3838
3839 err_powerdown:
3840         ssb_bus_may_powerdown(bus);
3841         return err;
3842 }
3843
3844 static void b43_one_core_detach(struct ssb_device *dev)
3845 {
3846         struct b43_wldev *wldev;
3847         struct b43_wl *wl;
3848
3849         wldev = ssb_get_drvdata(dev);
3850         wl = wldev->wl;
3851         cancel_work_sync(&wldev->restart_work);
3852         b43_debugfs_remove_device(wldev);
3853         b43_wireless_core_detach(wldev);
3854         list_del(&wldev->list);
3855         wl->nr_devs--;
3856         ssb_set_drvdata(dev, NULL);
3857         kfree(wldev);
3858 }
3859
3860 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3861 {
3862         struct b43_wldev *wldev;
3863         struct pci_dev *pdev;
3864         int err = -ENOMEM;
3865
3866         if (!list_empty(&wl->devlist)) {
3867                 /* We are not the first core on this chip. */
3868                 pdev = dev->bus->host_pci;
3869                 /* Only special chips support more than one wireless
3870                  * core, although some of the other chips have more than
3871                  * one wireless core as well. Check for this and
3872                  * bail out early.
3873                  */
3874                 if (!pdev ||
3875                     ((pdev->device != 0x4321) &&
3876                      (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3877                         b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3878                         return -ENODEV;
3879                 }
3880         }
3881
3882         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3883         if (!wldev)
3884                 goto out;
3885
3886         wldev->dev = dev;
3887         wldev->wl = wl;
3888         b43_set_status(wldev, B43_STAT_UNINIT);
3889         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3890         tasklet_init(&wldev->isr_tasklet,
3891                      (void (*)(unsigned long))b43_interrupt_tasklet,
3892                      (unsigned long)wldev);
3893         if (modparam_pio)
3894                 wldev->__using_pio = 1;
3895         INIT_LIST_HEAD(&wldev->list);
3896
3897         err = b43_wireless_core_attach(wldev);
3898         if (err)
3899                 goto err_kfree_wldev;
3900
3901         list_add(&wldev->list, &wl->devlist);
3902         wl->nr_devs++;
3903         ssb_set_drvdata(dev, wldev);
3904         b43_debugfs_add_device(wldev);
3905
3906       out:
3907         return err;
3908
3909       err_kfree_wldev:
3910         kfree(wldev);
3911         return err;
3912 }
3913
3914 static void b43_sprom_fixup(struct ssb_bus *bus)
3915 {
3916         /* boardflags workarounds */
3917         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3918             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3919                 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
3920         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3921             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3922                 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
3923 }
3924
3925 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3926 {
3927         struct ieee80211_hw *hw = wl->hw;
3928
3929         ssb_set_devtypedata(dev, NULL);
3930         ieee80211_free_hw(hw);
3931 }
3932
3933 static int b43_wireless_init(struct ssb_device *dev)
3934 {
3935         struct ssb_sprom *sprom = &dev->bus->sprom;
3936         struct ieee80211_hw *hw;
3937         struct b43_wl *wl;
3938         int err = -ENOMEM;
3939
3940         b43_sprom_fixup(dev->bus);
3941
3942         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3943         if (!hw) {
3944                 b43err(NULL, "Could not allocate ieee80211 device\n");
3945                 goto out;
3946         }
3947
3948         /* fill hw info */
3949         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3950                     IEEE80211_HW_RX_INCLUDES_FCS;
3951         hw->max_signal = 100;
3952         hw->max_rssi = -110;
3953         hw->max_noise = -110;
3954         hw->queues = 1;         /* FIXME: hardware has more queues */
3955         SET_IEEE80211_DEV(hw, dev->dev);
3956         if (is_valid_ether_addr(sprom->et1mac))
3957                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3958         else
3959                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3960
3961         /* Get and initialize struct b43_wl */
3962         wl = hw_to_b43_wl(hw);
3963         memset(wl, 0, sizeof(*wl));
3964         wl->hw = hw;
3965         spin_lock_init(&wl->irq_lock);
3966         spin_lock_init(&wl->leds_lock);
3967         mutex_init(&wl->mutex);
3968         INIT_LIST_HEAD(&wl->devlist);
3969
3970         ssb_set_devtypedata(dev, wl);
3971         b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3972         err = 0;
3973       out:
3974         return err;
3975 }
3976
3977 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3978 {
3979         struct b43_wl *wl;
3980         int err;
3981         int first = 0;
3982
3983         wl = ssb_get_devtypedata(dev);
3984         if (!wl) {
3985                 /* Probing the first core. Must setup common struct b43_wl */
3986                 first = 1;
3987                 err = b43_wireless_init(dev);
3988                 if (err)
3989                         goto out;
3990                 wl = ssb_get_devtypedata(dev);
3991                 B43_WARN_ON(!wl);
3992         }
3993         err = b43_one_core_attach(dev, wl);
3994         if (err)
3995                 goto err_wireless_exit;
3996
3997         if (first) {
3998                 err = ieee80211_register_hw(wl->hw);
3999                 if (err)
4000                         goto err_one_core_detach;
4001         }
4002
4003       out:
4004         return err;
4005
4006       err_one_core_detach:
4007         b43_one_core_detach(dev);
4008       err_wireless_exit:
4009         if (first)
4010                 b43_wireless_exit(dev, wl);
4011         return err;
4012 }
4013
4014 static void b43_remove(struct ssb_device *dev)
4015 {
4016         struct b43_wl *wl = ssb_get_devtypedata(dev);
4017         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4018
4019         B43_WARN_ON(!wl);
4020         if (wl->current_dev == wldev)
4021                 ieee80211_unregister_hw(wl->hw);
4022
4023         b43_one_core_detach(dev);
4024
4025         if (list_empty(&wl->devlist)) {
4026                 /* Last core on the chip unregistered.
4027                  * We can destroy common struct b43_wl.
4028                  */
4029                 b43_wireless_exit(dev, wl);
4030         }
4031 }
4032
4033 /* Perform a hardware reset. This can be called from any context. */
4034 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4035 {
4036         /* Must avoid requeueing, if we are in shutdown. */
4037         if (b43_status(dev) < B43_STAT_INITIALIZED)
4038                 return;
4039         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4040         queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4041 }
4042
4043 #ifdef CONFIG_PM
4044
4045 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4046 {
4047         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4048         struct b43_wl *wl = wldev->wl;
4049
4050         b43dbg(wl, "Suspending...\n");
4051
4052         mutex_lock(&wl->mutex);
4053         wldev->suspend_init_status = b43_status(wldev);
4054         if (wldev->suspend_init_status >= B43_STAT_STARTED)
4055                 b43_wireless_core_stop(wldev);
4056         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4057                 b43_wireless_core_exit(wldev);
4058         mutex_unlock(&wl->mutex);
4059
4060         b43dbg(wl, "Device suspended.\n");
4061
4062         return 0;
4063 }
4064
4065 static int b43_resume(struct ssb_device *dev)
4066 {
4067         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4068         struct b43_wl *wl = wldev->wl;
4069         int err = 0;
4070
4071         b43dbg(wl, "Resuming...\n");
4072
4073         mutex_lock(&wl->mutex);
4074         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4075                 err = b43_wireless_core_init(wldev);
4076                 if (err) {
4077                         b43err(wl, "Resume failed at core init\n");
4078                         goto out;
4079                 }
4080         }
4081         if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4082                 err = b43_wireless_core_start(wldev);
4083                 if (err) {
4084                         b43_wireless_core_exit(wldev);
4085                         b43err(wl, "Resume failed at core start\n");
4086                         goto out;
4087                 }
4088         }
4089         mutex_unlock(&wl->mutex);
4090
4091         b43dbg(wl, "Device resumed.\n");
4092       out:
4093         return err;
4094 }
4095
4096 #else /* CONFIG_PM */
4097 # define b43_suspend    NULL
4098 # define b43_resume     NULL
4099 #endif /* CONFIG_PM */
4100
4101 static struct ssb_driver b43_ssb_driver = {
4102         .name           = KBUILD_MODNAME,
4103         .id_table       = b43_ssb_tbl,
4104         .probe          = b43_probe,
4105         .remove         = b43_remove,
4106         .suspend        = b43_suspend,
4107         .resume         = b43_resume,
4108 };
4109
4110 static int __init b43_init(void)
4111 {
4112         int err;
4113
4114         b43_debugfs_init();
4115         err = b43_pcmcia_init();
4116         if (err)
4117                 goto err_dfs_exit;
4118         err = ssb_driver_register(&b43_ssb_driver);
4119         if (err)
4120                 goto err_pcmcia_exit;
4121
4122         return err;
4123
4124 err_pcmcia_exit:
4125         b43_pcmcia_exit();
4126 err_dfs_exit:
4127         b43_debugfs_exit();
4128         return err;
4129 }
4130
4131 static void __exit b43_exit(void)
4132 {
4133         ssb_driver_unregister(&b43_ssb_driver);
4134         b43_pcmcia_exit();
4135         b43_debugfs_exit();
4136 }
4137
4138 module_init(b43_init)
4139 module_exit(b43_exit)