2 * arch/s390/kernel/entry64.S
3 * S390 low-level entry points.
5 * Copyright (C) IBM Corp. 1999,2006
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/sys.h>
13 #include <linux/linkage.h>
14 #include <linux/init.h>
15 #include <asm/cache.h>
16 #include <asm/lowcore.h>
17 #include <asm/errno.h>
18 #include <asm/ptrace.h>
19 #include <asm/thread_info.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/unistd.h>
25 * Stack layout for the system_call stack entry.
26 * The first few entries are identical to the user_regs_struct.
28 SP_PTREGS = STACK_FRAME_OVERHEAD
29 SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
30 SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
31 SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
32 SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
33 SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
34 SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
35 SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
36 SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
37 SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
38 SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
39 SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64
40 SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72
41 SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80
42 SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88
43 SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96
44 SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104
45 SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112
46 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120
47 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
48 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
49 SP_SVCNR = STACK_FRAME_OVERHEAD + __PT_SVCNR
50 SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
52 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
53 STACK_SIZE = 1 << STACK_SHIFT
55 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
56 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
57 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
60 #define BASED(name) name-system_call(%r13)
62 #ifdef CONFIG_TRACE_IRQFLAGS
65 brasl %r14,trace_hardirqs_on_caller
70 brasl %r14,trace_hardirqs_off_caller
73 .macro TRACE_IRQS_CHECK
75 tm SP_PSW(%r15),0x03 # irqs enabled?
77 brasl %r14,trace_hardirqs_on_caller
79 0: brasl %r14,trace_hardirqs_off_caller
84 #define TRACE_IRQS_OFF
85 #define TRACE_IRQS_CHECK
89 .macro LOCKDEP_SYS_EXIT
90 tm SP_PSW+1(%r15),0x01 # returning to user ?
92 brasl %r14,lockdep_sys_exit
96 #define LOCKDEP_SYS_EXIT
99 .macro STORE_TIMER lc_offset
100 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
105 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
106 .macro UPDATE_VTIME lc_from,lc_to,lc_sum
115 * Register usage in interrupt handlers:
116 * R9 - pointer to current task structure
117 * R13 - pointer to literal pool
118 * R14 - return register for function calls
119 * R15 - kernel stack pointer
122 .macro SAVE_ALL_BASE savearea
123 stmg %r12,%r15,\savearea
124 larl %r13,system_call
127 .macro SAVE_ALL_SVC psworg,savearea
129 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
132 .macro SAVE_ALL_SYNC psworg,savearea
134 tm \psworg+1,0x01 # test problem state bit
135 jz 2f # skip stack setup save
136 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
137 #ifdef CONFIG_CHECK_STACK
139 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
146 .macro SAVE_ALL_ASYNC psworg,savearea
148 tm \psworg+1,0x01 # test problem state bit
149 jnz 1f # from user -> load kernel stack
150 clc \psworg+8(8),BASED(.Lcritical_end)
152 clc \psworg+8(8),BASED(.Lcritical_start)
154 brasl %r14,cleanup_critical
155 tm 1(%r12),0x01 # retest problem state after cleanup
157 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ?
159 srag %r14,%r14,STACK_SHIFT
161 1: lg %r15,__LC_ASYNC_STACK # load async stack
162 #ifdef CONFIG_CHECK_STACK
164 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
171 .macro CREATE_STACK_FRAME psworg,savearea
172 aghi %r15,-SP_SIZE # make room for registers & psw
173 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
174 stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
175 icm %r12,3,__LC_SVC_ILC
176 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
177 st %r12,SP_SVCNR(%r15)
178 mvc SP_R12(32,%r15),\savearea # move %r12-%r15 to stack
180 stg %r12,__SF_BACKCHAIN(%r15)
183 .macro RESTORE_ALL psworg,sync
184 mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore
186 ni \psworg+1,0xfd # clear wait state bit
188 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 of user
189 STORE_TIMER __LC_EXIT_TIMER
190 lpswe \psworg # back to caller
194 * Scheduler resume function, called by switch_to
195 * gpr2 = (task_struct *) prev
196 * gpr3 = (task_struct *) next
202 tm __THREAD_per+4(%r3),0xe8 # is the new process using per ?
203 jz __switch_to_noper # if not we're fine
204 stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff
205 clc __THREAD_per(24,%r3),__SF_EMPTY(%r15)
206 je __switch_to_noper # we got away without bashing TLB's
207 lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't
209 lg %r4,__THREAD_info(%r2) # get thread_info of prev
210 tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending?
211 jz __switch_to_no_mcck
212 ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
213 lg %r4,__THREAD_info(%r3) # get thread_info of next
214 oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next
216 stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task
217 stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
218 lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
219 lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task
220 stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct
221 lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
222 lg %r3,__THREAD_info(%r3) # load thread_info from task struct
223 stg %r3,__LC_THREAD_INFO
225 stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
230 * SVC interrupt handler routine. System calls are synchronous events and
231 * are executed with interrupts enabled.
236 STORE_TIMER __LC_SYNC_ENTER_TIMER
238 SAVE_ALL_BASE __LC_SAVE_AREA
239 SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
240 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
241 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
242 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
244 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
246 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
248 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
251 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
252 ltgr %r7,%r7 # test for svc 0
254 # svc 0: system call number in %r1
255 cl %r1,BASED(.Lnr_syscalls)
257 lgfr %r7,%r1 # clear high word in r1
259 mvc SP_ARGS(8,%r15),SP_R7(%r15)
261 sth %r7,SP_SVCNR(%r15)
262 sllg %r7,%r7,2 # svc number * 4
263 larl %r10,sys_call_table
265 tm __TI_flags+5(%r9),(_TIF_31BIT>>16) # running in 31 bit mode ?
267 larl %r10,sys_call_table_emu # use 31 bit emulation system calls
270 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
271 lgf %r8,0(%r7,%r10) # load address of system call routine
273 basr %r14,%r8 # call sys_xxxx
274 stg %r2,SP_R2(%r15) # store return value (change R2 on stack)
277 tm __TI_flags+7(%r9),_TIF_WORK_SVC
278 jnz sysc_work # there is work to do (signals etc.)
280 #ifdef CONFIG_TRACE_IRQFLAGS
281 larl %r1,sysc_restore_trace_psw
288 RESTORE_ALL __LC_RETURN_PSW,1
291 #ifdef CONFIG_TRACE_IRQFLAGS
293 .globl sysc_restore_trace_psw
294 sysc_restore_trace_psw:
295 .quad 0, sysc_restore_trace
299 # recheck if there is more work to do
302 tm __TI_flags+7(%r9),_TIF_WORK_SVC
303 jz sysc_restore # there is no work to do
305 # One of the work bits is on. Find out which one.
308 tm SP_PSW+1(%r15),0x01 # returning to user ?
310 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
312 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
314 tm __TI_flags+7(%r9),_TIF_SIGPENDING
316 tm __TI_flags+7(%r9),_TIF_NOTIFY_RESUME
317 jnz sysc_notify_resume
318 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
320 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
326 # _TIF_NEED_RESCHED is set, call schedule
329 larl %r14,sysc_work_loop
330 jg schedule # return point is sysc_return
333 # _TIF_MCCK_PENDING is set, call handler
336 larl %r14,sysc_work_loop
337 jg s390_handle_mcck # TIF bit will be cleared by handler
340 # _TIF_SIGPENDING is set, call do_signal
343 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
344 la %r2,SP_PTREGS(%r15) # load pt_regs
345 brasl %r14,do_signal # call do_signal
346 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
348 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
353 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
356 la %r2,SP_PTREGS(%r15) # load pt_regs
357 larl %r14,sysc_work_loop
358 jg do_notify_resume # call do_notify_resume
361 # _TIF_RESTART_SVC is set, set up registers and restart svc
364 ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
365 lg %r7,SP_R2(%r15) # load new svc number
366 mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument
367 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
368 j sysc_do_restart # restart svc
371 # _TIF_SINGLE_STEP is set, call do_single_step
374 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
375 xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
376 la %r2,SP_PTREGS(%r15) # address of register-save area
377 larl %r14,sysc_return # load adr. of system return
378 jg do_single_step # branch to do_sigtrap
381 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
382 # and after the system call
385 la %r2,SP_PTREGS(%r15) # load pt_regs
389 brasl %r14,do_syscall_trace_enter
393 sllg %r7,%r2,2 # svc number *4
396 lmg %r3,%r6,SP_R3(%r15)
397 lg %r2,SP_ORIG_R2(%r15)
398 basr %r14,%r8 # call sys_xxx
399 stg %r2,SP_R2(%r15) # store return value
401 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
403 la %r2,SP_PTREGS(%r15) # load pt_regs
404 larl %r14,sysc_return # return point is sysc_return
405 jg do_syscall_trace_exit
408 # a new process exits the kernel with ret_from_fork
412 lg %r13,__LC_SVC_NEW_PSW+8
413 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
414 tm SP_PSW+1(%r15),0x01 # forking a kernel thread ?
416 stg %r15,SP_R15(%r15) # store stack pointer for new kthread
417 0: brasl %r14,schedule_tail
419 stosm 24(%r15),0x03 # reenable interrupts
423 # kernel_execve function needs to deal with pt_regs that is not
428 stmg %r12,%r15,96(%r15)
431 stg %r14,__SF_BACKCHAIN(%r15)
432 la %r12,SP_PTREGS(%r15)
433 xc 0(__PT_SIZE,%r12),0(%r12)
439 lmg %r12,%r15,96(%r15)
442 0: stnsm __SF_EMPTY(%r15),0xfc # disable interrupts
443 lg %r15,__LC_KERNEL_STACK # load ksp
444 aghi %r15,-SP_SIZE # make room for registers & psw
445 lg %r13,__LC_SVC_NEW_PSW+8
446 lg %r9,__LC_THREAD_INFO
447 mvc SP_PTREGS(__PT_SIZE,%r15),0(%r12) # copy pt_regs
448 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
449 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
450 brasl %r14,execve_tail
454 * Program check handler routine
457 .globl pgm_check_handler
460 * First we need to check for a special case:
461 * Single stepping an instruction that disables the PER event mask will
462 * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
463 * For a single stepped SVC the program check handler gets control after
464 * the SVC new PSW has been loaded. But we want to execute the SVC first and
465 * then handle the PER event. Therefore we update the SVC old PSW to point
466 * to the pgm_check_handler and branch to the SVC handler after we checked
467 * if we have to load the kernel stack register.
468 * For every other possible cause for PER event without the PER mask set
469 * we just ignore the PER event (FIXME: is there anything we have to do
472 STORE_TIMER __LC_SYNC_ENTER_TIMER
473 SAVE_ALL_BASE __LC_SAVE_AREA
474 tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
475 jnz pgm_per # got per exception -> special case
476 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
477 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
478 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
479 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
481 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
482 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
483 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
486 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
487 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
489 lgf %r3,__LC_PGM_ILC # load program interruption code
494 larl %r1,pgm_check_table
495 lg %r1,0(%r8,%r1) # load address of handler routine
496 la %r2,SP_PTREGS(%r15) # address of register-save area
497 larl %r14,sysc_return
498 br %r1 # branch to interrupt-handler
501 # handle per exception
504 tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
505 jnz pgm_per_std # ok, normal per event from user space
506 # ok its one of the special cases, now we need to find out which one
507 clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
509 # no interesting special case, ignore PER event
510 lmg %r12,%r15,__LC_SAVE_AREA
511 lpswe __LC_PGM_OLD_PSW
514 # Normal per exception
517 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
518 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
519 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
520 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
522 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
523 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
524 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
527 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
529 lg %r1,__TI_task(%r9)
530 tm SP_PSW+1(%r15),0x01 # kernel per event ?
532 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
533 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
534 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
535 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
536 lgf %r3,__LC_PGM_ILC # load program interruption code
538 ngr %r8,%r3 # clear per-event-bit and ilc
543 # it was a single stepped SVC that is causing all the trouble
546 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
547 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
548 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
549 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
550 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
551 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
553 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
554 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
555 lg %r1,__TI_task(%r9)
556 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
557 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
558 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
559 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
561 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
565 # per was called from kernel, must be kprobes
568 xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
569 la %r2,SP_PTREGS(%r15) # address of register-save area
570 larl %r14,sysc_restore # load adr. of system ret, no work
571 jg do_single_step # branch to do_single_step
574 * IO interrupt handler routine
576 .globl io_int_handler
578 STORE_TIMER __LC_ASYNC_ENTER_TIMER
580 SAVE_ALL_BASE __LC_SAVE_AREA+32
581 SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
582 CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
583 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
584 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
586 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
587 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
588 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
591 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
593 la %r2,SP_PTREGS(%r15) # address of register-save area
594 brasl %r14,do_IRQ # call standard irq handler
596 tm __TI_flags+7(%r9),_TIF_WORK_INT
597 jnz io_work # there is work to do (signals etc.)
599 #ifdef CONFIG_TRACE_IRQFLAGS
600 larl %r1,io_restore_trace_psw
607 RESTORE_ALL __LC_RETURN_PSW,0
610 #ifdef CONFIG_TRACE_IRQFLAGS
612 .globl io_restore_trace_psw
613 io_restore_trace_psw:
614 .quad 0, io_restore_trace
618 # There is work todo, we need to check if we return to userspace, then
619 # check, if we are in SIE, if yes leave it
622 tm SP_PSW+1(%r15),0x01 # returning to user ?
623 #ifndef CONFIG_PREEMPT
624 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
625 jnz io_work_user # yes -> no need to check for SIE
626 la %r1, BASED(sie_opcode) # we return to kernel here
627 lg %r2, SP_PSW+8(%r15)
628 clc 0(2,%r1), 0(%r2) # is current instruction = SIE?
629 jne io_restore # no-> return to kernel
630 lg %r1, SP_PSW+8(%r15) # yes-> add 4 bytes to leave SIE
632 stg %r1, SP_PSW+8(%r15)
633 j io_restore # return to kernel
635 jno io_restore # no-> skip resched & signal
638 jnz io_work_user # yes -> do resched & signal
639 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
640 la %r1, BASED(sie_opcode)
641 lg %r2, SP_PSW+8(%r15)
642 clc 0(2,%r1), 0(%r2) # is current instruction = SIE?
643 jne 0f # no -> leave PSW alone
644 lg %r1, SP_PSW+8(%r15) # yes-> add 4 bytes to leave SIE
646 stg %r1, SP_PSW+8(%r15)
649 # check for preemptive scheduling
650 icm %r0,15,__TI_precount(%r9)
651 jnz io_restore # preemption is disabled
652 # switch to kernel stack
655 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
656 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
659 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
661 larl %r14,io_resume_loop
662 jg preempt_schedule_irq
666 lg %r1,__LC_KERNEL_STACK
668 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
669 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
672 # One of the work bits is on. Find out which one.
673 # Checked are: _TIF_SIGPENDING, _TIF_RESTORE_SIGPENDING, _TIF_NEED_RESCHED
674 # and _TIF_MCCK_PENDING
677 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
679 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
681 tm __TI_flags+7(%r9),_TIF_SIGPENDING
683 tm __TI_flags+7(%r9),_TIF_NOTIFY_RESUME
688 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
694 # _TIF_MCCK_PENDING is set, call handler
697 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
701 # _TIF_NEED_RESCHED is set, call schedule
705 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
706 brasl %r14,schedule # call scheduler
707 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
709 tm __TI_flags+7(%r9),_TIF_WORK_INT
710 jz io_restore # there is no work to do
714 # _TIF_SIGPENDING or is set, call do_signal
718 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
719 la %r2,SP_PTREGS(%r15) # load pt_regs
720 brasl %r14,do_signal # call do_signal
721 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
726 # _TIF_NOTIFY_RESUME or is set, call do_notify_resume
730 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
731 la %r2,SP_PTREGS(%r15) # load pt_regs
732 brasl %r14,do_notify_resume # call do_notify_resume
733 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
738 * External interrupt handler routine
740 .globl ext_int_handler
742 STORE_TIMER __LC_ASYNC_ENTER_TIMER
744 SAVE_ALL_BASE __LC_SAVE_AREA+32
745 SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
746 CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
747 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
748 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
750 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
751 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
752 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
755 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
757 la %r2,SP_PTREGS(%r15) # address of register-save area
758 llgh %r3,__LC_EXT_INT_CODE # get interruption code
765 * Machine check handler routines
767 .globl mcck_int_handler
769 la %r1,4095 # revalidate r1
770 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
771 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
772 SAVE_ALL_BASE __LC_SAVE_AREA+64
773 la %r12,__LC_MCK_OLD_PSW
774 tm __LC_MCCK_CODE,0x80 # system damage?
775 jo mcck_int_main # yes -> rest of mcck code invalid
776 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
778 mvc __LC_SAVE_AREA+104(8),__LC_ASYNC_ENTER_TIMER
779 mvc __LC_ASYNC_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14)
780 tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid?
782 la %r14,__LC_SYNC_ENTER_TIMER
783 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
785 la %r14,__LC_ASYNC_ENTER_TIMER
786 0: clc 0(8,%r14),__LC_EXIT_TIMER
788 la %r14,__LC_EXIT_TIMER
789 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
791 la %r14,__LC_LAST_UPDATE_TIMER
793 mvc __LC_ASYNC_ENTER_TIMER(8),0(%r14)
796 tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid?
797 jno mcck_int_main # no -> skip cleanup critical
798 tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit
799 jnz mcck_int_main # from user -> load kernel stack
800 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end)
802 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start)
804 brasl %r14,cleanup_critical
806 lg %r14,__LC_PANIC_STACK # are we already on the panic stack?
808 srag %r14,%r14,PAGE_SHIFT
810 lg %r15,__LC_PANIC_STACK # load panic stack
811 0: CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64
812 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
813 tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid?
814 jno mcck_no_vtime # no -> no timer update
815 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
817 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
818 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
819 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
822 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
823 la %r2,SP_PTREGS(%r15) # load pt_regs
824 brasl %r14,s390_do_machine_check
825 tm SP_PSW+1(%r15),0x01 # returning to user ?
827 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
829 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
830 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
832 stosm __SF_EMPTY(%r15),0x04 # turn dat on
833 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
836 brasl %r14,s390_handle_mcck
839 mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW
840 ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
841 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15
842 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
843 mvc __LC_ASYNC_ENTER_TIMER(8),__LC_SAVE_AREA+104
844 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
849 lpswe __LC_RETURN_MCCK_PSW # back to caller
852 * Restart interruption handler, kick starter for additional CPUs
856 .globl restart_int_handler
858 lg %r15,__LC_SAVE_AREA+120 # load ksp
859 lghi %r10,__LC_CREGS_SAVE_AREA
860 lctlg %c0,%c15,0(%r10) # get new ctl regs
861 lghi %r10,__LC_AREGS_SAVE_AREA
863 lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone
864 stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on
869 * If we do not run with SMP enabled, let the new CPU crash ...
871 .globl restart_int_handler
875 lpswe restart_crash-restart_base(%r1)
878 .long 0x000a0000,0x00000000,0x00000000,0x00000000
882 #ifdef CONFIG_CHECK_STACK
884 * The synchronous or the asynchronous stack overflowed. We are dead.
885 * No need to properly save the registers, we are going to panic anyway.
886 * Setup a pt_regs so that show_trace can provide a good call trace.
889 lg %r15,__LC_PANIC_STACK # change to panic stack
891 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
892 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
893 la %r1,__LC_SAVE_AREA
894 chi %r12,__LC_SVC_OLD_PSW
896 chi %r12,__LC_PGM_OLD_PSW
898 la %r1,__LC_SAVE_AREA+32
899 0: mvc SP_R12(32,%r15),0(%r1) # move %r12-%r15 to stack
900 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
901 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain
902 la %r2,SP_PTREGS(%r15) # load pt_regs
903 jg kernel_stack_overflow
906 cleanup_table_system_call:
907 .quad system_call, sysc_do_svc
908 cleanup_table_sysc_return:
909 .quad sysc_return, sysc_leave
910 cleanup_table_sysc_leave:
911 .quad sysc_leave, sysc_done
912 cleanup_table_sysc_work_loop:
913 .quad sysc_work_loop, sysc_work_done
914 cleanup_table_io_return:
915 .quad io_return, io_leave
916 cleanup_table_io_leave:
917 .quad io_leave, io_done
918 cleanup_table_io_work_loop:
919 .quad io_work_loop, io_work_done
922 clc 8(8,%r12),BASED(cleanup_table_system_call)
924 clc 8(8,%r12),BASED(cleanup_table_system_call+8)
925 jl cleanup_system_call
927 clc 8(8,%r12),BASED(cleanup_table_sysc_return)
929 clc 8(8,%r12),BASED(cleanup_table_sysc_return+8)
930 jl cleanup_sysc_return
932 clc 8(8,%r12),BASED(cleanup_table_sysc_leave)
934 clc 8(8,%r12),BASED(cleanup_table_sysc_leave+8)
935 jl cleanup_sysc_leave
937 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop)
939 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop+8)
940 jl cleanup_sysc_return
942 clc 8(8,%r12),BASED(cleanup_table_io_return)
944 clc 8(8,%r12),BASED(cleanup_table_io_return+8)
947 clc 8(8,%r12),BASED(cleanup_table_io_leave)
949 clc 8(8,%r12),BASED(cleanup_table_io_leave+8)
952 clc 8(8,%r12),BASED(cleanup_table_io_work_loop)
954 clc 8(8,%r12),BASED(cleanup_table_io_work_loop+8)
960 mvc __LC_RETURN_PSW(16),0(%r12)
961 cghi %r12,__LC_MCK_OLD_PSW
963 la %r12,__LC_SAVE_AREA+32
965 0: la %r12,__LC_SAVE_AREA+64
967 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
968 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8)
970 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
971 0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16)
974 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn)
976 mvc __LC_SAVE_AREA(32),0(%r12)
978 stg %r12,__LC_SAVE_AREA+96 # argh
979 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
980 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
981 lg %r12,__LC_SAVE_AREA+96 # argh
983 llgh %r7,__LC_SVC_INT_CODE
984 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
986 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24)
988 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
990 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32)
992 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
994 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
996 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)
997 la %r12,__LC_RETURN_PSW
999 cleanup_system_call_insn:
1001 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
1008 cleanup_sysc_return:
1009 mvc __LC_RETURN_PSW(8),0(%r12)
1010 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_return)
1011 la %r12,__LC_RETURN_PSW
1015 clc 8(8,%r12),BASED(cleanup_sysc_leave_insn)
1017 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
1018 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1019 clc 8(8,%r12),BASED(cleanup_sysc_leave_insn+8)
1022 mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
1023 cghi %r12,__LC_MCK_OLD_PSW
1025 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
1027 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
1028 1: lmg %r0,%r11,SP_R0(%r15)
1029 lg %r15,SP_R15(%r15)
1030 2: la %r12,__LC_RETURN_PSW
1032 cleanup_sysc_leave_insn:
1034 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
1039 mvc __LC_RETURN_PSW(8),0(%r12)
1040 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_work_loop)
1041 la %r12,__LC_RETURN_PSW
1045 clc 8(8,%r12),BASED(cleanup_io_leave_insn)
1047 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
1048 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1049 clc 8(8,%r12),BASED(cleanup_io_leave_insn+8)
1052 mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
1053 cghi %r12,__LC_MCK_OLD_PSW
1055 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
1057 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
1058 1: lmg %r0,%r11,SP_R0(%r15)
1059 lg %r15,SP_R15(%r15)
1060 2: la %r12,__LC_RETURN_PSW
1062 cleanup_io_leave_insn:
1064 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
1073 .Lnr_syscalls: .long NR_syscalls
1074 .L0x0130: .short 0x130
1075 .L0x0140: .short 0x140
1076 .L0x0150: .short 0x150
1077 .L0x0160: .short 0x160
1078 .L0x0170: .short 0x170
1080 .quad __critical_start
1082 .quad __critical_end
1084 .section .rodata, "a"
1085 #define SYSCALL(esa,esame,emu) .long esame
1087 #include "syscalls.S"
1090 #ifdef CONFIG_COMPAT
1092 #define SYSCALL(esa,esame,emu) .long emu
1094 #include "syscalls.S"