2 * Copyright (c) 2000-2005 LSI Logic Corporation.
6 * Title: MPI Config message, structures, and Pages
7 * Creation Date: July 27, 2000
9 * mpi_cnfg.h Version: 01.05.08
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
17 * 06-06-00 01.00.01 Update version number for 1.0 release.
18 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages.
19 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2
20 * fields to FC_DEVICE_0 page, updated the page version.
21 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in
22 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages
23 * and updated the page versions.
24 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1
25 * page and updated the page version.
26 * Added Information field and _INFO_PARAMS_NEGOTIATED
27 * definitionto SCSI_DEVICE_0 page.
28 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the
30 * Added BucketsRemaining to LAN_1 page, redefined the
31 * state values, and updated the page version.
32 * Revised bus width definitions in SCSI_PORT_0,
33 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages.
34 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page
36 * Moved FC_DEVICE_0 PageAddress description to spec.
37 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field
38 * widths in IOC_0 page and updated the page version.
39 * 11-02-00 01.01.01 Original release for post 1.0 work
40 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI
41 * Port Page 2, FC Port Page 4, FC Port Page 5
42 * 11-15-00 01.01.02 Interim changes to match proposals
43 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01.
44 * 12-05-00 01.01.04 Modified config page actions.
45 * 01-09-01 01.01.05 Added defines for page address formats.
46 * Data size for Manufacturing pages 2 and 3 no longer
48 * Io Unit Page 2 size is fixed at 4 adapters and some
50 * SCSI Port Page 2 Device Settings modified.
51 * New fields added to FC Port Page 0 and some flags
53 * Removed impedance flash from FC Port Page 1.
54 * Added FC Port pages 6 and 7.
55 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0.
56 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique.
57 * Added some LinkType defines for FcPortPage0.
58 * 02-20-01 01.01.08 Started using MPI_POINTER.
59 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with
60 * MPI_CONFIG_PAGETYPE_RAID_VOLUME.
61 * Added definitions and structures for IOC Page 2 and
63 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9.
64 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID.
65 * Added VendorId and ProductRevLevel fields to
66 * RAIDVOL2_IM_PHYS_ID struct.
67 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_
68 * defines to make them compatible to MPI version 1.0.
69 * Added structure offset comments.
70 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and
71 * removed some obsolete ones.
72 * Added IO Unit Page 3.
73 * Modified defines for Scsi Port Page 2.
74 * Modified RAID Volume Pages.
75 * 08-08-01 01.02.01 Original release for v1.2 work.
76 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct.
77 * Added defines for the SEP bits in RVP2 VolumeSettings.
78 * Modified the DeviceSettings field in RVP2 to use the
80 * Added defines for SES, SAF-TE, and cross channel for
81 * IOCPage2 CapabilitiesFlags.
82 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE.
84 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE.
85 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT.
86 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035.
87 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY
88 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY.
89 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS,
90 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and
91 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and
92 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED.
93 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED
94 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED.
95 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1.
96 * Added rejected bits to SCSI Device Page 0 Information.
97 * Increased size of ALPA array in FC Port Page 2 by one
98 * and removed a one byte reserved field.
99 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in
100 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering.
101 * Added structures for Manufacturing Page 4, IO Unit
102 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and
103 * RAID PhysDisk Page 0.
104 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.
105 * Modified some of the new defines to make them 32
107 * Modified how variable length pages (arrays) are defined.
108 * Added generic defines for hot spare pools and RAID
110 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR.
111 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with
112 * related define, and bumped the page version define.
113 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a
114 * reserved byte and added a define.
116 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE.
117 * Added new config page: CONFIG_PAGE_IOC_5.
118 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases
119 * fields to CONFIG_PAGE_FC_PORT_0.
120 * Added AltConnector and NumRequestedAliases fields to
121 * CONFIG_PAGE_FC_PORT_1.
122 * Added new config page: CONFIG_PAGE_FC_PORT_10.
123 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines.
124 * Added additional MPI_SCSIDEVPAGE0_NP_ defines.
125 * Added more MPI_SCSIDEVPAGE1_RP_ defines.
127 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE.
128 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3.
129 * Modified MPI_FCPORTPAGE5_FLAGS_ defines.
130 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define.
131 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0.
132 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
133 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0.
134 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for
135 * CONFIG_PAGE_FC_PORT_1.
136 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable
138 * Added more device id defines.
139 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define.
140 * Added TargetConfig and IDConfig fields to
141 * CONFIG_PAGE_SCSI_PORT_1.
142 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2
144 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
145 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field
146 * with ADISCHardALPA.
147 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define.
148 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout
149 * fields and related defines to CONFIG_PAGE_FC_PORT_1.
151 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK.
152 * Added new fields to the substructures of
153 * CONFIG_PAGE_FC_PORT_10.
154 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0,
155 * CONFIG_PAGE_SCSI_DEVICE_0, and
156 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for
158 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0.
159 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config
161 * Added a new structure for extended config page header.
162 * Added new extended config pages types and structures for
163 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY.
164 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4
165 * to add a Flags field.
166 * Two new Manufacturing config pages (5 and 6).
167 * Two new bits defined for IO Unit Page 1 Flags field.
168 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields
169 * to specify the BIOS boot device.
170 * Four new Flags bits defined for IO Unit Page 2.
171 * Added IO Unit Page 4.
172 * Added EEDP Flags settings to IOC Page 1.
173 * Added new BIOS Page 1 config page.
174 * 10-05-04 01.05.02 Added define for
175 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE.
176 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and
177 * associated defines.
178 * Added more defines for SAS IO Unit Page 0
179 * DiscoveryStatus field.
180 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK
181 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK.
182 * Added defines for Physical Mapping Modes to SAS IO Unit
185 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH.
186 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode.
187 * Added defines for MaxTargetSpinUp to BIOS Page 1.
188 * Added 5 new ControlFlags defines for SAS IO Unit
190 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit
192 * Added AccessStatus field to SAS Device Page 0 and added
193 * new Flags bits for supported SATA features.
194 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID
195 * Volume Page 1, and RAID Physical Disk Page 1.
196 * Replaced IO Unit Page 1 BootTargetID,BootBus, and
197 * BootAdapterNum with reserved field.
198 * Added DataScrubRate and ResyncRate to RAID Volume
200 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT
202 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1
204 * Added Auto Port Config flag define for SAS IOUNIT
205 * Page 1 ControlFlags.
206 * Added Disabled bad Phy define to Expander Page 1
207 * Discovery Info field.
208 * Added SAS/SATA device support to SAS IOUnit Page 1
210 * Added Unsupported device to SAS Dev Page 0 Flags field
211 * Added disable use SATA Hash Address for SAS IOUNIT
212 * page 1 in ControlFields.
213 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to
214 * Manufacturing Page 4.
215 * Added new defines for BIOS Page 1 IOCSettings field.
216 * Added ExtDiskIdentifier field to RAID Physical Disk
218 * Added new defines for SAS IO Unit Page 1 ControlFlags
219 * and to SAS Device Page 0 Flags to control SATA devices.
220 * Added defines and structures for the new Log Page 0, a
221 * new type of configuration page.
222 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0.
223 * Added WWID field to RAID Volume Page 1.
224 * Added PhysicalPort field to SAS Expander pages 0 and 1.
225 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1.
226 * Added Enclosure/Slot boot device format to BIOS Page 2.
227 * New status value for RAID Volume Page 0 VolumeStatus
228 * (VolumeState subfield).
229 * New value for RAID Physical Page 0 InactiveStatus.
230 * Added Inactive Volume Member flag RAID Physical Disk
231 * Page 0 PhysDiskStatus field.
232 * New physical mapping mode in SAS IO Unit Page 2.
233 * Added CONFIG_PAGE_SAS_ENCLOSURE_0.
234 * Added Slot and Enclosure fields to SAS Device Page 0.
235 * --------------------------------------------------------------------------
242 /*****************************************************************************
244 * C o n f i g M e s s a g e a n d S t r u c t u r e s
246 *****************************************************************************/
248 typedef struct _CONFIG_PAGE_HEADER
250 U8 PageVersion; /* 00h */
251 U8 PageLength; /* 01h */
252 U8 PageNumber; /* 02h */
253 U8 PageType; /* 03h */
254 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,
255 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;
257 typedef union _CONFIG_PAGE_HEADER_UNION
259 ConfigPageHeader_t Struct;
263 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
264 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
266 typedef struct _CONFIG_EXTENDED_PAGE_HEADER
268 U8 PageVersion; /* 00h */
269 U8 Reserved1; /* 01h */
270 U8 PageNumber; /* 02h */
271 U8 PageType; /* 03h */
272 U16 ExtPageLength; /* 04h */
273 U8 ExtPageType; /* 06h */
274 U8 Reserved2; /* 07h */
275 } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER,
276 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t;
280 /****************************************************************************
281 * PageType field values
282 ****************************************************************************/
283 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)
284 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)
285 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)
286 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30)
287 #define MPI_CONFIG_PAGEATTR_MASK (0xF0)
289 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00)
290 #define MPI_CONFIG_PAGETYPE_IOC (0x01)
291 #define MPI_CONFIG_PAGETYPE_BIOS (0x02)
292 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03)
293 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04)
294 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05)
295 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06)
296 #define MPI_CONFIG_PAGETYPE_LAN (0x07)
297 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
298 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09)
299 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
300 #define MPI_CONFIG_PAGETYPE_INBAND (0x0B)
301 #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F)
302 #define MPI_CONFIG_PAGETYPE_MASK (0x0F)
304 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF)
307 /****************************************************************************
308 * ExtPageType field values
309 ****************************************************************************/
310 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
311 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
312 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
313 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
314 #define MPI_CONFIG_EXTPAGETYPE_LOG (0x14)
315 #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
318 /****************************************************************************
319 * PageAddress field values
320 ****************************************************************************/
321 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF)
323 #define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000)
324 #define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000)
325 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF)
326 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0)
327 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00)
328 #define MPI_SCSI_DEVICE_BUS_SHIFT (8)
329 #define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000)
330 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF)
331 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0)
332 #define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00)
333 #define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8)
334 #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000)
335 #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16)
337 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000)
338 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28)
339 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000)
340 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000)
341 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF)
342 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0)
344 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000)
345 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28)
346 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000)
347 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000)
348 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000)
349 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28)
350 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF)
351 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0)
352 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000)
353 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
354 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8)
355 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
356 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0)
358 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
359 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0)
361 #define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
362 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28)
363 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
364 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001)
365 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002)
366 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF)
367 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0)
368 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000)
369 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16)
370 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF)
371 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0)
372 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF)
373 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0)
375 #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
376 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28)
377 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
378 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001)
379 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002)
380 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
381 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0)
382 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
383 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8)
384 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
385 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0)
386 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF)
387 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0)
389 #define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
390 #define MPI_SAS_PHY_PGAD_FORM_SHIFT (28)
391 #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0)
392 #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1)
393 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
394 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0)
395 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
396 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0)
398 #define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
399 #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28)
400 #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
401 #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001)
402 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
403 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0)
404 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF)
405 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0)
409 /****************************************************************************
410 * Config Request Message
411 ****************************************************************************/
412 typedef struct _MSG_CONFIG
415 U8 Reserved; /* 01h */
416 U8 ChainOffset; /* 02h */
417 U8 Function; /* 03h */
418 U16 ExtPageLength; /* 04h */
419 U8 ExtPageType; /* 06h */
420 U8 MsgFlags; /* 07h */
421 U32 MsgContext; /* 08h */
422 U8 Reserved2[8]; /* 0Ch */
423 CONFIG_PAGE_HEADER Header; /* 14h */
424 U32 PageAddress; /* 18h */
425 SGE_IO_UNION PageBufferSGE; /* 1Ch */
426 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
427 Config_t, MPI_POINTER pConfig_t;
430 /****************************************************************************
431 * Action field values
432 ****************************************************************************/
433 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00)
434 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
435 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
436 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03)
437 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
438 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
439 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
442 /* Config Reply Message */
443 typedef struct _MSG_CONFIG_REPLY
446 U8 Reserved; /* 01h */
447 U8 MsgLength; /* 02h */
448 U8 Function; /* 03h */
449 U16 ExtPageLength; /* 04h */
450 U8 ExtPageType; /* 06h */
451 U8 MsgFlags; /* 07h */
452 U32 MsgContext; /* 08h */
453 U8 Reserved2[2]; /* 0Ch */
454 U16 IOCStatus; /* 0Eh */
455 U32 IOCLogInfo; /* 10h */
456 CONFIG_PAGE_HEADER Header; /* 14h */
457 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
458 ConfigReply_t, MPI_POINTER pConfigReply_t;
462 /*****************************************************************************
464 * C o n f i g u r a t i o n P a g e s
466 *****************************************************************************/
468 /****************************************************************************
469 * Manufacturing Config pages
470 ****************************************************************************/
471 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)
473 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
474 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
475 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
476 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
477 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
478 #define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642)
479 #define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640)
481 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
482 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
483 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
484 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
485 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
486 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
488 #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050)
489 #define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C)
490 #define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056)
491 #define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E)
492 #define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A)
493 #define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054)
494 #define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058)
495 #define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0060)
498 typedef struct _CONFIG_PAGE_MANUFACTURING_0
500 CONFIG_PAGE_HEADER Header; /* 00h */
501 U8 ChipName[16]; /* 04h */
502 U8 ChipRevision[8]; /* 14h */
503 U8 BoardName[16]; /* 1Ch */
504 U8 BoardAssembly[16]; /* 2Ch */
505 U8 BoardTracerNumber[16]; /* 3Ch */
507 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,
508 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;
510 #define MPI_MANUFACTURING0_PAGEVERSION (0x00)
513 typedef struct _CONFIG_PAGE_MANUFACTURING_1
515 CONFIG_PAGE_HEADER Header; /* 00h */
516 U8 VPD[256]; /* 04h */
517 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,
518 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;
520 #define MPI_MANUFACTURING1_PAGEVERSION (0x00)
523 typedef struct _MPI_CHIP_REVISION_ID
525 U16 DeviceID; /* 00h */
526 U8 PCIRevisionID; /* 02h */
527 U8 Reserved; /* 03h */
528 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID,
529 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t;
533 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
534 * one and check Header.PageLength at runtime.
536 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
537 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
540 typedef struct _CONFIG_PAGE_MANUFACTURING_2
542 CONFIG_PAGE_HEADER Header; /* 00h */
543 MPI_CHIP_REVISION_ID ChipId; /* 04h */
544 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
545 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,
546 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;
548 #define MPI_MANUFACTURING2_PAGEVERSION (0x00)
552 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
553 * one and check Header.PageLength at runtime.
555 #ifndef MPI_MAN_PAGE_3_INFO_WORDS
556 #define MPI_MAN_PAGE_3_INFO_WORDS (1)
559 typedef struct _CONFIG_PAGE_MANUFACTURING_3
561 CONFIG_PAGE_HEADER Header; /* 00h */
562 MPI_CHIP_REVISION_ID ChipId; /* 04h */
563 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
564 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,
565 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;
567 #define MPI_MANUFACTURING3_PAGEVERSION (0x00)
570 typedef struct _CONFIG_PAGE_MANUFACTURING_4
572 CONFIG_PAGE_HEADER Header; /* 00h */
573 U32 Reserved1; /* 04h */
574 U8 InfoOffset0; /* 08h */
575 U8 InfoSize0; /* 09h */
576 U8 InfoOffset1; /* 0Ah */
577 U8 InfoSize1; /* 0Bh */
578 U8 InquirySize; /* 0Ch */
580 U16 Reserved2; /* 0Eh */
581 U8 InquiryData[56]; /* 10h */
582 U32 ISVolumeSettings; /* 48h */
583 U32 IMEVolumeSettings; /* 4Ch */
584 U32 IMVolumeSettings; /* 50h */
585 U32 Reserved3; /* 54h */
586 U32 Reserved4; /* 58h */
587 U8 ISDataScrubRate; /* 5Ch */
588 U8 ISResyncRate; /* 5Dh */
589 U16 Reserved5; /* 5Eh */
590 U8 IMEDataScrubRate; /* 60h */
591 U8 IMEResyncRate; /* 61h */
592 U16 Reserved6; /* 62h */
593 U8 IMDataScrubRate; /* 64h */
594 U8 IMResyncRate; /* 65h */
595 U16 Reserved7; /* 66h */
596 U32 Reserved8; /* 68h */
597 U32 Reserved9; /* 6Ch */
598 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
599 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
601 #define MPI_MANUFACTURING4_PAGEVERSION (0x02)
603 /* defines for the Flags field */
604 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01)
607 typedef struct _CONFIG_PAGE_MANUFACTURING_5
609 CONFIG_PAGE_HEADER Header; /* 00h */
610 U64 BaseWWID; /* 04h */
612 U8 Reserved1; /* 0Dh */
613 U16 Reserved2; /* 0Eh */
614 } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5,
615 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t;
617 #define MPI_MANUFACTURING5_PAGEVERSION (0x01)
619 /* defines for the Flags field */
620 #define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01)
623 typedef struct _CONFIG_PAGE_MANUFACTURING_6
625 CONFIG_PAGE_HEADER Header; /* 00h */
626 U32 ProductSpecificInfo;/* 04h */
627 } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6,
628 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t;
630 #define MPI_MANUFACTURING6_PAGEVERSION (0x00)
633 /****************************************************************************
634 * IO Unit Config Pages
635 ****************************************************************************/
637 typedef struct _CONFIG_PAGE_IO_UNIT_0
639 CONFIG_PAGE_HEADER Header; /* 00h */
640 U64 UniqueValue; /* 04h */
641 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,
642 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;
644 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00)
647 typedef struct _CONFIG_PAGE_IO_UNIT_1
649 CONFIG_PAGE_HEADER Header; /* 00h */
651 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
652 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
654 #define MPI_IOUNITPAGE1_PAGEVERSION (0x01)
656 /* IO Unit Page 1 Flags defines */
657 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
658 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)
659 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)
660 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
661 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
662 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020)
663 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)
664 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)
665 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
668 typedef struct _MPI_ADAPTER_INFO
670 U8 PciBusNumber; /* 00h */
671 U8 PciDeviceAndFunctionNumber; /* 01h */
672 U16 AdapterFlags; /* 02h */
673 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
674 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
676 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
677 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
679 typedef struct _CONFIG_PAGE_IO_UNIT_2
681 CONFIG_PAGE_HEADER Header; /* 00h */
683 U32 BiosVersion; /* 08h */
684 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */
685 U32 Reserved1; /* 1Ch */
686 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
687 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
689 #define MPI_IOUNITPAGE2_PAGEVERSION (0x02)
691 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)
692 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)
693 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
694 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)
696 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
697 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
698 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020)
699 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
703 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
704 * one and check Header.PageLength at runtime.
706 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
707 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
710 typedef struct _CONFIG_PAGE_IO_UNIT_3
712 CONFIG_PAGE_HEADER Header; /* 00h */
713 U8 GPIOCount; /* 04h */
714 U8 Reserved1; /* 05h */
715 U16 Reserved2; /* 06h */
716 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */
717 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,
718 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;
720 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01)
722 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)
723 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
724 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)
725 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)
728 typedef struct _CONFIG_PAGE_IO_UNIT_4
730 CONFIG_PAGE_HEADER Header; /* 00h */
731 U32 Reserved1; /* 04h */
732 SGE_SIMPLE_UNION FWImageSGE; /* 08h */
733 } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4,
734 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t;
736 #define MPI_IOUNITPAGE4_PAGEVERSION (0x00)
739 /****************************************************************************
741 ****************************************************************************/
743 typedef struct _CONFIG_PAGE_IOC_0
745 CONFIG_PAGE_HEADER Header; /* 00h */
746 U32 TotalNVStore; /* 04h */
747 U32 FreeNVStore; /* 08h */
748 U16 VendorID; /* 0Ch */
749 U16 DeviceID; /* 0Eh */
750 U8 RevisionID; /* 10h */
751 U8 Reserved[3]; /* 11h */
752 U32 ClassCode; /* 14h */
753 U16 SubsystemVendorID; /* 18h */
754 U16 SubsystemID; /* 1Ah */
755 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,
756 IOCPage0_t, MPI_POINTER pIOCPage0_t;
758 #define MPI_IOCPAGE0_PAGEVERSION (0x01)
761 typedef struct _CONFIG_PAGE_IOC_1
763 CONFIG_PAGE_HEADER Header; /* 00h */
765 U32 CoalescingTimeout; /* 08h */
766 U8 CoalescingDepth; /* 0Ch */
767 U8 PCISlotNum; /* 0Dh */
768 U8 Reserved[2]; /* 0Eh */
769 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
770 IOCPage1_t, MPI_POINTER pIOCPage1_t;
772 #define MPI_IOCPAGE1_PAGEVERSION (0x02)
774 /* defines for the Flags field */
775 #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010)
776 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
778 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
781 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
783 U8 VolumeID; /* 00h */
784 U8 VolumeBus; /* 01h */
785 U8 VolumeIOC; /* 02h */
786 U8 VolumePageNumber; /* 03h */
787 U8 VolumeType; /* 04h */
789 U16 Reserved3; /* 06h */
790 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
791 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
793 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
795 #define MPI_RAID_VOL_TYPE_IS (0x00)
796 #define MPI_RAID_VOL_TYPE_IME (0x01)
797 #define MPI_RAID_VOL_TYPE_IM (0x02)
799 /* IOC Page 2 Volume Flags values */
801 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)
804 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
805 * one and check Header.PageLength at runtime.
807 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
808 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1)
811 typedef struct _CONFIG_PAGE_IOC_2
813 CONFIG_PAGE_HEADER Header; /* 00h */
814 U32 CapabilitiesFlags; /* 04h */
815 U8 NumActiveVolumes; /* 08h */
816 U8 MaxVolumes; /* 09h */
817 U8 NumActivePhysDisks; /* 0Ah */
818 U8 MaxPhysDisks; /* 0Bh */
819 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
820 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
821 IOCPage2_t, MPI_POINTER pIOCPage2_t;
823 #define MPI_IOCPAGE2_PAGEVERSION (0x02)
825 /* IOC Page 2 Capabilities flags */
827 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)
828 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)
829 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)
830 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)
831 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)
832 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)
835 typedef struct _IOC_3_PHYS_DISK
837 U8 PhysDiskID; /* 00h */
838 U8 PhysDiskBus; /* 01h */
839 U8 PhysDiskIOC; /* 02h */
840 U8 PhysDiskNum; /* 03h */
841 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,
842 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;
845 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
846 * one and check Header.PageLength at runtime.
848 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
849 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1)
852 typedef struct _CONFIG_PAGE_IOC_3
854 CONFIG_PAGE_HEADER Header; /* 00h */
855 U8 NumPhysDisks; /* 04h */
856 U8 Reserved1; /* 05h */
857 U16 Reserved2; /* 06h */
858 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */
859 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,
860 IOCPage3_t, MPI_POINTER pIOCPage3_t;
862 #define MPI_IOCPAGE3_PAGEVERSION (0x00)
865 typedef struct _IOC_4_SEP
867 U8 SEPTargetID; /* 00h */
869 U16 Reserved; /* 02h */
870 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP,
871 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t;
874 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
875 * one and check Header.PageLength at runtime.
877 #ifndef MPI_IOC_PAGE_4_SEP_MAX
878 #define MPI_IOC_PAGE_4_SEP_MAX (1)
881 typedef struct _CONFIG_PAGE_IOC_4
883 CONFIG_PAGE_HEADER Header; /* 00h */
884 U8 ActiveSEP; /* 04h */
886 U16 Reserved1; /* 06h */
887 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */
888 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,
889 IOCPage4_t, MPI_POINTER pIOCPage4_t;
891 #define MPI_IOCPAGE4_PAGEVERSION (0x00)
894 typedef struct _IOC_5_HOT_SPARE
896 U8 PhysDiskNum; /* 00h */
897 U8 Reserved; /* 01h */
898 U8 HotSparePool; /* 02h */
900 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE,
901 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t;
903 /* IOC Page 5 HotSpare Flags */
904 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01)
907 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
908 * one and check Header.PageLength at runtime.
910 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX
911 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1)
914 typedef struct _CONFIG_PAGE_IOC_5
916 CONFIG_PAGE_HEADER Header; /* 00h */
917 U32 Reserved1; /* 04h */
918 U8 NumHotSpares; /* 08h */
919 U8 Reserved2; /* 09h */
920 U16 Reserved3; /* 0Ah */
921 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
922 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
923 IOCPage5_t, MPI_POINTER pIOCPage5_t;
925 #define MPI_IOCPAGE5_PAGEVERSION (0x00)
928 /****************************************************************************
930 ****************************************************************************/
932 typedef struct _CONFIG_PAGE_BIOS_1
934 CONFIG_PAGE_HEADER Header; /* 00h */
935 U32 BiosOptions; /* 04h */
936 U32 IOCSettings; /* 08h */
937 U32 Reserved1; /* 0Ch */
938 U32 DeviceSettings; /* 10h */
939 U16 NumberOfDevices; /* 14h */
940 U16 Reserved2; /* 16h */
941 U16 IOTimeoutBlockDevicesNonRM; /* 18h */
942 U16 IOTimeoutSequential; /* 1Ah */
943 U16 IOTimeoutOther; /* 1Ch */
944 U16 IOTimeoutBlockDevicesRM; /* 1Eh */
945 } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1,
946 BIOSPage1_t, MPI_POINTER pBIOSPage1_t;
948 #define MPI_BIOSPAGE1_PAGEVERSION (0x01)
950 /* values for the BiosOptions field */
951 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400)
952 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200)
953 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100)
954 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
956 /* values for the IOCSettings field */
957 #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
958 #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
959 #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
961 #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000)
962 #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12)
964 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00)
965 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8)
967 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
968 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
969 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
970 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
972 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
973 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
974 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
975 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
976 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
978 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
980 /* values for the DeviceSettings field */
981 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
982 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
983 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
984 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
986 typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER
988 U32 Reserved1; /* 00h */
989 U32 Reserved2; /* 04h */
990 U32 Reserved3; /* 08h */
991 U32 Reserved4; /* 0Ch */
992 U32 Reserved5; /* 10h */
993 U32 Reserved6; /* 14h */
994 U32 Reserved7; /* 18h */
995 U32 Reserved8; /* 1Ch */
996 U32 Reserved9; /* 20h */
997 U32 Reserved10; /* 24h */
998 U32 Reserved11; /* 28h */
999 U32 Reserved12; /* 2Ch */
1000 U32 Reserved13; /* 30h */
1001 U32 Reserved14; /* 34h */
1002 U32 Reserved15; /* 38h */
1003 U32 Reserved16; /* 3Ch */
1004 U32 Reserved17; /* 40h */
1005 } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER;
1007 typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER
1009 U8 TargetID; /* 00h */
1011 U8 AdapterNumber; /* 02h */
1012 U8 Reserved1; /* 03h */
1013 U32 Reserved2; /* 04h */
1014 U32 Reserved3; /* 08h */
1015 U32 Reserved4; /* 0Ch */
1016 U8 LUN[8]; /* 10h */
1017 U32 Reserved5; /* 18h */
1018 U32 Reserved6; /* 1Ch */
1019 U32 Reserved7; /* 20h */
1020 U32 Reserved8; /* 24h */
1021 U32 Reserved9; /* 28h */
1022 U32 Reserved10; /* 2Ch */
1023 U32 Reserved11; /* 30h */
1024 U32 Reserved12; /* 34h */
1025 U32 Reserved13; /* 38h */
1026 U32 Reserved14; /* 3Ch */
1027 U32 Reserved15; /* 40h */
1028 } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER;
1030 typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS
1032 U8 TargetID; /* 00h */
1034 U16 PCIAddress; /* 02h */
1035 U32 Reserved1; /* 04h */
1036 U32 Reserved2; /* 08h */
1037 U32 Reserved3; /* 0Ch */
1038 U8 LUN[8]; /* 10h */
1039 U32 Reserved4; /* 18h */
1040 U32 Reserved5; /* 1Ch */
1041 U32 Reserved6; /* 20h */
1042 U32 Reserved7; /* 24h */
1043 U32 Reserved8; /* 28h */
1044 U32 Reserved9; /* 2Ch */
1045 U32 Reserved10; /* 30h */
1046 U32 Reserved11; /* 34h */
1047 U32 Reserved12; /* 38h */
1048 U32 Reserved13; /* 3Ch */
1049 U32 Reserved14; /* 40h */
1050 } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS;
1052 typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER
1054 U8 TargetID; /* 00h */
1056 U8 PCISlotNumber; /* 02h */
1057 U8 Reserved1; /* 03h */
1058 U32 Reserved2; /* 04h */
1059 U32 Reserved3; /* 08h */
1060 U32 Reserved4; /* 0Ch */
1061 U8 LUN[8]; /* 10h */
1062 U32 Reserved5; /* 18h */
1063 U32 Reserved6; /* 1Ch */
1064 U32 Reserved7; /* 20h */
1065 U32 Reserved8; /* 24h */
1066 U32 Reserved9; /* 28h */
1067 U32 Reserved10; /* 2Ch */
1068 U32 Reserved11; /* 30h */
1069 U32 Reserved12; /* 34h */
1070 U32 Reserved13; /* 38h */
1071 U32 Reserved14; /* 3Ch */
1072 U32 Reserved15; /* 40h */
1073 } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER;
1075 typedef struct _MPI_BOOT_DEVICE_FC_WWN
1078 U32 Reserved1; /* 08h */
1079 U32 Reserved2; /* 0Ch */
1080 U8 LUN[8]; /* 10h */
1081 U32 Reserved3; /* 18h */
1082 U32 Reserved4; /* 1Ch */
1083 U32 Reserved5; /* 20h */
1084 U32 Reserved6; /* 24h */
1085 U32 Reserved7; /* 28h */
1086 U32 Reserved8; /* 2Ch */
1087 U32 Reserved9; /* 30h */
1088 U32 Reserved10; /* 34h */
1089 U32 Reserved11; /* 38h */
1090 U32 Reserved12; /* 3Ch */
1091 U32 Reserved13; /* 40h */
1092 } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN;
1094 typedef struct _MPI_BOOT_DEVICE_SAS_WWN
1096 U64 SASAddress; /* 00h */
1097 U32 Reserved1; /* 08h */
1098 U32 Reserved2; /* 0Ch */
1099 U8 LUN[8]; /* 10h */
1100 U32 Reserved3; /* 18h */
1101 U32 Reserved4; /* 1Ch */
1102 U32 Reserved5; /* 20h */
1103 U32 Reserved6; /* 24h */
1104 U32 Reserved7; /* 28h */
1105 U32 Reserved8; /* 2Ch */
1106 U32 Reserved9; /* 30h */
1107 U32 Reserved10; /* 34h */
1108 U32 Reserved11; /* 38h */
1109 U32 Reserved12; /* 3Ch */
1110 U32 Reserved13; /* 40h */
1111 } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN;
1113 typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT
1115 U64 EnclosureLogicalID; /* 00h */
1116 U32 Reserved1; /* 08h */
1117 U32 Reserved2; /* 0Ch */
1118 U8 LUN[8]; /* 10h */
1119 U16 SlotNumber; /* 18h */
1120 U16 Reserved3; /* 1Ah */
1121 U32 Reserved4; /* 1Ch */
1122 U32 Reserved5; /* 20h */
1123 U32 Reserved6; /* 24h */
1124 U32 Reserved7; /* 28h */
1125 U32 Reserved8; /* 2Ch */
1126 U32 Reserved9; /* 30h */
1127 U32 Reserved10; /* 34h */
1128 U32 Reserved11; /* 38h */
1129 U32 Reserved12; /* 3Ch */
1130 U32 Reserved13; /* 40h */
1131 } MPI_BOOT_DEVICE_ENCLOSURE_SLOT,
1132 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT;
1134 typedef union _MPI_BIOSPAGE2_BOOT_DEVICE
1136 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1137 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber;
1138 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress;
1139 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber;
1140 MPI_BOOT_DEVICE_FC_WWN FcWwn;
1141 MPI_BOOT_DEVICE_SAS_WWN SasWwn;
1142 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1143 } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE;
1145 typedef struct _CONFIG_PAGE_BIOS_2
1147 CONFIG_PAGE_HEADER Header; /* 00h */
1148 U32 Reserved1; /* 04h */
1149 U32 Reserved2; /* 08h */
1150 U32 Reserved3; /* 0Ch */
1151 U32 Reserved4; /* 10h */
1152 U32 Reserved5; /* 14h */
1153 U32 Reserved6; /* 18h */
1154 U8 BootDeviceForm; /* 1Ch */
1155 U8 Reserved7; /* 1Dh */
1156 U16 Reserved8; /* 1Eh */
1157 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */
1158 } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2,
1159 BIOSPage2_t, MPI_POINTER pBIOSPage2_t;
1161 #define MPI_BIOSPAGE2_PAGEVERSION (0x01)
1163 #define MPI_BIOSPAGE2_FORM_MASK (0x0F)
1164 #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00)
1165 #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01)
1166 #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02)
1167 #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03)
1168 #define MPI_BIOSPAGE2_FORM_FC_WWN (0x04)
1169 #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05)
1172 /****************************************************************************
1173 * SCSI Port Config Pages
1174 ****************************************************************************/
1176 typedef struct _CONFIG_PAGE_SCSI_PORT_0
1178 CONFIG_PAGE_HEADER Header; /* 00h */
1179 U32 Capabilities; /* 04h */
1180 U32 PhysicalInterface; /* 08h */
1181 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
1182 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
1184 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02)
1186 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)
1187 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
1188 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
1189 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1190 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00)
1191 #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32)
1192 #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19)
1193 #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C)
1194 #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B)
1195 #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A)
1196 #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09)
1197 #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08)
1198 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF)
1200 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8)
1201 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \
1202 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MIN_SYNC_PERIOD) \
1203 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \
1205 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1206 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16)
1207 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \
1208 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MAX_SYNC_OFFSET) \
1209 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \
1211 #define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000)
1212 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
1213 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
1215 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)
1216 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)
1217 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)
1218 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)
1219 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)
1220 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24)
1221 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE)
1222 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF)
1225 typedef struct _CONFIG_PAGE_SCSI_PORT_1
1227 CONFIG_PAGE_HEADER Header; /* 00h */
1228 U32 Configuration; /* 04h */
1229 U32 OnBusTimerValue; /* 08h */
1230 U8 TargetConfig; /* 0Ch */
1231 U8 Reserved1; /* 0Dh */
1232 U16 IDConfig; /* 0Eh */
1233 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
1234 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
1236 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)
1238 /* Configuration values */
1239 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
1240 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
1241 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16)
1243 /* TargetConfig values */
1244 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01)
1245 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02)
1248 typedef struct _MPI_DEVICE_INFO
1250 U8 Timeout; /* 00h */
1251 U8 SyncFactor; /* 01h */
1252 U16 DeviceFlags; /* 02h */
1253 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,
1254 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;
1256 typedef struct _CONFIG_PAGE_SCSI_PORT_2
1258 CONFIG_PAGE_HEADER Header; /* 00h */
1259 U32 PortFlags; /* 04h */
1260 U32 PortSettings; /* 08h */
1261 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */
1262 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,
1263 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;
1265 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02)
1267 /* PortFlags values */
1268 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001)
1269 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004)
1270 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1271 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)
1273 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060)
1274 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000)
1275 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020)
1276 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060)
1279 /* PortSettings values */
1280 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)
1281 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)
1282 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000)
1283 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010)
1284 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)
1285 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)
1286 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)
1287 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000)
1288 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040)
1289 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080)
1290 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)
1291 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8)
1292 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)
1293 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)
1294 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)
1295 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000)
1297 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001)
1298 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002)
1299 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004)
1300 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008)
1301 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010)
1302 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020)
1305 /****************************************************************************
1306 * SCSI Target Device Config Pages
1307 ****************************************************************************/
1309 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
1311 CONFIG_PAGE_HEADER Header; /* 00h */
1312 U32 NegotiatedParameters; /* 04h */
1313 U32 Information; /* 08h */
1314 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
1315 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
1317 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04)
1319 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)
1320 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)
1321 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)
1322 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)
1323 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)
1324 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)
1325 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)
1326 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)
1327 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
1328 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8)
1329 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
1330 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16)
1331 #define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000)
1332 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
1333 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
1335 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)
1336 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)
1337 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)
1338 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)
1341 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
1343 CONFIG_PAGE_HEADER Header; /* 00h */
1344 U32 RequestedParameters; /* 04h */
1345 U32 Reserved; /* 08h */
1346 U32 Configuration; /* 0Ch */
1347 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
1348 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
1350 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05)
1352 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)
1353 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)
1354 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)
1355 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)
1356 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)
1357 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)
1358 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)
1359 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)
1360 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1361 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8)
1362 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1363 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16)
1364 #define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000)
1365 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
1366 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
1368 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)
1369 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)
1370 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)
1371 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)
1374 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2
1376 CONFIG_PAGE_HEADER Header; /* 00h */
1377 U32 DomainValidation; /* 04h */
1378 U32 ParityPipeSelect; /* 08h */
1379 U32 DataPipeSelect; /* 0Ch */
1380 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,
1381 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;
1383 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01)
1385 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010)
1386 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020)
1387 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380)
1388 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00)
1389 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000)
1390 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000)
1391 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000)
1392 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000)
1393 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000)
1395 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003)
1397 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003)
1398 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C)
1399 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030)
1400 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0)
1401 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300)
1402 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00)
1403 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000)
1404 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000)
1405 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000)
1406 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000)
1407 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000)
1408 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000)
1409 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000)
1410 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000)
1411 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000)
1412 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000)
1415 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3
1417 CONFIG_PAGE_HEADER Header; /* 00h */
1418 U16 MsgRejectCount; /* 04h */
1419 U16 PhaseErrorCount; /* 06h */
1420 U16 ParityErrorCount; /* 08h */
1421 U16 Reserved; /* 0Ah */
1422 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3,
1423 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t;
1425 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00)
1427 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE)
1428 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF)
1431 /****************************************************************************
1432 * FC Port Config Pages
1433 ****************************************************************************/
1435 typedef struct _CONFIG_PAGE_FC_PORT_0
1437 CONFIG_PAGE_HEADER Header; /* 00h */
1438 U32 Flags; /* 04h */
1439 U8 MPIPortNumber; /* 08h */
1440 U8 LinkType; /* 09h */
1441 U8 PortState; /* 0Ah */
1442 U8 Reserved; /* 0Bh */
1443 U32 PortIdentifier; /* 0Ch */
1446 U32 SupportedServiceClass; /* 20h */
1447 U32 SupportedSpeeds; /* 24h */
1448 U32 CurrentSpeed; /* 28h */
1449 U32 MaxFrameSize; /* 2Ch */
1450 U64 FabricWWNN; /* 30h */
1451 U64 FabricWWPN; /* 38h */
1452 U32 DiscoveredPortsCount; /* 40h */
1453 U32 MaxInitiators; /* 44h */
1454 U8 MaxAliasesSupported; /* 48h */
1455 U8 MaxHardAliasesSupported; /* 49h */
1456 U8 NumCurrentAliases; /* 4Ah */
1457 U8 Reserved1; /* 4Bh */
1458 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,
1459 FCPortPage0_t, MPI_POINTER pFCPortPage0_t;
1461 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02)
1463 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F)
1464 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR)
1465 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET)
1466 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN)
1467 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)
1469 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010)
1470 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020)
1471 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040)
1473 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00)
1474 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000)
1475 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100)
1476 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200)
1477 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400)
1478 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800)
1480 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00)
1481 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01)
1482 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02)
1483 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03)
1484 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04)
1485 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05)
1486 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06)
1487 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07)
1488 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08)
1489 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09)
1490 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A)
1491 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B)
1492 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C)
1493 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D)
1494 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E)
1495 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F)
1497 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */
1498 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */
1499 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */
1500 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */
1501 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */
1502 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */
1503 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */
1504 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */
1506 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001)
1507 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002)
1508 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004)
1510 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */
1511 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */
1512 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */
1513 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */
1514 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */
1516 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN
1517 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
1518 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
1519 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
1520 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED
1521 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */
1524 typedef struct _CONFIG_PAGE_FC_PORT_1
1526 CONFIG_PAGE_HEADER Header; /* 00h */
1527 U32 Flags; /* 04h */
1528 U64 NoSEEPROMWWNN; /* 08h */
1529 U64 NoSEEPROMWWPN; /* 10h */
1530 U8 HardALPA; /* 18h */
1531 U8 LinkConfig; /* 19h */
1532 U8 TopologyConfig; /* 1Ah */
1533 U8 AltConnector; /* 1Bh */
1534 U8 NumRequestedAliases; /* 1Ch */
1535 U8 RR_TOV; /* 1Dh */
1536 U8 InitiatorDeviceTimeout; /* 1Eh */
1537 U8 InitiatorIoPendTimeout; /* 1Fh */
1538 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
1539 FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
1541 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06)
1543 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
1544 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
1545 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000)
1546 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)
1547 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)
1548 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000)
1549 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000)
1550 #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080)
1551 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)
1552 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008)
1553 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004)
1554 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002)
1555 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)
1556 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)
1558 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)
1559 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28)
1560 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1561 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1562 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1563 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1565 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000)
1566 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010)
1567 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030)
1568 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050)
1570 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF)
1572 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F)
1573 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00)
1574 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01)
1575 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02)
1576 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03)
1577 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F)
1579 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F)
1580 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01)
1581 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02)
1582 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F)
1584 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00)
1586 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F)
1587 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80)
1590 typedef struct _CONFIG_PAGE_FC_PORT_2
1592 CONFIG_PAGE_HEADER Header; /* 00h */
1593 U8 NumberActive; /* 04h */
1594 U8 ALPA[127]; /* 05h */
1595 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,
1596 FCPortPage2_t, MPI_POINTER pFCPortPage2_t;
1598 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01)
1601 typedef struct _WWN_FORMAT
1605 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT,
1606 WWNFormat, MPI_POINTER pWWNFormat;
1608 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID
1612 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID,
1613 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t;
1615 typedef struct _FC_PORT_PERSISTENT
1617 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */
1618 U8 TargetID; /* 10h */
1620 U16 Flags; /* 12h */
1621 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT,
1622 PersistentData_t, MPI_POINTER pPersistentData_t;
1624 #define MPI_PERSISTENT_FLAGS_SHIFT (16)
1625 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001)
1626 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002)
1627 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004)
1628 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008)
1629 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080)
1632 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1633 * one and check Header.PageLength at runtime.
1635 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
1636 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1)
1639 typedef struct _CONFIG_PAGE_FC_PORT_3
1641 CONFIG_PAGE_HEADER Header; /* 00h */
1642 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */
1643 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,
1644 FCPortPage3_t, MPI_POINTER pFCPortPage3_t;
1646 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01)
1649 typedef struct _CONFIG_PAGE_FC_PORT_4
1651 CONFIG_PAGE_HEADER Header; /* 00h */
1652 U32 PortFlags; /* 04h */
1653 U32 PortSettings; /* 08h */
1654 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,
1655 FCPortPage4_t, MPI_POINTER pFCPortPage4_t;
1657 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00)
1659 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1661 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030)
1662 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000)
1663 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010)
1664 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020)
1665 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030)
1666 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0)
1667 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00)
1670 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
1673 U8 AliasAlpa; /* 01h */
1674 U16 Reserved; /* 02h */
1675 U64 AliasWWNN; /* 04h */
1676 U64 AliasWWPN; /* 0Ch */
1677 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1678 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1679 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;
1681 typedef struct _CONFIG_PAGE_FC_PORT_5
1683 CONFIG_PAGE_HEADER Header; /* 00h */
1684 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */
1685 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,
1686 FCPortPage5_t, MPI_POINTER pFCPortPage5_t;
1688 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02)
1690 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01)
1691 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02)
1692 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04)
1693 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08)
1694 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10)
1696 typedef struct _CONFIG_PAGE_FC_PORT_6
1698 CONFIG_PAGE_HEADER Header; /* 00h */
1699 U32 Reserved; /* 04h */
1700 U64 TimeSinceReset; /* 08h */
1701 U64 TxFrames; /* 10h */
1702 U64 RxFrames; /* 18h */
1703 U64 TxWords; /* 20h */
1704 U64 RxWords; /* 28h */
1705 U64 LipCount; /* 30h */
1706 U64 NosCount; /* 38h */
1707 U64 ErrorFrames; /* 40h */
1708 U64 DumpedFrames; /* 48h */
1709 U64 LinkFailureCount; /* 50h */
1710 U64 LossOfSyncCount; /* 58h */
1711 U64 LossOfSignalCount; /* 60h */
1712 U64 PrimativeSeqErrCount; /* 68h */
1713 U64 InvalidTxWordCount; /* 70h */
1714 U64 InvalidCrcCount; /* 78h */
1715 U64 FcpInitiatorIoCount; /* 80h */
1716 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,
1717 FCPortPage6_t, MPI_POINTER pFCPortPage6_t;
1719 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00)
1722 typedef struct _CONFIG_PAGE_FC_PORT_7
1724 CONFIG_PAGE_HEADER Header; /* 00h */
1725 U32 Reserved; /* 04h */
1726 U8 PortSymbolicName[256]; /* 08h */
1727 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,
1728 FCPortPage7_t, MPI_POINTER pFCPortPage7_t;
1730 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00)
1733 typedef struct _CONFIG_PAGE_FC_PORT_8
1735 CONFIG_PAGE_HEADER Header; /* 00h */
1736 U32 BitVector[8]; /* 04h */
1737 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,
1738 FCPortPage8_t, MPI_POINTER pFCPortPage8_t;
1740 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00)
1743 typedef struct _CONFIG_PAGE_FC_PORT_9
1745 CONFIG_PAGE_HEADER Header; /* 00h */
1746 U32 Reserved; /* 04h */
1747 U64 GlobalWWPN; /* 08h */
1748 U64 GlobalWWNN; /* 10h */
1749 U32 UnitType; /* 18h */
1750 U32 PhysicalPortNumber; /* 1Ch */
1751 U32 NumAttachedNodes; /* 20h */
1752 U16 IPVersion; /* 24h */
1753 U16 UDPPortNumber; /* 26h */
1754 U8 IPAddress[16]; /* 28h */
1755 U16 Reserved1; /* 38h */
1756 U16 TopologyDiscoveryFlags; /* 3Ah */
1757 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,
1758 FCPortPage9_t, MPI_POINTER pFCPortPage9_t;
1760 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00)
1763 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA
1767 U8 Connector; /* 12h */
1768 U8 Transceiver[8]; /* 13h */
1769 U8 Encoding; /* 1Bh */
1770 U8 BitRate_100mbs; /* 1Ch */
1771 U8 Reserved1; /* 1Dh */
1772 U8 Length9u_km; /* 1Eh */
1773 U8 Length9u_100m; /* 1Fh */
1774 U8 Length50u_10m; /* 20h */
1775 U8 Length62p5u_10m; /* 21h */
1776 U8 LengthCopper_m; /* 22h */
1777 U8 Reseverved2; /* 22h */
1778 U8 VendorName[16]; /* 24h */
1779 U8 Reserved3; /* 34h */
1780 U8 VendorOUI[3]; /* 35h */
1781 U8 VendorPN[16]; /* 38h */
1782 U8 VendorRev[4]; /* 48h */
1783 U16 Wavelength; /* 4Ch */
1784 U8 Reserved4; /* 4Eh */
1785 U8 CC_BASE; /* 4Fh */
1786 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
1787 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
1788 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t;
1790 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00)
1791 #define MPI_FCPORT10_BASE_ID_GBIC (0x01)
1792 #define MPI_FCPORT10_BASE_ID_FIXED (0x02)
1793 #define MPI_FCPORT10_BASE_ID_SFP (0x03)
1794 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04)
1795 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F)
1796 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80)
1798 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00)
1799 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01)
1800 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02)
1801 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03)
1802 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04)
1803 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05)
1804 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06)
1805 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07)
1806 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80)
1808 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00)
1809 #define MPI_FCPORT10_BASE_CONN_SC (0x01)
1810 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02)
1811 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03)
1812 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04)
1813 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05)
1814 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06)
1815 #define MPI_FCPORT10_BASE_CONN_LC (0x07)
1816 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08)
1817 #define MPI_FCPORT10_BASE_CONN_MU (0x09)
1818 #define MPI_FCPORT10_BASE_CONN_SG (0x0A)
1819 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B)
1820 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C)
1821 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F)
1822 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20)
1823 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21)
1824 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22)
1825 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F)
1826 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80)
1828 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00)
1829 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01)
1830 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02)
1831 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03)
1832 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04)
1835 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA
1837 U8 Options[2]; /* 50h */
1838 U8 BitRateMax; /* 52h */
1839 U8 BitRateMin; /* 53h */
1840 U8 VendorSN[16]; /* 54h */
1841 U8 DateCode[8]; /* 64h */
1842 U8 DiagMonitoringType; /* 6Ch */
1843 U8 EnhancedOptions; /* 6Dh */
1844 U8 SFF8472Compliance; /* 6Eh */
1845 U8 CC_EXT; /* 6Fh */
1846 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
1847 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
1848 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t;
1850 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20)
1851 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10)
1852 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08)
1853 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04)
1854 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02)
1857 typedef struct _CONFIG_PAGE_FC_PORT_10
1859 CONFIG_PAGE_HEADER Header; /* 00h */
1861 U8 Reserved1; /* 05h */
1862 U16 Reserved2; /* 06h */
1863 U32 HwConfig1; /* 08h */
1864 U32 HwConfig2; /* 0Ch */
1865 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */
1866 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */
1867 U8 VendorSpecific[32]; /* 70h */
1868 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10,
1869 FCPortPage10_t, MPI_POINTER pFCPortPage10_t;
1871 #define MPI_FCPORTPAGE10_PAGEVERSION (0x01)
1873 /* standard MODDEF pin definitions (from GBIC spec.) */
1874 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007)
1875 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001)
1876 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002)
1877 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004)
1878 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007)
1879 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006)
1880 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005)
1881 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004)
1882 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003)
1883 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002)
1884 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001)
1885 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000)
1887 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010)
1888 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020)
1891 /****************************************************************************
1892 * FC Device Config Pages
1893 ****************************************************************************/
1895 typedef struct _CONFIG_PAGE_FC_DEVICE_0
1897 CONFIG_PAGE_HEADER Header; /* 00h */
1900 U32 PortIdentifier; /* 14h */
1901 U8 Protocol; /* 18h */
1903 U16 BBCredit; /* 1Ah */
1904 U16 MaxRxFrameSize; /* 1Ch */
1905 U8 ADISCHardALPA; /* 1Eh */
1906 U8 PortNumber; /* 1Fh */
1907 U8 FcPhLowestVersion; /* 20h */
1908 U8 FcPhHighestVersion; /* 21h */
1909 U8 CurrentTargetID; /* 22h */
1910 U8 CurrentBus; /* 23h */
1911 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,
1912 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;
1914 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03)
1916 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01)
1917 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02)
1918 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04)
1920 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01)
1921 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02)
1922 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04)
1923 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08)
1925 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK)
1926 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK)
1927 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
1928 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)
1929 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK)
1930 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)
1931 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)
1932 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK)
1934 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF)
1936 /****************************************************************************
1937 * RAID Volume Config Pages
1938 ****************************************************************************/
1940 typedef struct _RAID_VOL0_PHYS_DISK
1942 U16 Reserved; /* 00h */
1943 U8 PhysDiskMap; /* 02h */
1944 U8 PhysDiskNum; /* 03h */
1945 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK,
1946 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t;
1948 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1949 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1951 typedef struct _RAID_VOL0_STATUS
1955 U16 Reserved; /* 02h */
1956 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
1957 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
1959 /* RAID Volume Page 0 VolumeStatus defines */
1961 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)
1962 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)
1963 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)
1964 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08)
1966 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)
1967 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)
1968 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)
1969 #define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03)
1971 typedef struct _RAID_VOL0_SETTINGS
1973 U16 Settings; /* 00h */
1974 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */
1975 U8 Reserved; /* 02h */
1976 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,
1977 RaidVol0Settings, MPI_POINTER pRaidVol0Settings;
1979 /* RAID Volume Page 0 VolumeSettings defines */
1980 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001)
1981 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002)
1982 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004)
1983 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008)
1984 #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */
1985 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010)
1986 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000)
1988 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1989 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01)
1990 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02)
1991 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04)
1992 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08)
1993 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10)
1994 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20)
1995 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40)
1996 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80)
1999 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2000 * one and check Header.PageLength at runtime.
2002 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
2003 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
2006 typedef struct _CONFIG_PAGE_RAID_VOL_0
2008 CONFIG_PAGE_HEADER Header; /* 00h */
2009 U8 VolumeID; /* 04h */
2010 U8 VolumeBus; /* 05h */
2011 U8 VolumeIOC; /* 06h */
2012 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */
2013 RAID_VOL0_STATUS VolumeStatus; /* 08h */
2014 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */
2015 U32 MaxLBA; /* 10h */
2016 U32 Reserved1; /* 14h */
2017 U32 StripeSize; /* 18h */
2018 U32 Reserved2; /* 1Ch */
2019 U32 Reserved3; /* 20h */
2020 U8 NumPhysDisks; /* 24h */
2021 U8 DataScrubRate; /* 25h */
2022 U8 ResyncRate; /* 26h */
2023 U8 InactiveStatus; /* 27h */
2024 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
2025 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
2026 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
2028 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x04)
2030 /* values for RAID Volume Page 0 InactiveStatus field */
2031 #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
2032 #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
2033 #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
2034 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
2035 #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
2036 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
2037 #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
2040 typedef struct _CONFIG_PAGE_RAID_VOL_1
2042 CONFIG_PAGE_HEADER Header; /* 00h */
2043 U8 VolumeID; /* 01h */
2044 U8 VolumeBus; /* 02h */
2045 U8 VolumeIOC; /* 03h */
2046 U8 Reserved0; /* 04h */
2047 U8 GUID[24]; /* 05h */
2048 U8 Name[32]; /* 20h */
2050 U32 Reserved1; /* 48h */
2051 U32 Reserved2; /* 4Ch */
2052 } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1,
2053 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t;
2055 #define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01)
2058 /****************************************************************************
2059 * RAID Physical Disk Config Pages
2060 ****************************************************************************/
2062 typedef struct _RAID_PHYS_DISK0_ERROR_DATA
2064 U8 ErrorCdbByte; /* 00h */
2065 U8 ErrorSenseKey; /* 01h */
2066 U16 Reserved; /* 02h */
2067 U16 ErrorCount; /* 04h */
2068 U8 ErrorASC; /* 06h */
2069 U8 ErrorASCQ; /* 07h */
2070 U16 SmartCount; /* 08h */
2071 U8 SmartASC; /* 0Ah */
2072 U8 SmartASCQ; /* 0Bh */
2073 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA,
2074 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t;
2076 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA
2078 U8 VendorID[8]; /* 00h */
2079 U8 ProductID[16]; /* 08h */
2080 U8 ProductRevLevel[4]; /* 18h */
2081 U8 Info[32]; /* 1Ch */
2082 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA,
2083 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData;
2085 typedef struct _RAID_PHYS_DISK0_SETTINGS
2088 U8 SepBus; /* 01h */
2089 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2090 U8 PhysDiskSettings; /* 03h */
2091 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS,
2092 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t;
2094 typedef struct _RAID_PHYS_DISK0_STATUS
2098 U16 Reserved; /* 02h */
2099 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,
2100 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;
2102 /* RAID Volume 2 IM Physical Disk DiskStatus flags */
2104 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01)
2105 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02)
2106 #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04)
2108 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00)
2109 #define MPI_PHYSDISK0_STATUS_MISSING (0x01)
2110 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02)
2111 #define MPI_PHYSDISK0_STATUS_FAILED (0x03)
2112 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)
2113 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)
2114 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)
2115 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)
2117 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
2119 CONFIG_PAGE_HEADER Header; /* 00h */
2120 U8 PhysDiskID; /* 04h */
2121 U8 PhysDiskBus; /* 05h */
2122 U8 PhysDiskIOC; /* 06h */
2123 U8 PhysDiskNum; /* 07h */
2124 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */
2125 U32 Reserved1; /* 0Ch */
2126 U8 ExtDiskIdentifier[8]; /* 10h */
2127 U8 DiskIdentifier[16]; /* 18h */
2128 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */
2129 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */
2130 U32 MaxLBA; /* 68h */
2131 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */
2132 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
2133 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
2135 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x01)
2138 typedef struct _RAID_PHYS_DISK1_PATH
2140 U8 PhysDiskID; /* 00h */
2141 U8 PhysDiskBus; /* 01h */
2142 U16 Reserved1; /* 02h */
2144 U64 OwnerWWID; /* 0Ch */
2145 U8 OwnerIdentifier; /* 14h */
2146 U8 Reserved2; /* 15h */
2147 U16 Flags; /* 16h */
2148 } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH,
2149 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t;
2151 /* RAID Physical Disk Page 1 Flags field defines */
2152 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
2153 #define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
2155 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1
2157 CONFIG_PAGE_HEADER Header; /* 00h */
2158 U8 NumPhysDiskPaths; /* 04h */
2159 U8 PhysDiskNum; /* 05h */
2160 U16 Reserved2; /* 06h */
2161 U32 Reserved1; /* 08h */
2162 RAID_PHYS_DISK1_PATH Path[1]; /* 0Ch */
2163 } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1,
2164 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t;
2166 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00)
2169 /****************************************************************************
2171 ****************************************************************************/
2173 typedef struct _CONFIG_PAGE_LAN_0
2175 ConfigPageHeader_t Header; /* 00h */
2176 U16 TxRxModes; /* 04h */
2177 U16 Reserved; /* 06h */
2178 U32 PacketPrePad; /* 08h */
2179 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,
2180 LANPage0_t, MPI_POINTER pLANPage0_t;
2182 #define MPI_LAN_PAGE0_PAGEVERSION (0x01)
2184 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000)
2185 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001)
2186 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001)
2188 typedef struct _CONFIG_PAGE_LAN_1
2190 ConfigPageHeader_t Header; /* 00h */
2191 U16 Reserved; /* 04h */
2192 U8 CurrentDeviceState; /* 06h */
2193 U8 Reserved1; /* 07h */
2194 U32 MinPacketSize; /* 08h */
2195 U32 MaxPacketSize; /* 0Ch */
2196 U32 HardwareAddressLow; /* 10h */
2197 U32 HardwareAddressHigh; /* 14h */
2198 U32 MaxWireSpeedLow; /* 18h */
2199 U32 MaxWireSpeedHigh; /* 1Ch */
2200 U32 BucketsRemaining; /* 20h */
2201 U32 MaxReplySize; /* 24h */
2202 U32 NegWireSpeedLow; /* 28h */
2203 U32 NegWireSpeedHigh; /* 2Ch */
2204 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
2205 LANPage1_t, MPI_POINTER pLANPage1_t;
2207 #define MPI_LAN_PAGE1_PAGEVERSION (0x03)
2209 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
2210 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
2213 /****************************************************************************
2214 * Inband Config Pages
2215 ****************************************************************************/
2217 typedef struct _CONFIG_PAGE_INBAND_0
2219 CONFIG_PAGE_HEADER Header; /* 00h */
2220 MPI_VERSION_FORMAT InbandVersion; /* 04h */
2221 U16 MaximumBuffers; /* 08h */
2222 U16 Reserved1; /* 0Ah */
2223 } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0,
2224 InbandPage0_t, MPI_POINTER pInbandPage0_t;
2226 #define MPI_INBAND_PAGEVERSION (0x00)
2230 /****************************************************************************
2231 * SAS IO Unit Config Pages
2232 ****************************************************************************/
2234 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA
2237 U8 PortFlags; /* 01h */
2238 U8 PhyFlags; /* 02h */
2239 U8 NegotiatedLinkRate; /* 03h */
2240 U32 ControllerPhyDeviceInfo;/* 04h */
2241 U16 AttachedDeviceHandle; /* 08h */
2242 U16 ControllerDevHandle; /* 0Ah */
2243 U32 DiscoveryStatus; /* 0Ch */
2244 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA,
2245 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData;
2248 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2249 * one and check Header.PageLength at runtime.
2251 #ifndef MPI_SAS_IOUNIT0_PHY_MAX
2252 #define MPI_SAS_IOUNIT0_PHY_MAX (1)
2255 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0
2257 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2258 U32 Reserved1; /* 08h */
2259 U8 NumPhys; /* 0Ch */
2260 U8 Reserved2; /* 0Dh */
2261 U16 Reserved3; /* 0Eh */
2262 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */
2263 } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0,
2264 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t;
2266 #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x02)
2268 /* values for SAS IO Unit Page 0 PortFlags */
2269 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08)
2270 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2271 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2272 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2274 /* values for SAS IO Unit Page 0 PhyFlags */
2275 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04)
2276 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02)
2277 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01)
2279 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */
2280 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00)
2281 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01)
2282 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02)
2283 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03)
2284 #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08)
2285 #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09)
2287 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2289 /* values for SAS IO Unit Page 0 DiscoveryStatus */
2290 #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001)
2291 #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2292 #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2293 #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008)
2294 #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2295 #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2296 #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2297 #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2298 #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2299 #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2300 #define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400)
2301 #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2304 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA
2307 U8 PortFlags; /* 01h */
2308 U8 PhyFlags; /* 02h */
2309 U8 MaxMinLinkRate; /* 03h */
2310 U32 ControllerPhyDeviceInfo;/* 04h */
2311 U32 Reserved1; /* 08h */
2312 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA,
2313 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData;
2316 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2317 * one and check Header.PageLength at runtime.
2319 #ifndef MPI_SAS_IOUNIT1_PHY_MAX
2320 #define MPI_SAS_IOUNIT1_PHY_MAX (1)
2323 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1
2325 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2326 U16 ControlFlags; /* 08h */
2327 U16 MaxNumSATATargets; /* 0Ah */
2328 U32 Reserved1; /* 0Ch */
2329 U8 NumPhys; /* 10h */
2330 U8 SATAMaxQDepth; /* 11h */
2331 U16 Reserved2; /* 12h */
2332 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */
2333 } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1,
2334 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t;
2336 #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x04)
2338 /* values for SAS IO Unit Page 1 ControlFlags */
2339 #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2340 #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2341 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2342 #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800)
2344 #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2345 #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2346 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00)
2347 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01)
2348 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x10)
2350 #define MPI_SAS_IOUNIT1_CONTROL_AUTO_PORT_SAME_SAS_ADDR (0x0100)
2351 #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2352 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2353 #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2354 #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2355 #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008)
2356 #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2357 #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2358 #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2360 /* values for SAS IO Unit Page 1 PortFlags */
2361 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2362 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2363 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2365 /* values for SAS IO Unit Page 0 PhyFlags */
2366 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04)
2367 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02)
2368 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01)
2370 /* values for SAS IO Unit Page 0 MaxMinLinkRate */
2371 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0)
2372 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80)
2373 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90)
2374 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F)
2375 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08)
2376 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09)
2378 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2381 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2
2383 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2384 U32 Reserved1; /* 08h */
2385 U16 MaxPersistentIDs; /* 0Ch */
2386 U16 NumPersistentIDsUsed; /* 0Eh */
2387 U8 Status; /* 10h */
2389 U16 MaxNumPhysicalMappedIDs;/* 12h */ /* 12h */
2390 } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2,
2391 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t;
2393 #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x03)
2395 /* values for SAS IO Unit Page 2 Status field */
2396 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02)
2397 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01)
2399 /* values for SAS IO Unit Page 2 Flags field */
2400 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01)
2401 /* Physical Mapping Modes */
2402 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E)
2403 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1)
2404 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00)
2405 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01)
2406 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02)
2408 #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10)
2411 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3
2413 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2414 U32 Reserved1; /* 08h */
2415 U32 MaxInvalidDwordCount; /* 0Ch */
2416 U32 InvalidDwordCountTime; /* 10h */
2417 U32 MaxRunningDisparityErrorCount; /* 14h */
2418 U32 RunningDisparityErrorTime; /* 18h */
2419 U32 MaxLossDwordSynchCount; /* 1Ch */
2420 U32 LossDwordSynchCountTime; /* 20h */
2421 U32 MaxPhyResetProblemCount; /* 24h */
2422 U32 PhyResetProblemTime; /* 28h */
2423 } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3,
2424 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t;
2426 #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00)
2429 /****************************************************************************
2430 * SAS Expander Config Pages
2431 ****************************************************************************/
2433 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0
2435 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2436 U8 PhysicalPort; /* 08h */
2437 U8 Reserved1; /* 09h */
2438 U16 Reserved2; /* 0Ah */
2439 U64 SASAddress; /* 0Ch */
2440 U32 DiscoveryStatus; /* 14h */
2441 U16 DevHandle; /* 18h */
2442 U16 ParentDevHandle; /* 1Ah */
2443 U16 ExpanderChangeCount; /* 1Ch */
2444 U16 ExpanderRouteIndexes; /* 1Eh */
2445 U8 NumPhys; /* 20h */
2446 U8 SASLevel; /* 21h */
2448 U8 Reserved3; /* 23h */
2449 } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0,
2450 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t;
2452 #define MPI_SASEXPANDER0_PAGEVERSION (0x02)
2454 /* values for SAS Expander Page 0 DiscoveryStatus field */
2455 #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2456 #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2457 #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2458 #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008)
2459 #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2460 #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2461 #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2462 #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2463 #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2464 #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2465 #define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2466 #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2468 /* values for SAS Expander Page 0 Flags field */
2469 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02)
2470 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01)
2473 typedef struct _CONFIG_PAGE_SAS_EXPANDER_1
2475 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2476 U8 PhysicalPort; /* 08h */
2477 U8 Reserved1; /* 09h */
2478 U16 Reserved2; /* 0Ah */
2479 U8 NumPhys; /* 0Ch */
2481 U16 NumTableEntriesProgrammed; /* 0Eh */
2482 U8 ProgrammedLinkRate; /* 10h */
2483 U8 HwLinkRate; /* 11h */
2484 U16 AttachedDevHandle; /* 12h */
2485 U32 PhyInfo; /* 14h */
2486 U32 AttachedDeviceInfo; /* 18h */
2487 U16 OwnerDevHandle; /* 1Ch */
2488 U8 ChangeCount; /* 1Eh */
2489 U8 NegotiatedLinkRate; /* 1Fh */
2490 U8 PhyIdentifier; /* 20h */
2491 U8 AttachedPhyIdentifier; /* 21h */
2492 U8 NumTableEntriesProg; /* 22h */
2493 U8 DiscoveryInfo; /* 23h */
2494 U32 Reserved3; /* 24h */
2495 } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1,
2496 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t;
2498 #define MPI_SASEXPANDER1_PAGEVERSION (0x01)
2500 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */
2502 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */
2504 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */
2506 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */
2508 /* values for SAS Expander Page 1 DiscoveryInfo field */
2509 #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY DISABLED (0x04)
2510 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2511 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2513 /* values for SAS Expander Page 1 NegotiatedLinkRate field */
2514 #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00)
2515 #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01)
2516 #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02)
2517 #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03)
2518 #define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08)
2519 #define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09)
2522 /****************************************************************************
2523 * SAS Device Config Pages
2524 ****************************************************************************/
2526 typedef struct _CONFIG_PAGE_SAS_DEVICE_0
2528 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2530 U16 EnclosureHandle; /* 0Ah */
2531 U64 SASAddress; /* 0Ch */
2532 U16 ParentDevHandle; /* 14h */
2533 U8 PhyNum; /* 16h */
2534 U8 AccessStatus; /* 17h */
2535 U16 DevHandle; /* 18h */
2536 U8 TargetID; /* 1Ah */
2538 U32 DeviceInfo; /* 1Ch */
2539 U16 Flags; /* 20h */
2540 U8 PhysicalPort; /* 22h */
2541 U8 Reserved2; /* 23h */
2542 } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0,
2543 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t;
2545 #define MPI_SASDEVICE0_PAGEVERSION (0x04)
2547 /* values for SAS Device Page 0 AccessStatus field */
2548 #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2549 #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2550 #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2552 /* values for SAS Device Page 0 Flags field */
2553 #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2554 #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2555 #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2556 #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2557 #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2558 #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2559 #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2560 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004)
2561 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002)
2562 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2564 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */
2567 typedef struct _CONFIG_PAGE_SAS_DEVICE_1
2569 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2570 U32 Reserved1; /* 08h */
2571 U64 SASAddress; /* 0Ch */
2572 U32 Reserved2; /* 14h */
2573 U16 DevHandle; /* 18h */
2574 U8 TargetID; /* 1Ah */
2576 U8 InitialRegDeviceFIS[20];/* 1Ch */
2577 } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1,
2578 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t;
2580 #define MPI_SASDEVICE1_PAGEVERSION (0x00)
2583 typedef struct _CONFIG_PAGE_SAS_DEVICE_2
2585 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2586 U64 PhysicalIdentifier; /* 08h */
2587 U32 Reserved1; /* 10h */
2588 } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2,
2589 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t;
2591 #define MPI_SASDEVICE2_PAGEVERSION (0x00)
2594 /****************************************************************************
2595 * SAS PHY Config Pages
2596 ****************************************************************************/
2598 typedef struct _CONFIG_PAGE_SAS_PHY_0
2600 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2601 U32 Reserved1; /* 08h */
2602 U64 SASAddress; /* 0Ch */
2603 U16 AttachedDevHandle; /* 14h */
2604 U8 AttachedPhyIdentifier; /* 16h */
2605 U8 Reserved2; /* 17h */
2606 U32 AttachedDeviceInfo; /* 18h */
2607 U8 ProgrammedLinkRate; /* 20h */
2608 U8 HwLinkRate; /* 21h */
2609 U8 ChangeCount; /* 22h */
2610 U8 Reserved3; /* 23h */
2611 U32 PhyInfo; /* 24h */
2612 } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0,
2613 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t;
2615 #define MPI_SASPHY0_PAGEVERSION (0x00)
2617 /* values for SAS PHY Page 0 ProgrammedLinkRate field */
2618 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0)
2619 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
2620 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80)
2621 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90)
2622 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F)
2623 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
2624 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08)
2625 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09)
2627 /* values for SAS PHY Page 0 HwLinkRate field */
2628 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0)
2629 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80)
2630 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90)
2631 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F)
2632 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08)
2633 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09)
2635 /* values for SAS PHY Page 0 PhyInfo field */
2636 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
2637 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000)
2638 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000)
2640 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
2641 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
2643 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
2644 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000)
2645 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
2646 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020)
2648 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F)
2649 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000)
2650 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001)
2651 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002)
2652 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003)
2653 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008)
2654 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009)
2657 typedef struct _CONFIG_PAGE_SAS_PHY_1
2659 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2660 U32 Reserved1; /* 08h */
2661 U32 InvalidDwordCount; /* 0Ch */
2662 U32 RunningDisparityErrorCount; /* 10h */
2663 U32 LossDwordSynchCount; /* 14h */
2664 U32 PhyResetProblemCount; /* 18h */
2665 } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1,
2666 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t;
2668 #define MPI_SASPHY1_PAGEVERSION (0x00)
2671 /****************************************************************************
2672 * SAS Enclosure Config Pages
2673 ****************************************************************************/
2675 typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0
2677 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2678 U32 Reserved1; /* 08h */
2679 U64 EnclosureLogicalID; /* 0Ch */
2680 U16 Flags; /* 14h */
2681 U16 EnclosureHandle; /* 16h */
2682 U16 NumSlots; /* 18h */
2683 U16 StartSlot; /* 1Ah */
2684 U8 StartTargetID; /* 1Ch */
2685 U8 StartBus; /* 1Dh */
2686 U8 SEPTargetID; /* 1Eh */
2687 U8 SEPBus; /* 1Fh */
2688 U32 Reserved2; /* 20h */
2689 U32 Reserved3; /* 24h */
2690 } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0,
2691 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t;
2693 #define MPI_SASENCLOSURE0_PAGEVERSION (0x00)
2695 /* values for SAS Enclosure Page 0 Flags field */
2696 #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020)
2697 #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010)
2699 #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2700 #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2701 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2702 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2703 #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2704 #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2707 /****************************************************************************
2709 ****************************************************************************/
2711 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2712 * one and check NumLogEntries at runtime.
2714 #ifndef MPI_LOG_0_NUM_LOG_ENTRIES
2715 #define MPI_LOG_0_NUM_LOG_ENTRIES (1)
2718 #define MPI_LOG_0_LOG_DATA_LENGTH (20)
2720 typedef struct _MPI_LOG_0_ENTRY
2723 U32 TimeStamp; /* 08h */
2724 U32 Reserved1; /* 0Ch */
2725 U16 LogSequence; /* 10h */
2726 U16 LogEntryQualifier; /* 12h */
2727 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 14h */
2728 } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY,
2729 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t;
2731 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2732 #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2733 #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2735 typedef struct _CONFIG_PAGE_LOG_0
2737 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2738 U32 Reserved1; /* 08h */
2739 U32 Reserved2; /* 0Ch */
2740 U16 NumLogEntries; /* 10h */
2741 U16 Reserved3; /* 12h */
2742 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */
2743 } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0,
2744 LogPage0_t, MPI_POINTER pLogPage0_t;
2746 #define MPI_LOG_0_PAGEVERSION (0x00)