ath9k: Setup short preamble properly in rate registration
[linux-2.6] / drivers / net / wireless / ath9k / main.c
1 /*
2  * Copyright (c) 2008 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include <linux/nl80211.h>
18 #include "core.h"
19 #include "reg.h"
20 #include "hw.h"
21
22 #define ATH_PCI_VERSION "0.1"
23
24 static char *dev_info = "ath9k";
25
26 MODULE_AUTHOR("Atheros Communications");
27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29 MODULE_LICENSE("Dual BSD/GPL");
30
31 /* We use the hw_value as an index into our private channel structure */
32
33 #define CHAN2G(_freq, _idx)  { \
34         .center_freq = (_freq), \
35         .hw_value = (_idx), \
36         .max_power = 30, \
37 }
38
39 #define CHAN5G(_freq, _idx) { \
40         .band = IEEE80211_BAND_5GHZ, \
41         .center_freq = (_freq), \
42         .hw_value = (_idx), \
43         .max_power = 30, \
44 }
45
46 /* Some 2 GHz radios are actually tunable on 2312-2732
47  * on 5 MHz steps, we support the channels which we know
48  * we have calibration data for all cards though to make
49  * this static */
50 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51         CHAN2G(2412, 0), /* Channel 1 */
52         CHAN2G(2417, 1), /* Channel 2 */
53         CHAN2G(2422, 2), /* Channel 3 */
54         CHAN2G(2427, 3), /* Channel 4 */
55         CHAN2G(2432, 4), /* Channel 5 */
56         CHAN2G(2437, 5), /* Channel 6 */
57         CHAN2G(2442, 6), /* Channel 7 */
58         CHAN2G(2447, 7), /* Channel 8 */
59         CHAN2G(2452, 8), /* Channel 9 */
60         CHAN2G(2457, 9), /* Channel 10 */
61         CHAN2G(2462, 10), /* Channel 11 */
62         CHAN2G(2467, 11), /* Channel 12 */
63         CHAN2G(2472, 12), /* Channel 13 */
64         CHAN2G(2484, 13), /* Channel 14 */
65 };
66
67 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
68  * on 5 MHz steps, we support the channels which we know
69  * we have calibration data for all cards though to make
70  * this static */
71 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72         /* _We_ call this UNII 1 */
73         CHAN5G(5180, 14), /* Channel 36 */
74         CHAN5G(5200, 15), /* Channel 40 */
75         CHAN5G(5220, 16), /* Channel 44 */
76         CHAN5G(5240, 17), /* Channel 48 */
77         /* _We_ call this UNII 2 */
78         CHAN5G(5260, 18), /* Channel 52 */
79         CHAN5G(5280, 19), /* Channel 56 */
80         CHAN5G(5300, 20), /* Channel 60 */
81         CHAN5G(5320, 21), /* Channel 64 */
82         /* _We_ call this "Middle band" */
83         CHAN5G(5500, 22), /* Channel 100 */
84         CHAN5G(5520, 23), /* Channel 104 */
85         CHAN5G(5540, 24), /* Channel 108 */
86         CHAN5G(5560, 25), /* Channel 112 */
87         CHAN5G(5580, 26), /* Channel 116 */
88         CHAN5G(5600, 27), /* Channel 120 */
89         CHAN5G(5620, 28), /* Channel 124 */
90         CHAN5G(5640, 29), /* Channel 128 */
91         CHAN5G(5660, 30), /* Channel 132 */
92         CHAN5G(5680, 31), /* Channel 136 */
93         CHAN5G(5700, 32), /* Channel 140 */
94         /* _We_ call this UNII 3 */
95         CHAN5G(5745, 33), /* Channel 149 */
96         CHAN5G(5765, 34), /* Channel 153 */
97         CHAN5G(5785, 35), /* Channel 157 */
98         CHAN5G(5805, 36), /* Channel 161 */
99         CHAN5G(5825, 37), /* Channel 165 */
100 };
101
102 static void ath_cache_conf_rate(struct ath_softc *sc,
103                                 struct ieee80211_conf *conf)
104 {
105         switch (conf->channel->band) {
106         case IEEE80211_BAND_2GHZ:
107                 if (conf_is_ht20(conf))
108                         sc->cur_rate_table =
109                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110                 else if (conf_is_ht40_minus(conf))
111                         sc->cur_rate_table =
112                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113                 else if (conf_is_ht40_plus(conf))
114                         sc->cur_rate_table =
115                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
116                 else
117                         sc->cur_rate_table =
118                           sc->hw_rate_table[ATH9K_MODE_11G];
119                 break;
120         case IEEE80211_BAND_5GHZ:
121                 if (conf_is_ht20(conf))
122                         sc->cur_rate_table =
123                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124                 else if (conf_is_ht40_minus(conf))
125                         sc->cur_rate_table =
126                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127                 else if (conf_is_ht40_plus(conf))
128                         sc->cur_rate_table =
129                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130                 else
131                         sc->cur_rate_table =
132                           sc->hw_rate_table[ATH9K_MODE_11A];
133                 break;
134         default:
135                 BUG_ON(1);
136                 break;
137         }
138 }
139
140 static void ath_update_txpow(struct ath_softc *sc)
141 {
142         struct ath_hal *ah = sc->sc_ah;
143         u32 txpow;
144
145         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
146                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
147                 /* read back in case value is clamped */
148                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
149                 sc->sc_curtxpow = txpow;
150         }
151 }
152
153 static u8 parse_mpdudensity(u8 mpdudensity)
154 {
155         /*
156          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157          *   0 for no restriction
158          *   1 for 1/4 us
159          *   2 for 1/2 us
160          *   3 for 1 us
161          *   4 for 2 us
162          *   5 for 4 us
163          *   6 for 8 us
164          *   7 for 16 us
165          */
166         switch (mpdudensity) {
167         case 0:
168                 return 0;
169         case 1:
170         case 2:
171         case 3:
172                 /* Our lower layer calculations limit our precision to
173                    1 microsecond */
174                 return 1;
175         case 4:
176                 return 2;
177         case 5:
178                 return 4;
179         case 6:
180                 return 8;
181         case 7:
182                 return 16;
183         default:
184                 return 0;
185         }
186 }
187
188 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189 {
190         struct ath_rate_table *rate_table = NULL;
191         struct ieee80211_supported_band *sband;
192         struct ieee80211_rate *rate;
193         int i, maxrates;
194
195         switch (band) {
196         case IEEE80211_BAND_2GHZ:
197                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198                 break;
199         case IEEE80211_BAND_5GHZ:
200                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201                 break;
202         default:
203                 break;
204         }
205
206         if (rate_table == NULL)
207                 return;
208
209         sband = &sc->sbands[band];
210         rate = sc->rates[band];
211
212         if (rate_table->rate_cnt > ATH_RATE_MAX)
213                 maxrates = ATH_RATE_MAX;
214         else
215                 maxrates = rate_table->rate_cnt;
216
217         for (i = 0; i < maxrates; i++) {
218                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219                 rate[i].hw_value = rate_table->info[i].ratecode;
220                 if (rate_table->info[i].short_preamble) {
221                         rate[i].hw_value_short = rate_table->info[i].ratecode |
222                                 rate_table->info[i].short_preamble;
223                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
224                 }
225                 sband->n_bitrates++;
226
227                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
228                         rate[i].bitrate / 10, rate[i].hw_value);
229         }
230 }
231
232 /*
233  * Set/change channels.  If the channel is really being changed, it's done
234  * by reseting the chip.  To accomplish this we must first cleanup any pending
235  * DMA, then restart stuff.
236 */
237 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
238 {
239         struct ath_hal *ah = sc->sc_ah;
240         bool fastcc = true, stopped;
241         struct ieee80211_hw *hw = sc->hw;
242         struct ieee80211_channel *channel = hw->conf.channel;
243         int r;
244
245         if (sc->sc_flags & SC_OP_INVALID)
246                 return -EIO;
247
248         ath9k_ps_wakeup(sc);
249
250         /*
251          * This is only performed if the channel settings have
252          * actually changed.
253          *
254          * To switch channels clear any pending DMA operations;
255          * wait long enough for the RX fifo to drain, reset the
256          * hardware at the new frequency, and then re-enable
257          * the relevant bits of the h/w.
258          */
259         ath9k_hw_set_interrupts(ah, 0);
260         ath_drain_all_txq(sc, false);
261         stopped = ath_stoprecv(sc);
262
263         /* XXX: do not flush receive queue here. We don't want
264          * to flush data frames already in queue because of
265          * changing channel. */
266
267         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
268                 fastcc = false;
269
270         DPRINTF(sc, ATH_DBG_CONFIG,
271                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
272                 sc->sc_ah->ah_curchan->channel,
273                 channel->center_freq, sc->tx_chan_width);
274
275         spin_lock_bh(&sc->sc_resetlock);
276
277         r = ath9k_hw_reset(ah, hchan, fastcc);
278         if (r) {
279                 DPRINTF(sc, ATH_DBG_FATAL,
280                         "Unable to reset channel (%u Mhz) "
281                         "reset status %u\n",
282                         channel->center_freq, r);
283                 spin_unlock_bh(&sc->sc_resetlock);
284                 return r;
285         }
286         spin_unlock_bh(&sc->sc_resetlock);
287
288         sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
289         sc->sc_flags &= ~SC_OP_FULL_RESET;
290
291         if (ath_startrecv(sc) != 0) {
292                 DPRINTF(sc, ATH_DBG_FATAL,
293                         "Unable to restart recv logic\n");
294                 return -EIO;
295         }
296
297         ath_cache_conf_rate(sc, &hw->conf);
298         ath_update_txpow(sc);
299         ath9k_hw_set_interrupts(ah, sc->sc_imask);
300         ath9k_ps_restore(sc);
301         return 0;
302 }
303
304 /*
305  *  This routine performs the periodic noise floor calibration function
306  *  that is used to adjust and optimize the chip performance.  This
307  *  takes environmental changes (location, temperature) into account.
308  *  When the task is complete, it reschedules itself depending on the
309  *  appropriate interval that was calculated.
310  */
311 static void ath_ani_calibrate(unsigned long data)
312 {
313         struct ath_softc *sc;
314         struct ath_hal *ah;
315         bool longcal = false;
316         bool shortcal = false;
317         bool aniflag = false;
318         unsigned int timestamp = jiffies_to_msecs(jiffies);
319         u32 cal_interval;
320
321         sc = (struct ath_softc *)data;
322         ah = sc->sc_ah;
323
324         /*
325         * don't calibrate when we're scanning.
326         * we are most likely not on our home channel.
327         */
328         if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
329                 return;
330
331         /* Long calibration runs independently of short calibration. */
332         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
333                 longcal = true;
334                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
335                 sc->sc_ani.sc_longcal_timer = timestamp;
336         }
337
338         /* Short calibration applies only while sc_caldone is false */
339         if (!sc->sc_ani.sc_caldone) {
340                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
341                     ATH_SHORT_CALINTERVAL) {
342                         shortcal = true;
343                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
344                         sc->sc_ani.sc_shortcal_timer = timestamp;
345                         sc->sc_ani.sc_resetcal_timer = timestamp;
346                 }
347         } else {
348                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
349                     ATH_RESTART_CALINTERVAL) {
350                         sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
351                         if (sc->sc_ani.sc_caldone)
352                                 sc->sc_ani.sc_resetcal_timer = timestamp;
353                 }
354         }
355
356         /* Verify whether we must check ANI */
357         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
358            ATH_ANI_POLLINTERVAL) {
359                 aniflag = true;
360                 sc->sc_ani.sc_checkani_timer = timestamp;
361         }
362
363         /* Skip all processing if there's nothing to do. */
364         if (longcal || shortcal || aniflag) {
365                 /* Call ANI routine if necessary */
366                 if (aniflag)
367                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
368                                              ah->ah_curchan);
369
370                 /* Perform calibration if necessary */
371                 if (longcal || shortcal) {
372                         bool iscaldone = false;
373
374                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
375                                                sc->sc_rx_chainmask, longcal,
376                                                &iscaldone)) {
377                                 if (longcal)
378                                         sc->sc_ani.sc_noise_floor =
379                                                 ath9k_hw_getchan_noise(ah,
380                                                                ah->ah_curchan);
381
382                                 DPRINTF(sc, ATH_DBG_ANI,
383                                         "calibrate chan %u/%x nf: %d\n",
384                                         ah->ah_curchan->channel,
385                                         ah->ah_curchan->channelFlags,
386                                         sc->sc_ani.sc_noise_floor);
387                         } else {
388                                 DPRINTF(sc, ATH_DBG_ANY,
389                                         "calibrate chan %u/%x failed\n",
390                                         ah->ah_curchan->channel,
391                                         ah->ah_curchan->channelFlags);
392                         }
393                         sc->sc_ani.sc_caldone = iscaldone;
394                 }
395         }
396
397         /*
398         * Set timer interval based on previous results.
399         * The interval must be the shortest necessary to satisfy ANI,
400         * short calibration and long calibration.
401         */
402         cal_interval = ATH_LONG_CALINTERVAL;
403         if (sc->sc_ah->ah_config.enable_ani)
404                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
405         if (!sc->sc_ani.sc_caldone)
406                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
407
408         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
409 }
410
411 /*
412  * Update tx/rx chainmask. For legacy association,
413  * hard code chainmask to 1x1, for 11n association, use
414  * the chainmask configuration, for bt coexistence, use
415  * the chainmask configuration even in legacy mode.
416  */
417 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
418 {
419         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
420         if (is_ht ||
421             (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
422                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
423                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
424         } else {
425                 sc->sc_tx_chainmask = 1;
426                 sc->sc_rx_chainmask = 1;
427         }
428
429         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
430                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
431 }
432
433 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
434 {
435         struct ath_node *an;
436
437         an = (struct ath_node *)sta->drv_priv;
438
439         if (sc->sc_flags & SC_OP_TXAGGR)
440                 ath_tx_node_init(sc, an);
441
442         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
443                              sta->ht_cap.ampdu_factor);
444         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445 }
446
447 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
448 {
449         struct ath_node *an = (struct ath_node *)sta->drv_priv;
450
451         if (sc->sc_flags & SC_OP_TXAGGR)
452                 ath_tx_node_cleanup(sc, an);
453 }
454
455 static void ath9k_tasklet(unsigned long data)
456 {
457         struct ath_softc *sc = (struct ath_softc *)data;
458         u32 status = sc->sc_intrstatus;
459
460         if (status & ATH9K_INT_FATAL) {
461                 /* need a chip reset */
462                 ath_reset(sc, false);
463                 return;
464         } else {
465
466                 if (status &
467                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
468                         spin_lock_bh(&sc->rx.rxflushlock);
469                         ath_rx_tasklet(sc, 0);
470                         spin_unlock_bh(&sc->rx.rxflushlock);
471                 }
472                 /* XXX: optimize this */
473                 if (status & ATH9K_INT_TX)
474                         ath_tx_tasklet(sc);
475         }
476
477         /* re-enable hardware interrupt */
478         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
479 }
480
481 irqreturn_t ath_isr(int irq, void *dev)
482 {
483         struct ath_softc *sc = dev;
484         struct ath_hal *ah = sc->sc_ah;
485         enum ath9k_int status;
486         bool sched = false;
487
488         do {
489                 if (sc->sc_flags & SC_OP_INVALID) {
490                         /*
491                          * The hardware is not ready/present, don't
492                          * touch anything. Note this can happen early
493                          * on if the IRQ is shared.
494                          */
495                         return IRQ_NONE;
496                 }
497                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
498                         return IRQ_NONE;
499                 }
500
501                 /*
502                  * Figure out the reason(s) for the interrupt.  Note
503                  * that the hal returns a pseudo-ISR that may include
504                  * bits we haven't explicitly enabled so we mask the
505                  * value to insure we only process bits we requested.
506                  */
507                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
508
509                 status &= sc->sc_imask; /* discard unasked-for bits */
510
511                 /*
512                  * If there are no status bits set, then this interrupt was not
513                  * for me (should have been caught above).
514                  */
515                 if (!status)
516                         return IRQ_NONE;
517
518                 sc->sc_intrstatus = status;
519
520                 if (status & ATH9K_INT_FATAL) {
521                         /* need a chip reset */
522                         sched = true;
523                 } else if (status & ATH9K_INT_RXORN) {
524                         /* need a chip reset */
525                         sched = true;
526                 } else {
527                         if (status & ATH9K_INT_SWBA) {
528                                 /* schedule a tasklet for beacon handling */
529                                 tasklet_schedule(&sc->bcon_tasklet);
530                         }
531                         if (status & ATH9K_INT_RXEOL) {
532                                 /*
533                                  * NB: the hardware should re-read the link when
534                                  *     RXE bit is written, but it doesn't work
535                                  *     at least on older hardware revs.
536                                  */
537                                 sched = true;
538                         }
539
540                         if (status & ATH9K_INT_TXURN)
541                                 /* bump tx trigger level */
542                                 ath9k_hw_updatetxtriglevel(ah, true);
543                         /* XXX: optimize this */
544                         if (status & ATH9K_INT_RX)
545                                 sched = true;
546                         if (status & ATH9K_INT_TX)
547                                 sched = true;
548                         if (status & ATH9K_INT_BMISS)
549                                 sched = true;
550                         /* carrier sense timeout */
551                         if (status & ATH9K_INT_CST)
552                                 sched = true;
553                         if (status & ATH9K_INT_MIB) {
554                                 /*
555                                  * Disable interrupts until we service the MIB
556                                  * interrupt; otherwise it will continue to
557                                  * fire.
558                                  */
559                                 ath9k_hw_set_interrupts(ah, 0);
560                                 /*
561                                  * Let the hal handle the event. We assume
562                                  * it will clear whatever condition caused
563                                  * the interrupt.
564                                  */
565                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
566                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
567                         }
568                         if (status & ATH9K_INT_TIM_TIMER) {
569                                 if (!(ah->ah_caps.hw_caps &
570                                       ATH9K_HW_CAP_AUTOSLEEP)) {
571                                         /* Clear RxAbort bit so that we can
572                                          * receive frames */
573                                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
574                                         ath9k_hw_setrxabort(ah, 0);
575                                         sched = true;
576                                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
577                                 }
578                         }
579                 }
580         } while (0);
581
582         ath_debug_stat_interrupt(sc, status);
583
584         if (sched) {
585                 /* turn off every interrupt except SWBA */
586                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
587                 tasklet_schedule(&sc->intr_tq);
588         }
589
590         return IRQ_HANDLED;
591 }
592
593 static u32 ath_get_extchanmode(struct ath_softc *sc,
594                                struct ieee80211_channel *chan,
595                                enum nl80211_channel_type channel_type)
596 {
597         u32 chanmode = 0;
598
599         switch (chan->band) {
600         case IEEE80211_BAND_2GHZ:
601                 switch(channel_type) {
602                 case NL80211_CHAN_NO_HT:
603                 case NL80211_CHAN_HT20:
604                         chanmode = CHANNEL_G_HT20;
605                         break;
606                 case NL80211_CHAN_HT40PLUS:
607                         chanmode = CHANNEL_G_HT40PLUS;
608                         break;
609                 case NL80211_CHAN_HT40MINUS:
610                         chanmode = CHANNEL_G_HT40MINUS;
611                         break;
612                 }
613                 break;
614         case IEEE80211_BAND_5GHZ:
615                 switch(channel_type) {
616                 case NL80211_CHAN_NO_HT:
617                 case NL80211_CHAN_HT20:
618                         chanmode = CHANNEL_A_HT20;
619                         break;
620                 case NL80211_CHAN_HT40PLUS:
621                         chanmode = CHANNEL_A_HT40PLUS;
622                         break;
623                 case NL80211_CHAN_HT40MINUS:
624                         chanmode = CHANNEL_A_HT40MINUS;
625                         break;
626                 }
627                 break;
628         default:
629                 break;
630         }
631
632         return chanmode;
633 }
634
635 static int ath_keyset(struct ath_softc *sc, u16 keyix,
636                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
637 {
638         bool status;
639
640         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
641                 keyix, hk, mac, false);
642
643         return status != false;
644 }
645
646 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
647                            struct ath9k_keyval *hk,
648                            const u8 *addr)
649 {
650         const u8 *key_rxmic;
651         const u8 *key_txmic;
652
653         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
654         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
655
656         if (addr == NULL) {
657                 /* Group key installation */
658                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
659                 return ath_keyset(sc, keyix, hk, addr);
660         }
661         if (!sc->sc_splitmic) {
662                 /*
663                  * data key goes at first index,
664                  * the hal handles the MIC keys at index+64.
665                  */
666                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
667                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
668                 return ath_keyset(sc, keyix, hk, addr);
669         }
670         /*
671          * TX key goes at first index, RX key at +32.
672          * The hal handles the MIC keys at index+64.
673          */
674         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
675         if (!ath_keyset(sc, keyix, hk, NULL)) {
676                 /* Txmic entry failed. No need to proceed further */
677                 DPRINTF(sc, ATH_DBG_KEYCACHE,
678                         "Setting TX MIC Key Failed\n");
679                 return 0;
680         }
681
682         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
683         /* XXX delete tx key on failure? */
684         return ath_keyset(sc, keyix + 32, hk, addr);
685 }
686
687 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
688 {
689         int i;
690
691         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
692                 if (test_bit(i, sc->sc_keymap) ||
693                     test_bit(i + 64, sc->sc_keymap))
694                         continue; /* At least one part of TKIP key allocated */
695                 if (sc->sc_splitmic &&
696                     (test_bit(i + 32, sc->sc_keymap) ||
697                      test_bit(i + 64 + 32, sc->sc_keymap)))
698                         continue; /* At least one part of TKIP key allocated */
699
700                 /* Found a free slot for a TKIP key */
701                 return i;
702         }
703         return -1;
704 }
705
706 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
707 {
708         int i;
709
710         /* First, try to find slots that would not be available for TKIP. */
711         if (sc->sc_splitmic) {
712                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
713                         if (!test_bit(i, sc->sc_keymap) &&
714                             (test_bit(i + 32, sc->sc_keymap) ||
715                              test_bit(i + 64, sc->sc_keymap) ||
716                              test_bit(i + 64 + 32, sc->sc_keymap)))
717                                 return i;
718                         if (!test_bit(i + 32, sc->sc_keymap) &&
719                             (test_bit(i, sc->sc_keymap) ||
720                              test_bit(i + 64, sc->sc_keymap) ||
721                              test_bit(i + 64 + 32, sc->sc_keymap)))
722                                 return i + 32;
723                         if (!test_bit(i + 64, sc->sc_keymap) &&
724                             (test_bit(i , sc->sc_keymap) ||
725                              test_bit(i + 32, sc->sc_keymap) ||
726                              test_bit(i + 64 + 32, sc->sc_keymap)))
727                                 return i + 64;
728                         if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
729                             (test_bit(i, sc->sc_keymap) ||
730                              test_bit(i + 32, sc->sc_keymap) ||
731                              test_bit(i + 64, sc->sc_keymap)))
732                                 return i + 64 + 32;
733                 }
734         } else {
735                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
736                         if (!test_bit(i, sc->sc_keymap) &&
737                             test_bit(i + 64, sc->sc_keymap))
738                                 return i;
739                         if (test_bit(i, sc->sc_keymap) &&
740                             !test_bit(i + 64, sc->sc_keymap))
741                                 return i + 64;
742                 }
743         }
744
745         /* No partially used TKIP slots, pick any available slot */
746         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
747                 /* Do not allow slots that could be needed for TKIP group keys
748                  * to be used. This limitation could be removed if we know that
749                  * TKIP will not be used. */
750                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
751                         continue;
752                 if (sc->sc_splitmic) {
753                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
754                                 continue;
755                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
756                                 continue;
757                 }
758
759                 if (!test_bit(i, sc->sc_keymap))
760                         return i; /* Found a free slot for a key */
761         }
762
763         /* No free slot found */
764         return -1;
765 }
766
767 static int ath_key_config(struct ath_softc *sc,
768                           struct ieee80211_sta *sta,
769                           struct ieee80211_key_conf *key)
770 {
771         struct ath9k_keyval hk;
772         const u8 *mac = NULL;
773         int ret = 0;
774         int idx;
775
776         memset(&hk, 0, sizeof(hk));
777
778         switch (key->alg) {
779         case ALG_WEP:
780                 hk.kv_type = ATH9K_CIPHER_WEP;
781                 break;
782         case ALG_TKIP:
783                 hk.kv_type = ATH9K_CIPHER_TKIP;
784                 break;
785         case ALG_CCMP:
786                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
787                 break;
788         default:
789                 return -EOPNOTSUPP;
790         }
791
792         hk.kv_len = key->keylen;
793         memcpy(hk.kv_val, key->key, key->keylen);
794
795         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
796                 /* For now, use the default keys for broadcast keys. This may
797                  * need to change with virtual interfaces. */
798                 idx = key->keyidx;
799         } else if (key->keyidx) {
800                 struct ieee80211_vif *vif;
801
802                 if (WARN_ON(!sta))
803                         return -EOPNOTSUPP;
804                 mac = sta->addr;
805
806                 vif = sc->sc_vaps[0];
807                 if (vif->type != NL80211_IFTYPE_AP) {
808                         /* Only keyidx 0 should be used with unicast key, but
809                          * allow this for client mode for now. */
810                         idx = key->keyidx;
811                 } else
812                         return -EIO;
813         } else {
814                 if (WARN_ON(!sta))
815                         return -EOPNOTSUPP;
816                 mac = sta->addr;
817
818                 if (key->alg == ALG_TKIP)
819                         idx = ath_reserve_key_cache_slot_tkip(sc);
820                 else
821                         idx = ath_reserve_key_cache_slot(sc);
822                 if (idx < 0)
823                         return -ENOSPC; /* no free key cache entries */
824         }
825
826         if (key->alg == ALG_TKIP)
827                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
828         else
829                 ret = ath_keyset(sc, idx, &hk, mac);
830
831         if (!ret)
832                 return -EIO;
833
834         set_bit(idx, sc->sc_keymap);
835         if (key->alg == ALG_TKIP) {
836                 set_bit(idx + 64, sc->sc_keymap);
837                 if (sc->sc_splitmic) {
838                         set_bit(idx + 32, sc->sc_keymap);
839                         set_bit(idx + 64 + 32, sc->sc_keymap);
840                 }
841         }
842
843         return idx;
844 }
845
846 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
847 {
848         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
849         if (key->hw_key_idx < IEEE80211_WEP_NKID)
850                 return;
851
852         clear_bit(key->hw_key_idx, sc->sc_keymap);
853         if (key->alg != ALG_TKIP)
854                 return;
855
856         clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
857         if (sc->sc_splitmic) {
858                 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
859                 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
860         }
861 }
862
863 static void setup_ht_cap(struct ath_softc *sc,
864                          struct ieee80211_sta_ht_cap *ht_info)
865 {
866 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
867 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
868
869         ht_info->ht_supported = true;
870         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
871                        IEEE80211_HT_CAP_SM_PS |
872                        IEEE80211_HT_CAP_SGI_40 |
873                        IEEE80211_HT_CAP_DSSSCCK40;
874
875         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
876         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
877
878         /* set up supported mcs set */
879         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
880
881         switch(sc->sc_rx_chainmask) {
882         case 1:
883                 ht_info->mcs.rx_mask[0] = 0xff;
884                 break;
885         case 3:
886         case 5:
887         case 7:
888         default:
889                 ht_info->mcs.rx_mask[0] = 0xff;
890                 ht_info->mcs.rx_mask[1] = 0xff;
891                 break;
892         }
893
894         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
895 }
896
897 static void ath9k_bss_assoc_info(struct ath_softc *sc,
898                                  struct ieee80211_vif *vif,
899                                  struct ieee80211_bss_conf *bss_conf)
900 {
901         struct ath_vap *avp = (void *)vif->drv_priv;
902
903         if (bss_conf->assoc) {
904                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
905                         bss_conf->aid, sc->sc_curbssid);
906
907                 /* New association, store aid */
908                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
909                         sc->sc_curaid = bss_conf->aid;
910                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
911                                                sc->sc_curaid);
912                 }
913
914                 /* Configure the beacon */
915                 ath_beacon_config(sc, 0);
916                 sc->sc_flags |= SC_OP_BEACONS;
917
918                 /* Reset rssi stats */
919                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
920                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
921                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
922                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
923
924                 /* Start ANI */
925                 mod_timer(&sc->sc_ani.timer,
926                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
927
928         } else {
929                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
930                 sc->sc_curaid = 0;
931         }
932 }
933
934 /********************************/
935 /*       LED functions          */
936 /********************************/
937
938 static void ath_led_brightness(struct led_classdev *led_cdev,
939                                enum led_brightness brightness)
940 {
941         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
942         struct ath_softc *sc = led->sc;
943
944         switch (brightness) {
945         case LED_OFF:
946                 if (led->led_type == ATH_LED_ASSOC ||
947                     led->led_type == ATH_LED_RADIO)
948                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
949                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
950                                 (led->led_type == ATH_LED_RADIO) ? 1 :
951                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
952                 break;
953         case LED_FULL:
954                 if (led->led_type == ATH_LED_ASSOC)
955                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
956                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
957                 break;
958         default:
959                 break;
960         }
961 }
962
963 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
964                             char *trigger)
965 {
966         int ret;
967
968         led->sc = sc;
969         led->led_cdev.name = led->name;
970         led->led_cdev.default_trigger = trigger;
971         led->led_cdev.brightness_set = ath_led_brightness;
972
973         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
974         if (ret)
975                 DPRINTF(sc, ATH_DBG_FATAL,
976                         "Failed to register led:%s", led->name);
977         else
978                 led->registered = 1;
979         return ret;
980 }
981
982 static void ath_unregister_led(struct ath_led *led)
983 {
984         if (led->registered) {
985                 led_classdev_unregister(&led->led_cdev);
986                 led->registered = 0;
987         }
988 }
989
990 static void ath_deinit_leds(struct ath_softc *sc)
991 {
992         ath_unregister_led(&sc->assoc_led);
993         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
994         ath_unregister_led(&sc->tx_led);
995         ath_unregister_led(&sc->rx_led);
996         ath_unregister_led(&sc->radio_led);
997         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
998 }
999
1000 static void ath_init_leds(struct ath_softc *sc)
1001 {
1002         char *trigger;
1003         int ret;
1004
1005         /* Configure gpio 1 for output */
1006         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1007                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1008         /* LED off, active low */
1009         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1010
1011         trigger = ieee80211_get_radio_led_name(sc->hw);
1012         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1013                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1014         ret = ath_register_led(sc, &sc->radio_led, trigger);
1015         sc->radio_led.led_type = ATH_LED_RADIO;
1016         if (ret)
1017                 goto fail;
1018
1019         trigger = ieee80211_get_assoc_led_name(sc->hw);
1020         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1021                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1022         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1023         sc->assoc_led.led_type = ATH_LED_ASSOC;
1024         if (ret)
1025                 goto fail;
1026
1027         trigger = ieee80211_get_tx_led_name(sc->hw);
1028         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1029                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1030         ret = ath_register_led(sc, &sc->tx_led, trigger);
1031         sc->tx_led.led_type = ATH_LED_TX;
1032         if (ret)
1033                 goto fail;
1034
1035         trigger = ieee80211_get_rx_led_name(sc->hw);
1036         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1037                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1038         ret = ath_register_led(sc, &sc->rx_led, trigger);
1039         sc->rx_led.led_type = ATH_LED_RX;
1040         if (ret)
1041                 goto fail;
1042
1043         return;
1044
1045 fail:
1046         ath_deinit_leds(sc);
1047 }
1048
1049 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1050
1051 /*******************/
1052 /*      Rfkill     */
1053 /*******************/
1054
1055 static void ath_radio_enable(struct ath_softc *sc)
1056 {
1057         struct ath_hal *ah = sc->sc_ah;
1058         struct ieee80211_channel *channel = sc->hw->conf.channel;
1059         int r;
1060
1061         ath9k_ps_wakeup(sc);
1062         spin_lock_bh(&sc->sc_resetlock);
1063
1064         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1065
1066         if (r) {
1067                 DPRINTF(sc, ATH_DBG_FATAL,
1068                         "Unable to reset channel %u (%uMhz) ",
1069                         "reset status %u\n",
1070                         channel->center_freq, r);
1071         }
1072         spin_unlock_bh(&sc->sc_resetlock);
1073
1074         ath_update_txpow(sc);
1075         if (ath_startrecv(sc) != 0) {
1076                 DPRINTF(sc, ATH_DBG_FATAL,
1077                         "Unable to restart recv logic\n");
1078                 return;
1079         }
1080
1081         if (sc->sc_flags & SC_OP_BEACONS)
1082                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1083
1084         /* Re-Enable  interrupts */
1085         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1086
1087         /* Enable LED */
1088         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1089                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1090         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1091
1092         ieee80211_wake_queues(sc->hw);
1093         ath9k_ps_restore(sc);
1094 }
1095
1096 static void ath_radio_disable(struct ath_softc *sc)
1097 {
1098         struct ath_hal *ah = sc->sc_ah;
1099         struct ieee80211_channel *channel = sc->hw->conf.channel;
1100         int r;
1101
1102         ath9k_ps_wakeup(sc);
1103         ieee80211_stop_queues(sc->hw);
1104
1105         /* Disable LED */
1106         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1107         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1108
1109         /* Disable interrupts */
1110         ath9k_hw_set_interrupts(ah, 0);
1111
1112         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1113         ath_stoprecv(sc);               /* turn off frame recv */
1114         ath_flushrecv(sc);              /* flush recv queue */
1115
1116         spin_lock_bh(&sc->sc_resetlock);
1117         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1118         if (r) {
1119                 DPRINTF(sc, ATH_DBG_FATAL,
1120                         "Unable to reset channel %u (%uMhz) "
1121                         "reset status %u\n",
1122                         channel->center_freq, r);
1123         }
1124         spin_unlock_bh(&sc->sc_resetlock);
1125
1126         ath9k_hw_phy_disable(ah);
1127         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1128         ath9k_ps_restore(sc);
1129 }
1130
1131 static bool ath_is_rfkill_set(struct ath_softc *sc)
1132 {
1133         struct ath_hal *ah = sc->sc_ah;
1134
1135         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1136                                   ah->ah_rfkill_polarity;
1137 }
1138
1139 /* h/w rfkill poll function */
1140 static void ath_rfkill_poll(struct work_struct *work)
1141 {
1142         struct ath_softc *sc = container_of(work, struct ath_softc,
1143                                             rf_kill.rfkill_poll.work);
1144         bool radio_on;
1145
1146         if (sc->sc_flags & SC_OP_INVALID)
1147                 return;
1148
1149         radio_on = !ath_is_rfkill_set(sc);
1150
1151         /*
1152          * enable/disable radio only when there is a
1153          * state change in RF switch
1154          */
1155         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1156                 enum rfkill_state state;
1157
1158                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1159                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1160                                 : RFKILL_STATE_HARD_BLOCKED;
1161                 } else if (radio_on) {
1162                         ath_radio_enable(sc);
1163                         state = RFKILL_STATE_UNBLOCKED;
1164                 } else {
1165                         ath_radio_disable(sc);
1166                         state = RFKILL_STATE_HARD_BLOCKED;
1167                 }
1168
1169                 if (state == RFKILL_STATE_HARD_BLOCKED)
1170                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1171                 else
1172                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1173
1174                 rfkill_force_state(sc->rf_kill.rfkill, state);
1175         }
1176
1177         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1178                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1179 }
1180
1181 /* s/w rfkill handler */
1182 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1183 {
1184         struct ath_softc *sc = data;
1185
1186         switch (state) {
1187         case RFKILL_STATE_SOFT_BLOCKED:
1188                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1189                     SC_OP_RFKILL_SW_BLOCKED)))
1190                         ath_radio_disable(sc);
1191                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1192                 return 0;
1193         case RFKILL_STATE_UNBLOCKED:
1194                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1195                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1196                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1197                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1198                                         "radio as it is disabled by h/w\n");
1199                                 return -EPERM;
1200                         }
1201                         ath_radio_enable(sc);
1202                 }
1203                 return 0;
1204         default:
1205                 return -EINVAL;
1206         }
1207 }
1208
1209 /* Init s/w rfkill */
1210 static int ath_init_sw_rfkill(struct ath_softc *sc)
1211 {
1212         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1213                                              RFKILL_TYPE_WLAN);
1214         if (!sc->rf_kill.rfkill) {
1215                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1216                 return -ENOMEM;
1217         }
1218
1219         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1220                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1221         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1222         sc->rf_kill.rfkill->data = sc;
1223         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1224         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1225         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1226
1227         return 0;
1228 }
1229
1230 /* Deinitialize rfkill */
1231 static void ath_deinit_rfkill(struct ath_softc *sc)
1232 {
1233         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1234                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1235
1236         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1237                 rfkill_unregister(sc->rf_kill.rfkill);
1238                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1239                 sc->rf_kill.rfkill = NULL;
1240         }
1241 }
1242
1243 static int ath_start_rfkill_poll(struct ath_softc *sc)
1244 {
1245         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1246                 queue_delayed_work(sc->hw->workqueue,
1247                                    &sc->rf_kill.rfkill_poll, 0);
1248
1249         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1250                 if (rfkill_register(sc->rf_kill.rfkill)) {
1251                         DPRINTF(sc, ATH_DBG_FATAL,
1252                                 "Unable to register rfkill\n");
1253                         rfkill_free(sc->rf_kill.rfkill);
1254
1255                         /* Deinitialize the device */
1256                         ath_cleanup(sc);
1257                         return -EIO;
1258                 } else {
1259                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1260                 }
1261         }
1262
1263         return 0;
1264 }
1265 #endif /* CONFIG_RFKILL */
1266
1267 void ath_cleanup(struct ath_softc *sc)
1268 {
1269         ath_detach(sc);
1270         free_irq(sc->irq, sc);
1271         ath_bus_cleanup(sc);
1272         ieee80211_free_hw(sc->hw);
1273 }
1274
1275 void ath_detach(struct ath_softc *sc)
1276 {
1277         struct ieee80211_hw *hw = sc->hw;
1278         int i = 0;
1279
1280         ath9k_ps_wakeup(sc);
1281
1282         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1283
1284 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1285         ath_deinit_rfkill(sc);
1286 #endif
1287         ath_deinit_leds(sc);
1288
1289         ieee80211_unregister_hw(hw);
1290         ath_rx_cleanup(sc);
1291         ath_tx_cleanup(sc);
1292
1293         tasklet_kill(&sc->intr_tq);
1294         tasklet_kill(&sc->bcon_tasklet);
1295
1296         if (!(sc->sc_flags & SC_OP_INVALID))
1297                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1298
1299         /* cleanup tx queues */
1300         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1301                 if (ATH_TXQ_SETUP(sc, i))
1302                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1303
1304         ath9k_hw_detach(sc->sc_ah);
1305         ath9k_exit_debug(sc);
1306         ath9k_ps_restore(sc);
1307 }
1308
1309 static int ath_init(u16 devid, struct ath_softc *sc)
1310 {
1311         struct ath_hal *ah = NULL;
1312         int status;
1313         int error = 0, i;
1314         int csz = 0;
1315
1316         /* XXX: hardware will not be ready until ath_open() being called */
1317         sc->sc_flags |= SC_OP_INVALID;
1318
1319         if (ath9k_init_debug(sc) < 0)
1320                 printk(KERN_ERR "Unable to create debugfs files\n");
1321
1322         spin_lock_init(&sc->sc_resetlock);
1323         mutex_init(&sc->mutex);
1324         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1325         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1326                      (unsigned long)sc);
1327
1328         /*
1329          * Cache line size is used to size and align various
1330          * structures used to communicate with the hardware.
1331          */
1332         ath_read_cachesize(sc, &csz);
1333         /* XXX assert csz is non-zero */
1334         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1335
1336         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1337         if (ah == NULL) {
1338                 DPRINTF(sc, ATH_DBG_FATAL,
1339                         "Unable to attach hardware; HAL status %d\n", status);
1340                 error = -ENXIO;
1341                 goto bad;
1342         }
1343         sc->sc_ah = ah;
1344
1345         /* Get the hardware key cache size. */
1346         sc->sc_keymax = ah->ah_caps.keycache_size;
1347         if (sc->sc_keymax > ATH_KEYMAX) {
1348                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1349                         "Warning, using only %u entries in %u key cache\n",
1350                         ATH_KEYMAX, sc->sc_keymax);
1351                 sc->sc_keymax = ATH_KEYMAX;
1352         }
1353
1354         /*
1355          * Reset the key cache since some parts do not
1356          * reset the contents on initial power up.
1357          */
1358         for (i = 0; i < sc->sc_keymax; i++)
1359                 ath9k_hw_keyreset(ah, (u16) i);
1360
1361         if (ath9k_regd_init(sc->sc_ah))
1362                 goto bad;
1363
1364         /* default to MONITOR mode */
1365         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1366
1367         /* Setup rate tables */
1368
1369         ath_rate_attach(sc);
1370         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1371         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1372
1373         /*
1374          * Allocate hardware transmit queues: one queue for
1375          * beacon frames and one data queue for each QoS
1376          * priority.  Note that the hal handles reseting
1377          * these queues at the needed time.
1378          */
1379         sc->beacon.beaconq = ath_beaconq_setup(ah);
1380         if (sc->beacon.beaconq == -1) {
1381                 DPRINTF(sc, ATH_DBG_FATAL,
1382                         "Unable to setup a beacon xmit queue\n");
1383                 error = -EIO;
1384                 goto bad2;
1385         }
1386         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1387         if (sc->beacon.cabq == NULL) {
1388                 DPRINTF(sc, ATH_DBG_FATAL,
1389                         "Unable to setup CAB xmit queue\n");
1390                 error = -EIO;
1391                 goto bad2;
1392         }
1393
1394         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1395         ath_cabq_update(sc);
1396
1397         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1398                 sc->tx.hwq_map[i] = -1;
1399
1400         /* Setup data queues */
1401         /* NB: ensure BK queue is the lowest priority h/w queue */
1402         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1403                 DPRINTF(sc, ATH_DBG_FATAL,
1404                         "Unable to setup xmit queue for BK traffic\n");
1405                 error = -EIO;
1406                 goto bad2;
1407         }
1408
1409         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1410                 DPRINTF(sc, ATH_DBG_FATAL,
1411                         "Unable to setup xmit queue for BE traffic\n");
1412                 error = -EIO;
1413                 goto bad2;
1414         }
1415         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1416                 DPRINTF(sc, ATH_DBG_FATAL,
1417                         "Unable to setup xmit queue for VI traffic\n");
1418                 error = -EIO;
1419                 goto bad2;
1420         }
1421         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1422                 DPRINTF(sc, ATH_DBG_FATAL,
1423                         "Unable to setup xmit queue for VO traffic\n");
1424                 error = -EIO;
1425                 goto bad2;
1426         }
1427
1428         /* Initializes the noise floor to a reasonable default value.
1429          * Later on this will be updated during ANI processing. */
1430
1431         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1432         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1433
1434         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1435                                    ATH9K_CIPHER_TKIP, NULL)) {
1436                 /*
1437                  * Whether we should enable h/w TKIP MIC.
1438                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1439                  * report WMM capable, so it's always safe to turn on
1440                  * TKIP MIC in this case.
1441                  */
1442                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1443                                        0, 1, NULL);
1444         }
1445
1446         /*
1447          * Check whether the separate key cache entries
1448          * are required to handle both tx+rx MIC keys.
1449          * With split mic keys the number of stations is limited
1450          * to 27 otherwise 59.
1451          */
1452         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1453                                    ATH9K_CIPHER_TKIP, NULL)
1454             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1455                                       ATH9K_CIPHER_MIC, NULL)
1456             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1457                                       0, NULL))
1458                 sc->sc_splitmic = 1;
1459
1460         /* turn on mcast key search if possible */
1461         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1462                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1463                                              1, NULL);
1464
1465         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1466         sc->sc_config.txpowlimit_override = 0;
1467
1468         /* 11n Capabilities */
1469         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1470                 sc->sc_flags |= SC_OP_TXAGGR;
1471                 sc->sc_flags |= SC_OP_RXAGGR;
1472         }
1473
1474         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1475         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1476
1477         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1478         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1479
1480         ath9k_hw_getmac(ah, sc->sc_myaddr);
1481         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1482                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1483                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1484                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1485         }
1486
1487         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1488
1489         /* initialize beacon slots */
1490         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1491                 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1492
1493         /* save MISC configurations */
1494         sc->sc_config.swBeaconProcess = 1;
1495
1496         /* setup channels and rates */
1497
1498         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1499         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1500                 sc->rates[IEEE80211_BAND_2GHZ];
1501         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1502         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1503                 ARRAY_SIZE(ath9k_2ghz_chantable);
1504
1505         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1506                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1507                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1508                         sc->rates[IEEE80211_BAND_5GHZ];
1509                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1510                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1511                         ARRAY_SIZE(ath9k_5ghz_chantable);
1512         }
1513
1514         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1515                 ath9k_hw_btcoex_enable(sc->sc_ah);
1516
1517         return 0;
1518 bad2:
1519         /* cleanup tx queues */
1520         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1521                 if (ATH_TXQ_SETUP(sc, i))
1522                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1523 bad:
1524         if (ah)
1525                 ath9k_hw_detach(ah);
1526
1527         return error;
1528 }
1529
1530 int ath_attach(u16 devid, struct ath_softc *sc)
1531 {
1532         struct ieee80211_hw *hw = sc->hw;
1533         int error = 0;
1534
1535         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1536
1537         error = ath_init(devid, sc);
1538         if (error != 0)
1539                 return error;
1540
1541         /* get mac address from hardware and set in mac80211 */
1542
1543         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1544
1545         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1546                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1547                 IEEE80211_HW_SIGNAL_DBM |
1548                 IEEE80211_HW_AMPDU_AGGREGATION |
1549                 IEEE80211_HW_SUPPORTS_PS |
1550                 IEEE80211_HW_PS_NULLFUNC_STACK;
1551
1552         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1553                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1554
1555         hw->wiphy->interface_modes =
1556                 BIT(NL80211_IFTYPE_AP) |
1557                 BIT(NL80211_IFTYPE_STATION) |
1558                 BIT(NL80211_IFTYPE_ADHOC);
1559
1560         hw->wiphy->reg_notifier = ath9k_reg_notifier;
1561         hw->wiphy->strict_regulatory = true;
1562
1563         hw->queues = 4;
1564         hw->max_rates = 4;
1565         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1566         hw->sta_data_size = sizeof(struct ath_node);
1567         hw->vif_data_size = sizeof(struct ath_vap);
1568
1569         hw->rate_control_algorithm = "ath9k_rate_control";
1570
1571         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1572                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1573                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1574                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1575         }
1576
1577         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1578         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1579                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1580                         &sc->sbands[IEEE80211_BAND_5GHZ];
1581
1582         /* initialize tx/rx engine */
1583         error = ath_tx_init(sc, ATH_TXBUF);
1584         if (error != 0)
1585                 goto detach;
1586
1587         error = ath_rx_init(sc, ATH_RXBUF);
1588         if (error != 0)
1589                 goto detach;
1590
1591 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1592         /* Initialze h/w Rfkill */
1593         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1594                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1595
1596         /* Initialize s/w rfkill */
1597         if (ath_init_sw_rfkill(sc))
1598                 goto detach;
1599 #endif
1600
1601         if (ath9k_is_world_regd(sc->sc_ah)) {
1602                 /* Anything applied here (prior to wiphy registratoin) gets
1603                  * saved on the wiphy orig_* parameters */
1604                 const struct ieee80211_regdomain *regd =
1605                         ath9k_world_regdomain(sc->sc_ah);
1606                 hw->wiphy->custom_regulatory = true;
1607                 hw->wiphy->strict_regulatory = false;
1608                 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1609                 ath9k_reg_apply_radar_flags(hw->wiphy);
1610                 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1611         } else {
1612                 /* This gets applied in the case of the absense of CRDA,
1613                  * its our own custom world regulatory domain, similar to
1614                  * cfg80211's but we enable passive scanning */
1615                 const struct ieee80211_regdomain *regd =
1616                         ath9k_default_world_regdomain();
1617                 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1618                 ath9k_reg_apply_radar_flags(hw->wiphy);
1619                 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1620         }
1621
1622         error = ieee80211_register_hw(hw);
1623
1624         if (!ath9k_is_world_regd(sc->sc_ah))
1625                 regulatory_hint(hw->wiphy, sc->sc_ah->alpha2);
1626
1627         /* Initialize LED control */
1628         ath_init_leds(sc);
1629
1630
1631         return 0;
1632 detach:
1633         ath_detach(sc);
1634         return error;
1635 }
1636
1637 int ath_reset(struct ath_softc *sc, bool retry_tx)
1638 {
1639         struct ath_hal *ah = sc->sc_ah;
1640         struct ieee80211_hw *hw = sc->hw;
1641         int r;
1642
1643         ath9k_hw_set_interrupts(ah, 0);
1644         ath_drain_all_txq(sc, retry_tx);
1645         ath_stoprecv(sc);
1646         ath_flushrecv(sc);
1647
1648         spin_lock_bh(&sc->sc_resetlock);
1649         r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1650         if (r)
1651                 DPRINTF(sc, ATH_DBG_FATAL,
1652                         "Unable to reset hardware; reset status %u\n", r);
1653         spin_unlock_bh(&sc->sc_resetlock);
1654
1655         if (ath_startrecv(sc) != 0)
1656                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1657
1658         /*
1659          * We may be doing a reset in response to a request
1660          * that changes the channel so update any state that
1661          * might change as a result.
1662          */
1663         ath_cache_conf_rate(sc, &hw->conf);
1664
1665         ath_update_txpow(sc);
1666
1667         if (sc->sc_flags & SC_OP_BEACONS)
1668                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1669
1670         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1671
1672         if (retry_tx) {
1673                 int i;
1674                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1675                         if (ATH_TXQ_SETUP(sc, i)) {
1676                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1677                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1678                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1679                         }
1680                 }
1681         }
1682
1683         return r;
1684 }
1685
1686 /*
1687  *  This function will allocate both the DMA descriptor structure, and the
1688  *  buffers it contains.  These are used to contain the descriptors used
1689  *  by the system.
1690 */
1691 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1692                       struct list_head *head, const char *name,
1693                       int nbuf, int ndesc)
1694 {
1695 #define DS2PHYS(_dd, _ds)                                               \
1696         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1697 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1698 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1699
1700         struct ath_desc *ds;
1701         struct ath_buf *bf;
1702         int i, bsize, error;
1703
1704         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1705                 name, nbuf, ndesc);
1706
1707         /* ath_desc must be a multiple of DWORDs */
1708         if ((sizeof(struct ath_desc) % 4) != 0) {
1709                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1710                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1711                 error = -ENOMEM;
1712                 goto fail;
1713         }
1714
1715         dd->dd_name = name;
1716         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1717
1718         /*
1719          * Need additional DMA memory because we can't use
1720          * descriptors that cross the 4K page boundary. Assume
1721          * one skipped descriptor per 4K page.
1722          */
1723         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1724                 u32 ndesc_skipped =
1725                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1726                 u32 dma_len;
1727
1728                 while (ndesc_skipped) {
1729                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1730                         dd->dd_desc_len += dma_len;
1731
1732                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1733                 };
1734         }
1735
1736         /* allocate descriptors */
1737         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1738                                          &dd->dd_desc_paddr, GFP_ATOMIC);
1739         if (dd->dd_desc == NULL) {
1740                 error = -ENOMEM;
1741                 goto fail;
1742         }
1743         ds = dd->dd_desc;
1744         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1745                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1746                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1747
1748         /* allocate buffers */
1749         bsize = sizeof(struct ath_buf) * nbuf;
1750         bf = kmalloc(bsize, GFP_KERNEL);
1751         if (bf == NULL) {
1752                 error = -ENOMEM;
1753                 goto fail2;
1754         }
1755         memset(bf, 0, bsize);
1756         dd->dd_bufptr = bf;
1757
1758         INIT_LIST_HEAD(head);
1759         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1760                 bf->bf_desc = ds;
1761                 bf->bf_daddr = DS2PHYS(dd, ds);
1762
1763                 if (!(sc->sc_ah->ah_caps.hw_caps &
1764                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1765                         /*
1766                          * Skip descriptor addresses which can cause 4KB
1767                          * boundary crossing (addr + length) with a 32 dword
1768                          * descriptor fetch.
1769                          */
1770                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1771                                 ASSERT((caddr_t) bf->bf_desc <
1772                                        ((caddr_t) dd->dd_desc +
1773                                         dd->dd_desc_len));
1774
1775                                 ds += ndesc;
1776                                 bf->bf_desc = ds;
1777                                 bf->bf_daddr = DS2PHYS(dd, ds);
1778                         }
1779                 }
1780                 list_add_tail(&bf->list, head);
1781         }
1782         return 0;
1783 fail2:
1784         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1785                           dd->dd_desc_paddr);
1786 fail:
1787         memset(dd, 0, sizeof(*dd));
1788         return error;
1789 #undef ATH_DESC_4KB_BOUND_CHECK
1790 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1791 #undef DS2PHYS
1792 }
1793
1794 void ath_descdma_cleanup(struct ath_softc *sc,
1795                          struct ath_descdma *dd,
1796                          struct list_head *head)
1797 {
1798         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1799                           dd->dd_desc_paddr);
1800
1801         INIT_LIST_HEAD(head);
1802         kfree(dd->dd_bufptr);
1803         memset(dd, 0, sizeof(*dd));
1804 }
1805
1806 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1807 {
1808         int qnum;
1809
1810         switch (queue) {
1811         case 0:
1812                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1813                 break;
1814         case 1:
1815                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1816                 break;
1817         case 2:
1818                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1819                 break;
1820         case 3:
1821                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1822                 break;
1823         default:
1824                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1825                 break;
1826         }
1827
1828         return qnum;
1829 }
1830
1831 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1832 {
1833         int qnum;
1834
1835         switch (queue) {
1836         case ATH9K_WME_AC_VO:
1837                 qnum = 0;
1838                 break;
1839         case ATH9K_WME_AC_VI:
1840                 qnum = 1;
1841                 break;
1842         case ATH9K_WME_AC_BE:
1843                 qnum = 2;
1844                 break;
1845         case ATH9K_WME_AC_BK:
1846                 qnum = 3;
1847                 break;
1848         default:
1849                 qnum = -1;
1850                 break;
1851         }
1852
1853         return qnum;
1854 }
1855
1856 /* XXX: Remove me once we don't depend on ath9k_channel for all
1857  * this redundant data */
1858 static void ath9k_update_ichannel(struct ath_softc *sc,
1859                           struct ath9k_channel *ichan)
1860 {
1861         struct ieee80211_hw *hw = sc->hw;
1862         struct ieee80211_channel *chan = hw->conf.channel;
1863         struct ieee80211_conf *conf = &hw->conf;
1864
1865         ichan->channel = chan->center_freq;
1866         ichan->chan = chan;
1867
1868         if (chan->band == IEEE80211_BAND_2GHZ) {
1869                 ichan->chanmode = CHANNEL_G;
1870                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1871         } else {
1872                 ichan->chanmode = CHANNEL_A;
1873                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1874         }
1875
1876         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1877
1878         if (conf_is_ht(conf)) {
1879                 if (conf_is_ht40(conf))
1880                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1881
1882                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1883                                             conf->channel_type);
1884         }
1885 }
1886
1887 /**********************/
1888 /* mac80211 callbacks */
1889 /**********************/
1890
1891 static int ath9k_start(struct ieee80211_hw *hw)
1892 {
1893         struct ath_softc *sc = hw->priv;
1894         struct ieee80211_channel *curchan = hw->conf.channel;
1895         struct ath9k_channel *init_channel;
1896         int r, pos;
1897
1898         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1899                 "initial channel: %d MHz\n", curchan->center_freq);
1900
1901         /* setup initial channel */
1902
1903         pos = curchan->hw_value;
1904
1905         init_channel = &sc->sc_ah->ah_channels[pos];
1906         ath9k_update_ichannel(sc, init_channel);
1907
1908         /* Reset SERDES registers */
1909         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1910
1911         /*
1912          * The basic interface to setting the hardware in a good
1913          * state is ``reset''.  On return the hardware is known to
1914          * be powered up and with interrupts disabled.  This must
1915          * be followed by initialization of the appropriate bits
1916          * and then setup of the interrupt mask.
1917          */
1918         spin_lock_bh(&sc->sc_resetlock);
1919         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1920         if (r) {
1921                 DPRINTF(sc, ATH_DBG_FATAL,
1922                         "Unable to reset hardware; reset status %u "
1923                         "(freq %u MHz)\n", r,
1924                         curchan->center_freq);
1925                 spin_unlock_bh(&sc->sc_resetlock);
1926                 return r;
1927         }
1928         spin_unlock_bh(&sc->sc_resetlock);
1929
1930         /*
1931          * This is needed only to setup initial state
1932          * but it's best done after a reset.
1933          */
1934         ath_update_txpow(sc);
1935
1936         /*
1937          * Setup the hardware after reset:
1938          * The receive engine is set going.
1939          * Frame transmit is handled entirely
1940          * in the frame output path; there's nothing to do
1941          * here except setup the interrupt mask.
1942          */
1943         if (ath_startrecv(sc) != 0) {
1944                 DPRINTF(sc, ATH_DBG_FATAL,
1945                         "Unable to start recv logic\n");
1946                 return -EIO;
1947         }
1948
1949         /* Setup our intr mask. */
1950         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1951                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1952                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1953
1954         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1955                 sc->sc_imask |= ATH9K_INT_GTT;
1956
1957         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1958                 sc->sc_imask |= ATH9K_INT_CST;
1959
1960         /*
1961          * Enable MIB interrupts when there are hardware phy counters.
1962          * Note we only do this (at the moment) for station mode.
1963          */
1964         if (ath9k_hw_phycounters(sc->sc_ah) &&
1965             ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1966              (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1967                 sc->sc_imask |= ATH9K_INT_MIB;
1968         /*
1969          * Some hardware processes the TIM IE and fires an
1970          * interrupt when the TIM bit is set.  For hardware
1971          * that does, if not overridden by configuration,
1972          * enable the TIM interrupt when operating as station.
1973          */
1974         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1975             (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1976             !sc->sc_config.swBeaconProcess)
1977                 sc->sc_imask |= ATH9K_INT_TIM;
1978
1979         ath_cache_conf_rate(sc, &hw->conf);
1980
1981         sc->sc_flags &= ~SC_OP_INVALID;
1982
1983         /* Disable BMISS interrupt when we're not associated */
1984         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1985         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1986
1987         ieee80211_wake_queues(sc->hw);
1988
1989 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1990         r = ath_start_rfkill_poll(sc);
1991 #endif
1992         return r;
1993 }
1994
1995 static int ath9k_tx(struct ieee80211_hw *hw,
1996                     struct sk_buff *skb)
1997 {
1998         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1999         struct ath_softc *sc = hw->priv;
2000         struct ath_tx_control txctl;
2001         int hdrlen, padsize;
2002
2003         memset(&txctl, 0, sizeof(struct ath_tx_control));
2004
2005         /*
2006          * As a temporary workaround, assign seq# here; this will likely need
2007          * to be cleaned up to work better with Beacon transmission and virtual
2008          * BSSes.
2009          */
2010         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2011                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2012                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2013                         sc->tx.seq_no += 0x10;
2014                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2015                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2016         }
2017
2018         /* Add the padding after the header if this is not already done */
2019         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2020         if (hdrlen & 3) {
2021                 padsize = hdrlen % 4;
2022                 if (skb_headroom(skb) < padsize)
2023                         return -1;
2024                 skb_push(skb, padsize);
2025                 memmove(skb->data, skb->data + padsize, hdrlen);
2026         }
2027
2028         /* Check if a tx queue is available */
2029
2030         txctl.txq = ath_test_get_txq(sc, skb);
2031         if (!txctl.txq)
2032                 goto exit;
2033
2034         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2035
2036         if (ath_tx_start(sc, skb, &txctl) != 0) {
2037                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2038                 goto exit;
2039         }
2040
2041         return 0;
2042 exit:
2043         dev_kfree_skb_any(skb);
2044         return 0;
2045 }
2046
2047 static void ath9k_stop(struct ieee80211_hw *hw)
2048 {
2049         struct ath_softc *sc = hw->priv;
2050
2051         if (sc->sc_flags & SC_OP_INVALID) {
2052                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2053                 return;
2054         }
2055
2056         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2057
2058         ieee80211_stop_queues(sc->hw);
2059
2060         /* make sure h/w will not generate any interrupt
2061          * before setting the invalid flag. */
2062         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2063
2064         if (!(sc->sc_flags & SC_OP_INVALID)) {
2065                 ath_drain_all_txq(sc, false);
2066                 ath_stoprecv(sc);
2067                 ath9k_hw_phy_disable(sc->sc_ah);
2068         } else
2069                 sc->rx.rxlink = NULL;
2070
2071 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2072         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2073                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2074 #endif
2075         /* disable HAL and put h/w to sleep */
2076         ath9k_hw_disable(sc->sc_ah);
2077         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2078
2079         sc->sc_flags |= SC_OP_INVALID;
2080
2081         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2082 }
2083
2084 static int ath9k_add_interface(struct ieee80211_hw *hw,
2085                                struct ieee80211_if_init_conf *conf)
2086 {
2087         struct ath_softc *sc = hw->priv;
2088         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2089         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2090
2091         /* Support only vap for now */
2092
2093         if (sc->sc_nvaps)
2094                 return -ENOBUFS;
2095
2096         switch (conf->type) {
2097         case NL80211_IFTYPE_STATION:
2098                 ic_opmode = NL80211_IFTYPE_STATION;
2099                 break;
2100         case NL80211_IFTYPE_ADHOC:
2101                 ic_opmode = NL80211_IFTYPE_ADHOC;
2102                 break;
2103         case NL80211_IFTYPE_AP:
2104                 ic_opmode = NL80211_IFTYPE_AP;
2105                 break;
2106         default:
2107                 DPRINTF(sc, ATH_DBG_FATAL,
2108                         "Interface type %d not yet supported\n", conf->type);
2109                 return -EOPNOTSUPP;
2110         }
2111
2112         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2113
2114         /* Set the VAP opmode */
2115         avp->av_opmode = ic_opmode;
2116         avp->av_bslot = -1;
2117
2118         if (ic_opmode == NL80211_IFTYPE_AP)
2119                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2120
2121         sc->sc_vaps[0] = conf->vif;
2122         sc->sc_nvaps++;
2123
2124         /* Set the device opmode */
2125         sc->sc_ah->ah_opmode = ic_opmode;
2126
2127         if (conf->type == NL80211_IFTYPE_AP) {
2128                 /* TODO: is this a suitable place to start ANI for AP mode? */
2129                 /* Start ANI */
2130                 mod_timer(&sc->sc_ani.timer,
2131                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2132         }
2133
2134         return 0;
2135 }
2136
2137 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2138                                    struct ieee80211_if_init_conf *conf)
2139 {
2140         struct ath_softc *sc = hw->priv;
2141         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2142
2143         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2144
2145         /* Stop ANI */
2146         del_timer_sync(&sc->sc_ani.timer);
2147
2148         /* Reclaim beacon resources */
2149         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2150             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2151                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2152                 ath_beacon_return(sc, avp);
2153         }
2154
2155         sc->sc_flags &= ~SC_OP_BEACONS;
2156
2157         sc->sc_vaps[0] = NULL;
2158         sc->sc_nvaps--;
2159 }
2160
2161 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2162 {
2163         struct ath_softc *sc = hw->priv;
2164         struct ieee80211_conf *conf = &hw->conf;
2165
2166         mutex_lock(&sc->mutex);
2167         if (changed & IEEE80211_CONF_CHANGE_PS) {
2168                 if (conf->flags & IEEE80211_CONF_PS) {
2169                         if ((sc->sc_imask & ATH9K_INT_TIM_TIMER) == 0) {
2170                                 sc->sc_imask |= ATH9K_INT_TIM_TIMER;
2171                                 ath9k_hw_set_interrupts(sc->sc_ah,
2172                                                 sc->sc_imask);
2173                         }
2174                         ath9k_hw_setrxabort(sc->sc_ah, 1);
2175                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2176                 } else {
2177                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2178                         ath9k_hw_setrxabort(sc->sc_ah, 0);
2179                         sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2180                         if (sc->sc_imask & ATH9K_INT_TIM_TIMER) {
2181                                 sc->sc_imask &= ~ATH9K_INT_TIM_TIMER;
2182                                 ath9k_hw_set_interrupts(sc->sc_ah,
2183                                                 sc->sc_imask);
2184                         }
2185                 }
2186         }
2187
2188         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2189                 struct ieee80211_channel *curchan = hw->conf.channel;
2190                 int pos = curchan->hw_value;
2191
2192                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2193                         curchan->center_freq);
2194
2195                 /* XXX: remove me eventualy */
2196                 ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]);
2197
2198                 ath_update_chainmask(sc, conf_is_ht(conf));
2199
2200                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2201                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2202                         mutex_unlock(&sc->mutex);
2203                         return -EINVAL;
2204                 }
2205         }
2206
2207         if (changed & IEEE80211_CONF_CHANGE_POWER)
2208                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2209
2210         mutex_unlock(&sc->mutex);
2211         return 0;
2212 }
2213
2214 static int ath9k_config_interface(struct ieee80211_hw *hw,
2215                                   struct ieee80211_vif *vif,
2216                                   struct ieee80211_if_conf *conf)
2217 {
2218         struct ath_softc *sc = hw->priv;
2219         struct ath_hal *ah = sc->sc_ah;
2220         struct ath_vap *avp = (void *)vif->drv_priv;
2221         u32 rfilt = 0;
2222         int error, i;
2223
2224         /* TODO: Need to decide which hw opmode to use for multi-interface
2225          * cases */
2226         if (vif->type == NL80211_IFTYPE_AP &&
2227             ah->ah_opmode != NL80211_IFTYPE_AP) {
2228                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2229                 ath9k_hw_setopmode(ah);
2230                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2231                 /* Request full reset to get hw opmode changed properly */
2232                 sc->sc_flags |= SC_OP_FULL_RESET;
2233         }
2234
2235         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2236             !is_zero_ether_addr(conf->bssid)) {
2237                 switch (vif->type) {
2238                 case NL80211_IFTYPE_STATION:
2239                 case NL80211_IFTYPE_ADHOC:
2240                         /* Set BSSID */
2241                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2242                         sc->sc_curaid = 0;
2243                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2244                                                sc->sc_curaid);
2245
2246                         /* Set aggregation protection mode parameters */
2247                         sc->sc_config.ath_aggr_prot = 0;
2248
2249                         DPRINTF(sc, ATH_DBG_CONFIG,
2250                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2251                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2252
2253                         /* need to reconfigure the beacon */
2254                         sc->sc_flags &= ~SC_OP_BEACONS ;
2255
2256                         break;
2257                 default:
2258                         break;
2259                 }
2260         }
2261
2262         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2263             (vif->type == NL80211_IFTYPE_AP)) {
2264                 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2265                     (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2266                      conf->enable_beacon)) {
2267                         /*
2268                          * Allocate and setup the beacon frame.
2269                          *
2270                          * Stop any previous beacon DMA.  This may be
2271                          * necessary, for example, when an ibss merge
2272                          * causes reconfiguration; we may be called
2273                          * with beacon transmission active.
2274                          */
2275                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2276
2277                         error = ath_beacon_alloc(sc, 0);
2278                         if (error != 0)
2279                                 return error;
2280
2281                         ath_beacon_sync(sc, 0);
2282                 }
2283         }
2284
2285         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2286         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2287                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2288                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2289                                 ath9k_hw_keysetmac(sc->sc_ah,
2290                                                    (u16)i,
2291                                                    sc->sc_curbssid);
2292         }
2293
2294         /* Only legacy IBSS for now */
2295         if (vif->type == NL80211_IFTYPE_ADHOC)
2296                 ath_update_chainmask(sc, 0);
2297
2298         return 0;
2299 }
2300
2301 #define SUPPORTED_FILTERS                       \
2302         (FIF_PROMISC_IN_BSS |                   \
2303         FIF_ALLMULTI |                          \
2304         FIF_CONTROL |                           \
2305         FIF_OTHER_BSS |                         \
2306         FIF_BCN_PRBRESP_PROMISC |               \
2307         FIF_FCSFAIL)
2308
2309 /* FIXME: sc->sc_full_reset ? */
2310 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2311                                    unsigned int changed_flags,
2312                                    unsigned int *total_flags,
2313                                    int mc_count,
2314                                    struct dev_mc_list *mclist)
2315 {
2316         struct ath_softc *sc = hw->priv;
2317         u32 rfilt;
2318
2319         changed_flags &= SUPPORTED_FILTERS;
2320         *total_flags &= SUPPORTED_FILTERS;
2321
2322         sc->rx.rxfilter = *total_flags;
2323         rfilt = ath_calcrxfilter(sc);
2324         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2325
2326         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2327                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2328                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2329         }
2330
2331         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2332 }
2333
2334 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2335                              struct ieee80211_vif *vif,
2336                              enum sta_notify_cmd cmd,
2337                              struct ieee80211_sta *sta)
2338 {
2339         struct ath_softc *sc = hw->priv;
2340
2341         switch (cmd) {
2342         case STA_NOTIFY_ADD:
2343                 ath_node_attach(sc, sta);
2344                 break;
2345         case STA_NOTIFY_REMOVE:
2346                 ath_node_detach(sc, sta);
2347                 break;
2348         default:
2349                 break;
2350         }
2351 }
2352
2353 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2354                          u16 queue,
2355                          const struct ieee80211_tx_queue_params *params)
2356 {
2357         struct ath_softc *sc = hw->priv;
2358         struct ath9k_tx_queue_info qi;
2359         int ret = 0, qnum;
2360
2361         if (queue >= WME_NUM_AC)
2362                 return 0;
2363
2364         qi.tqi_aifs = params->aifs;
2365         qi.tqi_cwmin = params->cw_min;
2366         qi.tqi_cwmax = params->cw_max;
2367         qi.tqi_burstTime = params->txop;
2368         qnum = ath_get_hal_qnum(queue, sc);
2369
2370         DPRINTF(sc, ATH_DBG_CONFIG,
2371                 "Configure tx [queue/halq] [%d/%d],  "
2372                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2373                 queue, qnum, params->aifs, params->cw_min,
2374                 params->cw_max, params->txop);
2375
2376         ret = ath_txq_update(sc, qnum, &qi);
2377         if (ret)
2378                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2379
2380         return ret;
2381 }
2382
2383 static int ath9k_set_key(struct ieee80211_hw *hw,
2384                          enum set_key_cmd cmd,
2385                          struct ieee80211_vif *vif,
2386                          struct ieee80211_sta *sta,
2387                          struct ieee80211_key_conf *key)
2388 {
2389         struct ath_softc *sc = hw->priv;
2390         int ret = 0;
2391
2392         ath9k_ps_wakeup(sc);
2393         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2394
2395         switch (cmd) {
2396         case SET_KEY:
2397                 ret = ath_key_config(sc, sta, key);
2398                 if (ret >= 0) {
2399                         key->hw_key_idx = ret;
2400                         /* push IV and Michael MIC generation to stack */
2401                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2402                         if (key->alg == ALG_TKIP)
2403                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2404                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2405                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2406                         ret = 0;
2407                 }
2408                 break;
2409         case DISABLE_KEY:
2410                 ath_key_delete(sc, key);
2411                 break;
2412         default:
2413                 ret = -EINVAL;
2414         }
2415
2416         ath9k_ps_restore(sc);
2417         return ret;
2418 }
2419
2420 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2421                                    struct ieee80211_vif *vif,
2422                                    struct ieee80211_bss_conf *bss_conf,
2423                                    u32 changed)
2424 {
2425         struct ath_softc *sc = hw->priv;
2426
2427         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2428                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2429                         bss_conf->use_short_preamble);
2430                 if (bss_conf->use_short_preamble)
2431                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2432                 else
2433                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2434         }
2435
2436         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2437                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2438                         bss_conf->use_cts_prot);
2439                 if (bss_conf->use_cts_prot &&
2440                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2441                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2442                 else
2443                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2444         }
2445
2446         if (changed & BSS_CHANGED_ASSOC) {
2447                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2448                         bss_conf->assoc);
2449                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2450         }
2451 }
2452
2453 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2454 {
2455         u64 tsf;
2456         struct ath_softc *sc = hw->priv;
2457         struct ath_hal *ah = sc->sc_ah;
2458
2459         tsf = ath9k_hw_gettsf64(ah);
2460
2461         return tsf;
2462 }
2463
2464 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2465 {
2466         struct ath_softc *sc = hw->priv;
2467         struct ath_hal *ah = sc->sc_ah;
2468
2469         ath9k_hw_settsf64(ah, tsf);
2470 }
2471
2472 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2473 {
2474         struct ath_softc *sc = hw->priv;
2475         struct ath_hal *ah = sc->sc_ah;
2476
2477         ath9k_hw_reset_tsf(ah);
2478 }
2479
2480 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2481                        enum ieee80211_ampdu_mlme_action action,
2482                        struct ieee80211_sta *sta,
2483                        u16 tid, u16 *ssn)
2484 {
2485         struct ath_softc *sc = hw->priv;
2486         int ret = 0;
2487
2488         switch (action) {
2489         case IEEE80211_AMPDU_RX_START:
2490                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2491                         ret = -ENOTSUPP;
2492                 break;
2493         case IEEE80211_AMPDU_RX_STOP:
2494                 break;
2495         case IEEE80211_AMPDU_TX_START:
2496                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2497                 if (ret < 0)
2498                         DPRINTF(sc, ATH_DBG_FATAL,
2499                                 "Unable to start TX aggregation\n");
2500                 else
2501                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2502                 break;
2503         case IEEE80211_AMPDU_TX_STOP:
2504                 ret = ath_tx_aggr_stop(sc, sta, tid);
2505                 if (ret < 0)
2506                         DPRINTF(sc, ATH_DBG_FATAL,
2507                                 "Unable to stop TX aggregation\n");
2508
2509                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2510                 break;
2511         case IEEE80211_AMPDU_TX_RESUME:
2512                 ath_tx_aggr_resume(sc, sta, tid);
2513                 break;
2514         default:
2515                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2516         }
2517
2518         return ret;
2519 }
2520
2521 struct ieee80211_ops ath9k_ops = {
2522         .tx                 = ath9k_tx,
2523         .start              = ath9k_start,
2524         .stop               = ath9k_stop,
2525         .add_interface      = ath9k_add_interface,
2526         .remove_interface   = ath9k_remove_interface,
2527         .config             = ath9k_config,
2528         .config_interface   = ath9k_config_interface,
2529         .configure_filter   = ath9k_configure_filter,
2530         .sta_notify         = ath9k_sta_notify,
2531         .conf_tx            = ath9k_conf_tx,
2532         .bss_info_changed   = ath9k_bss_info_changed,
2533         .set_key            = ath9k_set_key,
2534         .get_tsf            = ath9k_get_tsf,
2535         .set_tsf            = ath9k_set_tsf,
2536         .reset_tsf          = ath9k_reset_tsf,
2537         .ampdu_action       = ath9k_ampdu_action,
2538 };
2539
2540 static struct {
2541         u32 version;
2542         const char * name;
2543 } ath_mac_bb_names[] = {
2544         { AR_SREV_VERSION_5416_PCI,     "5416" },
2545         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2546         { AR_SREV_VERSION_9100,         "9100" },
2547         { AR_SREV_VERSION_9160,         "9160" },
2548         { AR_SREV_VERSION_9280,         "9280" },
2549         { AR_SREV_VERSION_9285,         "9285" }
2550 };
2551
2552 static struct {
2553         u16 version;
2554         const char * name;
2555 } ath_rf_names[] = {
2556         { 0,                            "5133" },
2557         { AR_RAD5133_SREV_MAJOR,        "5133" },
2558         { AR_RAD5122_SREV_MAJOR,        "5122" },
2559         { AR_RAD2133_SREV_MAJOR,        "2133" },
2560         { AR_RAD2122_SREV_MAJOR,        "2122" }
2561 };
2562
2563 /*
2564  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2565  */
2566 const char *
2567 ath_mac_bb_name(u32 mac_bb_version)
2568 {
2569         int i;
2570
2571         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2572                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2573                         return ath_mac_bb_names[i].name;
2574                 }
2575         }
2576
2577         return "????";
2578 }
2579
2580 /*
2581  * Return the RF name. "????" is returned if the RF is unknown.
2582  */
2583 const char *
2584 ath_rf_name(u16 rf_version)
2585 {
2586         int i;
2587
2588         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2589                 if (ath_rf_names[i].version == rf_version) {
2590                         return ath_rf_names[i].name;
2591                 }
2592         }
2593
2594         return "????";
2595 }
2596
2597 static int __init ath9k_init(void)
2598 {
2599         int error;
2600
2601         /* Register rate control algorithm */
2602         error = ath_rate_control_register();
2603         if (error != 0) {
2604                 printk(KERN_ERR
2605                         "ath9k: Unable to register rate control "
2606                         "algorithm: %d\n",
2607                         error);
2608                 goto err_out;
2609         }
2610
2611         error = ath_pci_init();
2612         if (error < 0) {
2613                 printk(KERN_ERR
2614                         "ath9k: No PCI devices found, driver not installed.\n");
2615                 error = -ENODEV;
2616                 goto err_rate_unregister;
2617         }
2618
2619         error = ath_ahb_init();
2620         if (error < 0) {
2621                 error = -ENODEV;
2622                 goto err_pci_exit;
2623         }
2624
2625         return 0;
2626
2627  err_pci_exit:
2628         ath_pci_exit();
2629
2630  err_rate_unregister:
2631         ath_rate_control_unregister();
2632  err_out:
2633         return error;
2634 }
2635 module_init(ath9k_init);
2636
2637 static void __exit ath9k_exit(void)
2638 {
2639         ath_ahb_exit();
2640         ath_pci_exit();
2641         ath_rate_control_unregister();
2642         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2643 }
2644 module_exit(ath9k_exit);