1 #ifndef __ARCH_ORION5X_MPP_H
2 #define __ARCH_ORION5X_MPP_H
4 enum orion5x_mpp_type {
11 * This MPP pin is used as a generic GPIO pin. Valid for
12 * MPPs 0-15 and device bus data pins 16-31. On 5182, also
13 * valid for MPPs 16-19.
18 * This MPP is used as PCIe_RST_OUTn pin. Valid for
24 * This MPP is used as PCI arbiter pin (REQn/GNTn).
25 * Valid for MPPs 0-7 only.
30 * This MPP is used as PCI_PMEn pin. Valid for MPP 2 only.
35 * This MPP is used as GigE half-duplex (COL, CRS) or GMII
36 * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin. Valid for
42 * This MPP is used as NAND REn/WEn pin. Valid for MPPs
43 * 4-7 and 12-17 only, and only on the 5181l/5182/5281.
48 * This MPP is used as a PCI clock output pin. Valid for
49 * MPPs 6-7 only, and only on the 5181l.
54 * This MPP is used as a SATA presence/activity LED.
55 * Valid for MPPs 4-7 and 12-15 only, and only on the 5182.
60 * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin.
61 * Valid for MPPs 16-19 only.
66 struct orion5x_mpp_mode {
68 enum orion5x_mpp_type type;
71 void orion5x_mpp_conf(struct orion5x_mpp_mode *mode);