Merge git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux-2.6-for-linus
[linux-2.6] / arch / powerpc / boot / dts / mpc8544ds.dts
1 /*
2  * MPC8544 DS Device Tree Source
3  *
4  * Copyright 2007 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 / {
13         model = "MPC8544DS";
14         compatible = "MPC8544DS", "MPC85xxDS";
15         #address-cells = <1>;
16         #size-cells = <1>;
17
18         cpus {
19                 #cpus = <1>;
20                 #address-cells = <1>;
21                 #size-cells = <0>;
22
23                 PowerPC,8544@0 {
24                         device_type = "cpu";
25                         reg = <0>;
26                         d-cache-line-size = <20>;       // 32 bytes
27                         i-cache-line-size = <20>;       // 32 bytes
28                         d-cache-size = <8000>;          // L1, 32K
29                         i-cache-size = <8000>;          // L1, 32K
30                         timebase-frequency = <0>;
31                         bus-frequency = <0>;
32                         clock-frequency = <0>;
33                 };
34         };
35
36         memory {
37                 device_type = "memory";
38                 reg = <00000000 00000000>;      // Filled by U-Boot
39         };
40
41         soc8544@e0000000 {
42                 #address-cells = <1>;
43                 #size-cells = <1>;
44                 device_type = "soc";
45
46                 ranges = <00000000 e0000000 00100000>;
47                 reg = <e0000000 00001000>;      // CCSRBAR 1M
48                 bus-frequency = <0>;            // Filled out by uboot.
49
50                 memory-controller@2000 {
51                         compatible = "fsl,8544-memory-controller";
52                         reg = <2000 1000>;
53                         interrupt-parent = <&mpic>;
54                         interrupts = <12 2>;
55                 };
56
57                 l2-cache-controller@20000 {
58                         compatible = "fsl,8544-l2-cache-controller";
59                         reg = <20000 1000>;
60                         cache-line-size = <20>; // 32 bytes
61                         cache-size = <40000>;   // L2, 256K
62                         interrupt-parent = <&mpic>;
63                         interrupts = <10 2>;
64                 };
65
66                 i2c@3000 {
67                         device_type = "i2c";
68                         compatible = "fsl-i2c";
69                         reg = <3000 100>;
70                         interrupts = <2b 2>;
71                         interrupt-parent = <&mpic>;
72                         dfsrr;
73                 };
74
75                 mdio@24520 {
76                         #address-cells = <1>;
77                         #size-cells = <0>;
78                         device_type = "mdio";
79                         compatible = "gianfar";
80                         reg = <24520 20>;
81                         phy0: ethernet-phy@0 {
82                                 interrupt-parent = <&mpic>;
83                                 interrupts = <a 1>;
84                                 reg = <0>;
85                                 device_type = "ethernet-phy";
86                         };
87                         phy1: ethernet-phy@1 {
88                                 interrupt-parent = <&mpic>;
89                                 interrupts = <a 1>;
90                                 reg = <1>;
91                                 device_type = "ethernet-phy";
92                         };
93                 };
94
95                 ethernet@24000 {
96                         #address-cells = <1>;
97                         #size-cells = <0>;
98                         device_type = "network";
99                         model = "TSEC";
100                         compatible = "gianfar";
101                         reg = <24000 1000>;
102                         local-mac-address = [ 00 00 00 00 00 00 ];
103                         interrupts = <1d 2 1e 2 22 2>;
104                         interrupt-parent = <&mpic>;
105                         phy-handle = <&phy0>;
106                         phy-connection-type = "rgmii-id";
107                 };
108
109                 ethernet@26000 {
110                         #address-cells = <1>;
111                         #size-cells = <0>;
112                         device_type = "network";
113                         model = "TSEC";
114                         compatible = "gianfar";
115                         reg = <26000 1000>;
116                         local-mac-address = [ 00 00 00 00 00 00 ];
117                         interrupts = <1f 2 20 2 21 2>;
118                         interrupt-parent = <&mpic>;
119                         phy-handle = <&phy1>;
120                         phy-connection-type = "rgmii-id";
121                 };
122
123                 serial@4500 {
124                         device_type = "serial";
125                         compatible = "ns16550";
126                         reg = <4500 100>;
127                         clock-frequency = <0>;
128                         interrupts = <2a 2>;
129                         interrupt-parent = <&mpic>;
130                 };
131
132                 serial@4600 {
133                         device_type = "serial";
134                         compatible = "ns16550";
135                         reg = <4600 100>;
136                         clock-frequency = <0>;
137                         interrupts = <2a 2>;
138                         interrupt-parent = <&mpic>;
139                 };
140
141                 global-utilities@e0000 {        //global utilities block
142                         compatible = "fsl,mpc8548-guts";
143                         reg = <e0000 1000>;
144                         fsl,has-rstcr;
145                 };
146
147                 mpic: pic@40000 {
148                         clock-frequency = <0>;
149                         interrupt-controller;
150                         #address-cells = <0>;
151                         #interrupt-cells = <2>;
152                         reg = <40000 40000>;
153                         compatible = "chrp,open-pic";
154                         device_type = "open-pic";
155                         big-endian;
156                 };
157         };
158
159         pci@e0008000 {
160                 compatible = "fsl,mpc8540-pci";
161                 device_type = "pci";
162                 interrupt-map-mask = <f800 0 0 7>;
163                 interrupt-map = <
164
165                         /* IDSEL 0x11 J17 Slot 1 */
166                         8800 0 0 1 &mpic 2 1
167                         8800 0 0 2 &mpic 3 1
168                         8800 0 0 3 &mpic 4 1
169                         8800 0 0 4 &mpic 1 1
170
171                         /* IDSEL 0x12 J16 Slot 2 */
172
173                         9000 0 0 1 &mpic 3 1
174                         9000 0 0 2 &mpic 4 1
175                         9000 0 0 3 &mpic 2 1
176                         9000 0 0 4 &mpic 1 1>;
177
178                 interrupt-parent = <&mpic>;
179                 interrupts = <18 2>;
180                 bus-range = <0 ff>;
181                 ranges = <02000000 0 c0000000 c0000000 0 20000000
182                           01000000 0 00000000 e1000000 0 00010000>;
183                 clock-frequency = <3f940aa>;
184                 #interrupt-cells = <1>;
185                 #size-cells = <2>;
186                 #address-cells = <3>;
187                 reg = <e0008000 1000>;
188         };
189
190         pcie@e0009000 {
191                 compatible = "fsl,mpc8548-pcie";
192                 device_type = "pci";
193                 #interrupt-cells = <1>;
194                 #size-cells = <2>;
195                 #address-cells = <3>;
196                 reg = <e0009000 1000>;
197                 bus-range = <0 ff>;
198                 ranges = <02000000 0 80000000 80000000 0 20000000
199                           01000000 0 00000000 e1010000 0 00010000>;
200                 clock-frequency = <1fca055>;
201                 interrupt-parent = <&mpic>;
202                 interrupts = <1a 2>;
203                 interrupt-map-mask = <f800 0 0 7>;
204                 interrupt-map = <
205                         /* IDSEL 0x0 */
206                         0000 0 0 1 &mpic 4 1
207                         0000 0 0 2 &mpic 5 1
208                         0000 0 0 3 &mpic 6 1
209                         0000 0 0 4 &mpic 7 1
210                         >;
211                 pcie@0 {
212                         reg = <0 0 0 0 0>;
213                         #size-cells = <2>;
214                         #address-cells = <3>;
215                         device_type = "pci";
216                         ranges = <02000000 0 80000000
217                                   02000000 0 80000000
218                                   0 20000000
219
220                                   01000000 0 00000000
221                                   01000000 0 00000000
222                                   0 00010000>;
223                 };
224         };
225
226         pcie@e000a000 {
227                 compatible = "fsl,mpc8548-pcie";
228                 device_type = "pci";
229                 #interrupt-cells = <1>;
230                 #size-cells = <2>;
231                 #address-cells = <3>;
232                 reg = <e000a000 1000>;
233                 bus-range = <0 ff>;
234                 ranges = <02000000 0 a0000000 a0000000 0 10000000
235                           01000000 0 00000000 e1020000 0 00010000>;
236                 clock-frequency = <1fca055>;
237                 interrupt-parent = <&mpic>;
238                 interrupts = <19 2>;
239                 interrupt-map-mask = <f800 0 0 7>;
240                 interrupt-map = <
241                         /* IDSEL 0x0 */
242                         0000 0 0 1 &mpic 0 1
243                         0000 0 0 2 &mpic 1 1
244                         0000 0 0 3 &mpic 2 1
245                         0000 0 0 4 &mpic 3 1
246                         >;
247                 pcie@0 {
248                         reg = <0 0 0 0 0>;
249                         #size-cells = <2>;
250                         #address-cells = <3>;
251                         device_type = "pci";
252                         ranges = <02000000 0 a0000000
253                                   02000000 0 a0000000
254                                   0 10000000
255
256                                   01000000 0 00000000
257                                   01000000 0 00000000
258                                   0 00010000>;
259                 };
260         };
261
262         pcie@e000b000 {
263                 compatible = "fsl,mpc8548-pcie";
264                 device_type = "pci";
265                 #interrupt-cells = <1>;
266                 #size-cells = <2>;
267                 #address-cells = <3>;
268                 reg = <e000b000 1000>;
269                 bus-range = <0 ff>;
270                 ranges = <02000000 0 b0000000 b0000000 0 00100000
271                           01000000 0 00000000 b0100000 0 00100000>;
272                 clock-frequency = <1fca055>;
273                 interrupt-parent = <&mpic>;
274                 interrupts = <1b 2>;
275                 interrupt-map-mask = <ff00 0 0 1>;
276                 interrupt-map = <
277                         // IDSEL 0x1c  USB
278                         e000 0 0 1 &i8259 c 2
279                         e100 0 0 1 &i8259 9 2
280                         e200 0 0 1 &i8259 a 2
281                         e300 0 0 1 &i8259 b 2
282
283                         // IDSEL 0x1d  Audio
284                         e800 0 0 1 &i8259 6 2
285
286                         // IDSEL 0x1e Legacy
287                         f000 0 0 1 &i8259 7 2
288                         f100 0 0 1 &i8259 7 2
289
290                         // IDSEL 0x1f IDE/SATA
291                         f800 0 0 1 &i8259 e 2
292                         f900 0 0 1 &i8259 5 2
293                 >;
294
295                 pcie@0 {
296                         reg = <0 0 0 0 0>;
297                         #size-cells = <2>;
298                         #address-cells = <3>;
299                         device_type = "pci";
300                         ranges = <02000000 0 b0000000
301                                   02000000 0 b0000000
302                                   0 00100000
303
304                                   01000000 0 00000000
305                                   01000000 0 00000000
306                                   0 00100000>;
307
308                         uli1575@0 {
309                                 reg = <0 0 0 0 0>;
310                                 #size-cells = <2>;
311                                 #address-cells = <3>;
312                                 ranges = <02000000 0 b0000000
313                                           02000000 0 b0000000
314                                           0 00100000
315
316                                           01000000 0 00000000
317                                           01000000 0 00000000
318                                           0 00100000>;
319                                 isa@1e {
320                                         device_type = "isa";
321                                         #interrupt-cells = <2>;
322                                         #size-cells = <1>;
323                                         #address-cells = <2>;
324                                         reg = <f000 0 0 0 0>;
325                                         ranges = <1 0
326                                                   01000000 0 0
327                                                   00001000>;
328                                         interrupt-parent = <&i8259>;
329
330                                         i8259: interrupt-controller@20 {
331                                                 reg = <1 20 2
332                                                        1 a0 2
333                                                        1 4d0 2>;
334                                                 interrupt-controller;
335                                                 device_type = "interrupt-controller";
336                                                 #address-cells = <0>;
337                                                 #interrupt-cells = <2>;
338                                                 compatible = "chrp,iic";
339                                                 interrupts = <9 2>;
340                                                 interrupt-parent = <&mpic>;
341                                         };
342
343                                         i8042@60 {
344                                                 #size-cells = <0>;
345                                                 #address-cells = <1>;
346                                                 reg = <1 60 1 1 64 1>;
347                                                 interrupts = <1 3 c 3>;
348                                                 interrupt-parent = <&i8259>;
349
350                                                 keyboard@0 {
351                                                         reg = <0>;
352                                                         compatible = "pnpPNP,303";
353                                                 };
354
355                                                 mouse@1 {
356                                                         reg = <1>;
357                                                         compatible = "pnpPNP,f03";
358                                                 };
359                                         };
360
361                                         rtc@70 {
362                                                 compatible = "pnpPNP,b00";
363                                                 reg = <1 70 2>;
364                                         };
365
366                                         gpio@400 {
367                                                 reg = <1 400 80>;
368                                         };
369                                 };
370                         };
371                 };
372
373         };
374 };