git.oblomov.eu Git - linux-2.6/blob - drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #undef  DEBUG
  25 #undef  VERBOSE
  26
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/ioport.h>
  30 #include <linux/types.h>
  31 #include <linux/errno.h>
  32 #include <linux/delay.h>
  33 #include <linux/slab.h>
  34 #include <linux/init.h>
  35 #include <linux/timer.h>
  36 #include <linux/list.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/proc_fs.h>
  39 #include <linux/mm.h>
  40 #include <linux/moduleparam.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/usb/ch9.h>
  43 #include <linux/usb/gadget.h>
  44 #include <linux/usb/otg.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/clk.h>
  47
  48 #include <asm/byteorder.h>
  49 #include <asm/io.h>
  50 #include <asm/irq.h>
  51 #include <asm/system.h>
  52 #include <asm/unaligned.h>
  53 #include <asm/mach-types.h>
  54
  55 #include <asm/arch/dma.h>
  56 #include <asm/arch/usb.h>
  57
  58 #include "omap_udc.h"
  59
  60 #undef  USB_TRACE
  61
  62 /* bulk DMA seems to be behaving for both IN and OUT */
  63 #define USE_DMA
  64
  65 /* ISO too */
  66 #define USE_ISO
  67
  68 #define DRIVER_DESC     "OMAP UDC driver"
  69 #define DRIVER_VERSION  "4 October 2004"
  70
  71 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  72
  73 #define OMAP2_DMA_CH(ch)        (((ch) - 1) << 1)
  74 #define OMAP24XX_DMA(name, ch)  (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
  75
  76 /*
  77  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  78  * D+ pullup to allow enumeration.  That's too early for the gadget
  79  * framework to use from usb_endpoint_enable(), which happens after
  80  * enumeration as part of activating an interface.  (But if we add an
  81  * optional new "UDC not yet running" state to the gadget driver model,
  82  * even just during driver binding, the endpoint autoconfig logic is the
  83  * natural spot to manufacture new endpoints.)
  84  *
  85  * So instead of using endpoint enable calls to control the hardware setup,
  86  * this driver defines a "fifo mode" parameter.  It's used during driver
  87  * initialization to choose among a set of pre-defined endpoint configs.
  88  * See omap_udc_setup() for available modes, or to add others.  That code
  89  * lives in an init section, so use this driver as a module if you need
  90  * to change the fifo mode after the kernel boots.
  91  *
  92  * Gadget drivers normally ignore endpoints they don't care about, and
  93  * won't include them in configuration descriptors.  That means only
  94  * misbehaving hosts would even notice they exist.
  95  */
  96 #ifdef  USE_ISO
  97 static unsigned fifo_mode = 3;
  98 #else
  99 static unsigned fifo_mode = 0;
 100 #endif
 101
 102 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 103  * boot parameter "omap_udc:fifo_mode=42"
 104  */
 105 module_param (fifo_mode, uint, 0);
 106 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
 107
 108 #ifdef  USE_DMA
 109 static unsigned use_dma = 1;
 110
 111 /* "modprobe omap_udc use_dma=y", or else as a kernel
 112  * boot parameter "omap_udc:use_dma=y"
 113  */
 114 module_param (use_dma, bool, 0);
 115 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 116 #else   /* !USE_DMA */
 117
 118 /* save a bit of code */
 119 #define use_dma         0
 120 #endif  /* !USE_DMA */
 121
 122
 123 static const char driver_name [] = "omap_udc";
 124 static const char driver_desc [] = DRIVER_DESC;
 125
 126 /*-------------------------------------------------------------------------*/
 127
 128 /* there's a notion of "current endpoint" for modifying endpoint
 129  * state, and PIO access to its FIFO.
 130  */
 131
 132 static void use_ep(struct omap_ep *ep, u16 select)
 133 {
 134         u16     num = ep->bEndpointAddress & 0x0f;
 135
 136         if (ep->bEndpointAddress & USB_DIR_IN)
 137                 num |= UDC_EP_DIR;
 138         UDC_EP_NUM_REG = num | select;
 139         /* when select, MUST deselect later !! */
 140 }
 141
 142 static inline void deselect_ep(void)
 143 {
 144         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
 145         /* 6 wait states before TX will happen */
 146 }
 147
 148 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 149
 150 /*-------------------------------------------------------------------------*/
 151
 152 static int omap_ep_enable(struct usb_ep *_ep,
 153                 const struct usb_endpoint_descriptor *desc)
 154 {
 155         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 156         struct omap_udc *udc;
 157         unsigned long   flags;
 158         u16             maxp;
 159
 160         /* catch various bogus parameters */
 161         if (!_ep || !desc || ep->desc
 162                         || desc->bDescriptorType != USB_DT_ENDPOINT
 163                         || ep->bEndpointAddress != desc->bEndpointAddress
 164                         || ep->maxpacket < le16_to_cpu
 165                                                 (desc->wMaxPacketSize)) {
 166                 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
 167                 return -EINVAL;
 168         }
 169         maxp = le16_to_cpu (desc->wMaxPacketSize);
 170         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 171                                 && maxp != ep->maxpacket)
 172                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 173                         || !desc->wMaxPacketSize) {
 174                 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 175                 return -ERANGE;
 176         }
 177
 178 #ifdef  USE_ISO
 179         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 180                                 && desc->bInterval != 1)) {
 181                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 182                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 183                                 1 << (desc->bInterval - 1));
 184                 return -EDOM;
 185         }
 186 #else
 187         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 188                 DBG("%s, ISO nyet\n", _ep->name);
 189                 return -EDOM;
 190         }
 191 #endif
 192
 193         /* xfer types must match, except that interrupt ~= bulk */
 194         if (ep->bmAttributes != desc->bmAttributes
 195                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 196                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 197                 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 198                 return -EINVAL;
 199         }
 200
 201         udc = ep->udc;
 202         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 203                 DBG("%s, bogus device state\n", __FUNCTION__);
 204                 return -ESHUTDOWN;
 205         }
 206
 207         spin_lock_irqsave(&udc->lock, flags);
 208
 209         ep->desc = desc;
 210         ep->irqs = 0;
 211         ep->stopped = 0;
 212         ep->ep.maxpacket = maxp;
 213
 214         /* set endpoint to initial state */
 215         ep->dma_channel = 0;
 216         ep->has_dma = 0;
 217         ep->lch = -1;
 218         use_ep(ep, UDC_EP_SEL);
 219         UDC_CTRL_REG = udc->clr_halt;
 220         ep->ackwait = 0;
 221         deselect_ep();
 222
 223         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 224                 list_add(&ep->iso, &udc->iso);
 225
 226         /* maybe assign a DMA channel to this endpoint */
 227         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 228                 /* FIXME ISO can dma, but prefers first channel */
 229                 dma_channel_claim(ep, 0);
 230
 231         /* PIO OUT may RX packets */
 232         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 233                         && !ep->has_dma
 234                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 235                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 236                 ep->ackwait = 1 + ep->double_buf;
 237         }
 238
 239         spin_unlock_irqrestore(&udc->lock, flags);
 240         VDBG("%s enabled\n", _ep->name);
 241         return 0;
 242 }
 243
 244 static void nuke(struct omap_ep *, int status);
 245
 246 static int omap_ep_disable(struct usb_ep *_ep)
 247 {
 248         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 249         unsigned long   flags;
 250
 251         if (!_ep || !ep->desc) {
 252                 DBG("%s, %s not enabled\n", __FUNCTION__,
 253                         _ep ? ep->ep.name : NULL);
 254                 return -EINVAL;
 255         }
 256
 257         spin_lock_irqsave(&ep->udc->lock, flags);
 258         ep->desc = NULL;
 259         nuke (ep, -ESHUTDOWN);
 260         ep->ep.maxpacket = ep->maxpacket;
 261         ep->has_dma = 0;
 262         UDC_CTRL_REG = UDC_SET_HALT;
 263         list_del_init(&ep->iso);
 264         del_timer(&ep->timer);
 265
 266         spin_unlock_irqrestore(&ep->udc->lock, flags);
 267
 268         VDBG("%s disabled\n", _ep->name);
 269         return 0;
 270 }
 271
 272 /*-------------------------------------------------------------------------*/
 273
 274 static struct usb_request *
 275 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 276 {
 277         struct omap_req *req;
 278
 279         req = kzalloc(sizeof(*req), gfp_flags);
 280         if (req) {
 281                 req->req.dma = DMA_ADDR_INVALID;
 282                 INIT_LIST_HEAD (&req->queue);
 283         }
 284         return &req->req;
 285 }
 286
 287 static void
 288 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 289 {
 290         struct omap_req *req = container_of(_req, struct omap_req, req);
 291
 292         if (_req)
 293                 kfree (req);
 294 }
 295
 296 /*-------------------------------------------------------------------------*/
 297
 298 static void
 299 done(struct omap_ep *ep, struct omap_req *req, int status)
 300 {
 301         unsigned                stopped = ep->stopped;
 302
 303         list_del_init(&req->queue);
 304
 305         if (req->req.status == -EINPROGRESS)
 306                 req->req.status = status;
 307         else
 308                 status = req->req.status;
 309
 310         if (use_dma && ep->has_dma) {
 311                 if (req->mapped) {
 312                         dma_unmap_single(ep->udc->gadget.dev.parent,
 313                                 req->req.dma, req->req.length,
 314                                 (ep->bEndpointAddress & USB_DIR_IN)
 315                                         ? DMA_TO_DEVICE
 316                                         : DMA_FROM_DEVICE);
 317                         req->req.dma = DMA_ADDR_INVALID;
 318                         req->mapped = 0;
 319                 } else
 320                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 321                                 req->req.dma, req->req.length,
 322                                 (ep->bEndpointAddress & USB_DIR_IN)
 323                                         ? DMA_TO_DEVICE
 324                                         : DMA_FROM_DEVICE);
 325         }
 326
 327 #ifndef USB_TRACE
 328         if (status && status != -ESHUTDOWN)
 329 #endif
 330                 VDBG("complete %s req %p stat %d len %u/%u\n",
 331                         ep->ep.name, &req->req, status,
 332                         req->req.actual, req->req.length);
 333
 334         /* don't modify queue heads during completion callback */
 335         ep->stopped = 1;
 336         spin_unlock(&ep->udc->lock);
 337         req->req.complete(&ep->ep, &req->req);
 338         spin_lock(&ep->udc->lock);
 339         ep->stopped = stopped;
 340 }
 341
 342 /*-------------------------------------------------------------------------*/
 343
 344 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 345 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 346
 347 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 348 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 349
 350 static inline int
 351 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 352 {
 353         unsigned        len;
 354         u16             *wp;
 355
 356         len = min(req->req.length - req->req.actual, max);
 357         req->req.actual += len;
 358
 359         max = len;
 360         if (likely((((int)buf) & 1) == 0)) {
 361                 wp = (u16 *)buf;
 362                 while (max >= 2) {
 363                         UDC_DATA_REG = *wp++;
 364                         max -= 2;
 365                 }
 366                 buf = (u8 *)wp;
 367         }
 368         while (max--)
 369                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
 370         return len;
 371 }
 372
 373 // FIXME change r/w fifo calling convention
 374
 375
 376 // return:  0 = still running, 1 = completed, negative = errno
 377 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 378 {
 379         u8              *buf;
 380         unsigned        count;
 381         int             is_last;
 382         u16             ep_stat;
 383
 384         buf = req->req.buf + req->req.actual;
 385         prefetch(buf);
 386
 387         /* PIO-IN isn't double buffered except for iso */
 388         ep_stat = UDC_STAT_FLG_REG;
 389         if (ep_stat & UDC_FIFO_UNWRITABLE)
 390                 return 0;
 391
 392         count = ep->ep.maxpacket;
 393         count = write_packet(buf, req, count);
 394         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 395         ep->ackwait = 1;
 396
 397         /* last packet is often short (sometimes a zlp) */
 398         if (count != ep->ep.maxpacket)
 399                 is_last = 1;
 400         else if (req->req.length == req->req.actual
 401                         && !req->req.zero)
 402                 is_last = 1;
 403         else
 404                 is_last = 0;
 405
 406         /* NOTE:  requests complete when all IN data is in a
 407          * FIFO (or sometimes later, if a zlp was needed).
 408          * Use usb_ep_fifo_status() where needed.
 409          */
 410         if (is_last)
 411                 done(ep, req, 0);
 412         return is_last;
 413 }
 414
 415 static inline int
 416 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 417 {
 418         unsigned        len;
 419         u16             *wp;
 420
 421         len = min(req->req.length - req->req.actual, avail);
 422         req->req.actual += len;
 423         avail = len;
 424
 425         if (likely((((int)buf) & 1) == 0)) {
 426                 wp = (u16 *)buf;
 427                 while (avail >= 2) {
 428                         *wp++ = UDC_DATA_REG;
 429                         avail -= 2;
 430                 }
 431                 buf = (u8 *)wp;
 432         }
 433         while (avail--)
 434                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
 435         return len;
 436 }
 437
 438 // return:  0 = still running, 1 = queue empty, negative = errno
 439 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 440 {
 441         u8              *buf;
 442         unsigned        count, avail;
 443         int             is_last;
 444
 445         buf = req->req.buf + req->req.actual;
 446         prefetchw(buf);
 447
 448         for (;;) {
 449                 u16     ep_stat = UDC_STAT_FLG_REG;
 450
 451                 is_last = 0;
 452                 if (ep_stat & FIFO_EMPTY) {
 453                         if (!ep->double_buf)
 454                                 break;
 455                         ep->fnf = 1;
 456                 }
 457                 if (ep_stat & UDC_EP_HALTED)
 458                         break;
 459
 460                 if (ep_stat & UDC_FIFO_FULL)
 461                         avail = ep->ep.maxpacket;
 462                 else  {
 463                         avail = UDC_RXFSTAT_REG;
 464                         ep->fnf = ep->double_buf;
 465                 }
 466                 count = read_packet(buf, req, avail);
 467
 468                 /* partial packet reads may not be errors */
 469                 if (count < ep->ep.maxpacket) {
 470                         is_last = 1;
 471                         /* overflowed this request?  flush extra data */
 472                         if (count != avail) {
 473                                 req->req.status = -EOVERFLOW;
 474                                 avail -= count;
 475                                 while (avail--)
 476                                         (void) *(volatile u8 *)&UDC_DATA_REG;
 477                         }
 478                 } else if (req->req.length == req->req.actual)
 479                         is_last = 1;
 480                 else
 481                         is_last = 0;
 482
 483                 if (!ep->bEndpointAddress)
 484                         break;
 485                 if (is_last)
 486                         done(ep, req, 0);
 487                 break;
 488         }
 489         return is_last;
 490 }
 491
 492 /*-------------------------------------------------------------------------*/
 493
 494 static inline dma_addr_t dma_csac(unsigned lch)
 495 {
 496         dma_addr_t      csac;
 497
 498         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 499          * read before the DMA controller finished disabling the channel.
 500          */
 501         csac = OMAP_DMA_CSAC_REG(lch);
 502         if (csac == 0)
 503                 csac = OMAP_DMA_CSAC_REG(lch);
 504         return csac;
 505 }
 506
 507 static inline dma_addr_t dma_cdac(unsigned lch)
 508 {
 509         dma_addr_t      cdac;
 510
 511         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 512          * read before the DMA controller finished disabling the channel.
 513          */
 514         cdac = OMAP_DMA_CDAC_REG(lch);
 515         if (cdac == 0)
 516                 cdac = OMAP_DMA_CDAC_REG(lch);
 517         return cdac;
 518 }
 519
 520 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 521 {
 522         dma_addr_t      end;
 523
 524         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 525          * the last transfer's bytecount by more than a FIFO's worth.
 526          */
 527         if (cpu_is_omap15xx())
 528                 return 0;
 529
 530         end = dma_csac(ep->lch);
 531         if (end == ep->dma_counter)
 532                 return 0;
 533
 534         end |= start & (0xffff << 16);
 535         if (end < start)
 536                 end += 0x10000;
 537         return end - start;
 538 }
 539
 540 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
 541                 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
 542                 : dma_cdac(x))
 543
 544 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 545 {
 546         dma_addr_t      end;
 547
 548         end = DMA_DEST_LAST(ep->lch);
 549         if (end == ep->dma_counter)
 550                 return 0;
 551
 552         end |= start & (0xffff << 16);
 553         if (cpu_is_omap15xx())
 554                 end++;
 555         if (end < start)
 556                 end += 0x10000;
 557         return end - start;
 558 }
 559
 560
 561 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 562  * When DMA completion isn't request completion, the UDC continues with
 563  * the next DMA transfer for that USB transfer.
 564  */
 565
 566 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 567 {
 568         u16             txdma_ctrl;
 569         unsigned        length = req->req.length - req->req.actual;
 570         const int       sync_mode = cpu_is_omap15xx()
 571                                 ? OMAP_DMA_SYNC_FRAME
 572                                 : OMAP_DMA_SYNC_ELEMENT;
 573         int             dma_trigger = 0;
 574
 575         if (cpu_is_omap24xx())
 576                 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
 577
 578         /* measure length in either bytes or packets */
 579         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 580                         || (cpu_is_omap24xx() && length < ep->maxpacket)
 581                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 582                 txdma_ctrl = UDC_TXN_EOT | length;
 583                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 584                                 length, 1, sync_mode, dma_trigger, 0);
 585         } else {
 586                 length = min(length / ep->maxpacket,
 587                                 (unsigned) UDC_TXN_TSC + 1);
 588                 txdma_ctrl = length;
 589                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 590                                 ep->ep.maxpacket >> 1, length, sync_mode,
 591                                 dma_trigger, 0);
 592                 length *= ep->maxpacket;
 593         }
 594         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 595                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 596                 0, 0);
 597
 598         omap_start_dma(ep->lch);
 599         ep->dma_counter = dma_csac(ep->lch);
 600         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
 601         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
 602         req->dma_bytes = length;
 603 }
 604
 605 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 606 {
 607         if (status == 0) {
 608                 req->req.actual += req->dma_bytes;
 609
 610                 /* return if this request needs to send data or zlp */
 611                 if (req->req.actual < req->req.length)
 612                         return;
 613                 if (req->req.zero
 614                                 && req->dma_bytes != 0
 615                                 && (req->req.actual % ep->maxpacket) == 0)
 616                         return;
 617         } else
 618                 req->req.actual += dma_src_len(ep, req->req.dma
 619                                                         + req->req.actual);
 620
 621         /* tx completion */
 622         omap_stop_dma(ep->lch);
 623         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
 624         done(ep, req, status);
 625 }
 626
 627 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 628 {
 629         unsigned packets = req->req.length - req->req.actual;
 630         int dma_trigger = 0;
 631
 632         if (cpu_is_omap24xx())
 633                 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
 634
 635         /* NOTE:  we filtered out "short reads" before, so we know
 636          * the buffer has only whole numbers of packets.
 637          * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
 638          */
 639         if (cpu_is_omap24xx() && packets < ep->maxpacket) {
 640                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 641                                 packets, 1, OMAP_DMA_SYNC_ELEMENT,
 642                                 dma_trigger, 0);
 643                 req->dma_bytes = packets;
 644         } else {
 645                 /* set up this DMA transfer, enable the fifo, start */
 646                 packets /= ep->ep.maxpacket;
 647                 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 648                 req->dma_bytes = packets * ep->ep.maxpacket;
 649                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 650                                 ep->ep.maxpacket >> 1, packets,
 651                                 OMAP_DMA_SYNC_ELEMENT,
 652                                 dma_trigger, 0);
 653         }
 654         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 655                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 656                 0, 0);
 657         ep->dma_counter = DMA_DEST_LAST(ep->lch);
 658
 659         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
 660         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
 661         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
 662         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 663
 664         omap_start_dma(ep->lch);
 665 }
 666
 667 static void
 668 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 669 {
 670         u16     count;
 671
 672         if (status == 0)
 673                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 674         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 675         count += req->req.actual;
 676         if (one)
 677                 count--;
 678         if (count <= req->req.length)
 679                 req->req.actual = count;
 680
 681         if (count != req->dma_bytes || status)
 682                 omap_stop_dma(ep->lch);
 683
 684         /* if this wasn't short, request may need another transfer */
 685         else if (req->req.actual < req->req.length)
 686                 return;
 687
 688         /* rx completion */
 689         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
 690         done(ep, req, status);
 691 }
 692
 693 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 694 {
 695         u16             dman_stat = UDC_DMAN_STAT_REG;
 696         struct omap_ep  *ep;
 697         struct omap_req *req;
 698
 699         /* IN dma: tx to host */
 700         if (irq_src & UDC_TXN_DONE) {
 701                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 702                 ep->irqs++;
 703                 /* can see TXN_DONE after dma abort */
 704                 if (!list_empty(&ep->queue)) {
 705                         req = container_of(ep->queue.next,
 706                                                 struct omap_req, queue);
 707                         finish_in_dma(ep, req, 0);
 708                 }
 709                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
 710
 711                 if (!list_empty (&ep->queue)) {
 712                         req = container_of(ep->queue.next,
 713                                         struct omap_req, queue);
 714                         next_in_dma(ep, req);
 715                 }
 716         }
 717
 718         /* OUT dma: rx from host */
 719         if (irq_src & UDC_RXN_EOT) {
 720                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 721                 ep->irqs++;
 722                 /* can see RXN_EOT after dma abort */
 723                 if (!list_empty(&ep->queue)) {
 724                         req = container_of(ep->queue.next,
 725                                         struct omap_req, queue);
 726                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 727                 }
 728                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
 729
 730                 if (!list_empty (&ep->queue)) {
 731                         req = container_of(ep->queue.next,
 732                                         struct omap_req, queue);
 733                         next_out_dma(ep, req);
 734                 }
 735         }
 736
 737         if (irq_src & UDC_RXN_CNT) {
 738                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 739                 ep->irqs++;
 740                 /* omap15xx does this unasked... */
 741                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 742                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
 743         }
 744 }
 745
 746 static void dma_error(int lch, u16 ch_status, void *data)
 747 {
 748         struct omap_ep  *ep = data;
 749
 750         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 751         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 752         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 753
 754         /* complete current transfer ... */
 755 }
 756
 757 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 758 {
 759         u16     reg;
 760         int     status, restart, is_in;
 761         int     dma_channel;
 762
 763         is_in = ep->bEndpointAddress & USB_DIR_IN;
 764         if (is_in)
 765                 reg = UDC_TXDMA_CFG_REG;
 766         else
 767                 reg = UDC_RXDMA_CFG_REG;
 768         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 769
 770         ep->dma_channel = 0;
 771         ep->lch = -1;
 772         if (channel == 0 || channel > 3) {
 773                 if ((reg & 0x0f00) == 0)
 774                         channel = 3;
 775                 else if ((reg & 0x00f0) == 0)
 776                         channel = 2;
 777                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 778                         channel = 1;
 779                 else {
 780                         status = -EMLINK;
 781                         goto just_restart;
 782                 }
 783         }
 784         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 785         ep->dma_channel = channel;
 786
 787         if (is_in) {
 788                 if (cpu_is_omap24xx())
 789                         dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
 790                 else
 791                         dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
 792                 status = omap_request_dma(dma_channel,
 793                         ep->ep.name, dma_error, ep, &ep->lch);
 794                 if (status == 0) {
 795                         UDC_TXDMA_CFG_REG = reg;
 796                         /* EMIFF or SDRC */
 797                         omap_set_dma_src_burst_mode(ep->lch,
 798                                                 OMAP_DMA_DATA_BURST_4);
 799                         omap_set_dma_src_data_pack(ep->lch, 1);
 800                         /* TIPB */
 801                         omap_set_dma_dest_params(ep->lch,
 802                                 OMAP_DMA_PORT_TIPB,
 803                                 OMAP_DMA_AMODE_CONSTANT,
 804                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 805                                 0, 0);
 806                 }
 807         } else {
 808                 if (cpu_is_omap24xx())
 809                         dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
 810                 else
 811                         dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
 812
 813                 status = omap_request_dma(dma_channel,
 814                         ep->ep.name, dma_error, ep, &ep->lch);
 815                 if (status == 0) {
 816                         UDC_RXDMA_CFG_REG = reg;
 817                         /* TIPB */
 818                         omap_set_dma_src_params(ep->lch,
 819                                 OMAP_DMA_PORT_TIPB,
 820                                 OMAP_DMA_AMODE_CONSTANT,
 821                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 822                                 0, 0);
 823                         /* EMIFF or SDRC */
 824                         omap_set_dma_dest_burst_mode(ep->lch,
 825                                                 OMAP_DMA_DATA_BURST_4);
 826                         omap_set_dma_dest_data_pack(ep->lch, 1);
 827                 }
 828         }
 829         if (status)
 830                 ep->dma_channel = 0;
 831         else {
 832                 ep->has_dma = 1;
 833                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 834
 835                 /* channel type P: hw synch (fifo) */
 836                 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
 837                         OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
 838         }
 839
 840 just_restart:
 841         /* restart any queue, even if the claim failed  */
 842         restart = !ep->stopped && !list_empty(&ep->queue);
 843
 844         if (status)
 845                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 846                         restart ? " (restart)" : "");
 847         else
 848                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 849                         is_in ? 't' : 'r',
 850                         ep->dma_channel - 1, ep->lch,
 851                         restart ? " (restart)" : "");
 852
 853         if (restart) {
 854                 struct omap_req *req;
 855                 req = container_of(ep->queue.next, struct omap_req, queue);
 856                 if (ep->has_dma)
 857                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 858                 else {
 859                         use_ep(ep, UDC_EP_SEL);
 860                         (is_in ? write_fifo : read_fifo)(ep, req);
 861                         deselect_ep();
 862                         if (!is_in) {
 863                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 864                                 ep->ackwait = 1 + ep->double_buf;
 865                         }
 866                         /* IN: 6 wait states before it'll tx */
 867                 }
 868         }
 869 }
 870
 871 static void dma_channel_release(struct omap_ep *ep)
 872 {
 873         int             shift = 4 * (ep->dma_channel - 1);
 874         u16             mask = 0x0f << shift;
 875         struct omap_req *req;
 876         int             active;
 877
 878         /* abort any active usb transfer request */
 879         if (!list_empty(&ep->queue))
 880                 req = container_of(ep->queue.next, struct omap_req, queue);
 881         else
 882                 req = NULL;
 883
 884         active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
 885
 886         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 887                         active ? "active" : "idle",
 888                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 889                         ep->dma_channel - 1, req);
 890
 891         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 892          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 893          */
 894
 895         /* wait till current packet DMA finishes, and fifo empties */
 896         if (ep->bEndpointAddress & USB_DIR_IN) {
 897                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 898
 899                 if (req) {
 900                         finish_in_dma(ep, req, -ECONNRESET);
 901
 902                         /* clear FIFO; hosts probably won't empty it */
 903                         use_ep(ep, UDC_EP_SEL);
 904                         UDC_CTRL_REG = UDC_CLR_EP;
 905                         deselect_ep();
 906                 }
 907                 while (UDC_TXDMA_CFG_REG & mask)
 908                         udelay(10);
 909         } else {
 910                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 911
 912                 /* dma empties the fifo */
 913                 while (UDC_RXDMA_CFG_REG & mask)
 914                         udelay(10);
 915                 if (req)
 916                         finish_out_dma(ep, req, -ECONNRESET, 0);
 917         }
 918         omap_free_dma(ep->lch);
 919         ep->dma_channel = 0;
 920         ep->lch = -1;
 921         /* has_dma still set, till endpoint is fully quiesced */
 922 }
 923
 924
 925 /*-------------------------------------------------------------------------*/
 926
 927 static int
 928 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 929 {
 930         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 931         struct omap_req *req = container_of(_req, struct omap_req, req);
 932         struct omap_udc *udc;
 933         unsigned long   flags;
 934         int             is_iso = 0;
 935
 936         /* catch various bogus parameters */
 937         if (!_req || !req->req.complete || !req->req.buf
 938                         || !list_empty(&req->queue)) {
 939                 DBG("%s, bad params\n", __FUNCTION__);
 940                 return -EINVAL;
 941         }
 942         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
 943                 DBG("%s, bad ep\n", __FUNCTION__);
 944                 return -EINVAL;
 945         }
 946         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 947                 if (req->req.length > ep->ep.maxpacket)
 948                         return -EMSGSIZE;
 949                 is_iso = 1;
 950         }
 951
 952         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 953          * have a hard time with partial packet reads...  reject it.
 954          * Except OMAP2 can handle the small packets.
 955          */
 956         if (use_dma
 957                         && ep->has_dma
 958                         && ep->bEndpointAddress != 0
 959                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 960                         && !cpu_class_is_omap2()
 961                         && (req->req.length % ep->ep.maxpacket) != 0) {
 962                 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
 963                 return -EMSGSIZE;
 964         }
 965
 966         udc = ep->udc;
 967         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 968                 return -ESHUTDOWN;
 969
 970         if (use_dma && ep->has_dma) {
 971                 if (req->req.dma == DMA_ADDR_INVALID) {
 972                         req->req.dma = dma_map_single(
 973                                 ep->udc->gadget.dev.parent,
 974                                 req->req.buf,
 975                                 req->req.length,
 976                                 (ep->bEndpointAddress & USB_DIR_IN)
 977                                         ? DMA_TO_DEVICE
 978                                         : DMA_FROM_DEVICE);
 979                         req->mapped = 1;
 980                 } else {
 981                         dma_sync_single_for_device(
 982                                 ep->udc->gadget.dev.parent,
 983                                 req->req.dma, req->req.length,
 984                                 (ep->bEndpointAddress & USB_DIR_IN)
 985                                         ? DMA_TO_DEVICE
 986                                         : DMA_FROM_DEVICE);
 987                         req->mapped = 0;
 988                 }
 989         }
 990
 991         VDBG("%s queue req %p, len %d buf %p\n",
 992                 ep->ep.name, _req, _req->length, _req->buf);
 993
 994         spin_lock_irqsave(&udc->lock, flags);
 995
 996         req->req.status = -EINPROGRESS;
 997         req->req.actual = 0;
 998
 999         /* maybe kickstart non-iso i/o queues */
1000         if (is_iso)
1001                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
1002         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1003                 int     is_in;
1004
1005                 if (ep->bEndpointAddress == 0) {
1006                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1007                                 spin_unlock_irqrestore(&udc->lock, flags);
1008                                 return -EL2HLT;
1009                         }
1010
1011                         /* empty DATA stage? */
1012                         is_in = udc->ep0_in;
1013                         if (!req->req.length) {
1014
1015                                 /* chip became CONFIGURED or ADDRESSED
1016                                  * earlier; drivers may already have queued
1017                                  * requests to non-control endpoints
1018                                  */
1019                                 if (udc->ep0_set_config) {
1020                                         u16     irq_en = UDC_IRQ_EN_REG;
1021
1022                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1023                                         if (!udc->ep0_reset_config)
1024                                                 irq_en |= UDC_EPN_RX_IE
1025                                                         | UDC_EPN_TX_IE;
1026                                         UDC_IRQ_EN_REG = irq_en;
1027                                 }
1028
1029                                 /* STATUS for zero length DATA stages is
1030                                  * always an IN ... even for IN transfers,
1031                                  * a weird case which seem to stall OMAP.
1032                                  */
1033                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1034                                 UDC_CTRL_REG = UDC_CLR_EP;
1035                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1036                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1037
1038                                 /* cleanup */
1039                                 udc->ep0_pending = 0;
1040                                 done(ep, req, 0);
1041                                 req = NULL;
1042
1043                         /* non-empty DATA stage */
1044                         } else if (is_in) {
1045                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1046                         } else {
1047                                 if (udc->ep0_setup)
1048                                         goto irq_wait;
1049                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1050                         }
1051                 } else {
1052                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1053                         if (!ep->has_dma)
1054                                 use_ep(ep, UDC_EP_SEL);
1055                         /* if ISO: SOF IRQs must be enabled/disabled! */
1056                 }
1057
1058                 if (ep->has_dma)
1059                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1060                 else if (req) {
1061                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1062                                 req = NULL;
1063                         deselect_ep();
1064                         if (!is_in) {
1065                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1066                                 ep->ackwait = 1 + ep->double_buf;
1067                         }
1068                         /* IN: 6 wait states before it'll tx */
1069                 }
1070         }
1071
1072 irq_wait:
1073         /* irq handler advances the queue */
1074         if (req != NULL)
1075                 list_add_tail(&req->queue, &ep->queue);
1076         spin_unlock_irqrestore(&udc->lock, flags);
1077
1078         return 0;
1079 }
1080
1081 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1082 {
1083         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1084         struct omap_req *req;
1085         unsigned long   flags;
1086
1087         if (!_ep || !_req)
1088                 return -EINVAL;
1089
1090         spin_lock_irqsave(&ep->udc->lock, flags);
1091
1092         /* make sure it's actually queued on this endpoint */
1093         list_for_each_entry (req, &ep->queue, queue) {
1094                 if (&req->req == _req)
1095                         break;
1096         }
1097         if (&req->req != _req) {
1098                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1099                 return -EINVAL;
1100         }
1101
1102         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1103                 int channel = ep->dma_channel;
1104
1105                 /* releasing the channel cancels the request,
1106                  * reclaiming the channel restarts the queue
1107                  */
1108                 dma_channel_release(ep);
1109                 dma_channel_claim(ep, channel);
1110         } else
1111                 done(ep, req, -ECONNRESET);
1112         spin_unlock_irqrestore(&ep->udc->lock, flags);
1113         return 0;
1114 }
1115
1116 /*-------------------------------------------------------------------------*/
1117
1118 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1119 {
1120         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1121         unsigned long   flags;
1122         int             status = -EOPNOTSUPP;
1123
1124         spin_lock_irqsave(&ep->udc->lock, flags);
1125
1126         /* just use protocol stalls for ep0; real halts are annoying */
1127         if (ep->bEndpointAddress == 0) {
1128                 if (!ep->udc->ep0_pending)
1129                         status = -EINVAL;
1130                 else if (value) {
1131                         if (ep->udc->ep0_set_config) {
1132                                 WARN("error changing config?\n");
1133                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1134                         }
1135                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1136                         ep->udc->ep0_pending = 0;
1137                         status = 0;
1138                 } else /* NOP */
1139                         status = 0;
1140
1141         /* otherwise, all active non-ISO endpoints can halt */
1142         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1143
1144                 /* IN endpoints must already be idle */
1145                 if ((ep->bEndpointAddress & USB_DIR_IN)
1146                                 && !list_empty(&ep->queue)) {
1147                         status = -EAGAIN;
1148                         goto done;
1149                 }
1150
1151                 if (value) {
1152                         int     channel;
1153
1154                         if (use_dma && ep->dma_channel
1155                                         && !list_empty(&ep->queue)) {
1156                                 channel = ep->dma_channel;
1157                                 dma_channel_release(ep);
1158                         } else
1159                                 channel = 0;
1160
1161                         use_ep(ep, UDC_EP_SEL);
1162                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1163                                 UDC_CTRL_REG = UDC_SET_HALT;
1164                                 status = 0;
1165                         } else
1166                                 status = -EAGAIN;
1167                         deselect_ep();
1168
1169                         if (channel)
1170                                 dma_channel_claim(ep, channel);
1171                 } else {
1172                         use_ep(ep, 0);
1173                         UDC_CTRL_REG = ep->udc->clr_halt;
1174                         ep->ackwait = 0;
1175                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1176                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1177                                 ep->ackwait = 1 + ep->double_buf;
1178                         }
1179                 }
1180         }
1181 done:
1182         VDBG("%s %s halt stat %d\n", ep->ep.name,
1183                 value ? "set" : "clear", status);
1184
1185         spin_unlock_irqrestore(&ep->udc->lock, flags);
1186         return status;
1187 }
1188
1189 static struct usb_ep_ops omap_ep_ops = {
1190         .enable         = omap_ep_enable,
1191         .disable        = omap_ep_disable,
1192
1193         .alloc_request  = omap_alloc_request,
1194         .free_request   = omap_free_request,
1195
1196         .queue          = omap_ep_queue,
1197         .dequeue        = omap_ep_dequeue,
1198
1199         .set_halt       = omap_ep_set_halt,
1200         // fifo_status ... report bytes in fifo
1201         // fifo_flush ... flush fifo
1202 };
1203
1204 /*-------------------------------------------------------------------------*/
1205
1206 static int omap_get_frame(struct usb_gadget *gadget)
1207 {
1208         u16     sof = UDC_SOF_REG;
1209         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1210 }
1211
1212 static int omap_wakeup(struct usb_gadget *gadget)
1213 {
1214         struct omap_udc *udc;
1215         unsigned long   flags;
1216         int             retval = -EHOSTUNREACH;
1217
1218         udc = container_of(gadget, struct omap_udc, gadget);
1219
1220         spin_lock_irqsave(&udc->lock, flags);
1221         if (udc->devstat & UDC_SUS) {
1222                 /* NOTE:  OTG spec erratum says that OTG devices may
1223                  * issue wakeups without host enable.
1224                  */
1225                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1226                         DBG("remote wakeup...\n");
1227                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1228                         retval = 0;
1229                 }
1230
1231         /* NOTE:  non-OTG systems may use SRP TOO... */
1232         } else if (!(udc->devstat & UDC_ATT)) {
1233                 if (udc->transceiver)
1234                         retval = otg_start_srp(udc->transceiver);
1235         }
1236         spin_unlock_irqrestore(&udc->lock, flags);
1237
1238         return retval;
1239 }
1240
1241 static int
1242 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1243 {
1244         struct omap_udc *udc;
1245         unsigned long   flags;
1246         u16             syscon1;
1247
1248         udc = container_of(gadget, struct omap_udc, gadget);
1249         spin_lock_irqsave(&udc->lock, flags);
1250         syscon1 = UDC_SYSCON1_REG;
1251         if (is_selfpowered)
1252                 syscon1 |= UDC_SELF_PWR;
1253         else
1254                 syscon1 &= ~UDC_SELF_PWR;
1255         UDC_SYSCON1_REG = syscon1;
1256         spin_unlock_irqrestore(&udc->lock, flags);
1257
1258         return 0;
1259 }
1260
1261 static int can_pullup(struct omap_udc *udc)
1262 {
1263         return udc->driver && udc->softconnect && udc->vbus_active;
1264 }
1265
1266 static void pullup_enable(struct omap_udc *udc)
1267 {
1268         udc->gadget.dev.parent->power.power_state = PMSG_ON;
1269         udc->gadget.dev.power.power_state = PMSG_ON;
1270         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1271         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1272                 OTG_CTRL_REG |= OTG_BSESSVLD;
1273         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1274 }
1275
1276 static void pullup_disable(struct omap_udc *udc)
1277 {
1278         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1279                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1280         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1281         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1282 }
1283
1284 static struct omap_udc *udc;
1285
1286 static void omap_udc_enable_clock(int enable)
1287 {
1288         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1289                 return;
1290
1291         if (enable) {
1292                 clk_enable(udc->dc_clk);
1293                 clk_enable(udc->hhc_clk);
1294                 udelay(100);
1295         } else {
1296                 clk_disable(udc->hhc_clk);
1297                 clk_disable(udc->dc_clk);
1298         }
1299 }
1300
1301 /*
1302  * Called by whatever detects VBUS sessions:  external transceiver
1303  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1304  */
1305 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1306 {
1307         struct omap_udc *udc;
1308         unsigned long   flags;
1309
1310         udc = container_of(gadget, struct omap_udc, gadget);
1311         spin_lock_irqsave(&udc->lock, flags);
1312         VDBG("VBUS %s\n", is_active ? "on" : "off");
1313         udc->vbus_active = (is_active != 0);
1314         if (cpu_is_omap15xx()) {
1315                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1316                 if (is_active)
1317                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1318                 else
1319                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1320         }
1321         if (udc->dc_clk != NULL && is_active) {
1322                 if (!udc->clk_requested) {
1323                         omap_udc_enable_clock(1);
1324                         udc->clk_requested = 1;
1325                 }
1326         }
1327         if (can_pullup(udc))
1328                 pullup_enable(udc);
1329         else
1330                 pullup_disable(udc);
1331         if (udc->dc_clk != NULL && !is_active) {
1332                 if (udc->clk_requested) {
1333                         omap_udc_enable_clock(0);
1334                         udc->clk_requested = 0;
1335                 }
1336         }
1337         spin_unlock_irqrestore(&udc->lock, flags);
1338         return 0;
1339 }
1340
1341 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1342 {
1343         struct omap_udc *udc;
1344
1345         udc = container_of(gadget, struct omap_udc, gadget);
1346         if (udc->transceiver)
1347                 return otg_set_power(udc->transceiver, mA);
1348         return -EOPNOTSUPP;
1349 }
1350
1351 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1352 {
1353         struct omap_udc *udc;
1354         unsigned long   flags;
1355
1356         udc = container_of(gadget, struct omap_udc, gadget);
1357         spin_lock_irqsave(&udc->lock, flags);
1358         udc->softconnect = (is_on != 0);
1359         if (can_pullup(udc))
1360                 pullup_enable(udc);
1361         else
1362                 pullup_disable(udc);
1363         spin_unlock_irqrestore(&udc->lock, flags);
1364         return 0;
1365 }
1366
1367 static struct usb_gadget_ops omap_gadget_ops = {
1368         .get_frame              = omap_get_frame,
1369         .wakeup                 = omap_wakeup,
1370         .set_selfpowered        = omap_set_selfpowered,
1371         .vbus_session           = omap_vbus_session,
1372         .vbus_draw              = omap_vbus_draw,
1373         .pullup                 = omap_pullup,
1374 };
1375
1376 /*-------------------------------------------------------------------------*/
1377
1378 /* dequeue ALL requests; caller holds udc->lock */
1379 static void nuke(struct omap_ep *ep, int status)
1380 {
1381         struct omap_req *req;
1382
1383         ep->stopped = 1;
1384
1385         if (use_dma && ep->dma_channel)
1386                 dma_channel_release(ep);
1387
1388         use_ep(ep, 0);
1389         UDC_CTRL_REG = UDC_CLR_EP;
1390         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1391                 UDC_CTRL_REG = UDC_SET_HALT;
1392
1393         while (!list_empty(&ep->queue)) {
1394                 req = list_entry(ep->queue.next, struct omap_req, queue);
1395                 done(ep, req, status);
1396         }
1397 }
1398
1399 /* caller holds udc->lock */
1400 static void udc_quiesce(struct omap_udc *udc)
1401 {
1402         struct omap_ep  *ep;
1403
1404         udc->gadget.speed = USB_SPEED_UNKNOWN;
1405         nuke(&udc->ep[0], -ESHUTDOWN);
1406         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1407                 nuke(ep, -ESHUTDOWN);
1408 }
1409
1410 /*-------------------------------------------------------------------------*/
1411
1412 static void update_otg(struct omap_udc *udc)
1413 {
1414         u16     devstat;
1415
1416         if (!gadget_is_otg(&udc->gadget))
1417                 return;
1418
1419         if (OTG_CTRL_REG & OTG_ID)
1420                 devstat = UDC_DEVSTAT_REG;
1421         else
1422                 devstat = 0;
1423
1424         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1425         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1426         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1427
1428         /* Enable HNP early, avoiding races on suspend irq path.
1429          * ASSUMES OTG state machine B_BUS_REQ input is true.
1430          */
1431         if (udc->gadget.b_hnp_enable)
1432                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1433                                 & ~OTG_PULLUP;
1434 }
1435
1436 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1437 {
1438         struct omap_ep  *ep0 = &udc->ep[0];
1439         struct omap_req *req = NULL;
1440
1441         ep0->irqs++;
1442
1443         /* Clear any pending requests and then scrub any rx/tx state
1444          * before starting to handle the SETUP request.
1445          */
1446         if (irq_src & UDC_SETUP) {
1447                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1448
1449                 nuke(ep0, 0);
1450                 if (ack) {
1451                         UDC_IRQ_SRC_REG = ack;
1452                         irq_src = UDC_SETUP;
1453                 }
1454         }
1455
1456         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1457          * This driver uses only uses protocol stalls (ep0 never halts),
1458          * and if we got this far the gadget driver already had a
1459          * chance to stall.  Tries to be forgiving of host oddities.
1460          *
1461          * NOTE:  the last chance gadget drivers have to stall control
1462          * requests is during their request completion callback.
1463          */
1464         if (!list_empty(&ep0->queue))
1465                 req = container_of(ep0->queue.next, struct omap_req, queue);
1466
1467         /* IN == TX to host */
1468         if (irq_src & UDC_EP0_TX) {
1469                 int     stat;
1470
1471                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1472                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1473                 stat = UDC_STAT_FLG_REG;
1474                 if (stat & UDC_ACK) {
1475                         if (udc->ep0_in) {
1476                                 /* write next IN packet from response,
1477                                  * or set up the status stage.
1478                                  */
1479                                 if (req)
1480                                         stat = write_fifo(ep0, req);
1481                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1482                                 if (!req && udc->ep0_pending) {
1483                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1484                                         UDC_CTRL_REG = UDC_CLR_EP;
1485                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1486                                         UDC_EP_NUM_REG = 0;
1487                                         udc->ep0_pending = 0;
1488                                 } /* else:  6 wait states before it'll tx */
1489                         } else {
1490                                 /* ack status stage of OUT transfer */
1491                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1492                                 if (req)
1493                                         done(ep0, req, 0);
1494                         }
1495                         req = NULL;
1496                 } else if (stat & UDC_STALL) {
1497                         UDC_CTRL_REG = UDC_CLR_HALT;
1498                         UDC_EP_NUM_REG = UDC_EP_DIR;
1499                 } else {
1500                         UDC_EP_NUM_REG = UDC_EP_DIR;
1501                 }
1502         }
1503
1504         /* OUT == RX from host */
1505         if (irq_src & UDC_EP0_RX) {
1506                 int     stat;
1507
1508                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1509                 UDC_EP_NUM_REG = UDC_EP_SEL;
1510                 stat = UDC_STAT_FLG_REG;
1511                 if (stat & UDC_ACK) {
1512                         if (!udc->ep0_in) {
1513                                 stat = 0;
1514                                 /* read next OUT packet of request, maybe
1515                                  * reactiviting the fifo; stall on errors.
1516                                  */
1517                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1518                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1519                                         udc->ep0_pending = 0;
1520                                         stat = 0;
1521                                 } else if (stat == 0)
1522                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1523                                 UDC_EP_NUM_REG = 0;
1524
1525                                 /* activate status stage */
1526                                 if (stat == 1) {
1527                                         done(ep0, req, 0);
1528                                         /* that may have STALLed ep0... */
1529                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1530                                         UDC_CTRL_REG = UDC_CLR_EP;
1531                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1532                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1533                                         udc->ep0_pending = 0;
1534                                 }
1535                         } else {
1536                                 /* ack status stage of IN transfer */
1537                                 UDC_EP_NUM_REG = 0;
1538                                 if (req)
1539                                         done(ep0, req, 0);
1540                         }
1541                 } else if (stat & UDC_STALL) {
1542                         UDC_CTRL_REG = UDC_CLR_HALT;
1543                         UDC_EP_NUM_REG = 0;
1544                 } else {
1545                         UDC_EP_NUM_REG = 0;
1546                 }
1547         }
1548
1549         /* SETUP starts all control transfers */
1550         if (irq_src & UDC_SETUP) {
1551                 union u {
1552                         u16                     word[4];
1553                         struct usb_ctrlrequest  r;
1554                 } u;
1555                 int                     status = -EINVAL;
1556                 struct omap_ep          *ep;
1557
1558                 /* read the (latest) SETUP message */
1559                 do {
1560                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1561                         /* two bytes at a time */
1562                         u.word[0] = UDC_DATA_REG;
1563                         u.word[1] = UDC_DATA_REG;
1564                         u.word[2] = UDC_DATA_REG;
1565                         u.word[3] = UDC_DATA_REG;
1566                         UDC_EP_NUM_REG = 0;
1567                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1568
1569 #define w_value         le16_to_cpu(u.r.wValue)
1570 #define w_index         le16_to_cpu(u.r.wIndex)
1571 #define w_length        le16_to_cpu(u.r.wLength)
1572
1573                 /* Delegate almost all control requests to the gadget driver,
1574                  * except for a handful of ch9 status/feature requests that
1575                  * hardware doesn't autodecode _and_ the gadget API hides.
1576                  */
1577                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1578                 udc->ep0_set_config = 0;
1579                 udc->ep0_pending = 1;
1580                 ep0->stopped = 0;
1581                 ep0->ackwait = 0;
1582                 switch (u.r.bRequest) {
1583                 case USB_REQ_SET_CONFIGURATION:
1584                         /* udc needs to know when ep != 0 is valid */
1585                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1586                                 goto delegate;
1587                         if (w_length != 0)
1588                                 goto do_stall;
1589                         udc->ep0_set_config = 1;
1590                         udc->ep0_reset_config = (w_value == 0);
1591                         VDBG("set config %d\n", w_value);
1592
1593                         /* update udc NOW since gadget driver may start
1594                          * queueing requests immediately; clear config
1595                          * later if it fails the request.
1596                          */
1597                         if (udc->ep0_reset_config)
1598                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1599                         else
1600                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1601                         update_otg(udc);
1602                         goto delegate;
1603                 case USB_REQ_CLEAR_FEATURE:
1604                         /* clear endpoint halt */
1605                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1606                                 goto delegate;
1607                         if (w_value != USB_ENDPOINT_HALT
1608                                         || w_length != 0)
1609                                 goto do_stall;
1610                         ep = &udc->ep[w_index & 0xf];
1611                         if (ep != ep0) {
1612                                 if (w_index & USB_DIR_IN)
1613                                         ep += 16;
1614                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1615                                                 || !ep->desc)
1616                                         goto do_stall;
1617                                 use_ep(ep, 0);
1618                                 UDC_CTRL_REG = udc->clr_halt;
1619                                 ep->ackwait = 0;
1620                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1621                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1622                                         ep->ackwait = 1 + ep->double_buf;
1623                                 }
1624                                 /* NOTE:  assumes the host behaves sanely,
1625                                  * only clearing real halts.  Else we may
1626                                  * need to kill pending transfers and then
1627                                  * restart the queue... very messy for DMA!
1628                                  */
1629                         }
1630                         VDBG("%s halt cleared by host\n", ep->name);
1631                         goto ep0out_status_stage;
1632                 case USB_REQ_SET_FEATURE:
1633                         /* set endpoint halt */
1634                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1635                                 goto delegate;
1636                         if (w_value != USB_ENDPOINT_HALT
1637                                         || w_length != 0)
1638                                 goto do_stall;
1639                         ep = &udc->ep[w_index & 0xf];
1640                         if (w_index & USB_DIR_IN)
1641                                 ep += 16;
1642                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1643                                         || ep == ep0 || !ep->desc)
1644                                 goto do_stall;
1645                         if (use_dma && ep->has_dma) {
1646                                 /* this has rude side-effects (aborts) and
1647                                  * can't really work if DMA-IN is active
1648                                  */
1649                                 DBG("%s host set_halt, NYET \n", ep->name);
1650                                 goto do_stall;
1651                         }
1652                         use_ep(ep, 0);
1653                         /* can't halt if fifo isn't empty... */
1654                         UDC_CTRL_REG = UDC_CLR_EP;
1655                         UDC_CTRL_REG = UDC_SET_HALT;
1656                         VDBG("%s halted by host\n", ep->name);
1657 ep0out_status_stage:
1658                         status = 0;
1659                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1660                         UDC_CTRL_REG = UDC_CLR_EP;
1661                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1662                         UDC_EP_NUM_REG = UDC_EP_DIR;
1663                         udc->ep0_pending = 0;
1664                         break;
1665                 case USB_REQ_GET_STATUS:
1666                         /* USB_ENDPOINT_HALT status? */
1667                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1668                                 goto intf_status;
1669
1670                         /* ep0 never stalls */
1671                         if (!(w_index & 0xf))
1672                                 goto zero_status;
1673
1674                         /* only active endpoints count */
1675                         ep = &udc->ep[w_index & 0xf];
1676                         if (w_index & USB_DIR_IN)
1677                                 ep += 16;
1678                         if (!ep->desc)
1679                                 goto do_stall;
1680
1681                         /* iso never stalls */
1682                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1683                                 goto zero_status;
1684
1685                         /* FIXME don't assume non-halted endpoints!! */
1686                         ERR("%s status, can't report\n", ep->ep.name);
1687                         goto do_stall;
1688
1689 intf_status:
1690                         /* return interface status.  if we were pedantic,
1691                          * we'd detect non-existent interfaces, and stall.
1692                          */
1693                         if (u.r.bRequestType
1694                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1695                                 goto delegate;
1696
1697 zero_status:
1698                         /* return two zero bytes */
1699                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1700                         UDC_DATA_REG = 0;
1701                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1702                         UDC_EP_NUM_REG = UDC_EP_DIR;
1703                         status = 0;
1704                         VDBG("GET_STATUS, interface %d\n", w_index);
1705                         /* next, status stage */
1706                         break;
1707                 default:
1708 delegate:
1709                         /* activate the ep0out fifo right away */
1710                         if (!udc->ep0_in && w_length) {
1711                                 UDC_EP_NUM_REG = 0;
1712                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1713                         }
1714
1715                         /* gadget drivers see class/vendor specific requests,
1716                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1717                          * and more
1718                          */
1719                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1720                                 u.r.bRequestType, u.r.bRequest,
1721                                 w_value, w_index, w_length);
1722
1723 #undef  w_value
1724 #undef  w_index
1725 #undef  w_length
1726
1727                         /* The gadget driver may return an error here,
1728                          * causing an immediate protocol stall.
1729                          *
1730                          * Else it must issue a response, either queueing a
1731                          * response buffer for the DATA stage, or halting ep0
1732                          * (causing a protocol stall, not a real halt).  A
1733                          * zero length buffer means no DATA stage.
1734                          *
1735                          * It's fine to issue that response after the setup()
1736                          * call returns, and this IRQ was handled.
1737                          */
1738                         udc->ep0_setup = 1;
1739                         spin_unlock(&udc->lock);
1740                         status = udc->driver->setup (&udc->gadget, &u.r);
1741                         spin_lock(&udc->lock);
1742                         udc->ep0_setup = 0;
1743                 }
1744
1745                 if (status < 0) {
1746 do_stall:
1747                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1748                                         u.r.bRequestType, u.r.bRequest, status);
1749                         if (udc->ep0_set_config) {
1750                                 if (udc->ep0_reset_config)
1751                                         WARN("error resetting config?\n");
1752                                 else
1753                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1754                         }
1755                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1756                         udc->ep0_pending = 0;
1757                 }
1758         }
1759 }
1760
1761 /*-------------------------------------------------------------------------*/
1762
1763 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1764
1765 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1766 {
1767         u16     devstat, change;
1768
1769         devstat = UDC_DEVSTAT_REG;
1770         change = devstat ^ udc->devstat;
1771         udc->devstat = devstat;
1772
1773         if (change & (UDC_USB_RESET|UDC_ATT)) {
1774                 udc_quiesce(udc);
1775
1776                 if (change & UDC_ATT) {
1777                         /* driver for any external transceiver will
1778                          * have called omap_vbus_session() already
1779                          */
1780                         if (devstat & UDC_ATT) {
1781                                 udc->gadget.speed = USB_SPEED_FULL;
1782                                 VDBG("connect\n");
1783                                 if (!udc->transceiver)
1784                                         pullup_enable(udc);
1785                                 // if (driver->connect) call it
1786                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1787                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1788                                 if (!udc->transceiver)
1789                                         pullup_disable(udc);
1790                                 DBG("disconnect, gadget %s\n",
1791                                         udc->driver->driver.name);
1792                                 if (udc->driver->disconnect) {
1793                                         spin_unlock(&udc->lock);
1794                                         udc->driver->disconnect(&udc->gadget);
1795                                         spin_lock(&udc->lock);
1796                                 }
1797                         }
1798                         change &= ~UDC_ATT;
1799                 }
1800
1801                 if (change & UDC_USB_RESET) {
1802                         if (devstat & UDC_USB_RESET) {
1803                                 VDBG("RESET=1\n");
1804                         } else {
1805                                 udc->gadget.speed = USB_SPEED_FULL;
1806                                 INFO("USB reset done, gadget %s\n",
1807                                         udc->driver->driver.name);
1808                                 /* ep0 traffic is legal from now on */
1809                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1810                         }
1811                         change &= ~UDC_USB_RESET;
1812                 }
1813         }
1814         if (change & UDC_SUS) {
1815                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1816                         // FIXME tell isp1301 to suspend/resume (?)
1817                         if (devstat & UDC_SUS) {
1818                                 VDBG("suspend\n");
1819                                 update_otg(udc);
1820                                 /* HNP could be under way already */
1821                                 if (udc->gadget.speed == USB_SPEED_FULL
1822                                                 && udc->driver->suspend) {
1823                                         spin_unlock(&udc->lock);
1824                                         udc->driver->suspend(&udc->gadget);
1825                                         spin_lock(&udc->lock);
1826                                 }
1827                                 if (udc->transceiver)
1828                                         otg_set_suspend(udc->transceiver, 1);
1829                         } else {
1830                                 VDBG("resume\n");
1831                                 if (udc->transceiver)
1832                                         otg_set_suspend(udc->transceiver, 0);
1833                                 if (udc->gadget.speed == USB_SPEED_FULL
1834                                                 && udc->driver->resume) {
1835                                         spin_unlock(&udc->lock);
1836                                         udc->driver->resume(&udc->gadget);
1837                                         spin_lock(&udc->lock);
1838                                 }
1839                         }
1840                 }
1841                 change &= ~UDC_SUS;
1842         }
1843         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1844                 update_otg(udc);
1845                 change &= ~OTG_FLAGS;
1846         }
1847
1848         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1849         if (change)
1850                 VDBG("devstat %03x, ignore change %03x\n",
1851                         devstat,  change);
1852
1853         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1854 }
1855
1856 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1857 {
1858         struct omap_udc *udc = _udc;
1859         u16             irq_src;
1860         irqreturn_t     status = IRQ_NONE;
1861         unsigned long   flags;
1862
1863         spin_lock_irqsave(&udc->lock, flags);
1864         irq_src = UDC_IRQ_SRC_REG;
1865
1866         /* Device state change (usb ch9 stuff) */
1867         if (irq_src & UDC_DS_CHG) {
1868                 devstate_irq(_udc, irq_src);
1869                 status = IRQ_HANDLED;
1870                 irq_src &= ~UDC_DS_CHG;
1871         }
1872
1873         /* EP0 control transfers */
1874         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1875                 ep0_irq(_udc, irq_src);
1876                 status = IRQ_HANDLED;
1877                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1878         }
1879
1880         /* DMA transfer completion */
1881         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1882                 dma_irq(_udc, irq_src);
1883                 status = IRQ_HANDLED;
1884                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1885         }
1886
1887         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1888         if (irq_src)
1889                 DBG("udc_irq, unhandled %03x\n", irq_src);
1890         spin_unlock_irqrestore(&udc->lock, flags);
1891
1892         return status;
1893 }
1894
1895 /* workaround for seemingly-lost IRQs for RX ACKs... */
1896 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1897 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1898
1899 static void pio_out_timer(unsigned long _ep)
1900 {
1901         struct omap_ep  *ep = (void *) _ep;
1902         unsigned long   flags;
1903         u16             stat_flg;
1904
1905         spin_lock_irqsave(&ep->udc->lock, flags);
1906         if (!list_empty(&ep->queue) && ep->ackwait) {
1907                 use_ep(ep, UDC_EP_SEL);
1908                 stat_flg = UDC_STAT_FLG_REG;
1909
1910                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1911                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1912                         struct omap_req *req;
1913
1914                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1915                         req = container_of(ep->queue.next,
1916                                         struct omap_req, queue);
1917                         (void) read_fifo(ep, req);
1918                         UDC_EP_NUM_REG = ep->bEndpointAddress;
1919                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1920                         ep->ackwait = 1 + ep->double_buf;
1921                 } else
1922                         deselect_ep();
1923         }
1924         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1925         spin_unlock_irqrestore(&ep->udc->lock, flags);
1926 }
1927
1928 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1929 {
1930         u16             epn_stat, irq_src;
1931         irqreturn_t     status = IRQ_NONE;
1932         struct omap_ep  *ep;
1933         int             epnum;
1934         struct omap_udc *udc = _dev;
1935         struct omap_req *req;
1936         unsigned long   flags;
1937
1938         spin_lock_irqsave(&udc->lock, flags);
1939         epn_stat = UDC_EPN_STAT_REG;
1940         irq_src = UDC_IRQ_SRC_REG;
1941
1942         /* handle OUT first, to avoid some wasteful NAKs */
1943         if (irq_src & UDC_EPN_RX) {
1944                 epnum = (epn_stat >> 8) & 0x0f;
1945                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1946                 status = IRQ_HANDLED;
1947                 ep = &udc->ep[epnum];
1948                 ep->irqs++;
1949
1950                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1951                 ep->fnf = 0;
1952                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1953                         ep->ackwait--;
1954                         if (!list_empty(&ep->queue)) {
1955                                 int stat;
1956                                 req = container_of(ep->queue.next,
1957                                                 struct omap_req, queue);
1958                                 stat = read_fifo(ep, req);
1959                                 if (!ep->double_buf)
1960                                         ep->fnf = 1;
1961                         }
1962                 }
1963                 /* min 6 clock delay before clearing EP_SEL ... */
1964                 epn_stat = UDC_EPN_STAT_REG;
1965                 epn_stat = UDC_EPN_STAT_REG;
1966                 UDC_EP_NUM_REG = epnum;
1967
1968                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1969                  * reduces lossage; timer still needed though (sigh).
1970                  */
1971                 if (ep->fnf) {
1972                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1973                         ep->ackwait = 1 + ep->double_buf;
1974                 }
1975                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1976         }
1977
1978         /* then IN transfers */
1979         else if (irq_src & UDC_EPN_TX) {
1980                 epnum = epn_stat & 0x0f;
1981                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1982                 status = IRQ_HANDLED;
1983                 ep = &udc->ep[16 + epnum];
1984                 ep->irqs++;
1985
1986                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1987                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1988                         ep->ackwait = 0;
1989                         if (!list_empty(&ep->queue)) {
1990                                 req = container_of(ep->queue.next,
1991                                                 struct omap_req, queue);
1992                                 (void) write_fifo(ep, req);
1993                         }
1994                 }
1995                 /* min 6 clock delay before clearing EP_SEL ... */
1996                 epn_stat = UDC_EPN_STAT_REG;
1997                 epn_stat = UDC_EPN_STAT_REG;
1998                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
1999                 /* then 6 clocks before it'd tx */
2000         }
2001
2002         spin_unlock_irqrestore(&udc->lock, flags);
2003         return status;
2004 }
2005
2006 #ifdef  USE_ISO
2007 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2008 {
2009         struct omap_udc *udc = _dev;
2010         struct omap_ep  *ep;
2011         int             pending = 0;
2012         unsigned long   flags;
2013
2014         spin_lock_irqsave(&udc->lock, flags);
2015
2016         /* handle all non-DMA ISO transfers */
2017         list_for_each_entry (ep, &udc->iso, iso) {
2018                 u16             stat;
2019                 struct omap_req *req;
2020
2021                 if (ep->has_dma || list_empty(&ep->queue))
2022                         continue;
2023                 req = list_entry(ep->queue.next, struct omap_req, queue);
2024
2025                 use_ep(ep, UDC_EP_SEL);
2026                 stat = UDC_STAT_FLG_REG;
2027
2028                 /* NOTE: like the other controller drivers, this isn't
2029                  * currently reporting lost or damaged frames.
2030                  */
2031                 if (ep->bEndpointAddress & USB_DIR_IN) {
2032                         if (stat & UDC_MISS_IN)
2033                                 /* done(ep, req, -EPROTO) */;
2034                         else
2035                                 write_fifo(ep, req);
2036                 } else {
2037                         int     status = 0;
2038
2039                         if (stat & UDC_NO_RXPACKET)
2040                                 status = -EREMOTEIO;
2041                         else if (stat & UDC_ISO_ERR)
2042                                 status = -EILSEQ;
2043                         else if (stat & UDC_DATA_FLUSH)
2044                                 status = -ENOSR;
2045
2046                         if (status)
2047                                 /* done(ep, req, status) */;
2048                         else
2049                                 read_fifo(ep, req);
2050                 }
2051                 deselect_ep();
2052                 /* 6 wait states before next EP */
2053
2054                 ep->irqs++;
2055                 if (!list_empty(&ep->queue))
2056                         pending = 1;
2057         }
2058         if (!pending)
2059                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2060         UDC_IRQ_SRC_REG = UDC_SOF;
2061
2062         spin_unlock_irqrestore(&udc->lock, flags);
2063         return IRQ_HANDLED;
2064 }
2065 #endif
2066
2067 /*-------------------------------------------------------------------------*/
2068
2069 static inline int machine_without_vbus_sense(void)
2070 {
2071         return (machine_is_omap_innovator()
2072                 || machine_is_omap_osk()
2073                 || machine_is_omap_apollon()
2074 #ifndef CONFIG_MACH_OMAP_H4_OTG
2075                 || machine_is_omap_h4()
2076 #endif
2077                 || machine_is_sx1()
2078                 );
2079 }
2080
2081 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2082 {
2083         int             status = -ENODEV;
2084         struct omap_ep  *ep;
2085         unsigned long   flags;
2086
2087         /* basic sanity tests */
2088         if (!udc)
2089                 return -ENODEV;
2090         if (!driver
2091                         // FIXME if otg, check:  driver->is_otg
2092                         || driver->speed < USB_SPEED_FULL
2093                         || !driver->bind
2094                         || !driver->setup)
2095                 return -EINVAL;
2096
2097         spin_lock_irqsave(&udc->lock, flags);
2098         if (udc->driver) {
2099                 spin_unlock_irqrestore(&udc->lock, flags);
2100                 return -EBUSY;
2101         }
2102
2103         /* reset state */
2104         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2105                 ep->irqs = 0;
2106                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2107                         continue;
2108                 use_ep(ep, 0);
2109                 UDC_CTRL_REG = UDC_SET_HALT;
2110         }
2111         udc->ep0_pending = 0;
2112         udc->ep[0].irqs = 0;
2113         udc->softconnect = 1;
2114
2115         /* hook up the driver */
2116         driver->driver.bus = NULL;
2117         udc->driver = driver;
2118         udc->gadget.dev.driver = &driver->driver;
2119         spin_unlock_irqrestore(&udc->lock, flags);
2120
2121         if (udc->dc_clk != NULL)
2122                 omap_udc_enable_clock(1);
2123
2124         status = driver->bind (&udc->gadget);
2125         if (status) {
2126                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2127                 udc->gadget.dev.driver = NULL;
2128                 udc->driver = NULL;
2129                 goto done;
2130         }
2131         DBG("bound to driver %s\n", driver->driver.name);
2132
2133         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2134
2135         /* connect to bus through transceiver */
2136         if (udc->transceiver) {
2137                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2138                 if (status < 0) {
2139                         ERR("can't bind to transceiver\n");
2140                         if (driver->unbind) {
2141                                 driver->unbind (&udc->gadget);
2142                                 udc->gadget.dev.driver = NULL;
2143                                 udc->driver = NULL;
2144                         }
2145                         goto done;
2146                 }
2147         } else {
2148                 if (can_pullup(udc))
2149                         pullup_enable (udc);
2150                 else
2151                         pullup_disable (udc);
2152         }
2153
2154         /* boards that don't have VBUS sensing can't autogate 48MHz;
2155          * can't enter deep sleep while a gadget driver is active.
2156          */
2157         if (machine_without_vbus_sense())
2158                 omap_vbus_session(&udc->gadget, 1);
2159
2160 done:
2161         if (udc->dc_clk != NULL)
2162                 omap_udc_enable_clock(0);
2163         return status;
2164 }
2165 EXPORT_SYMBOL(usb_gadget_register_driver);
2166
2167 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2168 {
2169         unsigned long   flags;
2170         int             status = -ENODEV;
2171
2172         if (!udc)
2173                 return -ENODEV;
2174         if (!driver || driver != udc->driver || !driver->unbind)
2175                 return -EINVAL;
2176
2177         if (udc->dc_clk != NULL)
2178                 omap_udc_enable_clock(1);
2179
2180         if (machine_without_vbus_sense())
2181                 omap_vbus_session(&udc->gadget, 0);
2182
2183         if (udc->transceiver)
2184                 (void) otg_set_peripheral(udc->transceiver, NULL);
2185         else
2186                 pullup_disable(udc);
2187
2188         spin_lock_irqsave(&udc->lock, flags);
2189         udc_quiesce(udc);
2190         spin_unlock_irqrestore(&udc->lock, flags);
2191
2192         driver->unbind(&udc->gadget);
2193         udc->gadget.dev.driver = NULL;
2194         udc->driver = NULL;
2195
2196         if (udc->dc_clk != NULL)
2197                 omap_udc_enable_clock(0);
2198         DBG("unregistered driver '%s'\n", driver->driver.name);
2199         return status;
2200 }
2201 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2202
2203
2204 /*-------------------------------------------------------------------------*/
2205
2206 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2207
2208 #include <linux/seq_file.h>
2209
2210 static const char proc_filename[] = "driver/udc";
2211
2212 #define FOURBITS "%s%s%s%s"
2213 #define EIGHTBITS FOURBITS FOURBITS
2214
2215 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2216 {
2217         u16             stat_flg;
2218         struct omap_req *req;
2219         char            buf[20];
2220
2221         use_ep(ep, 0);
2222
2223         if (use_dma && ep->has_dma)
2224                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2225                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2226                         ep->dma_channel - 1, ep->lch);
2227         else
2228                 buf[0] = 0;
2229
2230         stat_flg = UDC_STAT_FLG_REG;
2231         seq_printf(s,
2232                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2233                 ep->name, buf,
2234                 ep->double_buf ? "dbuf " : "",
2235                 ({char *s; switch(ep->ackwait){
2236                 case 0: s = ""; break;
2237                 case 1: s = "(ackw) "; break;
2238                 case 2: s = "(ackw2) "; break;
2239                 default: s = "(?) "; break;
2240                 } s;}),
2241                 ep->irqs, stat_flg,
2242                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2243                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2244                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2245                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2246                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2247                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2248                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2249                 (stat_flg & UDC_STALL) ? "STALL " : "",
2250                 (stat_flg & UDC_NAK) ? "NAK " : "",
2251                 (stat_flg & UDC_ACK) ? "ACK " : "",
2252                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2253                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2254                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2255
2256         if (list_empty (&ep->queue))
2257                 seq_printf(s, "\t(queue empty)\n");
2258         else
2259                 list_for_each_entry (req, &ep->queue, queue) {
2260                         unsigned        length = req->req.actual;
2261
2262                         if (use_dma && buf[0]) {
2263                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2264                                                 ? dma_src_len : dma_dest_len)
2265                                         (ep, req->req.dma + length);
2266                                 buf[0] = 0;
2267                         }
2268                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2269                                         &req->req, length,
2270                                         req->req.length, req->req.buf);
2271                 }
2272 }
2273
2274 static char *trx_mode(unsigned m, int enabled)
2275 {
2276         switch (m) {
2277         case 0:         return enabled ? "*6wire" : "unused";
2278         case 1:         return "4wire";
2279         case 2:         return "3wire";
2280         case 3:         return "6wire";
2281         default:        return "unknown";
2282         }
2283 }
2284
2285 static int proc_otg_show(struct seq_file *s)
2286 {
2287         u32             tmp;
2288         u32             trans;
2289         char            *ctrl_name;
2290
2291         tmp = OTG_REV_REG;
2292         if (cpu_is_omap24xx()) {
2293                 ctrl_name = "control_devconf";
2294                 trans = CONTROL_DEVCONF_REG;
2295         } else {
2296                 ctrl_name = "tranceiver_ctrl";
2297                 trans = USB_TRANSCEIVER_CTRL_REG;
2298         }
2299         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2300                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2301         tmp = OTG_SYSCON_1_REG;
2302         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2303                         FOURBITS "\n", tmp,
2304                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2305                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2306                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2307                         ? "internal"
2308                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2309                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2310                 (tmp & HST_IDLE_EN) ? " !host" : "",
2311                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2312                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2313         tmp = OTG_SYSCON_2_REG;
2314         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2315                         " b_ase_brst=%d hmc=%d\n", tmp,
2316                 (tmp & OTG_EN) ? " otg_en" : "",
2317                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2318                 // much more SRP stuff
2319                 (tmp & SRP_DATA) ? " srp_data" : "",
2320                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2321                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2322                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2323                 (tmp & UHOST_EN) ? " uhost_en" : "",
2324                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2325                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2326                 B_ASE_BRST(tmp),
2327                 OTG_HMC(tmp));
2328         tmp = OTG_CTRL_REG;
2329         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2330                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2331                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2332                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2333                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2334                 (tmp & OTG_ID) ? " id" : "",
2335                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2336                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2337                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2338                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2339                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2340                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2341                 (tmp & OTG_PULLDOWN) ? " down" : "",
2342                 (tmp & OTG_PULLUP) ? " up" : "",
2343                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2344                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2345                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2346                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2347                 );
2348         tmp = OTG_IRQ_EN_REG;
2349         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2350         tmp = OTG_IRQ_SRC_REG;
2351         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2352         tmp = OTG_OUTCTRL_REG;
2353         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2354         tmp = OTG_TEST_REG;
2355         seq_printf(s, "otg_test    %04x" "\n", tmp);
2356         return 0;
2357 }
2358
2359 static int proc_udc_show(struct seq_file *s, void *_)
2360 {
2361         u32             tmp;
2362         struct omap_ep  *ep;
2363         unsigned long   flags;
2364
2365         spin_lock_irqsave(&udc->lock, flags);
2366
2367         seq_printf(s, "%s, version: " DRIVER_VERSION
2368 #ifdef  USE_ISO
2369                 " (iso)"
2370 #endif
2371                 "%s\n",
2372                 driver_desc,
2373                 use_dma ?  " (dma)" : "");
2374
2375         tmp = UDC_REV_REG & 0xff;
2376         seq_printf(s,
2377                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2378                 "hmc %d, transceiver %s\n",
2379                 tmp >> 4, tmp & 0xf,
2380                 fifo_mode,
2381                 udc->driver ? udc->driver->driver.name : "(none)",
2382                 HMC,
2383                 udc->transceiver
2384                         ? udc->transceiver->label
2385                         : ((cpu_is_omap1710() || cpu_is_omap24xx())
2386                                 ? "external" : "(none)"));
2387         if (cpu_class_is_omap1()) {
2388                 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2389                         __REG16(ULPD_CLOCK_CTRL),
2390                         __REG16(ULPD_SOFT_REQ),
2391                         __REG16(ULPD_STATUS_REQ));
2392         }
2393
2394         /* OTG controller registers */
2395         if (!cpu_is_omap15xx())
2396                 proc_otg_show(s);
2397
2398         tmp = UDC_SYSCON1_REG;
2399         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2400                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2401                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2402                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2403                 (tmp & UDC_NAK_EN) ? " nak" : "",
2404                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2405                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2406                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2407                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2408         // syscon2 is write-only
2409
2410         /* UDC controller registers */
2411         if (!(tmp & UDC_PULLUP_EN)) {
2412                 seq_printf(s, "(suspended)\n");
2413                 spin_unlock_irqrestore(&udc->lock, flags);
2414                 return 0;
2415         }
2416
2417         tmp = UDC_DEVSTAT_REG;
2418         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2419                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2420                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2421                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2422                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2423                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2424                 (tmp & UDC_SUS) ? " SUS" : "",
2425                 (tmp & UDC_CFG) ? " CFG" : "",
2426                 (tmp & UDC_ADD) ? " ADD" : "",
2427                 (tmp & UDC_DEF) ? " DEF" : "",
2428                 (tmp & UDC_ATT) ? " ATT" : "");
2429         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2430         tmp = UDC_IRQ_EN_REG;
2431         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2432                 (tmp & UDC_SOF_IE) ? " sof" : "",
2433                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2434                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2435                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2436                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2437         tmp = UDC_IRQ_SRC_REG;
2438         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2439                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2440                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2441                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2442                 (tmp & UDC_SOF) ? " sof" : "",
2443                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2444                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2445                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2446                 (tmp & UDC_SETUP) ? " setup" : "",
2447                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2448                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2449         if (use_dma) {
2450                 unsigned i;
2451
2452                 tmp = UDC_DMA_IRQ_EN_REG;
2453                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2454                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2455                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2456                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2457
2458                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2459                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2460                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2461
2462                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2463                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2464                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2465
2466                 tmp = UDC_RXDMA_CFG_REG;
2467                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2468                 if (tmp) {
2469                         for (i = 0; i < 3; i++) {
2470                                 if ((tmp & (0x0f << (i * 4))) == 0)
2471                                         continue;
2472                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2473                                                 UDC_RXDMA_REG(i + 1));
2474                         }
2475                 }
2476                 tmp = UDC_TXDMA_CFG_REG;
2477                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2478                 if (tmp) {
2479                         for (i = 0; i < 3; i++) {
2480                                 if (!(tmp & (0x0f << (i * 4))))
2481                                         continue;
2482                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2483                                                 UDC_TXDMA_REG(i + 1));
2484                         }
2485                 }
2486         }
2487
2488         tmp = UDC_DEVSTAT_REG;
2489         if (tmp & UDC_ATT) {
2490                 proc_ep_show(s, &udc->ep[0]);
2491                 if (tmp & UDC_ADD) {
2492                         list_for_each_entry (ep, &udc->gadget.ep_list,
2493                                         ep.ep_list) {
2494                                 if (ep->desc)
2495                                         proc_ep_show(s, ep);
2496                         }
2497                 }
2498         }
2499         spin_unlock_irqrestore(&udc->lock, flags);
2500         return 0;
2501 }
2502
2503 static int proc_udc_open(struct inode *inode, struct file *file)
2504 {
2505         return single_open(file, proc_udc_show, NULL);
2506 }
2507
2508 static const struct file_operations proc_ops = {
2509         .open           = proc_udc_open,
2510         .read           = seq_read,
2511         .llseek         = seq_lseek,
2512         .release        = single_release,
2513 };
2514
2515 static void create_proc_file(void)
2516 {
2517         struct proc_dir_entry *pde;
2518
2519         pde = create_proc_entry (proc_filename, 0, NULL);
2520         if (pde)
2521                 pde->proc_fops = &proc_ops;
2522 }
2523
2524 static void remove_proc_file(void)
2525 {
2526         remove_proc_entry(proc_filename, NULL);
2527 }
2528
2529 #else
2530
2531 static inline void create_proc_file(void) {}
2532 static inline void remove_proc_file(void) {}
2533
2534 #endif
2535
2536 /*-------------------------------------------------------------------------*/
2537
2538 /* Before this controller can enumerate, we need to pick an endpoint
2539  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2540  * buffer space among the endpoints we'll be operating.
2541  *
2542  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2543  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2544  * capability yet though.
2545  */
2546 static unsigned __init
2547 omap_ep_setup(char *name, u8 addr, u8 type,
2548                 unsigned buf, unsigned maxp, int dbuf)
2549 {
2550         struct omap_ep  *ep;
2551         u16             epn_rxtx = 0;
2552
2553         /* OUT endpoints first, then IN */
2554         ep = &udc->ep[addr & 0xf];
2555         if (addr & USB_DIR_IN)
2556                 ep += 16;
2557
2558         /* in case of ep init table bugs */
2559         BUG_ON(ep->name[0]);
2560
2561         /* chip setup ... bit values are same for IN, OUT */
2562         if (type == USB_ENDPOINT_XFER_ISOC) {
2563                 switch (maxp) {
2564                 case 8:         epn_rxtx = 0 << 12; break;
2565                 case 16:        epn_rxtx = 1 << 12; break;
2566                 case 32:        epn_rxtx = 2 << 12; break;
2567                 case 64:        epn_rxtx = 3 << 12; break;
2568                 case 128:       epn_rxtx = 4 << 12; break;
2569                 case 256:       epn_rxtx = 5 << 12; break;
2570                 case 512:       epn_rxtx = 6 << 12; break;
2571                 default:        BUG();
2572                 }
2573                 epn_rxtx |= UDC_EPN_RX_ISO;
2574                 dbuf = 1;
2575         } else {
2576                 /* double-buffering "not supported" on 15xx,
2577                  * and ignored for PIO-IN on newer chips
2578                  * (for more reliable behavior)
2579                  */
2580                 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2581                         dbuf = 0;
2582
2583                 switch (maxp) {
2584                 case 8:         epn_rxtx = 0 << 12; break;
2585                 case 16:        epn_rxtx = 1 << 12; break;
2586                 case 32:        epn_rxtx = 2 << 12; break;
2587                 case 64:        epn_rxtx = 3 << 12; break;
2588                 default:        BUG();
2589                 }
2590                 if (dbuf && addr)
2591                         epn_rxtx |= UDC_EPN_RX_DB;
2592                 init_timer(&ep->timer);
2593                 ep->timer.function = pio_out_timer;
2594                 ep->timer.data = (unsigned long) ep;
2595         }
2596         if (addr)
2597                 epn_rxtx |= UDC_EPN_RX_VALID;
2598         BUG_ON(buf & 0x07);
2599         epn_rxtx |= buf >> 3;
2600
2601         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2602                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2603
2604         if (addr & USB_DIR_IN)
2605                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2606         else
2607                 UDC_EP_RX_REG(addr) = epn_rxtx;
2608
2609         /* next endpoint's buffer starts after this one's */
2610         buf += maxp;
2611         if (dbuf)
2612                 buf += maxp;
2613         BUG_ON(buf > 2048);
2614
2615         /* set up driver data structures */
2616         BUG_ON(strlen(name) >= sizeof ep->name);
2617         strlcpy(ep->name, name, sizeof ep->name);
2618         INIT_LIST_HEAD(&ep->queue);
2619         INIT_LIST_HEAD(&ep->iso);
2620         ep->bEndpointAddress = addr;
2621         ep->bmAttributes = type;
2622         ep->double_buf = dbuf;
2623         ep->udc = udc;
2624
2625         ep->ep.name = ep->name;
2626         ep->ep.ops = &omap_ep_ops;
2627         ep->ep.maxpacket = ep->maxpacket = maxp;
2628         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2629
2630         return buf;
2631 }
2632
2633 static void omap_udc_release(struct device *dev)
2634 {
2635         complete(udc->done);
2636         kfree (udc);
2637         udc = NULL;
2638 }
2639
2640 static int __init
2641 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2642 {
2643         unsigned        tmp, buf;
2644
2645         /* abolish any previous hardware state */
2646         UDC_SYSCON1_REG = 0;
2647         UDC_IRQ_EN_REG = 0;
2648         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2649         UDC_DMA_IRQ_EN_REG = 0;
2650         UDC_RXDMA_CFG_REG = 0;
2651         UDC_TXDMA_CFG_REG = 0;
2652
2653         /* UDC_PULLUP_EN gates the chip clock */
2654         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2655
2656         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2657         if (!udc)
2658                 return -ENOMEM;
2659
2660         spin_lock_init (&udc->lock);
2661
2662         udc->gadget.ops = &omap_gadget_ops;
2663         udc->gadget.ep0 = &udc->ep[0].ep;
2664         INIT_LIST_HEAD(&udc->gadget.ep_list);
2665         INIT_LIST_HEAD(&udc->iso);
2666         udc->gadget.speed = USB_SPEED_UNKNOWN;
2667         udc->gadget.name = driver_name;
2668
2669         device_initialize(&udc->gadget.dev);
2670         strcpy (udc->gadget.dev.bus_id, "gadget");
2671         udc->gadget.dev.release = omap_udc_release;
2672         udc->gadget.dev.parent = &odev->dev;
2673         if (use_dma)
2674                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2675
2676         udc->transceiver = xceiv;
2677
2678         /* ep0 is special; put it right after the SETUP buffer */
2679         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2680                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2681         list_del_init(&udc->ep[0].ep.ep_list);
2682
2683         /* initially disable all non-ep0 endpoints */
2684         for (tmp = 1; tmp < 15; tmp++) {
2685                 UDC_EP_RX_REG(tmp) = 0;
2686                 UDC_EP_TX_REG(tmp) = 0;
2687         }
2688
2689 #define OMAP_BULK_EP(name,addr) \
2690         buf = omap_ep_setup(name "-bulk", addr, \
2691                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2692 #define OMAP_INT_EP(name,addr, maxp) \
2693         buf = omap_ep_setup(name "-int", addr, \
2694                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2695 #define OMAP_ISO_EP(name,addr, maxp) \
2696         buf = omap_ep_setup(name "-iso", addr, \
2697                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2698
2699         switch (fifo_mode) {
2700         case 0:
2701                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2702                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2703                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2704                 break;
2705         case 1:
2706                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2707                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2708                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2709
2710                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2711                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2712                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2713
2714                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2715                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2716                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2717
2718                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2719                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2720                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2721
2722                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2723                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2724                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2725                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2726
2727                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2728                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2729                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2730                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2731
2732                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2733                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2734
2735                 break;
2736
2737 #ifdef  USE_ISO
2738         case 2:                 /* mixed iso/bulk */
2739                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2740                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2741                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2742                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2743
2744                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2745
2746                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2747                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2748                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2749                 break;
2750         case 3:                 /* mixed bulk/iso */
2751                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2752                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2753                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2754
2755                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2756                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2757                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2758
2759                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2760                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2761                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2762                 break;
2763 #endif
2764
2765         /* add more modes as needed */
2766
2767         default:
2768                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2769                 return -ENODEV;
2770         }
2771         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2772         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2773         return 0;
2774 }
2775
2776 static int __init omap_udc_probe(struct platform_device *pdev)
2777 {
2778         int                     status = -ENODEV;
2779         int                     hmc;
2780         struct otg_transceiver  *xceiv = NULL;
2781         const char              *type = NULL;
2782         struct omap_usb_config  *config = pdev->dev.platform_data;
2783         struct clk              *dc_clk;
2784         struct clk              *hhc_clk;
2785
2786         /* NOTE:  "knows" the order of the resources! */
2787         if (!request_mem_region(pdev->resource[0].start,
2788                         pdev->resource[0].end - pdev->resource[0].start + 1,
2789                         driver_name)) {
2790                 DBG("request_mem_region failed\n");
2791                 return -EBUSY;
2792         }
2793
2794         if (cpu_is_omap16xx()) {
2795                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2796                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2797                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2798                 /* can't use omap_udc_enable_clock yet */
2799                 clk_enable(dc_clk);
2800                 clk_enable(hhc_clk);
2801                 udelay(100);
2802         }
2803
2804         if (cpu_is_omap24xx()) {
2805                 dc_clk = clk_get(&pdev->dev, "usb_fck");
2806                 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2807                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2808                 /* can't use omap_udc_enable_clock yet */
2809                 clk_enable(dc_clk);
2810                 clk_enable(hhc_clk);
2811                 udelay(100);
2812         }
2813
2814         INFO("OMAP UDC rev %d.%d%s\n",
2815                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2816                 config->otg ? ", Mini-AB" : "");
2817
2818         /* use the mode given to us by board init code */
2819         if (cpu_is_omap15xx()) {
2820                 hmc = HMC_1510;
2821                 type = "(unknown)";
2822
2823                 if (machine_without_vbus_sense()) {
2824                         /* just set up software VBUS detect, and then
2825                          * later rig it so we always report VBUS.
2826                          * FIXME without really sensing VBUS, we can't
2827                          * know when to turn PULLUP_EN on/off; and that
2828                          * means we always "need" the 48MHz clock.
2829                          */
2830                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2831
2832                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2833                         tmp |= VBUS_MODE_1510;
2834                         tmp &= ~VBUS_CTRL_1510;
2835                         FUNC_MUX_CTRL_0_REG = tmp;
2836                 }
2837         } else {
2838                 /* The transceiver may package some GPIO logic or handle
2839                  * loopback and/or transceiverless setup; if we find one,
2840                  * use it.  Except for OTG, we don't _need_ to talk to one;
2841                  * but not having one probably means no VBUS detection.
2842                  */
2843                 xceiv = otg_get_transceiver();
2844                 if (xceiv)
2845                         type = xceiv->label;
2846                 else if (config->otg) {
2847                         DBG("OTG requires external transceiver!\n");
2848                         goto cleanup0;
2849                 }
2850
2851                 hmc = HMC_1610;
2852
2853                 if (cpu_is_omap24xx()) {
2854                         /* this could be transceiverless in one of the
2855                          * "we don't need to know" modes.
2856                          */
2857                         type = "external";
2858                         goto known;
2859                 }
2860
2861                 switch (hmc) {
2862                 case 0:                 /* POWERUP DEFAULT == 0 */
2863                 case 4:
2864                 case 12:
2865                 case 20:
2866                         if (!cpu_is_omap1710()) {
2867                                 type = "integrated";
2868                                 break;
2869                         }
2870                         /* FALL THROUGH */
2871                 case 3:
2872                 case 11:
2873                 case 16:
2874                 case 19:
2875                 case 25:
2876                         if (!xceiv) {
2877                                 DBG("external transceiver not registered!\n");
2878                                 type = "unknown";
2879                         }
2880                         break;
2881                 case 21:                        /* internal loopback */
2882                         type = "loopback";
2883                         break;
2884                 case 14:                        /* transceiverless */
2885                         if (cpu_is_omap1710())
2886                                 goto bad_on_1710;
2887                         /* FALL THROUGH */
2888                 case 13:
2889                 case 15:
2890                         type = "no";
2891                         break;
2892
2893                 default:
2894 bad_on_1710:
2895                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2896                         goto cleanup0;
2897                 }
2898         }
2899 known:
2900         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2901
2902         /* a "gadget" abstracts/virtualizes the controller */
2903         status = omap_udc_setup(pdev, xceiv);
2904         if (status) {
2905                 goto cleanup0;
2906         }
2907         xceiv = NULL;
2908         // "udc" is now valid
2909         pullup_disable(udc);
2910 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2911         udc->gadget.is_otg = (config->otg != 0);
2912 #endif
2913
2914         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2915         if (UDC_REV_REG >= 0x61)
2916                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2917         else
2918                 udc->clr_halt = UDC_RESET_EP;
2919
2920         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2921         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2922                         IRQF_SAMPLE_RANDOM, driver_name, udc);
2923         if (status != 0) {
2924                 ERR("can't get irq %d, err %d\n",
2925                         (int) pdev->resource[1].start, status);
2926                 goto cleanup1;
2927         }
2928
2929         /* USB "non-iso" IRQ (PIO for all but ep0) */
2930         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2931                         IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2932         if (status != 0) {
2933                 ERR("can't get irq %d, err %d\n",
2934                         (int) pdev->resource[2].start, status);
2935                 goto cleanup2;
2936         }
2937 #ifdef  USE_ISO
2938         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2939                         IRQF_DISABLED, "omap_udc iso", udc);
2940         if (status != 0) {
2941                 ERR("can't get irq %d, err %d\n",
2942                         (int) pdev->resource[3].start, status);
2943                 goto cleanup3;
2944         }
2945 #endif
2946         if (cpu_is_omap16xx()) {
2947                 udc->dc_clk = dc_clk;
2948                 udc->hhc_clk = hhc_clk;
2949                 clk_disable(hhc_clk);
2950                 clk_disable(dc_clk);
2951         }
2952
2953         if (cpu_is_omap24xx()) {
2954                 udc->dc_clk = dc_clk;
2955                 udc->hhc_clk = hhc_clk;
2956                 /* FIXME OMAP2 don't release hhc & dc clock */
2957 #if 0
2958                 clk_disable(hhc_clk);
2959                 clk_disable(dc_clk);
2960 #endif
2961         }
2962
2963         create_proc_file();
2964         status = device_add(&udc->gadget.dev);
2965         if (!status)
2966                 return status;
2967         /* If fail, fall through */
2968 #ifdef  USE_ISO
2969 cleanup3:
2970         free_irq(pdev->resource[2].start, udc);
2971 #endif
2972
2973 cleanup2:
2974         free_irq(pdev->resource[1].start, udc);
2975
2976 cleanup1:
2977         kfree (udc);
2978         udc = NULL;
2979
2980 cleanup0:
2981         if (xceiv)
2982                 put_device(xceiv->dev);
2983
2984         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
2985                 clk_disable(hhc_clk);
2986                 clk_disable(dc_clk);
2987                 clk_put(hhc_clk);
2988                 clk_put(dc_clk);
2989         }
2990
2991         release_mem_region(pdev->resource[0].start,
2992                         pdev->resource[0].end - pdev->resource[0].start + 1);
2993
2994         return status;
2995 }
2996
2997 static int __exit omap_udc_remove(struct platform_device *pdev)
2998 {
2999         DECLARE_COMPLETION_ONSTACK(done);
3000
3001         if (!udc)
3002                 return -ENODEV;
3003         if (udc->driver)
3004                 return -EBUSY;
3005
3006         udc->done = &done;
3007
3008         pullup_disable(udc);
3009         if (udc->transceiver) {
3010                 put_device(udc->transceiver->dev);
3011                 udc->transceiver = NULL;
3012         }
3013         UDC_SYSCON1_REG = 0;
3014
3015         remove_proc_file();
3016
3017 #ifdef  USE_ISO
3018         free_irq(pdev->resource[3].start, udc);
3019 #endif
3020         free_irq(pdev->resource[2].start, udc);
3021         free_irq(pdev->resource[1].start, udc);
3022
3023         if (udc->dc_clk) {
3024                 if (udc->clk_requested)
3025                         omap_udc_enable_clock(0);
3026                 clk_put(udc->hhc_clk);
3027                 clk_put(udc->dc_clk);
3028         }
3029
3030         release_mem_region(pdev->resource[0].start,
3031                         pdev->resource[0].end - pdev->resource[0].start + 1);
3032
3033         device_unregister(&udc->gadget.dev);
3034         wait_for_completion(&done);
3035
3036         return 0;
3037 }
3038
3039 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3040  * system is forced into deep sleep
3041  *
3042  * REVISIT we should probably reject suspend requests when there's a host
3043  * session active, rather than disconnecting, at least on boards that can
3044  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
3045  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3046  * may involve talking to an external transceiver (e.g. isp1301).
3047  */
3048
3049 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3050 {
3051         u32     devstat;
3052
3053         devstat = UDC_DEVSTAT_REG;
3054
3055         /* we're requesting 48 MHz clock if the pullup is enabled
3056          * (== we're attached to the host) and we're not suspended,
3057          * which would prevent entry to deep sleep...
3058          */
3059         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3060                 WARN("session active; suspend requires disconnect\n");
3061                 omap_pullup(&udc->gadget, 0);
3062         }
3063
3064         udc->gadget.dev.power.power_state = PMSG_SUSPEND;
3065         udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
3066         return 0;
3067 }
3068
3069 static int omap_udc_resume(struct platform_device *dev)
3070 {
3071         DBG("resume + wakeup/SRP\n");
3072         omap_pullup(&udc->gadget, 1);
3073
3074         /* maybe the host would enumerate us if we nudged it */
3075         msleep(100);
3076         return omap_wakeup(&udc->gadget);
3077 }
3078
3079 /*-------------------------------------------------------------------------*/
3080
3081 static struct platform_driver udc_driver = {
3082         .probe          = omap_udc_probe,
3083         .remove         = __exit_p(omap_udc_remove),
3084         .suspend        = omap_udc_suspend,
3085         .resume         = omap_udc_resume,
3086         .driver         = {
3087                 .owner  = THIS_MODULE,
3088                 .name   = (char *) driver_name,
3089         },
3090 };
3091
3092 static int __init udc_init(void)
3093 {
3094         INFO("%s, version: " DRIVER_VERSION
3095 #ifdef  USE_ISO
3096                 " (iso)"
3097 #endif
3098                 "%s\n", driver_desc,
3099                 use_dma ?  " (dma)" : "");
3100         return platform_driver_register(&udc_driver);
3101 }
3102 module_init(udc_init);
3103
3104 static void __exit udc_exit(void)
3105 {
3106         platform_driver_unregister(&udc_driver);
3107 }
3108 module_exit(udc_exit);
3109
3110 MODULE_DESCRIPTION(DRIVER_DESC);
3111 MODULE_LICENSE("GPL");
3112 MODULE_ALIAS("platform:omap_udc");