git.oblomov.eu Git - linux-2.6/blob - drivers/usb/gadget/pxa2xx_udc.c

   1 /*
   2  * linux/drivers/usb/gadget/pxa2xx_udc.c
   3  * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
   4  *
   5  * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
   6  * Copyright (C) 2003 Robert Schwebel, Pengutronix
   7  * Copyright (C) 2003 Benedikt Spranger, Pengutronix
   8  * Copyright (C) 2003 David Brownell
   9  * Copyright (C) 2003 Joshua Wise
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24  *
  25  */
  26
  27 /* #define VERBOSE_DEBUG */
  28
  29 #include <linux/device.h>
  30 #include <linux/module.h>
  31 #include <linux/kernel.h>
  32 #include <linux/ioport.h>
  33 #include <linux/types.h>
  34 #include <linux/errno.h>
  35 #include <linux/delay.h>
  36 #include <linux/slab.h>
  37 #include <linux/init.h>
  38 #include <linux/timer.h>
  39 #include <linux/list.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/mm.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/irq.h>
  45 #include <linux/clk.h>
  46 #include <linux/err.h>
  47 #include <linux/seq_file.h>
  48 #include <linux/debugfs.h>
  49
  50 #include <asm/byteorder.h>
  51 #include <asm/dma.h>
  52 #include <asm/gpio.h>
  53 #include <asm/io.h>
  54 #include <asm/system.h>
  55 #include <asm/mach-types.h>
  56 #include <asm/unaligned.h>
  57 #include <asm/hardware.h>
  58
  59 #include <linux/usb/ch9.h>
  60 #include <linux/usb/gadget.h>
  61
  62 #include <asm/mach/udc_pxa2xx.h>
  63
  64
  65 /*
  66  * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
  67  * series processors.  The UDC for the IXP 4xx series is very similar.
  68  * There are fifteen endpoints, in addition to ep0.
  69  *
  70  * Such controller drivers work with a gadget driver.  The gadget driver
  71  * returns descriptors, implements configuration and data protocols used
  72  * by the host to interact with this device, and allocates endpoints to
  73  * the different protocol interfaces.  The controller driver virtualizes
  74  * usb hardware so that the gadget drivers will be more portable.
  75  *
  76  * This UDC hardware wants to implement a bit too much USB protocol, so
  77  * it constrains the sorts of USB configuration change events that work.
  78  * The errata for these chips are misleading; some "fixed" bugs from
  79  * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
  80  *
  81  * Note that the UDC hardware supports DMA (except on IXP) but that's
  82  * not used here.  IN-DMA (to host) is simple enough, when the data is
  83  * suitably aligned (16 bytes) ... the network stack doesn't do that,
  84  * other software can.  OUT-DMA is buggy in most chip versions, as well
  85  * as poorly designed (data toggle not automatic).  So this driver won't
  86  * bother using DMA.  (Mostly-working IN-DMA support was available in
  87  * kernels before 2.6.23, but was never enabled or well tested.)
  88  */
  89
  90 #define DRIVER_VERSION  "30-June-2007"
  91 #define DRIVER_DESC     "PXA 25x USB Device Controller driver"
  92
  93
  94 static const char driver_name [] = "pxa2xx_udc";
  95
  96 static const char ep0name [] = "ep0";
  97
  98
  99 #ifdef CONFIG_ARCH_IXP4XX
 100
 101 /* cpu-specific register addresses are compiled in to this code */
 102 #ifdef CONFIG_ARCH_PXA
 103 #error "Can't configure both IXP and PXA"
 104 #endif
 105
 106 /* IXP doesn't yet support <linux/clk.h> */
 107 #define clk_get(dev,name)       NULL
 108 #define clk_enable(clk)         do { } while (0)
 109 #define clk_disable(clk)        do { } while (0)
 110 #define clk_put(clk)            do { } while (0)
 111
 112 #endif
 113
 114 #include "pxa2xx_udc.h"
 115
 116
 117 #ifdef  CONFIG_USB_PXA2XX_SMALL
 118 #define SIZE_STR        " (small)"
 119 #else
 120 #define SIZE_STR        ""
 121 #endif
 122
 123 /* ---------------------------------------------------------------------------
 124  *      endpoint related parts of the api to the usb controller hardware,
 125  *      used by gadget driver; and the inner talker-to-hardware core.
 126  * ---------------------------------------------------------------------------
 127  */
 128
 129 static void pxa2xx_ep_fifo_flush (struct usb_ep *ep);
 130 static void nuke (struct pxa2xx_ep *, int status);
 131
 132 /* one GPIO should be used to detect VBUS from the host */
 133 static int is_vbus_present(void)
 134 {
 135         struct pxa2xx_udc_mach_info             *mach = the_controller->mach;
 136
 137         if (mach->gpio_vbus) {
 138                 int value = gpio_get_value(mach->gpio_vbus);
 139                 return mach->gpio_vbus_inverted ? !value : value;
 140         }
 141         if (mach->udc_is_connected)
 142                 return mach->udc_is_connected();
 143         return 1;
 144 }
 145
 146 /* one GPIO should control a D+ pullup, so host sees this device (or not) */
 147 static void pullup_off(void)
 148 {
 149         struct pxa2xx_udc_mach_info             *mach = the_controller->mach;
 150
 151         if (mach->gpio_pullup)
 152                 gpio_set_value(mach->gpio_pullup, 0);
 153         else if (mach->udc_command)
 154                 mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
 155 }
 156
 157 static void pullup_on(void)
 158 {
 159         struct pxa2xx_udc_mach_info             *mach = the_controller->mach;
 160
 161         if (mach->gpio_pullup)
 162                 gpio_set_value(mach->gpio_pullup, 1);
 163         else if (mach->udc_command)
 164                 mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
 165 }
 166
 167 static void pio_irq_enable(int bEndpointAddress)
 168 {
 169         bEndpointAddress &= 0xf;
 170         if (bEndpointAddress < 8)
 171                 UICR0 &= ~(1 << bEndpointAddress);
 172         else {
 173                 bEndpointAddress -= 8;
 174                 UICR1 &= ~(1 << bEndpointAddress);
 175         }
 176 }
 177
 178 static void pio_irq_disable(int bEndpointAddress)
 179 {
 180         bEndpointAddress &= 0xf;
 181         if (bEndpointAddress < 8)
 182                 UICR0 |= 1 << bEndpointAddress;
 183         else {
 184                 bEndpointAddress -= 8;
 185                 UICR1 |= 1 << bEndpointAddress;
 186         }
 187 }
 188
 189 /* The UDCCR reg contains mask and interrupt status bits,
 190  * so using '|=' isn't safe as it may ack an interrupt.
 191  */
 192 #define UDCCR_MASK_BITS         (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
 193
 194 static inline void udc_set_mask_UDCCR(int mask)
 195 {
 196         UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
 197 }
 198
 199 static inline void udc_clear_mask_UDCCR(int mask)
 200 {
 201         UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
 202 }
 203
 204 static inline void udc_ack_int_UDCCR(int mask)
 205 {
 206         /* udccr contains the bits we dont want to change */
 207         __u32 udccr = UDCCR & UDCCR_MASK_BITS;
 208
 209         UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
 210 }
 211
 212 /*
 213  * endpoint enable/disable
 214  *
 215  * we need to verify the descriptors used to enable endpoints.  since pxa2xx
 216  * endpoint configurations are fixed, and are pretty much always enabled,
 217  * there's not a lot to manage here.
 218  *
 219  * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
 220  * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
 221  * for a single interface (with only the default altsetting) and for gadget
 222  * drivers that don't halt endpoints (not reset by set_interface).  that also
 223  * means that if you use ISO, you must violate the USB spec rule that all
 224  * iso endpoints must be in non-default altsettings.
 225  */
 226 static int pxa2xx_ep_enable (struct usb_ep *_ep,
 227                 const struct usb_endpoint_descriptor *desc)
 228 {
 229         struct pxa2xx_ep        *ep;
 230         struct pxa2xx_udc       *dev;
 231
 232         ep = container_of (_ep, struct pxa2xx_ep, ep);
 233         if (!_ep || !desc || ep->desc || _ep->name == ep0name
 234                         || desc->bDescriptorType != USB_DT_ENDPOINT
 235                         || ep->bEndpointAddress != desc->bEndpointAddress
 236                         || ep->fifo_size < le16_to_cpu
 237                                                 (desc->wMaxPacketSize)) {
 238                 DMSG("%s, bad ep or descriptor\n", __FUNCTION__);
 239                 return -EINVAL;
 240         }
 241
 242         /* xfer types must match, except that interrupt ~= bulk */
 243         if (ep->bmAttributes != desc->bmAttributes
 244                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 245                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 246                 DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 247                 return -EINVAL;
 248         }
 249
 250         /* hardware _could_ do smaller, but driver doesn't */
 251         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 252                                 && le16_to_cpu (desc->wMaxPacketSize)
 253                                                 != BULK_FIFO_SIZE)
 254                         || !desc->wMaxPacketSize) {
 255                 DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 256                 return -ERANGE;
 257         }
 258
 259         dev = ep->dev;
 260         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
 261                 DMSG("%s, bogus device state\n", __FUNCTION__);
 262                 return -ESHUTDOWN;
 263         }
 264
 265         ep->desc = desc;
 266         ep->stopped = 0;
 267         ep->pio_irqs = 0;
 268         ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
 269
 270         /* flush fifo (mostly for OUT buffers) */
 271         pxa2xx_ep_fifo_flush (_ep);
 272
 273         /* ... reset halt state too, if we could ... */
 274
 275         DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
 276         return 0;
 277 }
 278
 279 static int pxa2xx_ep_disable (struct usb_ep *_ep)
 280 {
 281         struct pxa2xx_ep        *ep;
 282         unsigned long           flags;
 283
 284         ep = container_of (_ep, struct pxa2xx_ep, ep);
 285         if (!_ep || !ep->desc) {
 286                 DMSG("%s, %s not enabled\n", __FUNCTION__,
 287                         _ep ? ep->ep.name : NULL);
 288                 return -EINVAL;
 289         }
 290         local_irq_save(flags);
 291
 292         nuke (ep, -ESHUTDOWN);
 293
 294         /* flush fifo (mostly for IN buffers) */
 295         pxa2xx_ep_fifo_flush (_ep);
 296
 297         ep->desc = NULL;
 298         ep->stopped = 1;
 299
 300         local_irq_restore(flags);
 301         DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
 302         return 0;
 303 }
 304
 305 /*-------------------------------------------------------------------------*/
 306
 307 /* for the pxa2xx, these can just wrap kmalloc/kfree.  gadget drivers
 308  * must still pass correctly initialized endpoints, since other controller
 309  * drivers may care about how it's currently set up (dma issues etc).
 310  */
 311
 312 /*
 313  *      pxa2xx_ep_alloc_request - allocate a request data structure
 314  */
 315 static struct usb_request *
 316 pxa2xx_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags)
 317 {
 318         struct pxa2xx_request *req;
 319
 320         req = kzalloc(sizeof(*req), gfp_flags);
 321         if (!req)
 322                 return NULL;
 323
 324         INIT_LIST_HEAD (&req->queue);
 325         return &req->req;
 326 }
 327
 328
 329 /*
 330  *      pxa2xx_ep_free_request - deallocate a request data structure
 331  */
 332 static void
 333 pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
 334 {
 335         struct pxa2xx_request   *req;
 336
 337         req = container_of (_req, struct pxa2xx_request, req);
 338         WARN_ON (!list_empty (&req->queue));
 339         kfree(req);
 340 }
 341
 342 /*-------------------------------------------------------------------------*/
 343
 344 /*
 345  *      done - retire a request; caller blocked irqs
 346  */
 347 static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status)
 348 {
 349         unsigned                stopped = ep->stopped;
 350
 351         list_del_init(&req->queue);
 352
 353         if (likely (req->req.status == -EINPROGRESS))
 354                 req->req.status = status;
 355         else
 356                 status = req->req.status;
 357
 358         if (status && status != -ESHUTDOWN)
 359                 DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
 360                         ep->ep.name, &req->req, status,
 361                         req->req.actual, req->req.length);
 362
 363         /* don't modify queue heads during completion callback */
 364         ep->stopped = 1;
 365         req->req.complete(&ep->ep, &req->req);
 366         ep->stopped = stopped;
 367 }
 368
 369
 370 static inline void ep0_idle (struct pxa2xx_udc *dev)
 371 {
 372         dev->ep0state = EP0_IDLE;
 373 }
 374
 375 static int
 376 write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max)
 377 {
 378         u8              *buf;
 379         unsigned        length, count;
 380
 381         buf = req->req.buf + req->req.actual;
 382         prefetch(buf);
 383
 384         /* how big will this packet be? */
 385         length = min(req->req.length - req->req.actual, max);
 386         req->req.actual += length;
 387
 388         count = length;
 389         while (likely(count--))
 390                 *uddr = *buf++;
 391
 392         return length;
 393 }
 394
 395 /*
 396  * write to an IN endpoint fifo, as many packets as possible.
 397  * irqs will use this to write the rest later.
 398  * caller guarantees at least one packet buffer is ready (or a zlp).
 399  */
 400 static int
 401 write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 402 {
 403         unsigned                max;
 404
 405         max = le16_to_cpu(ep->desc->wMaxPacketSize);
 406         do {
 407                 unsigned        count;
 408                 int             is_last, is_short;
 409
 410                 count = write_packet(ep->reg_uddr, req, max);
 411
 412                 /* last packet is usually short (or a zlp) */
 413                 if (unlikely (count != max))
 414                         is_last = is_short = 1;
 415                 else {
 416                         if (likely(req->req.length != req->req.actual)
 417                                         || req->req.zero)
 418                                 is_last = 0;
 419                         else
 420                                 is_last = 1;
 421                         /* interrupt/iso maxpacket may not fill the fifo */
 422                         is_short = unlikely (max < ep->fifo_size);
 423                 }
 424
 425                 DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
 426                         ep->ep.name, count,
 427                         is_last ? "/L" : "", is_short ? "/S" : "",
 428                         req->req.length - req->req.actual, req);
 429
 430                 /* let loose that packet. maybe try writing another one,
 431                  * double buffering might work.  TSP, TPC, and TFS
 432                  * bit values are the same for all normal IN endpoints.
 433                  */
 434                 *ep->reg_udccs = UDCCS_BI_TPC;
 435                 if (is_short)
 436                         *ep->reg_udccs = UDCCS_BI_TSP;
 437
 438                 /* requests complete when all IN data is in the FIFO */
 439                 if (is_last) {
 440                         done (ep, req, 0);
 441                         if (list_empty(&ep->queue))
 442                                 pio_irq_disable (ep->bEndpointAddress);
 443                         return 1;
 444                 }
 445
 446                 // TODO experiment: how robust can fifo mode tweaking be?
 447                 // double buffering is off in the default fifo mode, which
 448                 // prevents TFS from being set here.
 449
 450         } while (*ep->reg_udccs & UDCCS_BI_TFS);
 451         return 0;
 452 }
 453
 454 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
 455  * ep0 data stage.  these chips want very simple state transitions.
 456  */
 457 static inline
 458 void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag)
 459 {
 460         UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR;
 461         USIR0 = USIR0_IR0;
 462         dev->req_pending = 0;
 463         DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
 464                 __FUNCTION__, tag, UDCCS0, flags);
 465 }
 466
 467 static int
 468 write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 469 {
 470         unsigned        count;
 471         int             is_short;
 472
 473         count = write_packet(&UDDR0, req, EP0_FIFO_SIZE);
 474         ep->dev->stats.write.bytes += count;
 475
 476         /* last packet "must be" short (or a zlp) */
 477         is_short = (count != EP0_FIFO_SIZE);
 478
 479         DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
 480                 req->req.length - req->req.actual, req);
 481
 482         if (unlikely (is_short)) {
 483                 if (ep->dev->req_pending)
 484                         ep0start(ep->dev, UDCCS0_IPR, "short IN");
 485                 else
 486                         UDCCS0 = UDCCS0_IPR;
 487
 488                 count = req->req.length;
 489                 done (ep, req, 0);
 490                 ep0_idle(ep->dev);
 491 #ifndef CONFIG_ARCH_IXP4XX
 492 #if 1
 493                 /* This seems to get rid of lost status irqs in some cases:
 494                  * host responds quickly, or next request involves config
 495                  * change automagic, or should have been hidden, or ...
 496                  *
 497                  * FIXME get rid of all udelays possible...
 498                  */
 499                 if (count >= EP0_FIFO_SIZE) {
 500                         count = 100;
 501                         do {
 502                                 if ((UDCCS0 & UDCCS0_OPR) != 0) {
 503                                         /* clear OPR, generate ack */
 504                                         UDCCS0 = UDCCS0_OPR;
 505                                         break;
 506                                 }
 507                                 count--;
 508                                 udelay(1);
 509                         } while (count);
 510                 }
 511 #endif
 512 #endif
 513         } else if (ep->dev->req_pending)
 514                 ep0start(ep->dev, 0, "IN");
 515         return is_short;
 516 }
 517
 518
 519 /*
 520  * read_fifo -  unload packet(s) from the fifo we use for usb OUT
 521  * transfers and put them into the request.  caller should have made
 522  * sure there's at least one packet ready.
 523  *
 524  * returns true if the request completed because of short packet or the
 525  * request buffer having filled (and maybe overran till end-of-packet).
 526  */
 527 static int
 528 read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 529 {
 530         for (;;) {
 531                 u32             udccs;
 532                 u8              *buf;
 533                 unsigned        bufferspace, count, is_short;
 534
 535                 /* make sure there's a packet in the FIFO.
 536                  * UDCCS_{BO,IO}_RPC are all the same bit value.
 537                  * UDCCS_{BO,IO}_RNE are all the same bit value.
 538                  */
 539                 udccs = *ep->reg_udccs;
 540                 if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
 541                         break;
 542                 buf = req->req.buf + req->req.actual;
 543                 prefetchw(buf);
 544                 bufferspace = req->req.length - req->req.actual;
 545
 546                 /* read all bytes from this packet */
 547                 if (likely (udccs & UDCCS_BO_RNE)) {
 548                         count = 1 + (0x0ff & *ep->reg_ubcr);
 549                         req->req.actual += min (count, bufferspace);
 550                 } else /* zlp */
 551                         count = 0;
 552                 is_short = (count < ep->ep.maxpacket);
 553                 DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
 554                         ep->ep.name, udccs, count,
 555                         is_short ? "/S" : "",
 556                         req, req->req.actual, req->req.length);
 557                 while (likely (count-- != 0)) {
 558                         u8      byte = (u8) *ep->reg_uddr;
 559
 560                         if (unlikely (bufferspace == 0)) {
 561                                 /* this happens when the driver's buffer
 562                                  * is smaller than what the host sent.
 563                                  * discard the extra data.
 564                                  */
 565                                 if (req->req.status != -EOVERFLOW)
 566                                         DMSG("%s overflow %d\n",
 567                                                 ep->ep.name, count);
 568                                 req->req.status = -EOVERFLOW;
 569                         } else {
 570                                 *buf++ = byte;
 571                                 bufferspace--;
 572                         }
 573                 }
 574                 *ep->reg_udccs =  UDCCS_BO_RPC;
 575                 /* RPC/RSP/RNE could now reflect the other packet buffer */
 576
 577                 /* iso is one request per packet */
 578                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 579                         if (udccs & UDCCS_IO_ROF)
 580                                 req->req.status = -EHOSTUNREACH;
 581                         /* more like "is_done" */
 582                         is_short = 1;
 583                 }
 584
 585                 /* completion */
 586                 if (is_short || req->req.actual == req->req.length) {
 587                         done (ep, req, 0);
 588                         if (list_empty(&ep->queue))
 589                                 pio_irq_disable (ep->bEndpointAddress);
 590                         return 1;
 591                 }
 592
 593                 /* finished that packet.  the next one may be waiting... */
 594         }
 595         return 0;
 596 }
 597
 598 /*
 599  * special ep0 version of the above.  no UBCR0 or double buffering; status
 600  * handshaking is magic.  most device protocols don't need control-OUT.
 601  * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
 602  * protocols do use them.
 603  */
 604 static int
 605 read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 606 {
 607         u8              *buf, byte;
 608         unsigned        bufferspace;
 609
 610         buf = req->req.buf + req->req.actual;
 611         bufferspace = req->req.length - req->req.actual;
 612
 613         while (UDCCS0 & UDCCS0_RNE) {
 614                 byte = (u8) UDDR0;
 615
 616                 if (unlikely (bufferspace == 0)) {
 617                         /* this happens when the driver's buffer
 618                          * is smaller than what the host sent.
 619                          * discard the extra data.
 620                          */
 621                         if (req->req.status != -EOVERFLOW)
 622                                 DMSG("%s overflow\n", ep->ep.name);
 623                         req->req.status = -EOVERFLOW;
 624                 } else {
 625                         *buf++ = byte;
 626                         req->req.actual++;
 627                         bufferspace--;
 628                 }
 629         }
 630
 631         UDCCS0 = UDCCS0_OPR | UDCCS0_IPR;
 632
 633         /* completion */
 634         if (req->req.actual >= req->req.length)
 635                 return 1;
 636
 637         /* finished that packet.  the next one may be waiting... */
 638         return 0;
 639 }
 640
 641 /*-------------------------------------------------------------------------*/
 642
 643 static int
 644 pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 645 {
 646         struct pxa2xx_request   *req;
 647         struct pxa2xx_ep        *ep;
 648         struct pxa2xx_udc       *dev;
 649         unsigned long           flags;
 650
 651         req = container_of(_req, struct pxa2xx_request, req);
 652         if (unlikely (!_req || !_req->complete || !_req->buf
 653                         || !list_empty(&req->queue))) {
 654                 DMSG("%s, bad params\n", __FUNCTION__);
 655                 return -EINVAL;
 656         }
 657
 658         ep = container_of(_ep, struct pxa2xx_ep, ep);
 659         if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 660                 DMSG("%s, bad ep\n", __FUNCTION__);
 661                 return -EINVAL;
 662         }
 663
 664         dev = ep->dev;
 665         if (unlikely (!dev->driver
 666                         || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 667                 DMSG("%s, bogus device state\n", __FUNCTION__);
 668                 return -ESHUTDOWN;
 669         }
 670
 671         /* iso is always one packet per request, that's the only way
 672          * we can report per-packet status.  that also helps with dma.
 673          */
 674         if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
 675                         && req->req.length > le16_to_cpu
 676                                                 (ep->desc->wMaxPacketSize)))
 677                 return -EMSGSIZE;
 678
 679         DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
 680                 _ep->name, _req, _req->length, _req->buf);
 681
 682         local_irq_save(flags);
 683
 684         _req->status = -EINPROGRESS;
 685         _req->actual = 0;
 686
 687         /* kickstart this i/o queue? */
 688         if (list_empty(&ep->queue) && !ep->stopped) {
 689                 if (ep->desc == NULL/* ep0 */) {
 690                         unsigned        length = _req->length;
 691
 692                         switch (dev->ep0state) {
 693                         case EP0_IN_DATA_PHASE:
 694                                 dev->stats.write.ops++;
 695                                 if (write_ep0_fifo(ep, req))
 696                                         req = NULL;
 697                                 break;
 698
 699                         case EP0_OUT_DATA_PHASE:
 700                                 dev->stats.read.ops++;
 701                                 /* messy ... */
 702                                 if (dev->req_config) {
 703                                         DBG(DBG_VERBOSE, "ep0 config ack%s\n",
 704                                                 dev->has_cfr ?  "" : " raced");
 705                                         if (dev->has_cfr)
 706                                                 UDCCFR = UDCCFR_AREN|UDCCFR_ACM
 707                                                         |UDCCFR_MB1;
 708                                         done(ep, req, 0);
 709                                         dev->ep0state = EP0_END_XFER;
 710                                         local_irq_restore (flags);
 711                                         return 0;
 712                                 }
 713                                 if (dev->req_pending)
 714                                         ep0start(dev, UDCCS0_IPR, "OUT");
 715                                 if (length == 0 || ((UDCCS0 & UDCCS0_RNE) != 0
 716                                                 && read_ep0_fifo(ep, req))) {
 717                                         ep0_idle(dev);
 718                                         done(ep, req, 0);
 719                                         req = NULL;
 720                                 }
 721                                 break;
 722
 723                         default:
 724                                 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
 725                                 local_irq_restore (flags);
 726                                 return -EL2HLT;
 727                         }
 728                 /* can the FIFO can satisfy the request immediately? */
 729                 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
 730                         if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0
 731                                         && write_fifo(ep, req))
 732                                 req = NULL;
 733                 } else if ((*ep->reg_udccs & UDCCS_BO_RFS) != 0
 734                                 && read_fifo(ep, req)) {
 735                         req = NULL;
 736                 }
 737
 738                 if (likely (req && ep->desc))
 739                         pio_irq_enable(ep->bEndpointAddress);
 740         }
 741
 742         /* pio or dma irq handler advances the queue. */
 743         if (likely(req != NULL))
 744                 list_add_tail(&req->queue, &ep->queue);
 745         local_irq_restore(flags);
 746
 747         return 0;
 748 }
 749
 750
 751 /*
 752  *      nuke - dequeue ALL requests
 753  */
 754 static void nuke(struct pxa2xx_ep *ep, int status)
 755 {
 756         struct pxa2xx_request *req;
 757
 758         /* called with irqs blocked */
 759         while (!list_empty(&ep->queue)) {
 760                 req = list_entry(ep->queue.next,
 761                                 struct pxa2xx_request,
 762                                 queue);
 763                 done(ep, req, status);
 764         }
 765         if (ep->desc)
 766                 pio_irq_disable (ep->bEndpointAddress);
 767 }
 768
 769
 770 /* dequeue JUST ONE request */
 771 static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 772 {
 773         struct pxa2xx_ep        *ep;
 774         struct pxa2xx_request   *req;
 775         unsigned long           flags;
 776
 777         ep = container_of(_ep, struct pxa2xx_ep, ep);
 778         if (!_ep || ep->ep.name == ep0name)
 779                 return -EINVAL;
 780
 781         local_irq_save(flags);
 782
 783         /* make sure it's actually queued on this endpoint */
 784         list_for_each_entry (req, &ep->queue, queue) {
 785                 if (&req->req == _req)
 786                         break;
 787         }
 788         if (&req->req != _req) {
 789                 local_irq_restore(flags);
 790                 return -EINVAL;
 791         }
 792
 793         done(ep, req, -ECONNRESET);
 794
 795         local_irq_restore(flags);
 796         return 0;
 797 }
 798
 799 /*-------------------------------------------------------------------------*/
 800
 801 static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value)
 802 {
 803         struct pxa2xx_ep        *ep;
 804         unsigned long           flags;
 805
 806         ep = container_of(_ep, struct pxa2xx_ep, ep);
 807         if (unlikely (!_ep
 808                         || (!ep->desc && ep->ep.name != ep0name))
 809                         || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 810                 DMSG("%s, bad ep\n", __FUNCTION__);
 811                 return -EINVAL;
 812         }
 813         if (value == 0) {
 814                 /* this path (reset toggle+halt) is needed to implement
 815                  * SET_INTERFACE on normal hardware.  but it can't be
 816                  * done from software on the PXA UDC, and the hardware
 817                  * forgets to do it as part of SET_INTERFACE automagic.
 818                  */
 819                 DMSG("only host can clear %s halt\n", _ep->name);
 820                 return -EROFS;
 821         }
 822
 823         local_irq_save(flags);
 824
 825         if ((ep->bEndpointAddress & USB_DIR_IN) != 0
 826                         && ((*ep->reg_udccs & UDCCS_BI_TFS) == 0
 827                            || !list_empty(&ep->queue))) {
 828                 local_irq_restore(flags);
 829                 return -EAGAIN;
 830         }
 831
 832         /* FST bit is the same for control, bulk in, bulk out, interrupt in */
 833         *ep->reg_udccs = UDCCS_BI_FST|UDCCS_BI_FTF;
 834
 835         /* ep0 needs special care */
 836         if (!ep->desc) {
 837                 start_watchdog(ep->dev);
 838                 ep->dev->req_pending = 0;
 839                 ep->dev->ep0state = EP0_STALL;
 840
 841         /* and bulk/intr endpoints like dropping stalls too */
 842         } else {
 843                 unsigned i;
 844                 for (i = 0; i < 1000; i += 20) {
 845                         if (*ep->reg_udccs & UDCCS_BI_SST)
 846                                 break;
 847                         udelay(20);
 848                 }
 849         }
 850         local_irq_restore(flags);
 851
 852         DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
 853         return 0;
 854 }
 855
 856 static int pxa2xx_ep_fifo_status(struct usb_ep *_ep)
 857 {
 858         struct pxa2xx_ep        *ep;
 859
 860         ep = container_of(_ep, struct pxa2xx_ep, ep);
 861         if (!_ep) {
 862                 DMSG("%s, bad ep\n", __FUNCTION__);
 863                 return -ENODEV;
 864         }
 865         /* pxa can't report unclaimed bytes from IN fifos */
 866         if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
 867                 return -EOPNOTSUPP;
 868         if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
 869                         || (*ep->reg_udccs & UDCCS_BO_RFS) == 0)
 870                 return 0;
 871         else
 872                 return (*ep->reg_ubcr & 0xfff) + 1;
 873 }
 874
 875 static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep)
 876 {
 877         struct pxa2xx_ep        *ep;
 878
 879         ep = container_of(_ep, struct pxa2xx_ep, ep);
 880         if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
 881                 DMSG("%s, bad ep\n", __FUNCTION__);
 882                 return;
 883         }
 884
 885         /* toggle and halt bits stay unchanged */
 886
 887         /* for OUT, just read and discard the FIFO contents. */
 888         if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
 889                 while (((*ep->reg_udccs) & UDCCS_BO_RNE) != 0)
 890                         (void) *ep->reg_uddr;
 891                 return;
 892         }
 893
 894         /* most IN status is the same, but ISO can't stall */
 895         *ep->reg_udccs = UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
 896                 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 897                         ? 0 : UDCCS_BI_SST;
 898 }
 899
 900
 901 static struct usb_ep_ops pxa2xx_ep_ops = {
 902         .enable         = pxa2xx_ep_enable,
 903         .disable        = pxa2xx_ep_disable,
 904
 905         .alloc_request  = pxa2xx_ep_alloc_request,
 906         .free_request   = pxa2xx_ep_free_request,
 907
 908         .queue          = pxa2xx_ep_queue,
 909         .dequeue        = pxa2xx_ep_dequeue,
 910
 911         .set_halt       = pxa2xx_ep_set_halt,
 912         .fifo_status    = pxa2xx_ep_fifo_status,
 913         .fifo_flush     = pxa2xx_ep_fifo_flush,
 914 };
 915
 916
 917 /* ---------------------------------------------------------------------------
 918  *      device-scoped parts of the api to the usb controller hardware
 919  * ---------------------------------------------------------------------------
 920  */
 921
 922 static int pxa2xx_udc_get_frame(struct usb_gadget *_gadget)
 923 {
 924         return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff);
 925 }
 926
 927 static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget)
 928 {
 929         /* host may not have enabled remote wakeup */
 930         if ((UDCCS0 & UDCCS0_DRWF) == 0)
 931                 return -EHOSTUNREACH;
 932         udc_set_mask_UDCCR(UDCCR_RSM);
 933         return 0;
 934 }
 935
 936 static void stop_activity(struct pxa2xx_udc *, struct usb_gadget_driver *);
 937 static void udc_enable (struct pxa2xx_udc *);
 938 static void udc_disable(struct pxa2xx_udc *);
 939
 940 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
 941  * in active use.
 942  */
 943 static int pullup(struct pxa2xx_udc *udc)
 944 {
 945         int is_active = udc->vbus && udc->pullup && !udc->suspended;
 946         DMSG("%s\n", is_active ? "active" : "inactive");
 947         if (is_active) {
 948                 if (!udc->active) {
 949                         udc->active = 1;
 950                         /* Enable clock for USB device */
 951                         clk_enable(udc->clk);
 952                         udc_enable(udc);
 953                 }
 954         } else {
 955                 if (udc->active) {
 956                         if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
 957                                 DMSG("disconnect %s\n", udc->driver
 958                                         ? udc->driver->driver.name
 959                                         : "(no driver)");
 960                                 stop_activity(udc, udc->driver);
 961                         }
 962                         udc_disable(udc);
 963                         /* Disable clock for USB device */
 964                         clk_disable(udc->clk);
 965                         udc->active = 0;
 966                 }
 967
 968         }
 969         return 0;
 970 }
 971
 972 /* VBUS reporting logically comes from a transceiver */
 973 static int pxa2xx_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
 974 {
 975         struct pxa2xx_udc       *udc;
 976
 977         udc = container_of(_gadget, struct pxa2xx_udc, gadget);
 978         udc->vbus = (is_active != 0);
 979         DMSG("vbus %s\n", is_active ? "supplied" : "inactive");
 980         pullup(udc);
 981         return 0;
 982 }
 983
 984 /* drivers may have software control over D+ pullup */
 985 static int pxa2xx_udc_pullup(struct usb_gadget *_gadget, int is_active)
 986 {
 987         struct pxa2xx_udc       *udc;
 988
 989         udc = container_of(_gadget, struct pxa2xx_udc, gadget);
 990
 991         /* not all boards support pullup control */
 992         if (!udc->mach->gpio_pullup && !udc->mach->udc_command)
 993                 return -EOPNOTSUPP;
 994
 995         udc->pullup = (is_active != 0);
 996         pullup(udc);
 997         return 0;
 998 }
 999
1000 static const struct usb_gadget_ops pxa2xx_udc_ops = {
1001         .get_frame      = pxa2xx_udc_get_frame,
1002         .wakeup         = pxa2xx_udc_wakeup,
1003         .vbus_session   = pxa2xx_udc_vbus_session,
1004         .pullup         = pxa2xx_udc_pullup,
1005
1006         // .vbus_draw ... boards may consume current from VBUS, up to
1007         // 100-500mA based on config.  the 500uA suspend ceiling means
1008         // that exclusively vbus-powered PXA designs violate USB specs.
1009 };
1010
1011 /*-------------------------------------------------------------------------*/
1012
1013 #ifdef CONFIG_USB_GADGET_DEBUG_FS
1014
1015 static int
1016 udc_seq_show(struct seq_file *m, void *_d)
1017 {
1018         struct pxa2xx_udc       *dev = m->private;
1019         unsigned long           flags;
1020         int                     i;
1021         u32                     tmp;
1022
1023         local_irq_save(flags);
1024
1025         /* basic device status */
1026         seq_printf(m, DRIVER_DESC "\n"
1027                 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1028                 driver_name, DRIVER_VERSION SIZE_STR "(pio)",
1029                 dev->driver ? dev->driver->driver.name : "(none)",
1030                 is_vbus_present() ? "full speed" : "disconnected");
1031
1032         /* registers for device and ep0 */
1033         seq_printf(m,
1034                 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1035                 UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
1036
1037         tmp = UDCCR;
1038         seq_printf(m,
1039                 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1040                 (tmp & UDCCR_REM) ? " rem" : "",
1041                 (tmp & UDCCR_RSTIR) ? " rstir" : "",
1042                 (tmp & UDCCR_SRM) ? " srm" : "",
1043                 (tmp & UDCCR_SUSIR) ? " susir" : "",
1044                 (tmp & UDCCR_RESIR) ? " resir" : "",
1045                 (tmp & UDCCR_RSM) ? " rsm" : "",
1046                 (tmp & UDCCR_UDA) ? " uda" : "",
1047                 (tmp & UDCCR_UDE) ? " ude" : "");
1048
1049         tmp = UDCCS0;
1050         seq_printf(m,
1051                 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1052                 (tmp & UDCCS0_SA) ? " sa" : "",
1053                 (tmp & UDCCS0_RNE) ? " rne" : "",
1054                 (tmp & UDCCS0_FST) ? " fst" : "",
1055                 (tmp & UDCCS0_SST) ? " sst" : "",
1056                 (tmp & UDCCS0_DRWF) ? " dwrf" : "",
1057                 (tmp & UDCCS0_FTF) ? " ftf" : "",
1058                 (tmp & UDCCS0_IPR) ? " ipr" : "",
1059                 (tmp & UDCCS0_OPR) ? " opr" : "");
1060
1061         if (dev->has_cfr) {
1062                 tmp = UDCCFR;
1063                 seq_printf(m,
1064                         "udccfr %02X =%s%s\n", tmp,
1065                         (tmp & UDCCFR_AREN) ? " aren" : "",
1066                         (tmp & UDCCFR_ACM) ? " acm" : "");
1067         }
1068
1069         if (!is_vbus_present() || !dev->driver)
1070                 goto done;
1071
1072         seq_printf(m, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1073                 dev->stats.write.bytes, dev->stats.write.ops,
1074                 dev->stats.read.bytes, dev->stats.read.ops,
1075                 dev->stats.irqs);
1076
1077         /* dump endpoint queues */
1078         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1079                 struct pxa2xx_ep        *ep = &dev->ep [i];
1080                 struct pxa2xx_request   *req;
1081
1082                 if (i != 0) {
1083                         const struct usb_endpoint_descriptor    *desc;
1084
1085                         desc = ep->desc;
1086                         if (!desc)
1087                                 continue;
1088                         tmp = *dev->ep [i].reg_udccs;
1089                         seq_printf(m,
1090                                 "%s max %d %s udccs %02x irqs %lu\n",
1091                                 ep->ep.name, le16_to_cpu(desc->wMaxPacketSize),
1092                                 "pio", tmp, ep->pio_irqs);
1093                         /* TODO translate all five groups of udccs bits! */
1094
1095                 } else /* ep0 should only have one transfer queued */
1096                         seq_printf(m, "ep0 max 16 pio irqs %lu\n",
1097                                 ep->pio_irqs);
1098
1099                 if (list_empty(&ep->queue)) {
1100                         seq_printf(m, "\t(nothing queued)\n");
1101                         continue;
1102                 }
1103                 list_for_each_entry(req, &ep->queue, queue) {
1104                         seq_printf(m,
1105                                         "\treq %p len %d/%d buf %p\n",
1106                                         &req->req, req->req.actual,
1107                                         req->req.length, req->req.buf);
1108                 }
1109         }
1110
1111 done:
1112         local_irq_restore(flags);
1113         return 0;
1114 }
1115
1116 static int
1117 udc_debugfs_open(struct inode *inode, struct file *file)
1118 {
1119         return single_open(file, udc_seq_show, inode->i_private);
1120 }
1121
1122 static const struct file_operations debug_fops = {
1123         .open           = udc_debugfs_open,
1124         .read           = seq_read,
1125         .llseek         = seq_lseek,
1126         .release        = single_release,
1127         .owner          = THIS_MODULE,
1128 };
1129
1130 #define create_debug_files(dev) \
1131         do { \
1132                 dev->debugfs_udc = debugfs_create_file(dev->gadget.name, \
1133                         S_IRUGO, NULL, dev, &debug_fops); \
1134         } while (0)
1135 #define remove_debug_files(dev) \
1136         do { \
1137                 if (dev->debugfs_udc) \
1138                         debugfs_remove(dev->debugfs_udc); \
1139         } while (0)
1140
1141 #else   /* !CONFIG_USB_GADGET_DEBUG_FILES */
1142
1143 #define create_debug_files(dev) do {} while (0)
1144 #define remove_debug_files(dev) do {} while (0)
1145
1146 #endif  /* CONFIG_USB_GADGET_DEBUG_FILES */
1147
1148 /*-------------------------------------------------------------------------*/
1149
1150 /*
1151  *      udc_disable - disable USB device controller
1152  */
1153 static void udc_disable(struct pxa2xx_udc *dev)
1154 {
1155         /* block all irqs */
1156         udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1157         UICR0 = UICR1 = 0xff;
1158         UFNRH = UFNRH_SIM;
1159
1160         /* if hardware supports it, disconnect from usb */
1161         pullup_off();
1162
1163         udc_clear_mask_UDCCR(UDCCR_UDE);
1164
1165         ep0_idle (dev);
1166         dev->gadget.speed = USB_SPEED_UNKNOWN;
1167 }
1168
1169
1170 /*
1171  *      udc_reinit - initialize software state
1172  */
1173 static void udc_reinit(struct pxa2xx_udc *dev)
1174 {
1175         u32     i;
1176
1177         /* device/ep0 records init */
1178         INIT_LIST_HEAD (&dev->gadget.ep_list);
1179         INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1180         dev->ep0state = EP0_IDLE;
1181
1182         /* basic endpoint records init */
1183         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1184                 struct pxa2xx_ep *ep = &dev->ep[i];
1185
1186                 if (i != 0)
1187                         list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1188
1189                 ep->desc = NULL;
1190                 ep->stopped = 0;
1191                 INIT_LIST_HEAD (&ep->queue);
1192                 ep->pio_irqs = 0;
1193         }
1194
1195         /* the rest was statically initialized, and is read-only */
1196 }
1197
1198 /* until it's enabled, this UDC should be completely invisible
1199  * to any USB host.
1200  */
1201 static void udc_enable (struct pxa2xx_udc *dev)
1202 {
1203         udc_clear_mask_UDCCR(UDCCR_UDE);
1204
1205         /* try to clear these bits before we enable the udc */
1206         udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1207
1208         ep0_idle(dev);
1209         dev->gadget.speed = USB_SPEED_UNKNOWN;
1210         dev->stats.irqs = 0;
1211
1212         /*
1213          * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1214          * - enable UDC
1215          * - if RESET is already in progress, ack interrupt
1216          * - unmask reset interrupt
1217          */
1218         udc_set_mask_UDCCR(UDCCR_UDE);
1219         if (!(UDCCR & UDCCR_UDA))
1220                 udc_ack_int_UDCCR(UDCCR_RSTIR);
1221
1222         if (dev->has_cfr /* UDC_RES2 is defined */) {
1223                 /* pxa255 (a0+) can avoid a set_config race that could
1224                  * prevent gadget drivers from configuring correctly
1225                  */
1226                 UDCCFR = UDCCFR_ACM | UDCCFR_MB1;
1227         } else {
1228                 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1229                  * which could result in missing packets and interrupts.
1230                  * supposedly one bit per endpoint, controlling whether it
1231                  * double buffers or not; ACM/AREN bits fit into the holes.
1232                  * zero bits (like USIR0_IRx) disable double buffering.
1233                  */
1234                 UDC_RES1 = 0x00;
1235                 UDC_RES2 = 0x00;
1236         }
1237
1238         /* enable suspend/resume and reset irqs */
1239         udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1240
1241         /* enable ep0 irqs */
1242         UICR0 &= ~UICR0_IM0;
1243
1244         /* if hardware supports it, pullup D+ and wait for reset */
1245         pullup_on();
1246 }
1247
1248
1249 /* when a driver is successfully registered, it will receive
1250  * control requests including set_configuration(), which enables
1251  * non-control requests.  then usb traffic follows until a
1252  * disconnect is reported.  then a host may connect again, or
1253  * the driver might get unbound.
1254  */
1255 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1256 {
1257         struct pxa2xx_udc       *dev = the_controller;
1258         int                     retval;
1259
1260         if (!driver
1261                         || driver->speed < USB_SPEED_FULL
1262                         || !driver->bind
1263                         || !driver->disconnect
1264                         || !driver->setup)
1265                 return -EINVAL;
1266         if (!dev)
1267                 return -ENODEV;
1268         if (dev->driver)
1269                 return -EBUSY;
1270
1271         /* first hook up the driver ... */
1272         dev->driver = driver;
1273         dev->gadget.dev.driver = &driver->driver;
1274         dev->pullup = 1;
1275
1276         retval = device_add (&dev->gadget.dev);
1277         if (retval) {
1278 fail:
1279                 dev->driver = NULL;
1280                 dev->gadget.dev.driver = NULL;
1281                 return retval;
1282         }
1283         retval = driver->bind(&dev->gadget);
1284         if (retval) {
1285                 DMSG("bind to driver %s --> error %d\n",
1286                                 driver->driver.name, retval);
1287                 device_del (&dev->gadget.dev);
1288                 goto fail;
1289         }
1290
1291         /* ... then enable host detection and ep0; and we're ready
1292          * for set_configuration as well as eventual disconnect.
1293          */
1294         DMSG("registered gadget driver '%s'\n", driver->driver.name);
1295         pullup(dev);
1296         dump_state(dev);
1297         return 0;
1298 }
1299 EXPORT_SYMBOL(usb_gadget_register_driver);
1300
1301 static void
1302 stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver)
1303 {
1304         int i;
1305
1306         /* don't disconnect drivers more than once */
1307         if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1308                 driver = NULL;
1309         dev->gadget.speed = USB_SPEED_UNKNOWN;
1310
1311         /* prevent new request submissions, kill any outstanding requests  */
1312         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1313                 struct pxa2xx_ep *ep = &dev->ep[i];
1314
1315                 ep->stopped = 1;
1316                 nuke(ep, -ESHUTDOWN);
1317         }
1318         del_timer_sync(&dev->timer);
1319
1320         /* report disconnect; the driver is already quiesced */
1321         if (driver)
1322                 driver->disconnect(&dev->gadget);
1323
1324         /* re-init driver-visible data structures */
1325         udc_reinit(dev);
1326 }
1327
1328 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1329 {
1330         struct pxa2xx_udc       *dev = the_controller;
1331
1332         if (!dev)
1333                 return -ENODEV;
1334         if (!driver || driver != dev->driver || !driver->unbind)
1335                 return -EINVAL;
1336
1337         local_irq_disable();
1338         dev->pullup = 0;
1339         pullup(dev);
1340         stop_activity(dev, driver);
1341         local_irq_enable();
1342
1343         driver->unbind(&dev->gadget);
1344         dev->gadget.dev.driver = NULL;
1345         dev->driver = NULL;
1346
1347         device_del (&dev->gadget.dev);
1348
1349         DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1350         dump_state(dev);
1351         return 0;
1352 }
1353 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1354
1355
1356 /*-------------------------------------------------------------------------*/
1357
1358 #ifdef CONFIG_ARCH_LUBBOCK
1359
1360 /* Lubbock has separate connect and disconnect irqs.  More typical designs
1361  * use one GPIO as the VBUS IRQ, and another to control the D+ pullup.
1362  */
1363
1364 static irqreturn_t
1365 lubbock_vbus_irq(int irq, void *_dev)
1366 {
1367         struct pxa2xx_udc       *dev = _dev;
1368         int                     vbus;
1369
1370         dev->stats.irqs++;
1371         switch (irq) {
1372         case LUBBOCK_USB_IRQ:
1373                 vbus = 1;
1374                 disable_irq(LUBBOCK_USB_IRQ);
1375                 enable_irq(LUBBOCK_USB_DISC_IRQ);
1376                 break;
1377         case LUBBOCK_USB_DISC_IRQ:
1378                 vbus = 0;
1379                 disable_irq(LUBBOCK_USB_DISC_IRQ);
1380                 enable_irq(LUBBOCK_USB_IRQ);
1381                 break;
1382         default:
1383                 return IRQ_NONE;
1384         }
1385
1386         pxa2xx_udc_vbus_session(&dev->gadget, vbus);
1387         return IRQ_HANDLED;
1388 }
1389
1390 #endif
1391
1392 static irqreturn_t udc_vbus_irq(int irq, void *_dev)
1393 {
1394         struct pxa2xx_udc       *dev = _dev;
1395         int                     vbus = gpio_get_value(dev->mach->gpio_vbus);
1396
1397         if (dev->mach->gpio_vbus_inverted)
1398                 vbus = !vbus;
1399
1400         pxa2xx_udc_vbus_session(&dev->gadget, vbus);
1401         return IRQ_HANDLED;
1402 }
1403
1404
1405 /*-------------------------------------------------------------------------*/
1406
1407 static inline void clear_ep_state (struct pxa2xx_udc *dev)
1408 {
1409         unsigned i;
1410
1411         /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1412          * fifos, and pending transactions mustn't be continued in any case.
1413          */
1414         for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1415                 nuke(&dev->ep[i], -ECONNABORTED);
1416 }
1417
1418 static void udc_watchdog(unsigned long _dev)
1419 {
1420         struct pxa2xx_udc       *dev = (void *)_dev;
1421
1422         local_irq_disable();
1423         if (dev->ep0state == EP0_STALL
1424                         && (UDCCS0 & UDCCS0_FST) == 0
1425                         && (UDCCS0 & UDCCS0_SST) == 0) {
1426                 UDCCS0 = UDCCS0_FST|UDCCS0_FTF;
1427                 DBG(DBG_VERBOSE, "ep0 re-stall\n");
1428                 start_watchdog(dev);
1429         }
1430         local_irq_enable();
1431 }
1432
1433 static void handle_ep0 (struct pxa2xx_udc *dev)
1434 {
1435         u32                     udccs0 = UDCCS0;
1436         struct pxa2xx_ep        *ep = &dev->ep [0];
1437         struct pxa2xx_request   *req;
1438         union {
1439                 struct usb_ctrlrequest  r;
1440                 u8                      raw [8];
1441                 u32                     word [2];
1442         } u;
1443
1444         if (list_empty(&ep->queue))
1445                 req = NULL;
1446         else
1447                 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
1448
1449         /* clear stall status */
1450         if (udccs0 & UDCCS0_SST) {
1451                 nuke(ep, -EPIPE);
1452                 UDCCS0 = UDCCS0_SST;
1453                 del_timer(&dev->timer);
1454                 ep0_idle(dev);
1455         }
1456
1457         /* previous request unfinished?  non-error iff back-to-back ... */
1458         if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1459                 nuke(ep, 0);
1460                 del_timer(&dev->timer);
1461                 ep0_idle(dev);
1462         }
1463
1464         switch (dev->ep0state) {
1465         case EP0_IDLE:
1466                 /* late-breaking status? */
1467                 udccs0 = UDCCS0;
1468
1469                 /* start control request? */
1470                 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1471                                 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1472                         int i;
1473
1474                         nuke (ep, -EPROTO);
1475
1476                         /* read SETUP packet */
1477                         for (i = 0; i < 8; i++) {
1478                                 if (unlikely(!(UDCCS0 & UDCCS0_RNE))) {
1479 bad_setup:
1480                                         DMSG("SETUP %d!\n", i);
1481                                         goto stall;
1482                                 }
1483                                 u.raw [i] = (u8) UDDR0;
1484                         }
1485                         if (unlikely((UDCCS0 & UDCCS0_RNE) != 0))
1486                                 goto bad_setup;
1487
1488 got_setup:
1489                         DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1490                                 u.r.bRequestType, u.r.bRequest,
1491                                 le16_to_cpu(u.r.wValue),
1492                                 le16_to_cpu(u.r.wIndex),
1493                                 le16_to_cpu(u.r.wLength));
1494
1495                         /* cope with automagic for some standard requests. */
1496                         dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1497                                                 == USB_TYPE_STANDARD;
1498                         dev->req_config = 0;
1499                         dev->req_pending = 1;
1500                         switch (u.r.bRequest) {
1501                         /* hardware restricts gadget drivers here! */
1502                         case USB_REQ_SET_CONFIGURATION:
1503                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1504                                         /* reflect hardware's automagic
1505                                          * up to the gadget driver.
1506                                          */
1507 config_change:
1508                                         dev->req_config = 1;
1509                                         clear_ep_state(dev);
1510                                         /* if !has_cfr, there's no synch
1511                                          * else use AREN (later) not SA|OPR
1512                                          * USIR0_IR0 acts edge sensitive
1513                                          */
1514                                 }
1515                                 break;
1516                         /* ... and here, even more ... */
1517                         case USB_REQ_SET_INTERFACE:
1518                                 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1519                                         /* udc hardware is broken by design:
1520                                          *  - altsetting may only be zero;
1521                                          *  - hw resets all interfaces' eps;
1522                                          *  - ep reset doesn't include halt(?).
1523                                          */
1524                                         DMSG("broken set_interface (%d/%d)\n",
1525                                                 le16_to_cpu(u.r.wIndex),
1526                                                 le16_to_cpu(u.r.wValue));
1527                                         goto config_change;
1528                                 }
1529                                 break;
1530                         /* hardware was supposed to hide this */
1531                         case USB_REQ_SET_ADDRESS:
1532                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1533                                         ep0start(dev, 0, "address");
1534                                         return;
1535                                 }
1536                                 break;
1537                         }
1538
1539                         if (u.r.bRequestType & USB_DIR_IN)
1540                                 dev->ep0state = EP0_IN_DATA_PHASE;
1541                         else
1542                                 dev->ep0state = EP0_OUT_DATA_PHASE;
1543
1544                         i = dev->driver->setup(&dev->gadget, &u.r);
1545                         if (i < 0) {
1546                                 /* hardware automagic preventing STALL... */
1547                                 if (dev->req_config) {
1548                                         /* hardware sometimes neglects to tell
1549                                          * tell us about config change events,
1550                                          * so later ones may fail...
1551                                          */
1552                                         WARN("config change %02x fail %d?\n",
1553                                                 u.r.bRequest, i);
1554                                         return;
1555                                         /* TODO experiment:  if has_cfr,
1556                                          * hardware didn't ACK; maybe we
1557                                          * could actually STALL!
1558                                          */
1559                                 }
1560                                 DBG(DBG_VERBOSE, "protocol STALL, "
1561                                         "%02x err %d\n", UDCCS0, i);
1562 stall:
1563                                 /* the watchdog timer helps deal with cases
1564                                  * where udc seems to clear FST wrongly, and
1565                                  * then NAKs instead of STALLing.
1566                                  */
1567                                 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1568                                 start_watchdog(dev);
1569                                 dev->ep0state = EP0_STALL;
1570
1571                         /* deferred i/o == no response yet */
1572                         } else if (dev->req_pending) {
1573                                 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1574                                                 || dev->req_std || u.r.wLength))
1575                                         ep0start(dev, 0, "defer");
1576                                 else
1577                                         ep0start(dev, UDCCS0_IPR, "defer/IPR");
1578                         }
1579
1580                         /* expect at least one data or status stage irq */
1581                         return;
1582
1583                 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1584                                 == (UDCCS0_OPR|UDCCS0_SA))) {
1585                         unsigned i;
1586
1587                         /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1588                          * still observed on a pxa255 a0.
1589                          */
1590                         DBG(DBG_VERBOSE, "e131\n");
1591                         nuke(ep, -EPROTO);
1592
1593                         /* read SETUP data, but don't trust it too much */
1594                         for (i = 0; i < 8; i++)
1595                                 u.raw [i] = (u8) UDDR0;
1596                         if ((u.r.bRequestType & USB_RECIP_MASK)
1597                                         > USB_RECIP_OTHER)
1598                                 goto stall;
1599                         if (u.word [0] == 0 && u.word [1] == 0)
1600                                 goto stall;
1601                         goto got_setup;
1602                 } else {
1603                         /* some random early IRQ:
1604                          * - we acked FST
1605                          * - IPR cleared
1606                          * - OPR got set, without SA (likely status stage)
1607                          */
1608                         UDCCS0 = udccs0 & (UDCCS0_SA|UDCCS0_OPR);
1609                 }
1610                 break;
1611         case EP0_IN_DATA_PHASE:                 /* GET_DESCRIPTOR etc */
1612                 if (udccs0 & UDCCS0_OPR) {
1613                         UDCCS0 = UDCCS0_OPR|UDCCS0_FTF;
1614                         DBG(DBG_VERBOSE, "ep0in premature status\n");
1615                         if (req)
1616                                 done(ep, req, 0);
1617                         ep0_idle(dev);
1618                 } else /* irq was IPR clearing */ {
1619                         if (req) {
1620                                 /* this IN packet might finish the request */
1621                                 (void) write_ep0_fifo(ep, req);
1622                         } /* else IN token before response was written */
1623                 }
1624                 break;
1625         case EP0_OUT_DATA_PHASE:                /* SET_DESCRIPTOR etc */
1626                 if (udccs0 & UDCCS0_OPR) {
1627                         if (req) {
1628                                 /* this OUT packet might finish the request */
1629                                 if (read_ep0_fifo(ep, req))
1630                                         done(ep, req, 0);
1631                                 /* else more OUT packets expected */
1632                         } /* else OUT token before read was issued */
1633                 } else /* irq was IPR clearing */ {
1634                         DBG(DBG_VERBOSE, "ep0out premature status\n");
1635                         if (req)
1636                                 done(ep, req, 0);
1637                         ep0_idle(dev);
1638                 }
1639                 break;
1640         case EP0_END_XFER:
1641                 if (req)
1642                         done(ep, req, 0);
1643                 /* ack control-IN status (maybe in-zlp was skipped)
1644                  * also appears after some config change events.
1645                  */
1646                 if (udccs0 & UDCCS0_OPR)
1647                         UDCCS0 = UDCCS0_OPR;
1648                 ep0_idle(dev);
1649                 break;
1650         case EP0_STALL:
1651                 UDCCS0 = UDCCS0_FST;
1652                 break;
1653         }
1654         USIR0 = USIR0_IR0;
1655 }
1656
1657 static void handle_ep(struct pxa2xx_ep *ep)
1658 {
1659         struct pxa2xx_request   *req;
1660         int                     is_in = ep->bEndpointAddress & USB_DIR_IN;
1661         int                     completed;
1662         u32                     udccs, tmp;
1663
1664         do {
1665                 completed = 0;
1666                 if (likely (!list_empty(&ep->queue)))
1667                         req = list_entry(ep->queue.next,
1668                                         struct pxa2xx_request, queue);
1669                 else
1670                         req = NULL;
1671
1672                 // TODO check FST handling
1673
1674                 udccs = *ep->reg_udccs;
1675                 if (unlikely(is_in)) {  /* irq from TPC, SST, or (ISO) TUR */
1676                         tmp = UDCCS_BI_TUR;
1677                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1678                                 tmp |= UDCCS_BI_SST;
1679                         tmp &= udccs;
1680                         if (likely (tmp))
1681                                 *ep->reg_udccs = tmp;
1682                         if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
1683                                 completed = write_fifo(ep, req);
1684
1685                 } else {        /* irq from RPC (or for ISO, ROF) */
1686                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1687                                 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1688                         else
1689                                 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1690                         tmp &= udccs;
1691                         if (likely(tmp))
1692                                 *ep->reg_udccs = tmp;
1693
1694                         /* fifos can hold packets, ready for reading... */
1695                         if (likely(req)) {
1696                                 completed = read_fifo(ep, req);
1697                         } else
1698                                 pio_irq_disable (ep->bEndpointAddress);
1699                 }
1700                 ep->pio_irqs++;
1701         } while (completed);
1702 }
1703
1704 /*
1705  *      pxa2xx_udc_irq - interrupt handler
1706  *
1707  * avoid delays in ep0 processing. the control handshaking isn't always
1708  * under software control (pxa250c0 and the pxa255 are better), and delays
1709  * could cause usb protocol errors.
1710  */
1711 static irqreturn_t
1712 pxa2xx_udc_irq(int irq, void *_dev)
1713 {
1714         struct pxa2xx_udc       *dev = _dev;
1715         int                     handled;
1716
1717         dev->stats.irqs++;
1718         do {
1719                 u32             udccr = UDCCR;
1720
1721                 handled = 0;
1722
1723                 /* SUSpend Interrupt Request */
1724                 if (unlikely(udccr & UDCCR_SUSIR)) {
1725                         udc_ack_int_UDCCR(UDCCR_SUSIR);
1726                         handled = 1;
1727                         DBG(DBG_VERBOSE, "USB suspend%s\n", is_vbus_present()
1728                                 ? "" : "+disconnect");
1729
1730                         if (!is_vbus_present())
1731                                 stop_activity(dev, dev->driver);
1732                         else if (dev->gadget.speed != USB_SPEED_UNKNOWN
1733                                         && dev->driver
1734                                         && dev->driver->suspend)
1735                                 dev->driver->suspend(&dev->gadget);
1736                         ep0_idle (dev);
1737                 }
1738
1739                 /* RESume Interrupt Request */
1740                 if (unlikely(udccr & UDCCR_RESIR)) {
1741                         udc_ack_int_UDCCR(UDCCR_RESIR);
1742                         handled = 1;
1743                         DBG(DBG_VERBOSE, "USB resume\n");
1744
1745                         if (dev->gadget.speed != USB_SPEED_UNKNOWN
1746                                         && dev->driver
1747                                         && dev->driver->resume
1748                                         && is_vbus_present())
1749                                 dev->driver->resume(&dev->gadget);
1750                 }
1751
1752                 /* ReSeT Interrupt Request - USB reset */
1753                 if (unlikely(udccr & UDCCR_RSTIR)) {
1754                         udc_ack_int_UDCCR(UDCCR_RSTIR);
1755                         handled = 1;
1756
1757                         if ((UDCCR & UDCCR_UDA) == 0) {
1758                                 DBG(DBG_VERBOSE, "USB reset start\n");
1759
1760                                 /* reset driver and endpoints,
1761                                  * in case that's not yet done
1762                                  */
1763                                 stop_activity (dev, dev->driver);
1764
1765                         } else {
1766                                 DBG(DBG_VERBOSE, "USB reset end\n");
1767                                 dev->gadget.speed = USB_SPEED_FULL;
1768                                 memset(&dev->stats, 0, sizeof dev->stats);
1769                                 /* driver and endpoints are still reset */
1770                         }
1771
1772                 } else {
1773                         u32     usir0 = USIR0 & ~UICR0;
1774                         u32     usir1 = USIR1 & ~UICR1;
1775                         int     i;
1776
1777                         if (unlikely (!usir0 && !usir1))
1778                                 continue;
1779
1780                         DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
1781
1782                         /* control traffic */
1783                         if (usir0 & USIR0_IR0) {
1784                                 dev->ep[0].pio_irqs++;
1785                                 handle_ep0(dev);
1786                                 handled = 1;
1787                         }
1788
1789                         /* endpoint data transfers */
1790                         for (i = 0; i < 8; i++) {
1791                                 u32     tmp = 1 << i;
1792
1793                                 if (i && (usir0 & tmp)) {
1794                                         handle_ep(&dev->ep[i]);
1795                                         USIR0 |= tmp;
1796                                         handled = 1;
1797                                 }
1798                                 if (usir1 & tmp) {
1799                                         handle_ep(&dev->ep[i+8]);
1800                                         USIR1 |= tmp;
1801                                         handled = 1;
1802                                 }
1803                         }
1804                 }
1805
1806                 /* we could also ask for 1 msec SOF (SIR) interrupts */
1807
1808         } while (handled);
1809         return IRQ_HANDLED;
1810 }
1811
1812 /*-------------------------------------------------------------------------*/
1813
1814 static void nop_release (struct device *dev)
1815 {
1816         DMSG("%s %s\n", __FUNCTION__, dev->bus_id);
1817 }
1818
1819 /* this uses load-time allocation and initialization (instead of
1820  * doing it at run-time) to save code, eliminate fault paths, and
1821  * be more obviously correct.
1822  */
1823 static struct pxa2xx_udc memory = {
1824         .gadget = {
1825                 .ops            = &pxa2xx_udc_ops,
1826                 .ep0            = &memory.ep[0].ep,
1827                 .name           = driver_name,
1828                 .dev = {
1829                         .bus_id         = "gadget",
1830                         .release        = nop_release,
1831                 },
1832         },
1833
1834         /* control endpoint */
1835         .ep[0] = {
1836                 .ep = {
1837                         .name           = ep0name,
1838                         .ops            = &pxa2xx_ep_ops,
1839                         .maxpacket      = EP0_FIFO_SIZE,
1840                 },
1841                 .dev            = &memory,
1842                 .reg_udccs      = &UDCCS0,
1843                 .reg_uddr       = &UDDR0,
1844         },
1845
1846         /* first group of endpoints */
1847         .ep[1] = {
1848                 .ep = {
1849                         .name           = "ep1in-bulk",
1850                         .ops            = &pxa2xx_ep_ops,
1851                         .maxpacket      = BULK_FIFO_SIZE,
1852                 },
1853                 .dev            = &memory,
1854                 .fifo_size      = BULK_FIFO_SIZE,
1855                 .bEndpointAddress = USB_DIR_IN | 1,
1856                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1857                 .reg_udccs      = &UDCCS1,
1858                 .reg_uddr       = &UDDR1,
1859         },
1860         .ep[2] = {
1861                 .ep = {
1862                         .name           = "ep2out-bulk",
1863                         .ops            = &pxa2xx_ep_ops,
1864                         .maxpacket      = BULK_FIFO_SIZE,
1865                 },
1866                 .dev            = &memory,
1867                 .fifo_size      = BULK_FIFO_SIZE,
1868                 .bEndpointAddress = 2,
1869                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1870                 .reg_udccs      = &UDCCS2,
1871                 .reg_ubcr       = &UBCR2,
1872                 .reg_uddr       = &UDDR2,
1873         },
1874 #ifndef CONFIG_USB_PXA2XX_SMALL
1875         .ep[3] = {
1876                 .ep = {
1877                         .name           = "ep3in-iso",
1878                         .ops            = &pxa2xx_ep_ops,
1879                         .maxpacket      = ISO_FIFO_SIZE,
1880                 },
1881                 .dev            = &memory,
1882                 .fifo_size      = ISO_FIFO_SIZE,
1883                 .bEndpointAddress = USB_DIR_IN | 3,
1884                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1885                 .reg_udccs      = &UDCCS3,
1886                 .reg_uddr       = &UDDR3,
1887         },
1888         .ep[4] = {
1889                 .ep = {
1890                         .name           = "ep4out-iso",
1891                         .ops            = &pxa2xx_ep_ops,
1892                         .maxpacket      = ISO_FIFO_SIZE,
1893                 },
1894                 .dev            = &memory,
1895                 .fifo_size      = ISO_FIFO_SIZE,
1896                 .bEndpointAddress = 4,
1897                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1898                 .reg_udccs      = &UDCCS4,
1899                 .reg_ubcr       = &UBCR4,
1900                 .reg_uddr       = &UDDR4,
1901         },
1902         .ep[5] = {
1903                 .ep = {
1904                         .name           = "ep5in-int",
1905                         .ops            = &pxa2xx_ep_ops,
1906                         .maxpacket      = INT_FIFO_SIZE,
1907                 },
1908                 .dev            = &memory,
1909                 .fifo_size      = INT_FIFO_SIZE,
1910                 .bEndpointAddress = USB_DIR_IN | 5,
1911                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
1912                 .reg_udccs      = &UDCCS5,
1913                 .reg_uddr       = &UDDR5,
1914         },
1915
1916         /* second group of endpoints */
1917         .ep[6] = {
1918                 .ep = {
1919                         .name           = "ep6in-bulk",
1920                         .ops            = &pxa2xx_ep_ops,
1921                         .maxpacket      = BULK_FIFO_SIZE,
1922                 },
1923                 .dev            = &memory,
1924                 .fifo_size      = BULK_FIFO_SIZE,
1925                 .bEndpointAddress = USB_DIR_IN | 6,
1926                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1927                 .reg_udccs      = &UDCCS6,
1928                 .reg_uddr       = &UDDR6,
1929         },
1930         .ep[7] = {
1931                 .ep = {
1932                         .name           = "ep7out-bulk",
1933                         .ops            = &pxa2xx_ep_ops,
1934                         .maxpacket      = BULK_FIFO_SIZE,
1935                 },
1936                 .dev            = &memory,
1937                 .fifo_size      = BULK_FIFO_SIZE,
1938                 .bEndpointAddress = 7,
1939                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1940                 .reg_udccs      = &UDCCS7,
1941                 .reg_ubcr       = &UBCR7,
1942                 .reg_uddr       = &UDDR7,
1943         },
1944         .ep[8] = {
1945                 .ep = {
1946                         .name           = "ep8in-iso",
1947                         .ops            = &pxa2xx_ep_ops,
1948                         .maxpacket      = ISO_FIFO_SIZE,
1949                 },
1950                 .dev            = &memory,
1951                 .fifo_size      = ISO_FIFO_SIZE,
1952                 .bEndpointAddress = USB_DIR_IN | 8,
1953                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1954                 .reg_udccs      = &UDCCS8,
1955                 .reg_uddr       = &UDDR8,
1956         },
1957         .ep[9] = {
1958                 .ep = {
1959                         .name           = "ep9out-iso",
1960                         .ops            = &pxa2xx_ep_ops,
1961                         .maxpacket      = ISO_FIFO_SIZE,
1962                 },
1963                 .dev            = &memory,
1964                 .fifo_size      = ISO_FIFO_SIZE,
1965                 .bEndpointAddress = 9,
1966                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1967                 .reg_udccs      = &UDCCS9,
1968                 .reg_ubcr       = &UBCR9,
1969                 .reg_uddr       = &UDDR9,
1970         },
1971         .ep[10] = {
1972                 .ep = {
1973                         .name           = "ep10in-int",
1974                         .ops            = &pxa2xx_ep_ops,
1975                         .maxpacket      = INT_FIFO_SIZE,
1976                 },
1977                 .dev            = &memory,
1978                 .fifo_size      = INT_FIFO_SIZE,
1979                 .bEndpointAddress = USB_DIR_IN | 10,
1980                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
1981                 .reg_udccs      = &UDCCS10,
1982                 .reg_uddr       = &UDDR10,
1983         },
1984
1985         /* third group of endpoints */
1986         .ep[11] = {
1987                 .ep = {
1988                         .name           = "ep11in-bulk",
1989                         .ops            = &pxa2xx_ep_ops,
1990                         .maxpacket      = BULK_FIFO_SIZE,
1991                 },
1992                 .dev            = &memory,
1993                 .fifo_size      = BULK_FIFO_SIZE,
1994                 .bEndpointAddress = USB_DIR_IN | 11,
1995                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1996                 .reg_udccs      = &UDCCS11,
1997                 .reg_uddr       = &UDDR11,
1998         },
1999         .ep[12] = {
2000                 .ep = {
2001                         .name           = "ep12out-bulk",
2002                         .ops            = &pxa2xx_ep_ops,
2003                         .maxpacket      = BULK_FIFO_SIZE,
2004                 },
2005                 .dev            = &memory,
2006                 .fifo_size      = BULK_FIFO_SIZE,
2007                 .bEndpointAddress = 12,
2008                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2009                 .reg_udccs      = &UDCCS12,
2010                 .reg_ubcr       = &UBCR12,
2011                 .reg_uddr       = &UDDR12,
2012         },
2013         .ep[13] = {
2014                 .ep = {
2015                         .name           = "ep13in-iso",
2016                         .ops            = &pxa2xx_ep_ops,
2017                         .maxpacket      = ISO_FIFO_SIZE,
2018                 },
2019                 .dev            = &memory,
2020                 .fifo_size      = ISO_FIFO_SIZE,
2021                 .bEndpointAddress = USB_DIR_IN | 13,
2022                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2023                 .reg_udccs      = &UDCCS13,
2024                 .reg_uddr       = &UDDR13,
2025         },
2026         .ep[14] = {
2027                 .ep = {
2028                         .name           = "ep14out-iso",
2029                         .ops            = &pxa2xx_ep_ops,
2030                         .maxpacket      = ISO_FIFO_SIZE,
2031                 },
2032                 .dev            = &memory,
2033                 .fifo_size      = ISO_FIFO_SIZE,
2034                 .bEndpointAddress = 14,
2035                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2036                 .reg_udccs      = &UDCCS14,
2037                 .reg_ubcr       = &UBCR14,
2038                 .reg_uddr       = &UDDR14,
2039         },
2040         .ep[15] = {
2041                 .ep = {
2042                         .name           = "ep15in-int",
2043                         .ops            = &pxa2xx_ep_ops,
2044                         .maxpacket      = INT_FIFO_SIZE,
2045                 },
2046                 .dev            = &memory,
2047                 .fifo_size      = INT_FIFO_SIZE,
2048                 .bEndpointAddress = USB_DIR_IN | 15,
2049                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2050                 .reg_udccs      = &UDCCS15,
2051                 .reg_uddr       = &UDDR15,
2052         },
2053 #endif /* !CONFIG_USB_PXA2XX_SMALL */
2054 };
2055
2056 #define CP15R0_VENDOR_MASK      0xffffe000
2057
2058 #if     defined(CONFIG_ARCH_PXA)
2059 #define CP15R0_XSCALE_VALUE     0x69052000      /* intel/arm/xscale */
2060
2061 #elif   defined(CONFIG_ARCH_IXP4XX)
2062 #define CP15R0_XSCALE_VALUE     0x69054000      /* intel/arm/ixp4xx */
2063
2064 #endif
2065
2066 #define CP15R0_PROD_MASK        0x000003f0
2067 #define PXA25x                  0x00000100      /* and PXA26x */
2068 #define PXA210                  0x00000120
2069
2070 #define CP15R0_REV_MASK         0x0000000f
2071
2072 #define CP15R0_PRODREV_MASK     (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2073
2074 #define PXA255_A0               0x00000106      /* or PXA260_B1 */
2075 #define PXA250_C0               0x00000105      /* or PXA26x_B0 */
2076 #define PXA250_B2               0x00000104
2077 #define PXA250_B1               0x00000103      /* or PXA260_A0 */
2078 #define PXA250_B0               0x00000102
2079 #define PXA250_A1               0x00000101
2080 #define PXA250_A0               0x00000100
2081
2082 #define PXA210_C0               0x00000125
2083 #define PXA210_B2               0x00000124
2084 #define PXA210_B1               0x00000123
2085 #define PXA210_B0               0x00000122
2086 #define IXP425_A0               0x000001c1
2087 #define IXP425_B0               0x000001f1
2088 #define IXP465_AD               0x00000200
2089
2090 /*
2091  *      probe - binds to the platform device
2092  */
2093 static int __init pxa2xx_udc_probe(struct platform_device *pdev)
2094 {
2095         struct pxa2xx_udc *dev = &memory;
2096         int retval, vbus_irq, irq;
2097         u32 chiprev;
2098
2099         /* insist on Intel/ARM/XScale */
2100         asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2101         if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2102                 pr_err("%s: not XScale!\n", driver_name);
2103                 return -ENODEV;
2104         }
2105
2106         /* trigger chiprev-specific logic */
2107         switch (chiprev & CP15R0_PRODREV_MASK) {
2108 #if     defined(CONFIG_ARCH_PXA)
2109         case PXA255_A0:
2110                 dev->has_cfr = 1;
2111                 break;
2112         case PXA250_A0:
2113         case PXA250_A1:
2114                 /* A0/A1 "not released"; ep 13, 15 unusable */
2115                 /* fall through */
2116         case PXA250_B2: case PXA210_B2:
2117         case PXA250_B1: case PXA210_B1:
2118         case PXA250_B0: case PXA210_B0:
2119                 /* OUT-DMA is broken ... */
2120                 /* fall through */
2121         case PXA250_C0: case PXA210_C0:
2122                 break;
2123 #elif   defined(CONFIG_ARCH_IXP4XX)
2124         case IXP425_A0:
2125         case IXP425_B0:
2126         case IXP465_AD:
2127                 dev->has_cfr = 1;
2128                 break;
2129 #endif
2130         default:
2131                 pr_err("%s: unrecognized processor: %08x\n",
2132                         driver_name, chiprev);
2133                 /* iop3xx, ixp4xx, ... */
2134                 return -ENODEV;
2135         }
2136
2137         irq = platform_get_irq(pdev, 0);
2138         if (irq < 0)
2139                 return -ENODEV;
2140
2141         dev->clk = clk_get(&pdev->dev, "UDCCLK");
2142         if (IS_ERR(dev->clk)) {
2143                 retval = PTR_ERR(dev->clk);
2144                 goto err_clk;
2145         }
2146
2147         pr_debug("%s: IRQ %d%s%s\n", driver_name, irq,
2148                 dev->has_cfr ? "" : " (!cfr)",
2149                 SIZE_STR "(pio)"
2150                 );
2151
2152         /* other non-static parts of init */
2153         dev->dev = &pdev->dev;
2154         dev->mach = pdev->dev.platform_data;
2155
2156         if (dev->mach->gpio_vbus) {
2157                 if ((retval = gpio_request(dev->mach->gpio_vbus,
2158                                 "pxa2xx_udc GPIO VBUS"))) {
2159                         dev_dbg(&pdev->dev,
2160                                 "can't get vbus gpio %d, err: %d\n",
2161                                 dev->mach->gpio_vbus, retval);
2162                         goto err_gpio_vbus;
2163                 }
2164                 gpio_direction_input(dev->mach->gpio_vbus);
2165                 vbus_irq = gpio_to_irq(dev->mach->gpio_vbus);
2166         } else
2167                 vbus_irq = 0;
2168
2169         if (dev->mach->gpio_pullup) {
2170                 if ((retval = gpio_request(dev->mach->gpio_pullup,
2171                                 "pca2xx_udc GPIO PULLUP"))) {
2172                         dev_dbg(&pdev->dev,
2173                                 "can't get pullup gpio %d, err: %d\n",
2174                                 dev->mach->gpio_pullup, retval);
2175                         goto err_gpio_pullup;
2176                 }
2177                 gpio_direction_output(dev->mach->gpio_pullup, 0);
2178         }
2179
2180         init_timer(&dev->timer);
2181         dev->timer.function = udc_watchdog;
2182         dev->timer.data = (unsigned long) dev;
2183
2184         device_initialize(&dev->gadget.dev);
2185         dev->gadget.dev.parent = &pdev->dev;
2186         dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2187
2188         the_controller = dev;
2189         platform_set_drvdata(pdev, dev);
2190
2191         udc_disable(dev);
2192         udc_reinit(dev);
2193
2194         dev->vbus = is_vbus_present();
2195
2196         /* irq setup after old hardware state is cleaned up */
2197         retval = request_irq(irq, pxa2xx_udc_irq,
2198                         IRQF_DISABLED, driver_name, dev);
2199         if (retval != 0) {
2200                 pr_err("%s: can't get irq %d, err %d\n",
2201                         driver_name, irq, retval);
2202                 goto err_irq1;
2203         }
2204         dev->got_irq = 1;
2205
2206 #ifdef CONFIG_ARCH_LUBBOCK
2207         if (machine_is_lubbock()) {
2208                 retval = request_irq(LUBBOCK_USB_DISC_IRQ,
2209                                 lubbock_vbus_irq,
2210                                 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
2211                                 driver_name, dev);
2212                 if (retval != 0) {
2213                         pr_err("%s: can't get irq %i, err %d\n",
2214                                 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2215 lubbock_fail0:
2216                         goto err_irq_lub;
2217                 }
2218                 retval = request_irq(LUBBOCK_USB_IRQ,
2219                                 lubbock_vbus_irq,
2220                                 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
2221                                 driver_name, dev);
2222                 if (retval != 0) {
2223                         pr_err("%s: can't get irq %i, err %d\n",
2224                                 driver_name, LUBBOCK_USB_IRQ, retval);
2225                         free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2226                         goto lubbock_fail0;
2227                 }
2228         } else
2229 #endif
2230         if (vbus_irq) {
2231                 retval = request_irq(vbus_irq, udc_vbus_irq,
2232                                 IRQF_DISABLED | IRQF_SAMPLE_RANDOM |
2233                                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2234                                 driver_name, dev);
2235                 if (retval != 0) {
2236                         pr_err("%s: can't get irq %i, err %d\n",
2237                                 driver_name, vbus_irq, retval);
2238                         goto err_vbus_irq;
2239                 }
2240         }
2241         create_debug_files(dev);
2242
2243         return 0;
2244
2245  err_vbus_irq:
2246 #ifdef  CONFIG_ARCH_LUBBOCK
2247         free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2248  err_irq_lub:
2249 #endif
2250         free_irq(irq, dev);
2251  err_irq1:
2252         if (dev->mach->gpio_pullup)
2253                 gpio_free(dev->mach->gpio_pullup);
2254  err_gpio_pullup:
2255         if (dev->mach->gpio_vbus)
2256                 gpio_free(dev->mach->gpio_vbus);
2257  err_gpio_vbus:
2258         clk_put(dev->clk);
2259  err_clk:
2260         return retval;
2261 }
2262
2263 static void pxa2xx_udc_shutdown(struct platform_device *_dev)
2264 {
2265         pullup_off();
2266 }
2267
2268 static int __exit pxa2xx_udc_remove(struct platform_device *pdev)
2269 {
2270         struct pxa2xx_udc *dev = platform_get_drvdata(pdev);
2271
2272         if (dev->driver)
2273                 return -EBUSY;
2274
2275         dev->pullup = 0;
2276         pullup(dev);
2277
2278         remove_debug_files(dev);
2279
2280         if (dev->got_irq) {
2281                 free_irq(platform_get_irq(pdev, 0), dev);
2282                 dev->got_irq = 0;
2283         }
2284 #ifdef CONFIG_ARCH_LUBBOCK
2285         if (machine_is_lubbock()) {
2286                 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2287                 free_irq(LUBBOCK_USB_IRQ, dev);
2288         }
2289 #endif
2290         if (dev->mach->gpio_vbus) {
2291                 free_irq(gpio_to_irq(dev->mach->gpio_vbus), dev);
2292                 gpio_free(dev->mach->gpio_vbus);
2293         }
2294         if (dev->mach->gpio_pullup)
2295                 gpio_free(dev->mach->gpio_pullup);
2296
2297         clk_put(dev->clk);
2298
2299         platform_set_drvdata(pdev, NULL);
2300         the_controller = NULL;
2301         return 0;
2302 }
2303
2304 /*-------------------------------------------------------------------------*/
2305
2306 #ifdef  CONFIG_PM
2307
2308 /* USB suspend (controlled by the host) and system suspend (controlled
2309  * by the PXA) don't necessarily work well together.  If USB is active,
2310  * the 48 MHz clock is required; so the system can't enter 33 MHz idle
2311  * mode, or any deeper PM saving state.
2312  *
2313  * For now, we punt and forcibly disconnect from the USB host when PXA
2314  * enters any suspend state.  While we're disconnected, we always disable
2315  * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states.
2316  * Boards without software pullup control shouldn't use those states.
2317  * VBUS IRQs should probably be ignored so that the PXA device just acts
2318  * "dead" to USB hosts until system resume.
2319  */
2320 static int pxa2xx_udc_suspend(struct platform_device *dev, pm_message_t state)
2321 {
2322         struct pxa2xx_udc       *udc = platform_get_drvdata(dev);
2323         unsigned long flags;
2324
2325         if (!udc->mach->gpio_pullup && !udc->mach->udc_command)
2326                 WARN("USB host won't detect disconnect!\n");
2327         udc->suspended = 1;
2328
2329         local_irq_save(flags);
2330         pullup(udc);
2331         local_irq_restore(flags);
2332
2333         return 0;
2334 }
2335
2336 static int pxa2xx_udc_resume(struct platform_device *dev)
2337 {
2338         struct pxa2xx_udc       *udc = platform_get_drvdata(dev);
2339         unsigned long flags;
2340
2341         udc->suspended = 0;
2342         local_irq_save(flags);
2343         pullup(udc);
2344         local_irq_restore(flags);
2345
2346         return 0;
2347 }
2348
2349 #else
2350 #define pxa2xx_udc_suspend      NULL
2351 #define pxa2xx_udc_resume       NULL
2352 #endif
2353
2354 /*-------------------------------------------------------------------------*/
2355
2356 static struct platform_driver udc_driver = {
2357         .shutdown       = pxa2xx_udc_shutdown,
2358         .remove         = __exit_p(pxa2xx_udc_remove),
2359         .suspend        = pxa2xx_udc_suspend,
2360         .resume         = pxa2xx_udc_resume,
2361         .driver         = {
2362                 .owner  = THIS_MODULE,
2363                 .name   = "pxa2xx-udc",
2364         },
2365 };
2366
2367 static int __init udc_init(void)
2368 {
2369         pr_info("%s: version %s\n", driver_name, DRIVER_VERSION);
2370         return platform_driver_probe(&udc_driver, pxa2xx_udc_probe);
2371 }
2372 module_init(udc_init);
2373
2374 static void __exit udc_exit(void)
2375 {
2376         platform_driver_unregister(&udc_driver);
2377 }
2378 module_exit(udc_exit);
2379
2380 MODULE_DESCRIPTION(DRIVER_DESC);
2381 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2382 MODULE_LICENSE("GPL");
2383 MODULE_ALIAS("platform:pxa2xx-udc");