git.oblomov.eu Git - linux-2.6/blob - arch/sh/kernel/cpu/sh4a/setup-sh7785.c

   1 /*
   2  * SH7785 Setup
   3  *
   4  *  Copyright (C) 2007  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/io.h>
  15 #include <linux/mm.h>
  16 #include <asm/mmzone.h>
  17
  18 static struct plat_sci_port sci_platform_data[] = {
  19         {
  20                 .mapbase        = 0xffea0000,
  21                 .flags          = UPF_BOOT_AUTOCONF,
  22                 .type           = PORT_SCIF,
  23                 .irqs           = { 40, 40, 40, 40 },
  24         }, {
  25                 .mapbase        = 0xffeb0000,
  26                 .flags          = UPF_BOOT_AUTOCONF,
  27                 .type           = PORT_SCIF,
  28                 .irqs           = { 44, 44, 44, 44 },
  29         }, {
  30                 .mapbase        = 0xffec0000,
  31                 .flags          = UPF_BOOT_AUTOCONF,
  32                 .type           = PORT_SCIF,
  33                 .irqs           = { 60, 60, 60, 60 },
  34         }, {
  35                 .mapbase        = 0xffed0000,
  36                 .flags          = UPF_BOOT_AUTOCONF,
  37                 .type           = PORT_SCIF,
  38                 .irqs           = { 61, 61, 61, 61 },
  39         }, {
  40                 .mapbase        = 0xffee0000,
  41                 .flags          = UPF_BOOT_AUTOCONF,
  42                 .type           = PORT_SCIF,
  43                 .irqs           = { 62, 62, 62, 62 },
  44         }, {
  45                 .mapbase        = 0xffef0000,
  46                 .flags          = UPF_BOOT_AUTOCONF,
  47                 .type           = PORT_SCIF,
  48                 .irqs           = { 63, 63, 63, 63 },
  49         }, {
  50                 .flags = 0,
  51         }
  52 };
  53
  54 static struct platform_device sci_device = {
  55         .name           = "sh-sci",
  56         .id             = -1,
  57         .dev            = {
  58                 .platform_data  = sci_platform_data,
  59         },
  60 };
  61
  62 static struct platform_device *sh7785_devices[] __initdata = {
  63         &sci_device,
  64 };
  65
  66 static int __init sh7785_devices_setup(void)
  67 {
  68         return platform_add_devices(sh7785_devices,
  69                                     ARRAY_SIZE(sh7785_devices));
  70 }
  71 __initcall(sh7785_devices_setup);
  72
  73 enum {
  74         UNUSED = 0,
  75
  76         /* interrupt sources */
  77
  78         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
  79         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
  80         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
  81         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
  82
  83         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
  84         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
  85         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
  86         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
  87
  88         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  89         WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
  90         HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
  91         SCIF2, SCIF3, SCIF4, SCIF5,
  92         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
  93         SIOF, MMCIF, DU, GDTA,
  94         TMU3, TMU4, TMU5,
  95         SSI0, SSI1,
  96         HAC0, HAC1,
  97         FLCTL, GPIO,
  98
  99         /* interrupt groups */
 100
 101         TMU012, TMU345
 102 };
 103
 104 static struct intc_vect vectors[] __initdata = {
 105         INTC_VECT(WDT, 0x560),
 106         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 107         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 108         INTC_VECT(HUDI, 0x600),
 109         INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
 110         INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
 111         INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
 112         INTC_VECT(DMAC0, 0x6e0),
 113         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 114         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 115         INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
 116         INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
 117         INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
 118         INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
 119         INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
 120         INTC_VECT(DMAC1, 0x940),
 121         INTC_VECT(HSPI, 0x960),
 122         INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
 123         INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
 124         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 125         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 126         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 127         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 128         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 129         INTC_VECT(SIOF, 0xc00),
 130         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 131         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 132         INTC_VECT(DU, 0xd80),
 133         INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
 134         INTC_VECT(GDTA, 0xde0),
 135         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 136         INTC_VECT(TMU5, 0xe40),
 137         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 138         INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
 139         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
 140         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
 141         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 142         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 143 };
 144
 145 static struct intc_group groups[] __initdata = {
 146         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 147         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 148 };
 149
 150 static struct intc_mask_reg mask_registers[] __initdata = {
 151         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 152           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 153
 154         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 155           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 156             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 157             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 158             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 159             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 160             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 161             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 162             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 163
 164         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 165           { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
 166             FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 167             PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
 168             SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
 169 };
 170
 171 static struct intc_prio_reg prio_registers[] __initdata = {
 172         { 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 173                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 174         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 175                                                  TMU2, TMU2_TICPI } },
 176         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
 177         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
 178                                                  SCIF2, SCIF3 } },
 179         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
 180         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
 181         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
 182                                                  PCISERR, PCIINTA } },
 183         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
 184                                                  PCIINTD, PCIC5 } },
 185         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
 186         { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
 187         { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
 188 };
 189
 190 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
 191                          mask_registers, prio_registers, NULL);
 192
 193 /* Support for external interrupt pins in IRQ mode */
 194
 195 static struct intc_vect vectors_irq0123[] __initdata = {
 196         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 197         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 198 };
 199
 200 static struct intc_vect vectors_irq4567[] __initdata = {
 201         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 202         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 203 };
 204
 205 static struct intc_sense_reg sense_registers[] __initdata = {
 206         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 207                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 208 };
 209
 210 static struct intc_mask_reg ack_registers[] __initdata = {
 211         { 0xffd00024, 0, 32, /* INTREQ */
 212           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 213 };
 214
 215 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
 216                              vectors_irq0123, NULL, mask_registers,
 217                              prio_registers, sense_registers, ack_registers);
 218
 219 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
 220                              vectors_irq4567, NULL, mask_registers,
 221                              prio_registers, sense_registers, ack_registers);
 222
 223 /* External interrupt pins in IRL mode */
 224
 225 static struct intc_vect vectors_irl0123[] __initdata = {
 226         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 227         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 228         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 229         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 230         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 231         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 232         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 233         INTC_VECT(IRL0_HHHL, 0x3c0),
 234 };
 235
 236 static struct intc_vect vectors_irl4567[] __initdata = {
 237         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
 238         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
 239         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
 240         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
 241         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
 242         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
 243         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
 244         INTC_VECT(IRL4_HHHL, 0xcc0),
 245 };
 246
 247 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
 248                          NULL, mask_registers, NULL, NULL);
 249
 250 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 251                          NULL, mask_registers, NULL, NULL);
 252
 253 #define INTC_ICR0       0xffd00000
 254 #define INTC_INTMSK0    0xffd00044
 255 #define INTC_INTMSK1    0xffd00048
 256 #define INTC_INTMSK2    0xffd40080
 257 #define INTC_INTMSKCLR1 0xffd00068
 258 #define INTC_INTMSKCLR2 0xffd40084
 259
 260 void __init plat_irq_setup(void)
 261 {
 262         /* disable IRQ3-0 + IRQ7-4 */
 263         ctrl_outl(0xff000000, INTC_INTMSK0);
 264
 265         /* disable IRL3-0 + IRL7-4 */
 266         ctrl_outl(0xc0000000, INTC_INTMSK1);
 267         ctrl_outl(0xfffefffe, INTC_INTMSK2);
 268
 269         /* select IRL mode for IRL3-0 + IRL7-4 */
 270         ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 271
 272         /* disable holding function, ie enable "SH-4 Mode" */
 273         ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 274
 275         register_intc_controller(&intc_desc);
 276 }
 277
 278 void __init plat_irq_setup_pins(int mode)
 279 {
 280         switch (mode) {
 281         case IRQ_MODE_IRQ7654:
 282                 /* select IRQ mode for IRL7-4 */
 283                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 284                 register_intc_controller(&intc_desc_irq4567);
 285                 break;
 286         case IRQ_MODE_IRQ3210:
 287                 /* select IRQ mode for IRL3-0 */
 288                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 289                 register_intc_controller(&intc_desc_irq0123);
 290                 break;
 291         case IRQ_MODE_IRL7654:
 292                 /* enable IRL7-4 but don't provide any masking */
 293                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 294                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
 295                 break;
 296         case IRQ_MODE_IRL3210:
 297                 /* enable IRL0-3 but don't provide any masking */
 298                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 299                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
 300                 break;
 301         case IRQ_MODE_IRL7654_MASK:
 302                 /* enable IRL7-4 and mask using cpu intc controller */
 303                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 304                 register_intc_controller(&intc_desc_irl4567);
 305                 break;
 306         case IRQ_MODE_IRL3210_MASK:
 307                 /* enable IRL0-3 and mask using cpu intc controller */
 308                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 309                 register_intc_controller(&intc_desc_irl0123);
 310                 break;
 311         default:
 312                 BUG();
 313         }
 314 }
 315
 316 void __init plat_mem_setup(void)
 317 {
 318         /* Register the URAM space as Node 1 */
 319         setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
 320 }