2 * BRIEF MODULE DESCRIPTION
3 * Au1000 interrupt routines.
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 #include <linux/bitops.h>
30 #include <linux/init.h>
32 #include <linux/interrupt.h>
33 #include <linux/irq.h>
35 #include <asm/mipsregs.h>
36 #include <asm/mach-au1x00/au1000.h>
37 #ifdef CONFIG_MIPS_PB1000
38 #include <asm/mach-pb1x00/pb1000.h>
41 #define EXT_INTC0_REQ0 2 /* IP 2 */
42 #define EXT_INTC0_REQ1 3 /* IP 3 */
43 #define EXT_INTC1_REQ0 4 /* IP 4 */
44 #define EXT_INTC1_REQ1 5 /* IP 5 */
45 #define MIPS_TIMER_IP 7 /* IP 7 */
47 void (*board_init_irq)(void);
49 static DEFINE_SPINLOCK(irq_lock);
54 * Save/restore the interrupt controller state.
55 * Called from the save/restore core registers as part of the
56 * au_sleep function in power.c.....maybe I should just pm_register()
59 static unsigned int sleep_intctl_config0[2];
60 static unsigned int sleep_intctl_config1[2];
61 static unsigned int sleep_intctl_config2[2];
62 static unsigned int sleep_intctl_src[2];
63 static unsigned int sleep_intctl_assign[2];
64 static unsigned int sleep_intctl_wake[2];
65 static unsigned int sleep_intctl_mask[2];
67 void save_au1xxx_intctl(void)
69 sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
70 sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
71 sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
72 sleep_intctl_src[0] = au_readl(IC0_SRCRD);
73 sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
74 sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
75 sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
77 sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
78 sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
79 sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
80 sleep_intctl_src[1] = au_readl(IC1_SRCRD);
81 sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
82 sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
83 sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
87 * For most restore operations, we clear the entire register and
88 * then set the bits we found during the save.
90 void restore_au1xxx_intctl(void)
92 au_writel(0xffffffff, IC0_MASKCLR); au_sync();
94 au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
95 au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
96 au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
97 au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
98 au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
99 au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
100 au_writel(0xffffffff, IC0_SRCCLR); au_sync();
101 au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
102 au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
103 au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
104 au_writel(0xffffffff, IC0_WAKECLR); au_sync();
105 au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
106 au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
107 au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
108 au_writel(0x00000000, IC0_TESTBIT); au_sync();
110 au_writel(0xffffffff, IC1_MASKCLR); au_sync();
112 au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
113 au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
114 au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
115 au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
116 au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
117 au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
118 au_writel(0xffffffff, IC1_SRCCLR); au_sync();
119 au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
120 au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
121 au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
122 au_writel(0xffffffff, IC1_WAKECLR); au_sync();
123 au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
124 au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
125 au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
126 au_writel(0x00000000, IC1_TESTBIT); au_sync();
128 au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
130 au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
132 #endif /* CONFIG_PM */
135 inline void local_enable_irq(unsigned int irq_nr)
137 if (irq_nr > AU1000_LAST_INTC0_INT) {
138 au_writel(1 << (irq_nr - 32), IC1_MASKSET);
139 au_writel(1 << (irq_nr - 32), IC1_WAKESET);
141 au_writel(1 << irq_nr, IC0_MASKSET);
142 au_writel(1 << irq_nr, IC0_WAKESET);
148 inline void local_disable_irq(unsigned int irq_nr)
150 if (irq_nr > AU1000_LAST_INTC0_INT) {
151 au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
152 au_writel(1 << (irq_nr - 32), IC1_WAKECLR);
154 au_writel(1 << irq_nr, IC0_MASKCLR);
155 au_writel(1 << irq_nr, IC0_WAKECLR);
161 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
163 if (irq_nr > AU1000_LAST_INTC0_INT) {
164 au_writel(1 << (irq_nr - 32), IC1_RISINGCLR);
165 au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
167 au_writel(1 << irq_nr, IC0_RISINGCLR);
168 au_writel(1 << irq_nr, IC0_MASKCLR);
174 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
176 if (irq_nr > AU1000_LAST_INTC0_INT) {
177 au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR);
178 au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
180 au_writel(1 << irq_nr, IC0_FALLINGCLR);
181 au_writel(1 << irq_nr, IC0_MASKCLR);
187 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
189 /* This may assume that we don't get interrupts from
190 * both edges at once, or if we do, that we don't care.
192 if (irq_nr > AU1000_LAST_INTC0_INT) {
193 au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR);
194 au_writel(1 << (irq_nr - 32), IC1_RISINGCLR);
195 au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
197 au_writel(1 << irq_nr, IC0_FALLINGCLR);
198 au_writel(1 << irq_nr, IC0_RISINGCLR);
199 au_writel(1 << irq_nr, IC0_MASKCLR);
205 static inline void mask_and_ack_level_irq(unsigned int irq_nr)
208 local_disable_irq(irq_nr);
210 #if defined(CONFIG_MIPS_PB1000)
211 if (irq_nr == AU1000_GPIO_15) {
212 au_writel(0x8000, PB1000_MDR); /* ack int */
220 static void end_irq(unsigned int irq_nr)
222 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
223 local_enable_irq(irq_nr);
225 #if defined(CONFIG_MIPS_PB1000)
226 if (irq_nr == AU1000_GPIO_15) {
227 au_writel(0x4000, PB1000_MDR); /* enable int */
233 unsigned long save_local_and_disable(int controller)
236 unsigned long flags, mask;
238 spin_lock_irqsave(&irq_lock, flags);
240 mask = au_readl(IC1_MASKSET);
241 for (i = 32; i < 64; i++)
242 local_disable_irq(i);
244 mask = au_readl(IC0_MASKSET);
245 for (i = 0; i < 32; i++)
246 local_disable_irq(i);
248 spin_unlock_irqrestore(&irq_lock, flags);
253 void restore_local_and_enable(int controller, unsigned long mask)
256 unsigned long flags, new_mask;
258 spin_lock_irqsave(&irq_lock, flags);
259 for (i = 0; i < 32; i++) {
260 if (mask & (1 << i)) {
262 local_enable_irq(i + 32);
268 new_mask = au_readl(IC1_MASKSET);
270 new_mask = au_readl(IC0_MASKSET);
272 spin_unlock_irqrestore(&irq_lock, flags);
276 static struct irq_chip rise_edge_irq_type = {
277 .name = "Au1000 Rise Edge",
278 .ack = mask_and_ack_rise_edge_irq,
279 .mask = local_disable_irq,
280 .mask_ack = mask_and_ack_rise_edge_irq,
281 .unmask = local_enable_irq,
285 static struct irq_chip fall_edge_irq_type = {
286 .name = "Au1000 Fall Edge",
287 .ack = mask_and_ack_fall_edge_irq,
288 .mask = local_disable_irq,
289 .mask_ack = mask_and_ack_fall_edge_irq,
290 .unmask = local_enable_irq,
294 static struct irq_chip either_edge_irq_type = {
295 .name = "Au1000 Rise or Fall Edge",
296 .ack = mask_and_ack_either_edge_irq,
297 .mask = local_disable_irq,
298 .mask_ack = mask_and_ack_either_edge_irq,
299 .unmask = local_enable_irq,
303 static struct irq_chip level_irq_type = {
304 .name = "Au1000 Level",
305 .ack = mask_and_ack_level_irq,
306 .mask = local_disable_irq,
307 .mask_ack = mask_and_ack_level_irq,
308 .unmask = local_enable_irq,
313 void startup_match20_interrupt(irq_handler_t handler)
315 struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT];
317 static struct irqaction action;
318 memset(&action, 0, sizeof(struct irqaction));
321 * This is a big problem.... since we didn't use request_irq
322 * when kernel/irq.c calls probe_irq_xxx this interrupt will
323 * be probed for usage. This will end up disabling the device :(
324 * Give it a bogus "action" pointer -- this will keep it from
325 * getting auto-probed!
327 * By setting the status to match that of request_irq() we
328 * can avoid it. --cgray
330 action.dev_id = handler;
331 action.flags = IRQF_DISABLED;
332 cpus_clear(action.mask);
333 action.name = "Au1xxx TOY";
334 action.handler = handler;
337 desc->action = &action;
338 desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS);
340 local_enable_irq(AU1000_TOY_MATCH2_INT);
344 static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
346 if (irq_nr > AU1000_MAX_INTR) return;
347 /* Config2[n], Config1[n], Config0[n] */
348 if (irq_nr > AU1000_LAST_INTC0_INT) {
350 case INTC_INT_RISE_EDGE: /* 0:0:1 */
351 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
352 au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
353 au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
354 set_irq_chip(irq_nr, &rise_edge_irq_type);
356 case INTC_INT_FALL_EDGE: /* 0:1:0 */
357 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
358 au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
359 au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
360 set_irq_chip(irq_nr, &fall_edge_irq_type);
362 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
363 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
364 au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
365 au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
366 set_irq_chip(irq_nr, &either_edge_irq_type);
368 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
369 au_writel(1 << (irq_nr - 32), IC1_CFG2SET);
370 au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
371 au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
372 set_irq_chip(irq_nr, &level_irq_type);
374 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
375 au_writel(1 << (irq_nr - 32), IC1_CFG2SET);
376 au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
377 au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
378 set_irq_chip(irq_nr, &level_irq_type);
380 case INTC_INT_DISABLED: /* 0:0:0 */
381 au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
382 au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
383 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
385 default: /* disable the interrupt */
386 printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
388 au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
389 au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
390 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
393 if (int_req) /* assign to interrupt request 1 */
394 au_writel(1 << (irq_nr - 32), IC1_ASSIGNCLR);
395 else /* assign to interrupt request 0 */
396 au_writel(1 << (irq_nr - 32), IC1_ASSIGNSET);
397 au_writel(1 << (irq_nr - 32), IC1_SRCSET);
398 au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
399 au_writel(1 << (irq_nr - 32), IC1_WAKECLR);
402 case INTC_INT_RISE_EDGE: /* 0:0:1 */
403 au_writel(1 << irq_nr, IC0_CFG2CLR);
404 au_writel(1 << irq_nr, IC0_CFG1CLR);
405 au_writel(1 << irq_nr, IC0_CFG0SET);
406 set_irq_chip(irq_nr, &rise_edge_irq_type);
408 case INTC_INT_FALL_EDGE: /* 0:1:0 */
409 au_writel(1 << irq_nr, IC0_CFG2CLR);
410 au_writel(1 << irq_nr, IC0_CFG1SET);
411 au_writel(1 << irq_nr, IC0_CFG0CLR);
412 set_irq_chip(irq_nr, &fall_edge_irq_type);
414 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
415 au_writel(1 << irq_nr, IC0_CFG2CLR);
416 au_writel(1 << irq_nr, IC0_CFG1SET);
417 au_writel(1 << irq_nr, IC0_CFG0SET);
418 set_irq_chip(irq_nr, &either_edge_irq_type);
420 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
421 au_writel(1 << irq_nr, IC0_CFG2SET);
422 au_writel(1 << irq_nr, IC0_CFG1CLR);
423 au_writel(1 << irq_nr, IC0_CFG0SET);
424 set_irq_chip(irq_nr, &level_irq_type);
426 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
427 au_writel(1 << irq_nr, IC0_CFG2SET);
428 au_writel(1 << irq_nr, IC0_CFG1SET);
429 au_writel(1 << irq_nr, IC0_CFG0CLR);
430 set_irq_chip(irq_nr, &level_irq_type);
432 case INTC_INT_DISABLED: /* 0:0:0 */
433 au_writel(1 << irq_nr, IC0_CFG0CLR);
434 au_writel(1 << irq_nr, IC0_CFG1CLR);
435 au_writel(1 << irq_nr, IC0_CFG2CLR);
437 default: /* disable the interrupt */
438 printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
440 au_writel(1 << irq_nr, IC0_CFG0CLR);
441 au_writel(1 << irq_nr, IC0_CFG1CLR);
442 au_writel(1 << irq_nr, IC0_CFG2CLR);
445 if (int_req) /* assign to interrupt request 1 */
446 au_writel(1 << irq_nr, IC0_ASSIGNCLR);
447 else /* assign to interrupt request 0 */
448 au_writel(1 << irq_nr, IC0_ASSIGNSET);
449 au_writel(1 << irq_nr, IC0_SRCSET);
450 au_writel(1 << irq_nr, IC0_MASKCLR);
451 au_writel(1 << irq_nr, IC0_WAKECLR);
457 * Interrupts are nested. Even if an interrupt handler is registered
458 * as "fast", we might get another interrupt before we return from
459 * intcX_reqX_irqdispatch().
462 static void intc0_req0_irqdispatch(void)
465 static unsigned long intc0_req0;
467 intc0_req0 |= au_readl(IC0_REQ0INT);
472 #ifdef AU1000_USB_DEV_REQ_INT
474 * Because of the tight timing of SETUP token to reply
475 * transactions, the USB devices-side packet complete
476 * interrupt needs the highest priority.
478 if ((intc0_req0 & (1 << AU1000_USB_DEV_REQ_INT))) {
479 intc0_req0 &= ~(1 << AU1000_USB_DEV_REQ_INT);
480 do_IRQ(AU1000_USB_DEV_REQ_INT);
484 irq = ffs(intc0_req0);
485 intc0_req0 &= ~(1 << irq);
490 static void intc0_req1_irqdispatch(void)
493 static unsigned long intc0_req1;
495 intc0_req1 |= au_readl(IC0_REQ1INT);
500 irq = ffs(intc0_req1);
501 intc0_req1 &= ~(1 << irq);
507 * Interrupt Controller 1:
510 static void intc1_req0_irqdispatch(void)
513 static unsigned long intc1_req0;
515 intc1_req0 |= au_readl(IC1_REQ0INT);
520 irq = ffs(intc1_req0);
521 intc1_req0 &= ~(1 << irq);
527 static void intc1_req1_irqdispatch(void)
530 static unsigned long intc1_req1;
532 intc1_req1 |= au_readl(IC1_REQ1INT);
537 irq = ffs(intc1_req1);
538 intc1_req1 &= ~(1 << irq);
543 asmlinkage void plat_irq_dispatch(void)
545 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
547 if (pending & CAUSEF_IP7)
549 else if (pending & CAUSEF_IP2)
550 intc0_req0_irqdispatch();
551 else if (pending & CAUSEF_IP3)
552 intc0_req1_irqdispatch();
553 else if (pending & CAUSEF_IP4)
554 intc1_req0_irqdispatch();
555 else if (pending & CAUSEF_IP5)
556 intc1_req1_irqdispatch();
558 spurious_interrupt();
561 void __init arch_init_irq(void)
564 unsigned long cp0_status;
565 struct au1xxx_irqmap *imp;
566 extern struct au1xxx_irqmap au1xxx_irq_map[];
567 extern struct au1xxx_irqmap au1xxx_ic0_map[];
568 extern int au1xxx_nr_irqs;
569 extern int au1xxx_ic0_nr_irqs;
571 cp0_status = read_c0_status();
573 /* Initialize interrupt controllers to a safe state.
575 au_writel(0xffffffff, IC0_CFG0CLR);
576 au_writel(0xffffffff, IC0_CFG1CLR);
577 au_writel(0xffffffff, IC0_CFG2CLR);
578 au_writel(0xffffffff, IC0_MASKCLR);
579 au_writel(0xffffffff, IC0_ASSIGNSET);
580 au_writel(0xffffffff, IC0_WAKECLR);
581 au_writel(0xffffffff, IC0_SRCSET);
582 au_writel(0xffffffff, IC0_FALLINGCLR);
583 au_writel(0xffffffff, IC0_RISINGCLR);
584 au_writel(0x00000000, IC0_TESTBIT);
586 au_writel(0xffffffff, IC1_CFG0CLR);
587 au_writel(0xffffffff, IC1_CFG1CLR);
588 au_writel(0xffffffff, IC1_CFG2CLR);
589 au_writel(0xffffffff, IC1_MASKCLR);
590 au_writel(0xffffffff, IC1_ASSIGNSET);
591 au_writel(0xffffffff, IC1_WAKECLR);
592 au_writel(0xffffffff, IC1_SRCSET);
593 au_writel(0xffffffff, IC1_FALLINGCLR);
594 au_writel(0xffffffff, IC1_RISINGCLR);
595 au_writel(0x00000000, IC1_TESTBIT);
597 /* Initialize IC0, which is fixed per processor.
599 imp = au1xxx_ic0_map;
600 for (i = 0; i < au1xxx_ic0_nr_irqs; i++) {
601 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
605 /* Now set up the irq mapping for the board.
607 imp = au1xxx_irq_map;
608 for (i = 0; i < au1xxx_nr_irqs; i++) {
609 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
613 set_c0_status(ALLINTS);
615 /* Board specific IRQ initialization.