Merge HEAD from ../scsi-iscsi-2.6
[linux-2.6] / drivers / video / aty / atyfb_base.c
1 /*
2  *  ATI Frame Buffer Device Driver Core
3  *
4  *      Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
5  *      Copyright (C) 1997-2001  Geert Uytterhoeven
6  *      Copyright (C) 1998  Bernd Harries
7  *      Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
8  *
9  *  This driver supports the following ATI graphics chips:
10  *    - ATI Mach64
11  *
12  *  To do: add support for
13  *    - ATI Rage128 (from aty128fb.c)
14  *    - ATI Radeon (from radeonfb.c)
15  *
16  *  This driver is partly based on the PowerMac console driver:
17  *
18  *      Copyright (C) 1996 Paul Mackerras
19  *
20  *  and on the PowerMac ATI/mach64 display driver:
21  *
22  *      Copyright (C) 1997 Michael AK Tesch
23  *
24  *            with work by Jon Howell
25  *                         Harry AC Eaton
26  *                         Anthony Tong <atong@uiuc.edu>
27  *
28  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
30  *
31  *  This file is subject to the terms and conditions of the GNU General Public
32  *  License. See the file COPYING in the main directory of this archive for
33  *  more details.
34  *
35  *  Many thanks to Nitya from ATI devrel for support and patience !
36  */
37
38 /******************************************************************************
39
40   TODO:
41
42     - cursor support on all cards and all ramdacs.
43     - cursor parameters controlable via ioctl()s.
44     - guess PLL and MCLK based on the original PLL register values initialized
45       by Open Firmware (if they are initialized). BIOS is done
46
47     (Anyone with Mac to help with this?)
48
49 ******************************************************************************/
50
51
52 #include <linux/config.h>
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/kernel.h>
56 #include <linux/errno.h>
57 #include <linux/string.h>
58 #include <linux/mm.h>
59 #include <linux/slab.h>
60 #include <linux/vmalloc.h>
61 #include <linux/delay.h>
62 #include <linux/console.h>
63 #include <linux/fb.h>
64 #include <linux/init.h>
65 #include <linux/pci.h>
66 #include <linux/interrupt.h>
67 #include <linux/spinlock.h>
68 #include <linux/wait.h>
69
70 #include <asm/io.h>
71 #include <asm/uaccess.h>
72
73 #include <video/mach64.h>
74 #include "atyfb.h"
75 #include "ati_ids.h"
76
77 #ifdef __powerpc__
78 #include <asm/prom.h>
79 #include "../macmodes.h"
80 #endif
81 #ifdef __sparc__
82 #include <asm/pbm.h>
83 #include <asm/fbio.h>
84 #endif
85
86 #ifdef CONFIG_ADB_PMU
87 #include <linux/adb.h>
88 #include <linux/pmu.h>
89 #endif
90 #ifdef CONFIG_BOOTX_TEXT
91 #include <asm/btext.h>
92 #endif
93 #ifdef CONFIG_PMAC_BACKLIGHT
94 #include <asm/backlight.h>
95 #endif
96 #ifdef CONFIG_MTRR
97 #include <asm/mtrr.h>
98 #endif
99
100 /*
101  * Debug flags.
102  */
103 #undef DEBUG
104 /*#define DEBUG*/
105
106 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
107 /*  - must be large enough to catch all GUI-Regs   */
108 /*  - must be aligned to a PAGE boundary           */
109 #define GUI_RESERVE     (1 * PAGE_SIZE)
110
111 /* FIXME: remove the FAIL definition */
112 #define FAIL(msg) do { printk(KERN_CRIT "atyfb: " msg "\n"); return -EINVAL; } while (0)
113 #define FAIL_MAX(msg, x, _max_) do { if(x > _max_) { printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); return -EINVAL; } } while (0)
114
115 #ifdef DEBUG
116 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "atyfb: " fmt, ## args)
117 #else
118 #define DPRINTK(fmt, args...)
119 #endif
120
121 #define PRINTKI(fmt, args...)   printk(KERN_INFO "atyfb: " fmt, ## args)
122 #define PRINTKE(fmt, args...)    printk(KERN_ERR "atyfb: " fmt, ## args)
123
124 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
125 static const u32 lt_lcd_regs[] = {
126         CONFIG_PANEL_LG,
127         LCD_GEN_CNTL_LG,
128         DSTN_CONTROL_LG,
129         HFB_PITCH_ADDR_LG,
130         HORZ_STRETCHING_LG,
131         VERT_STRETCHING_LG,
132         0, /* EXT_VERT_STRETCH */
133         LT_GIO_LG,
134         POWER_MANAGEMENT_LG
135 };
136
137 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
138 {
139         if (M64_HAS(LT_LCD_REGS)) {
140                 aty_st_le32(lt_lcd_regs[index], val, par);
141         } else {
142                 unsigned long temp;
143
144                 /* write addr byte */
145                 temp = aty_ld_le32(LCD_INDEX, par);
146                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
147                 /* write the register value */
148                 aty_st_le32(LCD_DATA, val, par);
149         }
150 }
151
152 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
153 {
154         if (M64_HAS(LT_LCD_REGS)) {
155                 return aty_ld_le32(lt_lcd_regs[index], par);
156         } else {
157                 unsigned long temp;
158
159                 /* write addr byte */
160                 temp = aty_ld_le32(LCD_INDEX, par);
161                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
162                 /* read the register value */
163                 return aty_ld_le32(LCD_DATA, par);
164         }
165 }
166 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
167
168 #ifdef CONFIG_FB_ATY_GENERIC_LCD
169 /*
170  * ATIReduceRatio --
171  *
172  * Reduce a fraction by factoring out the largest common divider of the
173  * fraction's numerator and denominator.
174  */
175 static void ATIReduceRatio(int *Numerator, int *Denominator)
176 {
177     int Multiplier, Divider, Remainder;
178
179     Multiplier = *Numerator;
180     Divider = *Denominator;
181
182     while ((Remainder = Multiplier % Divider))
183     {
184         Multiplier = Divider;
185         Divider = Remainder;
186     }
187
188     *Numerator /= Divider;
189     *Denominator /= Divider;
190 }
191 #endif
192     /*
193      *  The Hardware parameters for each card
194      */
195
196 struct aty_cmap_regs {
197         u8 windex;
198         u8 lut;
199         u8 mask;
200         u8 rindex;
201         u8 cntl;
202 };
203
204 struct pci_mmap_map {
205         unsigned long voff;
206         unsigned long poff;
207         unsigned long size;
208         unsigned long prot_flag;
209         unsigned long prot_mask;
210 };
211
212 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
213         .id             = "ATY Mach64",
214         .type           = FB_TYPE_PACKED_PIXELS,
215         .visual         = FB_VISUAL_PSEUDOCOLOR,
216         .xpanstep       = 8,
217         .ypanstep       = 1,
218 };
219
220     /*
221      *  Frame buffer device API
222      */
223
224 static int atyfb_open(struct fb_info *info, int user);
225 static int atyfb_release(struct fb_info *info, int user);
226 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
227 static int atyfb_set_par(struct fb_info *info);
228 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
229         u_int transp, struct fb_info *info);
230 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
231 static int atyfb_blank(int blank, struct fb_info *info);
232 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
233         u_long arg, struct fb_info *info);
234 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
235 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
236 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
237 #ifdef __sparc__
238 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma);
239 #endif
240 static int atyfb_sync(struct fb_info *info);
241
242     /*
243      *  Internal routines
244      */
245
246 static int aty_init(struct fb_info *info, const char *name);
247 #ifdef CONFIG_ATARI
248 static int store_video_par(char *videopar, unsigned char m64_num);
249 #endif
250
251 static struct crtc saved_crtc;
252 static union aty_pll saved_pll;
253 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
254
255 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
256 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
257 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
258 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
259 #ifdef CONFIG_PPC
260 static int read_aty_sense(const struct atyfb_par *par);
261 #endif
262
263
264     /*
265      *  Interface used by the world
266      */
267
268 static struct fb_var_screeninfo default_var = {
269         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
270         640, 480, 640, 480, 0, 0, 8, 0,
271         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
272         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
273         0, FB_VMODE_NONINTERLACED
274 };
275
276 static struct fb_videomode defmode = {
277         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
278         NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
279         0, FB_VMODE_NONINTERLACED
280 };
281
282 static struct fb_ops atyfb_ops = {
283         .owner          = THIS_MODULE,
284         .fb_open        = atyfb_open,
285         .fb_release     = atyfb_release,
286         .fb_check_var   = atyfb_check_var,
287         .fb_set_par     = atyfb_set_par,
288         .fb_setcolreg   = atyfb_setcolreg,
289         .fb_pan_display = atyfb_pan_display,
290         .fb_blank       = atyfb_blank,
291         .fb_ioctl       = atyfb_ioctl,
292         .fb_fillrect    = atyfb_fillrect,
293         .fb_copyarea    = atyfb_copyarea,
294         .fb_imageblit   = atyfb_imageblit,
295         .fb_cursor      = soft_cursor,
296 #ifdef __sparc__
297         .fb_mmap        = atyfb_mmap,
298 #endif
299         .fb_sync        = atyfb_sync,
300 };
301
302 static int noaccel;
303 #ifdef CONFIG_MTRR
304 static int nomtrr;
305 #endif
306 static int vram;
307 static int pll;
308 static int mclk;
309 static int xclk;
310 static int comp_sync __initdata = -1;
311 static char *mode;
312
313 #ifdef CONFIG_PPC
314 static int default_vmode __initdata = VMODE_CHOOSE;
315 static int default_cmode __initdata = CMODE_CHOOSE;
316
317 module_param_named(vmode, default_vmode, int, 0);
318 MODULE_PARM_DESC(vmode, "int: video mode for mac");
319 module_param_named(cmode, default_cmode, int, 0);
320 MODULE_PARM_DESC(cmode, "int: color mode for mac");
321 #endif
322
323 #ifdef CONFIG_ATARI
324 static unsigned int mach64_count __initdata = 0;
325 static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
326 static unsigned long phys_size[FB_MAX] __initdata = { 0, };
327 static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
328 #endif
329
330 /* top -> down is an evolution of mach64 chipset, any corrections? */
331 #define ATI_CHIP_88800GX   (M64F_GX)
332 #define ATI_CHIP_88800CX   (M64F_GX)
333
334 #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
335 #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
336
337 #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
338 #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
339
340 #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
341 #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
342 #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
343
344 #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
345
346 /* make sets shorter */
347 #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
348
349 #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
350 /*#define ATI_CHIP_264GTDVD  ?*/
351 #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
352
353 #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
354 #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
355 #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
356
357 #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
358 #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
359
360 static struct {
361         u16 pci_id;
362         const char *name;
363         int pll, mclk, xclk;
364         u32 features;
365 } aty_chips[] __devinitdata = {
366 #ifdef CONFIG_FB_ATY_GX
367         /* Mach64 GX */
368         { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, ATI_CHIP_88800GX },
369         { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, ATI_CHIP_88800CX },
370 #endif /* CONFIG_FB_ATY_GX */
371
372 #ifdef CONFIG_FB_ATY_CT
373         { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, ATI_CHIP_264CT },
374         { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, ATI_CHIP_264ET },
375         { PCI_CHIP_MACH64VT, "ATI264VT? (Mach64 VT)", 170, 67, 67, ATI_CHIP_264VT },
376         { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, ATI_CHIP_264GT },
377         /* FIXME { ...ATI_264GU, maybe ATI_CHIP_264GTDVD }, */
378         { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GTB)", 200, 67, 67, ATI_CHIP_264GTB  },
379         { PCI_CHIP_MACH64VU, "ATI264VTB (Mach64 VU)", 200, 67, 67, ATI_CHIP_264VT3 },
380
381         { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, ATI_CHIP_264LT },
382          /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */
383         { PCI_CHIP_MACH64LG, "3D RAGE LT-G (Mach64 LG)", 230, 63, 63, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
384
385         { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, ATI_CHIP_264VT4 },
386
387         { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
388         { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
389         { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
390         { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
391
392         { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, ATI_CHIP_264GTPRO },
393         { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, ATI_CHIP_264GTPRO },
394         { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
395         { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO },
396         { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, ATI_CHIP_264GTPRO },
397
398         { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, ATI_CHIP_264LTPRO },
399         { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, ATI_CHIP_264LTPRO },
400         { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
401         { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
402         { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
403
404         { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP)", 230, 83, 63, ATI_CHIP_264XL },
405         { PCI_CHIP_MACH64GN, "3D RAGE XL (Mach64 GN, AGP)", 230, 83, 63, ATI_CHIP_264XL },
406         { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66/BGA)", 230, 83, 63, ATI_CHIP_264XL },
407         { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33MHz)", 230, 83, 63, ATI_CHIP_264XL },
408         { PCI_CHIP_MACH64GL, "3D RAGE XL (Mach64 GL, PCI)", 230, 83, 63, ATI_CHIP_264XL },
409         { PCI_CHIP_MACH64GS, "3D RAGE XL (Mach64 GS, PCI)", 230, 83, 63, ATI_CHIP_264XL },
410
411         { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
412         { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
413         { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
414         { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
415 #endif /* CONFIG_FB_ATY_CT */
416 };
417
418 /* can not fail */
419 static int __devinit correct_chipset(struct atyfb_par *par)
420 {
421         u8 rev;
422         u16 type;
423         u32 chip_id;
424         const char *name;
425         int i;
426
427         for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
428                 if (par->pci_id == aty_chips[i].pci_id)
429                         break;
430
431         name = aty_chips[i].name;
432         par->pll_limits.pll_max = aty_chips[i].pll;
433         par->pll_limits.mclk = aty_chips[i].mclk;
434         par->pll_limits.xclk = aty_chips[i].xclk;
435         par->features = aty_chips[i].features;
436
437         chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
438         type = chip_id & CFG_CHIP_TYPE;
439         rev = (chip_id & CFG_CHIP_REV) >> 24;
440
441         switch(par->pci_id) {
442 #ifdef CONFIG_FB_ATY_GX
443         case PCI_CHIP_MACH64GX:
444                 if(type != 0x00d7)
445                         return -ENODEV;
446                 break;
447         case PCI_CHIP_MACH64CX:
448                 if(type != 0x0057)
449                         return -ENODEV;
450                 break;
451 #endif
452 #ifdef CONFIG_FB_ATY_CT
453         case PCI_CHIP_MACH64VT:
454                 rev &= 0xc7;
455                 if(rev == 0x00) {
456                         name = "ATI264VTA3 (Mach64 VT)";
457                         par->pll_limits.pll_max = 170;
458                         par->pll_limits.mclk = 67;
459                         par->pll_limits.xclk = 67;
460                         par->features = ATI_CHIP_264VT;
461                 } else if(rev == 0x40) {
462                         name = "ATI264VTA4 (Mach64 VT)";
463                         par->pll_limits.pll_max = 200;
464                         par->pll_limits.mclk = 67;
465                         par->pll_limits.xclk = 67;
466                         par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
467                 } else {
468                         name = "ATI264VTB (Mach64 VT)";
469                         par->pll_limits.pll_max = 200;
470                         par->pll_limits.mclk = 67;
471                         par->pll_limits.xclk = 67;
472                         par->features = ATI_CHIP_264VTB;
473                 }
474                 break;
475         case PCI_CHIP_MACH64GT:
476                 rev &= 0x07;
477                 if(rev == 0x01) {
478                         par->pll_limits.pll_max = 170;
479                         par->pll_limits.mclk = 67;
480                         par->pll_limits.xclk = 67;
481                         par->features = ATI_CHIP_264GTB;
482                 } else if(rev == 0x02) {
483                         par->pll_limits.pll_max = 200;
484                         par->pll_limits.mclk = 67;
485                         par->pll_limits.xclk = 67;
486                         par->features = ATI_CHIP_264GTB;
487                 }
488                 break;
489 #endif
490         }
491
492         PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
493         return 0;
494 }
495
496 static char ram_dram[] __devinitdata = "DRAM";
497 static char ram_resv[] __devinitdata = "RESV";
498 #ifdef CONFIG_FB_ATY_GX
499 static char ram_vram[] __devinitdata = "VRAM";
500 #endif /* CONFIG_FB_ATY_GX */
501 #ifdef CONFIG_FB_ATY_CT
502 static char ram_edo[] __devinitdata = "EDO";
503 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
504 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
505 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
506 static char ram_off[] __devinitdata = "OFF";
507 #endif /* CONFIG_FB_ATY_CT */
508
509
510 static u32 pseudo_palette[17];
511
512 #ifdef CONFIG_FB_ATY_GX
513 static char *aty_gx_ram[8] __devinitdata = {
514         ram_dram, ram_vram, ram_vram, ram_dram,
515         ram_dram, ram_vram, ram_vram, ram_resv
516 };
517 #endif /* CONFIG_FB_ATY_GX */
518
519 #ifdef CONFIG_FB_ATY_CT
520 static char *aty_ct_ram[8] __devinitdata = {
521         ram_off, ram_dram, ram_edo, ram_edo,
522         ram_sdram, ram_sgram, ram_sdram32, ram_resv
523 };
524 #endif /* CONFIG_FB_ATY_CT */
525
526 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
527 {
528         u32 pixclock = var->pixclock;
529 #ifdef CONFIG_FB_ATY_GENERIC_LCD
530         u32 lcd_on_off;
531         par->pll.ct.xres = 0;
532         if (par->lcd_table != 0) {
533                 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
534                 if(lcd_on_off & LCD_ON) {
535                         par->pll.ct.xres = var->xres;
536                         pixclock = par->lcd_pixclock;
537                 }
538         }
539 #endif
540         return pixclock;
541 }
542
543 #if defined(CONFIG_PPC)
544
545 /*
546  *  Apple monitor sense
547  */
548
549 static int __init read_aty_sense(const struct atyfb_par *par)
550 {
551         int sense, i;
552
553         aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
554         __delay(200);
555         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
556         __delay(2000);
557         i = aty_ld_le32(GP_IO, par); /* get primary sense value */
558         sense = ((i & 0x3000) >> 3) | (i & 0x100);
559
560         /* drive each sense line low in turn and collect the other 2 */
561         aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
562         __delay(2000);
563         i = aty_ld_le32(GP_IO, par);
564         sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
565         aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
566         __delay(200);
567
568         aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
569         __delay(2000);
570         i = aty_ld_le32(GP_IO, par);
571         sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
572         aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
573         __delay(200);
574
575         aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
576         __delay(2000);
577         sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
578         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
579         return sense;
580 }
581
582 #endif /* defined(CONFIG_PPC) */
583
584 /* ------------------------------------------------------------------------- */
585
586 /*
587  *  CRTC programming
588  */
589
590 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
591 {
592 #ifdef CONFIG_FB_ATY_GENERIC_LCD
593         if (par->lcd_table != 0) {
594                 if(!M64_HAS(LT_LCD_REGS)) {
595                     crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
596                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
597                 }
598                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
599                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
600
601
602                 /* switch to non shadow registers */
603                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
604                     ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
605
606                 /* save stretching */
607                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
608                 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
609                 if (!M64_HAS(LT_LCD_REGS))
610                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
611         }
612 #endif
613         crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
614         crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
615         crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
616         crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
617         crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
618         crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
619         crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
620
621 #ifdef CONFIG_FB_ATY_GENERIC_LCD
622         if (par->lcd_table != 0) {
623                 /* switch to shadow registers */
624                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
625                         SHADOW_EN | SHADOW_RW_EN, par);
626
627                 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
628                 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
629                 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
630                 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
631
632                 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
633         }
634 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
635 }
636
637 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
638 {
639 #ifdef CONFIG_FB_ATY_GENERIC_LCD
640         if (par->lcd_table != 0) {
641                 /* stop CRTC */
642                 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
643
644                 /* update non-shadow registers first */
645                 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
646                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
647                         ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
648
649                 /* temporarily disable stretching */
650                 aty_st_lcd(HORZ_STRETCHING,
651                         crtc->horz_stretching &
652                         ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
653                 aty_st_lcd(VERT_STRETCHING,
654                         crtc->vert_stretching &
655                         ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
656                         VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
657         }
658 #endif
659         /* turn off CRT */
660         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
661
662         DPRINTK("setting up CRTC\n");
663         DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
664             ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
665             (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
666             (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
667
668         DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
669         DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
670         DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
671         DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
672         DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
673         DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
674         DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
675
676         aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
677         aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
678         aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
679         aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
680         aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
681         aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
682
683         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
684 #if 0
685         FIXME
686         if (par->accel_flags & FB_ACCELF_TEXT)
687                 aty_init_engine(par, info);
688 #endif
689 #ifdef CONFIG_FB_ATY_GENERIC_LCD
690         /* after setting the CRTC registers we should set the LCD registers. */
691         if (par->lcd_table != 0) {
692                 /* switch to shadow registers */
693                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
694                         (SHADOW_EN | SHADOW_RW_EN), par);
695
696                 DPRINTK("set secondary CRT to %ix%i %c%c\n",
697                     ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
698                     (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
699
700                 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
701                 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
702                 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
703                 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
704
705                 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
706                 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
707                 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
708                 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
709
710                 /* restore CRTC selection & shadow state and enable stretching */
711                 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
712                 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
713                 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
714                 if(!M64_HAS(LT_LCD_REGS))
715                     DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
716
717                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
718                 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
719                 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
720                 if(!M64_HAS(LT_LCD_REGS)) {
721                     aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
722                     aty_ld_le32(LCD_INDEX, par);
723                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
724                 }
725         }
726 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
727 }
728
729 static int aty_var_to_crtc(const struct fb_info *info,
730         const struct fb_var_screeninfo *var, struct crtc *crtc)
731 {
732         struct atyfb_par *par = (struct atyfb_par *) info->par;
733         u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
734         u32 sync, vmode, vdisplay;
735         u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
736         u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
737         u32 pix_width, dp_pix_width, dp_chain_mask;
738
739         /* input */
740         xres = var->xres;
741         yres = var->yres;
742         vxres = var->xres_virtual;
743         vyres = var->yres_virtual;
744         xoffset = var->xoffset;
745         yoffset = var->yoffset;
746         bpp = var->bits_per_pixel;
747         if (bpp == 16)
748                 bpp = (var->green.length == 5) ? 15 : 16;
749         sync = var->sync;
750         vmode = var->vmode;
751
752         /* convert (and round up) and validate */
753         if (vxres < xres + xoffset)
754                 vxres = xres + xoffset;
755         h_disp = xres;
756
757         if (vyres < yres + yoffset)
758                 vyres = yres + yoffset;
759         v_disp = yres;
760
761         if (bpp <= 8) {
762                 bpp = 8;
763                 pix_width = CRTC_PIX_WIDTH_8BPP;
764                 dp_pix_width =
765                     HOST_8BPP | SRC_8BPP | DST_8BPP |
766                     BYTE_ORDER_LSB_TO_MSB;
767                 dp_chain_mask = DP_CHAIN_8BPP;
768         } else if (bpp <= 15) {
769                 bpp = 16;
770                 pix_width = CRTC_PIX_WIDTH_15BPP;
771                 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
772                     BYTE_ORDER_LSB_TO_MSB;
773                 dp_chain_mask = DP_CHAIN_15BPP;
774         } else if (bpp <= 16) {
775                 bpp = 16;
776                 pix_width = CRTC_PIX_WIDTH_16BPP;
777                 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
778                     BYTE_ORDER_LSB_TO_MSB;
779                 dp_chain_mask = DP_CHAIN_16BPP;
780         } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
781                 bpp = 24;
782                 pix_width = CRTC_PIX_WIDTH_24BPP;
783                 dp_pix_width =
784                     HOST_8BPP | SRC_8BPP | DST_8BPP |
785                     BYTE_ORDER_LSB_TO_MSB;
786                 dp_chain_mask = DP_CHAIN_24BPP;
787         } else if (bpp <= 32) {
788                 bpp = 32;
789                 pix_width = CRTC_PIX_WIDTH_32BPP;
790                 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
791                     BYTE_ORDER_LSB_TO_MSB;
792                 dp_chain_mask = DP_CHAIN_32BPP;
793         } else
794                 FAIL("invalid bpp");
795
796         if (vxres * vyres * bpp / 8 > info->fix.smem_len)
797                 FAIL("not enough video RAM");
798
799         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
800         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
801
802         if((xres > 1600) || (yres > 1200)) {
803                 FAIL("MACH64 chips are designed for max 1600x1200\n"
804                 "select anoter resolution.");
805         }
806         h_sync_strt = h_disp + var->right_margin;
807         h_sync_end = h_sync_strt + var->hsync_len;
808         h_sync_dly  = var->right_margin & 7;
809         h_total = h_sync_end + h_sync_dly + var->left_margin;
810
811         v_sync_strt = v_disp + var->lower_margin;
812         v_sync_end = v_sync_strt + var->vsync_len;
813         v_total = v_sync_end + var->upper_margin;
814
815 #ifdef CONFIG_FB_ATY_GENERIC_LCD
816         if (par->lcd_table != 0) {
817                 if(!M64_HAS(LT_LCD_REGS)) {
818                     u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
819                     crtc->lcd_index = lcd_index &
820                         ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
821                     aty_st_le32(LCD_INDEX, lcd_index, par);
822                 }
823
824                 if (!M64_HAS(MOBIL_BUS))
825                         crtc->lcd_index |= CRTC2_DISPLAY_DIS;
826
827                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
828                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
829
830                 crtc->lcd_gen_cntl &=
831                         ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
832                         /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
833                         USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
834                 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
835
836                 if((crtc->lcd_gen_cntl & LCD_ON) &&
837                         ((xres > par->lcd_width) || (yres > par->lcd_height))) {
838                         /* We cannot display the mode on the LCD. If the CRT is enabled
839                            we can turn off the LCD.
840                            If the CRT is off, it isn't a good idea to switch it on; we don't
841                            know if one is connected. So it's better to fail then.
842                          */
843                         if (crtc->lcd_gen_cntl & CRT_ON) {
844                                 PRINTKI("Disable lcd panel, because video mode does not fit.\n");
845                                 crtc->lcd_gen_cntl &= ~LCD_ON;
846                                 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
847                         } else {
848                                 FAIL("Video mode exceeds size of lcd panel.\nConnect this computer to a conventional monitor if you really need this mode.");
849                         }
850                 }
851         }
852
853         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
854                 int VScan = 1;
855                 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
856                 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
857                 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
858
859                 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
860
861                 /* This is horror! When we simulate, say 640x480 on an 800x600
862                    lcd monitor, the CRTC should be programmed 800x600 values for
863                    the non visible part, but 640x480 for the visible part.
864                    This code has been tested on a laptop with it's 1400x1050 lcd
865                    monitor and a conventional monitor both switched on.
866                    Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
867                     works with little glitches also with DOUBLESCAN modes
868                  */
869                 if (yres < par->lcd_height) {
870                         VScan = par->lcd_height / yres;
871                         if(VScan > 1) {
872                                 VScan = 2;
873                                 vmode |= FB_VMODE_DOUBLE;
874                         }
875                 }
876
877                 h_sync_strt = h_disp + par->lcd_right_margin;
878                 h_sync_end = h_sync_strt + par->lcd_hsync_len;
879                 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
880                 h_total = h_disp + par->lcd_hblank_len;
881
882                 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
883                 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
884                 v_total = v_disp + par->lcd_vblank_len / VScan;
885         }
886 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
887
888         h_disp = (h_disp >> 3) - 1;
889         h_sync_strt = (h_sync_strt >> 3) - 1;
890         h_sync_end = (h_sync_end >> 3) - 1;
891         h_total = (h_total >> 3) - 1;
892         h_sync_wid = h_sync_end - h_sync_strt;
893
894         FAIL_MAX("h_disp too large", h_disp, 0xff);
895         FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
896         /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
897         if(h_sync_wid > 0x1f)
898                 h_sync_wid = 0x1f;
899         FAIL_MAX("h_total too large", h_total, 0x1ff);
900
901         if (vmode & FB_VMODE_DOUBLE) {
902                 v_disp <<= 1;
903                 v_sync_strt <<= 1;
904                 v_sync_end <<= 1;
905                 v_total <<= 1;
906         }
907
908         vdisplay = yres;
909 #ifdef CONFIG_FB_ATY_GENERIC_LCD
910         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
911                 vdisplay  = par->lcd_height;
912 #endif
913
914         if(vdisplay < 400) {
915                 h_sync_pol = 1;
916                 v_sync_pol = 0;
917         } else if(vdisplay < 480) {
918                 h_sync_pol = 0;
919                 v_sync_pol = 1;
920         } else if(vdisplay < 768) {
921                 h_sync_pol = 0;
922                 v_sync_pol = 0;
923         } else {
924                 h_sync_pol = 1;
925                 v_sync_pol = 1;
926         }
927
928         v_disp--;
929         v_sync_strt--;
930         v_sync_end--;
931         v_total--;
932         v_sync_wid = v_sync_end - v_sync_strt;
933
934         FAIL_MAX("v_disp too large", v_disp, 0x7ff);
935         FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
936         /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
937         if(v_sync_wid > 0x1f)
938                 v_sync_wid = 0x1f;
939         FAIL_MAX("v_total too large", v_total, 0x7ff);
940
941         c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
942
943         /* output */
944         crtc->vxres = vxres;
945         crtc->vyres = vyres;
946         crtc->xoffset = xoffset;
947         crtc->yoffset = yoffset;
948         crtc->bpp = bpp;
949         crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
950         crtc->vline_crnt_vline = 0;
951
952         crtc->h_tot_disp = h_total | (h_disp<<16);
953         crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
954                 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
955         crtc->v_tot_disp = v_total | (v_disp<<16);
956         crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
957
958         /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
959         crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
960         crtc->gen_cntl |= CRTC_VGA_LINEAR;
961
962         /* Enable doublescan mode if requested */
963         if (vmode & FB_VMODE_DOUBLE)
964                 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
965         /* Enable interlaced mode if requested */
966         if (vmode & FB_VMODE_INTERLACED)
967                 crtc->gen_cntl |= CRTC_INTERLACE_EN;
968 #ifdef CONFIG_FB_ATY_GENERIC_LCD
969         if (par->lcd_table != 0) {
970                 vdisplay = yres;
971                 if(vmode & FB_VMODE_DOUBLE)
972                         vdisplay <<= 1;
973                 if(vmode & FB_VMODE_INTERLACED) {
974                         vdisplay >>= 1;
975
976                         /* The prefered mode for the lcd is not interlaced, so disable it if
977                            it was enabled. For doublescan there is no problem, because we can
978                            compensate for it in the hardware stretching (we stretch half as much)
979                          */
980                         vmode &= ~FB_VMODE_INTERLACED;
981                         /*crtc->gen_cntl &= ~CRTC_INTERLACE_EN;*/
982                 }
983                 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
984                 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
985                         /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
986                         USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
987                 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
988
989                 /* MOBILITY M1 tested, FIXME: LT */
990                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
991                 if (!M64_HAS(LT_LCD_REGS))
992                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
993                                 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
994
995                 crtc->horz_stretching &=
996                         ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
997                         HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
998                 if (xres < par->lcd_width) {
999                         do {
1000                                 /*
1001                                 * The horizontal blender misbehaves when HDisplay is less than a
1002                                 * a certain threshold (440 for a 1024-wide panel).  It doesn't
1003                                 * stretch such modes enough.  Use pixel replication instead of
1004                                 * blending to stretch modes that can be made to exactly fit the
1005                                 * panel width.  The undocumented "NoLCDBlend" option allows the
1006                                 * pixel-replicated mode to be slightly wider or narrower than the
1007                                 * panel width.  It also causes a mode that is exactly half as wide
1008                                 * as the panel to be pixel-replicated, rather than blended.
1009                                 */
1010                                 int HDisplay  = xres & ~7;
1011                                 int nStretch  = par->lcd_width / HDisplay;
1012                                 int Remainder = par->lcd_width % HDisplay;
1013
1014                                 if ((!Remainder && ((nStretch > 2))) ||
1015                                         (((HDisplay * 16) / par->lcd_width) < 7)) {
1016                                         static const char StretchLoops[] = {10, 12, 13, 15, 16};
1017                                         int horz_stretch_loop = -1, BestRemainder;
1018                                         int Numerator = HDisplay, Denominator = par->lcd_width;
1019                                         int Index = 5;
1020                                         ATIReduceRatio(&Numerator, &Denominator);
1021
1022                                         BestRemainder = (Numerator * 16) / Denominator;
1023                                         while (--Index >= 0) {
1024                                                 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1025                                                         Denominator;
1026                                                 if (Remainder < BestRemainder) {
1027                                                         horz_stretch_loop = Index;
1028                                                         if (!(BestRemainder = Remainder))
1029                                                                 break;
1030                                                 }
1031                                         }
1032
1033                                         if ((horz_stretch_loop >= 0) && !BestRemainder) {
1034                                                 int horz_stretch_ratio = 0, Accumulator = 0;
1035                                                 int reuse_previous = 1;
1036
1037                                                 Index = StretchLoops[horz_stretch_loop];
1038
1039                                                 while (--Index >= 0) {
1040                                                         if (Accumulator > 0)
1041                                                                 horz_stretch_ratio |= reuse_previous;
1042                                                         else
1043                                                                 Accumulator += Denominator;
1044                                                         Accumulator -= Numerator;
1045                                                         reuse_previous <<= 1;
1046                                                 }
1047
1048                                                 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1049                                                         ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1050                                                         (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1051                                                 break;      /* Out of the do { ... } while (0) */
1052                                         }
1053                                 }
1054
1055                                 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1056                                         (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1057                         } while (0);
1058                 }
1059
1060                 if (vdisplay < par->lcd_height) {
1061                         crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1062                                 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1063
1064                         if (!M64_HAS(LT_LCD_REGS) &&
1065                             xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1066                                 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1067                 } else {
1068                         /*
1069                          * Don't use vertical blending if the mode is too wide or not
1070                          * vertically stretched.
1071                          */
1072                         crtc->vert_stretching = 0;
1073                 }
1074                 /* copy to shadow crtc */
1075                 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1076                 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1077                 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1078                 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1079         }
1080 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1081
1082         if (M64_HAS(MAGIC_FIFO)) {
1083                 /* Not VTB/GTB */
1084                 /* FIXME: magic FIFO values */
1085                 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC2_PIX_WIDTH);
1086         }
1087         crtc->dp_pix_width = dp_pix_width;
1088         crtc->dp_chain_mask = dp_chain_mask;
1089
1090         return 0;
1091 }
1092
1093 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1094 {
1095         u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1096         u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1097             h_sync_pol;
1098         u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1099         u32 pix_width;
1100         u32 double_scan, interlace;
1101
1102         /* input */
1103         h_total = crtc->h_tot_disp & 0x1ff;
1104         h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1105         h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1106         h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1107         h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1108         h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1109         v_total = crtc->v_tot_disp & 0x7ff;
1110         v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1111         v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1112         v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1113         v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1114         c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1115         pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1116         double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1117         interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1118
1119         /* convert */
1120         xres = (h_disp + 1) * 8;
1121         yres = v_disp + 1;
1122         left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1123         right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1124         hslen = h_sync_wid * 8;
1125         upper = v_total - v_sync_strt - v_sync_wid;
1126         lower = v_sync_strt - v_disp;
1127         vslen = v_sync_wid;
1128         sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1129             (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1130             (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1131
1132         switch (pix_width) {
1133 #if 0
1134         case CRTC_PIX_WIDTH_4BPP:
1135                 bpp = 4;
1136                 var->red.offset = 0;
1137                 var->red.length = 8;
1138                 var->green.offset = 0;
1139                 var->green.length = 8;
1140                 var->blue.offset = 0;
1141                 var->blue.length = 8;
1142                 var->transp.offset = 0;
1143                 var->transp.length = 0;
1144                 break;
1145 #endif
1146         case CRTC_PIX_WIDTH_8BPP:
1147                 bpp = 8;
1148                 var->red.offset = 0;
1149                 var->red.length = 8;
1150                 var->green.offset = 0;
1151                 var->green.length = 8;
1152                 var->blue.offset = 0;
1153                 var->blue.length = 8;
1154                 var->transp.offset = 0;
1155                 var->transp.length = 0;
1156                 break;
1157         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1158                 bpp = 16;
1159                 var->red.offset = 10;
1160                 var->red.length = 5;
1161                 var->green.offset = 5;
1162                 var->green.length = 5;
1163                 var->blue.offset = 0;
1164                 var->blue.length = 5;
1165                 var->transp.offset = 0;
1166                 var->transp.length = 0;
1167                 break;
1168         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1169                 bpp = 16;
1170                 var->red.offset = 11;
1171                 var->red.length = 5;
1172                 var->green.offset = 5;
1173                 var->green.length = 6;
1174                 var->blue.offset = 0;
1175                 var->blue.length = 5;
1176                 var->transp.offset = 0;
1177                 var->transp.length = 0;
1178                 break;
1179         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1180                 bpp = 24;
1181                 var->red.offset = 16;
1182                 var->red.length = 8;
1183                 var->green.offset = 8;
1184                 var->green.length = 8;
1185                 var->blue.offset = 0;
1186                 var->blue.length = 8;
1187                 var->transp.offset = 0;
1188                 var->transp.length = 0;
1189                 break;
1190         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1191                 bpp = 32;
1192                 var->red.offset = 16;
1193                 var->red.length = 8;
1194                 var->green.offset = 8;
1195                 var->green.length = 8;
1196                 var->blue.offset = 0;
1197                 var->blue.length = 8;
1198                 var->transp.offset = 24;
1199                 var->transp.length = 8;
1200                 break;
1201         default:
1202                 FAIL("Invalid pixel width");
1203         }
1204
1205         /* output */
1206         var->xres = xres;
1207         var->yres = yres;
1208         var->xres_virtual = crtc->vxres;
1209         var->yres_virtual = crtc->vyres;
1210         var->bits_per_pixel = bpp;
1211         var->left_margin = left;
1212         var->right_margin = right;
1213         var->upper_margin = upper;
1214         var->lower_margin = lower;
1215         var->hsync_len = hslen;
1216         var->vsync_len = vslen;
1217         var->sync = sync;
1218         var->vmode = FB_VMODE_NONINTERLACED;
1219         /* In double scan mode, the vertical parameters are doubled, so we need to
1220            half them to get the right values.
1221            In interlaced mode the values are already correct, so no correction is
1222            necessary.
1223          */
1224         if (interlace)
1225                 var->vmode = FB_VMODE_INTERLACED;
1226
1227         if (double_scan) {
1228                 var->vmode = FB_VMODE_DOUBLE;
1229                 var->yres>>=1;
1230                 var->upper_margin>>=1;
1231                 var->lower_margin>>=1;
1232                 var->vsync_len>>=1;
1233         }
1234
1235         return 0;
1236 }
1237
1238 /* ------------------------------------------------------------------------- */
1239
1240 static int atyfb_set_par(struct fb_info *info)
1241 {
1242         struct atyfb_par *par = (struct atyfb_par *) info->par;
1243         struct fb_var_screeninfo *var = &info->var;
1244         u32 tmp, pixclock;
1245         int err;
1246 #ifdef DEBUG
1247         struct fb_var_screeninfo debug;
1248         u32 pixclock_in_ps;
1249 #endif
1250         if (par->asleep)
1251                 return 0;
1252
1253         if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1254                 return err;
1255
1256         pixclock = atyfb_get_pixclock(var, par);
1257
1258         if (pixclock == 0) {
1259                 FAIL("Invalid pixclock");
1260         } else {
1261                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1262                         return err;
1263         }
1264
1265         par->accel_flags = var->accel_flags; /* hack */
1266
1267         if (par->blitter_may_be_busy)
1268                 wait_for_idle(par);
1269
1270         aty_set_crtc(par, &par->crtc);
1271         par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1272         par->pll_ops->set_pll(info, &par->pll);
1273
1274 #ifdef DEBUG
1275         if(par->pll_ops && par->pll_ops->pll_to_var)
1276                 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1277         else
1278                 pixclock_in_ps = 0;
1279
1280         if(0 == pixclock_in_ps) {
1281                 PRINTKE("ALERT ops->pll_to_var get 0\n");
1282                 pixclock_in_ps = pixclock;
1283         }
1284
1285         memset(&debug, 0, sizeof(debug));
1286         if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1287                 u32 hSync, vRefresh;
1288                 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1289                 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1290
1291                 h_disp = debug.xres;
1292                 h_sync_strt = h_disp + debug.right_margin;
1293                 h_sync_end = h_sync_strt + debug.hsync_len;
1294                 h_total = h_sync_end + debug.left_margin;
1295                 v_disp = debug.yres;
1296                 v_sync_strt = v_disp + debug.lower_margin;
1297                 v_sync_end = v_sync_strt + debug.vsync_len;
1298                 v_total = v_sync_end + debug.upper_margin;
1299
1300                 hSync = 1000000000 / (pixclock_in_ps * h_total);
1301                 vRefresh = (hSync * 1000) / v_total;
1302                 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1303                 vRefresh *= 2;
1304                 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1305                 vRefresh /= 2;
1306
1307                 DPRINTK("atyfb_set_par\n");
1308                 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1309                 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1310                         var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1311                 DPRINTK(" Dot clock:           %i MHz\n", 1000000 / pixclock_in_ps);
1312                 DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
1313                 DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
1314                 DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
1315                         1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1316                         h_disp, h_sync_strt, h_sync_end, h_total,
1317                         v_disp, v_sync_strt, v_sync_end, v_total);
1318                 DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
1319                         pixclock_in_ps,
1320                         debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1321                         debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1322         }
1323 #endif /* DEBUG */
1324
1325         if (!M64_HAS(INTEGRATED)) {
1326                 /* Don't forget MEM_CNTL */
1327                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1328                 switch (var->bits_per_pixel) {
1329                 case 8:
1330                         tmp |= 0x02000000;
1331                         break;
1332                 case 16:
1333                         tmp |= 0x03000000;
1334                         break;
1335                 case 32:
1336                         tmp |= 0x06000000;
1337                         break;
1338                 }
1339                 aty_st_le32(MEM_CNTL, tmp, par);
1340         } else {
1341                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1342                 if (!M64_HAS(MAGIC_POSTDIV))
1343                         tmp |= par->mem_refresh_rate << 20;
1344                 switch (var->bits_per_pixel) {
1345                 case 8:
1346                 case 24:
1347                         tmp |= 0x00000000;
1348                         break;
1349                 case 16:
1350                         tmp |= 0x04000000;
1351                         break;
1352                 case 32:
1353                         tmp |= 0x08000000;
1354                         break;
1355                 }
1356                 if (M64_HAS(CT_BUS)) {
1357                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1358                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1359                 } else if (M64_HAS(VT_BUS)) {
1360                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1361                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1362                 } else if (M64_HAS(MOBIL_BUS)) {
1363                         aty_st_le32(DAC_CNTL, 0x80010102, par);
1364                         aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1365                 } else {
1366                         /* GT */
1367                         aty_st_le32(DAC_CNTL, 0x86010102, par);
1368                         aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1369                         aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1370                 }
1371                 aty_st_le32(MEM_CNTL, tmp, par);
1372         }
1373         aty_st_8(DAC_MASK, 0xff, par);
1374
1375         info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1376         info->fix.visual = var->bits_per_pixel <= 8 ?
1377                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1378
1379         /* Initialize the graphics engine */
1380         if (par->accel_flags & FB_ACCELF_TEXT)
1381                 aty_init_engine(par, info);
1382
1383 #ifdef CONFIG_BOOTX_TEXT
1384         btext_update_display(info->fix.smem_start,
1385                 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1386                 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1387                 var->bits_per_pixel,
1388                 par->crtc.vxres * var->bits_per_pixel / 8);
1389 #endif /* CONFIG_BOOTX_TEXT */
1390 #if 0
1391         /* switch to accelerator mode */
1392         if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1393                 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1394 #endif
1395 #ifdef DEBUG
1396 {
1397         /* dump non shadow CRTC, pll, LCD registers */
1398         int i; u32 base;
1399
1400         /* CRTC registers */
1401         base = 0x2000;
1402         printk("debug atyfb: Mach64 non-shadow register values:");
1403         for (i = 0; i < 256; i = i+4) {
1404                 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1405                 printk(" %08X", aty_ld_le32(i, par));
1406         }
1407         printk("\n\n");
1408
1409 #ifdef CONFIG_FB_ATY_CT
1410         /* PLL registers */
1411         base = 0x00;
1412         printk("debug atyfb: Mach64 PLL register values:");
1413         for (i = 0; i < 64; i++) {
1414                 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1415                 if(i%4 == 0)  printk(" ");
1416                 printk("%02X", aty_ld_pll_ct(i, par));
1417         }
1418         printk("\n\n");
1419 #endif  /* CONFIG_FB_ATY_CT */
1420
1421 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1422         if (par->lcd_table != 0) {
1423                 /* LCD registers */
1424                 base = 0x00;
1425                 printk("debug atyfb: LCD register values:");
1426                 if(M64_HAS(LT_LCD_REGS)) {
1427                     for(i = 0; i <= POWER_MANAGEMENT; i++) {
1428                         if(i == EXT_VERT_STRETCH)
1429                             continue;
1430                         printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1431                         printk(" %08X", aty_ld_lcd(i, par));
1432                     }
1433
1434                 } else {
1435                     for (i = 0; i < 64; i++) {
1436                         if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1437                         printk(" %08X", aty_ld_lcd(i, par));
1438                     }
1439                 }
1440                 printk("\n\n");
1441         }
1442 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1443 }
1444 #endif /* DEBUG */
1445         return 0;
1446 }
1447
1448 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1449 {
1450         struct atyfb_par *par = (struct atyfb_par *) info->par;
1451         int err;
1452         struct crtc crtc;
1453         union aty_pll pll;
1454         u32 pixclock;
1455
1456         memcpy(&pll, &(par->pll), sizeof(pll));
1457
1458         if((err = aty_var_to_crtc(info, var, &crtc)))
1459                 return err;
1460
1461         pixclock = atyfb_get_pixclock(var, par);
1462
1463         if (pixclock == 0) {
1464                 FAIL("Invalid pixclock");
1465         } else {
1466                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1467                         return err;
1468         }
1469
1470         if (var->accel_flags & FB_ACCELF_TEXT)
1471                 info->var.accel_flags = FB_ACCELF_TEXT;
1472         else
1473                 info->var.accel_flags = 0;
1474
1475 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1476         if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1477                 return -EINVAL;
1478 #endif
1479         aty_crtc_to_var(&crtc, var);
1480         var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1481         return 0;
1482 }
1483
1484 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1485 {
1486         u32 xoffset = info->var.xoffset;
1487         u32 yoffset = info->var.yoffset;
1488         u32 vxres = par->crtc.vxres;
1489         u32 bpp = info->var.bits_per_pixel;
1490
1491         par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1492 }
1493
1494
1495     /*
1496      *  Open/Release the frame buffer device
1497      */
1498
1499 static int atyfb_open(struct fb_info *info, int user)
1500 {
1501         struct atyfb_par *par = (struct atyfb_par *) info->par;
1502
1503         if (user) {
1504                 par->open++;
1505 #ifdef __sparc__
1506                 par->mmaped = 0;
1507 #endif
1508         }
1509         return (0);
1510 }
1511
1512 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1513 {
1514         struct atyfb_par *par = dev_id;
1515         int handled = 0;
1516         u32 int_cntl;
1517
1518         spin_lock(&par->int_lock);
1519
1520         int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1521
1522         if (int_cntl & CRTC_VBLANK_INT) {
1523                 /* clear interrupt */
1524                 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1525                 par->vblank.count++;
1526                 if (par->vblank.pan_display) {
1527                         par->vblank.pan_display = 0;
1528                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1529                 }
1530                 wake_up_interruptible(&par->vblank.wait);
1531                 handled = 1;
1532         }
1533
1534         spin_unlock(&par->int_lock);
1535
1536         return IRQ_RETVAL(handled);
1537 }
1538
1539 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1540 {
1541         u32 int_cntl;
1542
1543         if (!test_and_set_bit(0, &par->irq_flags)) {
1544                 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1545                         clear_bit(0, &par->irq_flags);
1546                         return -EINVAL;
1547                 }
1548                 spin_lock_irq(&par->int_lock);
1549                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1550                 /* clear interrupt */
1551                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1552                 /* enable interrupt */
1553                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1554                 spin_unlock_irq(&par->int_lock);
1555         } else if (reenable) {
1556                 spin_lock_irq(&par->int_lock);
1557                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1558                 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1559                         printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1560                         /* re-enable interrupt */
1561                         aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1562                 }
1563                 spin_unlock_irq(&par->int_lock);
1564         }
1565
1566         return 0;
1567 }
1568
1569 static int aty_disable_irq(struct atyfb_par *par)
1570 {
1571         u32 int_cntl;
1572
1573         if (test_and_clear_bit(0, &par->irq_flags)) {
1574                 if (par->vblank.pan_display) {
1575                         par->vblank.pan_display = 0;
1576                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1577                 }
1578                 spin_lock_irq(&par->int_lock);
1579                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1580                 /* disable interrupt */
1581                 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1582                 spin_unlock_irq(&par->int_lock);
1583                 free_irq(par->irq, par);
1584         }
1585
1586         return 0;
1587 }
1588
1589 static int atyfb_release(struct fb_info *info, int user)
1590 {
1591         struct atyfb_par *par = (struct atyfb_par *) info->par;
1592         if (user) {
1593                 par->open--;
1594                 mdelay(1);
1595                 wait_for_idle(par);
1596                 if (!par->open) {
1597 #ifdef __sparc__
1598                         int was_mmaped = par->mmaped;
1599
1600                         par->mmaped = 0;
1601
1602                         if (was_mmaped) {
1603                                 struct fb_var_screeninfo var;
1604
1605                                 /* Now reset the default display config, we have no
1606                                  * idea what the program(s) which mmap'd the chip did
1607                                  * to the configuration, nor whether it restored it
1608                                  * correctly.
1609                                  */
1610                                 var = default_var;
1611                                 if (noaccel)
1612                                         var.accel_flags &= ~FB_ACCELF_TEXT;
1613                                 else
1614                                         var.accel_flags |= FB_ACCELF_TEXT;
1615                                 if (var.yres == var.yres_virtual) {
1616                                         u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1617                                         var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1618                                         if (var.yres_virtual < var.yres)
1619                                                 var.yres_virtual = var.yres;
1620                                 }
1621                         }
1622 #endif
1623                         aty_disable_irq(par);
1624                 }
1625         }
1626         return (0);
1627 }
1628
1629     /*
1630      *  Pan or Wrap the Display
1631      *
1632      *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1633      */
1634
1635 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1636 {
1637         struct atyfb_par *par = (struct atyfb_par *) info->par;
1638         u32 xres, yres, xoffset, yoffset;
1639
1640         xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1641         yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1642         if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1643                 yres >>= 1;
1644         xoffset = (var->xoffset + 7) & ~7;
1645         yoffset = var->yoffset;
1646         if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1647                 return -EINVAL;
1648         info->var.xoffset = xoffset;
1649         info->var.yoffset = yoffset;
1650         if (par->asleep)
1651                 return 0;
1652
1653         set_off_pitch(par, info);
1654         if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1655                 par->vblank.pan_display = 1;
1656         } else {
1657                 par->vblank.pan_display = 0;
1658                 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1659         }
1660
1661         return 0;
1662 }
1663
1664 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1665 {
1666         struct aty_interrupt *vbl;
1667         unsigned int count;
1668         int ret;
1669
1670         switch (crtc) {
1671         case 0:
1672                 vbl = &par->vblank;
1673                 break;
1674         default:
1675                 return -ENODEV;
1676         }
1677
1678         ret = aty_enable_irq(par, 0);
1679         if (ret)
1680                 return ret;
1681
1682         count = vbl->count;
1683         ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1684         if (ret < 0) {
1685                 return ret;
1686         }
1687         if (ret == 0) {
1688                 aty_enable_irq(par, 1);
1689                 return -ETIMEDOUT;
1690         }
1691
1692         return 0;
1693 }
1694
1695
1696 #ifdef DEBUG
1697 #define ATYIO_CLKR              0x41545900      /* ATY\00 */
1698 #define ATYIO_CLKW              0x41545901      /* ATY\01 */
1699
1700 struct atyclk {
1701         u32 ref_clk_per;
1702         u8 pll_ref_div;
1703         u8 mclk_fb_div;
1704         u8 mclk_post_div;       /* 1,2,3,4,8 */
1705         u8 mclk_fb_mult;        /* 2 or 4 */
1706         u8 xclk_post_div;       /* 1,2,3,4,8 */
1707         u8 vclk_fb_div;
1708         u8 vclk_post_div;       /* 1,2,3,4,6,8,12 */
1709         u32 dsp_xclks_per_row;  /* 0-16383 */
1710         u32 dsp_loop_latency;   /* 0-15 */
1711         u32 dsp_precision;      /* 0-7 */
1712         u32 dsp_on;             /* 0-2047 */
1713         u32 dsp_off;            /* 0-2047 */
1714 };
1715
1716 #define ATYIO_FEATR             0x41545902      /* ATY\02 */
1717 #define ATYIO_FEATW             0x41545903      /* ATY\03 */
1718 #endif
1719
1720 #ifndef FBIO_WAITFORVSYNC
1721 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1722 #endif
1723
1724 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
1725         u_long arg, struct fb_info *info)
1726 {
1727         struct atyfb_par *par = (struct atyfb_par *) info->par;
1728 #ifdef __sparc__
1729         struct fbtype fbtyp;
1730 #endif
1731
1732         switch (cmd) {
1733 #ifdef __sparc__
1734         case FBIOGTYPE:
1735                 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1736                 fbtyp.fb_width = par->crtc.vxres;
1737                 fbtyp.fb_height = par->crtc.vyres;
1738                 fbtyp.fb_depth = info->var.bits_per_pixel;
1739                 fbtyp.fb_cmsize = info->cmap.len;
1740                 fbtyp.fb_size = info->fix.smem_len;
1741                 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1742                         return -EFAULT;
1743                 break;
1744 #endif /* __sparc__ */
1745
1746         case FBIO_WAITFORVSYNC:
1747                 {
1748                         u32 crtc;
1749
1750                         if (get_user(crtc, (__u32 __user *) arg))
1751                                 return -EFAULT;
1752
1753                         return aty_waitforvblank(par, crtc);
1754                 }
1755                 break;
1756
1757 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1758         case ATYIO_CLKR:
1759                 if (M64_HAS(INTEGRATED)) {
1760                         struct atyclk clk;
1761                         union aty_pll *pll = &(par->pll);
1762                         u32 dsp_config = pll->ct.dsp_config;
1763                         u32 dsp_on_off = pll->ct.dsp_on_off;
1764                         clk.ref_clk_per = par->ref_clk_per;
1765                         clk.pll_ref_div = pll->ct.pll_ref_div;
1766                         clk.mclk_fb_div = pll->ct.mclk_fb_div;
1767                         clk.mclk_post_div = pll->ct.mclk_post_div_real;
1768                         clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1769                         clk.xclk_post_div = pll->ct.xclk_post_div_real;
1770                         clk.vclk_fb_div = pll->ct.vclk_fb_div;
1771                         clk.vclk_post_div = pll->ct.vclk_post_div_real;
1772                         clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1773                         clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1774                         clk.dsp_precision = (dsp_config >> 20) & 7;
1775                         clk.dsp_off = dsp_on_off & 0x7ff;
1776                         clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1777                         if (copy_to_user((struct atyclk __user *) arg, &clk,
1778                                          sizeof(clk)))
1779                                 return -EFAULT;
1780                 } else
1781                         return -EINVAL;
1782                 break;
1783         case ATYIO_CLKW:
1784                 if (M64_HAS(INTEGRATED)) {
1785                         struct atyclk clk;
1786                         union aty_pll *pll = &(par->pll);
1787                         if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1788                                 return -EFAULT;
1789                         par->ref_clk_per = clk.ref_clk_per;
1790                         pll->ct.pll_ref_div = clk.pll_ref_div;
1791                         pll->ct.mclk_fb_div = clk.mclk_fb_div;
1792                         pll->ct.mclk_post_div_real = clk.mclk_post_div;
1793                         pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1794                         pll->ct.xclk_post_div_real = clk.xclk_post_div;
1795                         pll->ct.vclk_fb_div = clk.vclk_fb_div;
1796                         pll->ct.vclk_post_div_real = clk.vclk_post_div;
1797                         pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1798                                 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1799                         pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1800                         /*aty_calc_pll_ct(info, &pll->ct);*/
1801                         aty_set_pll_ct(info, pll);
1802                 } else
1803                         return -EINVAL;
1804                 break;
1805         case ATYIO_FEATR:
1806                 if (get_user(par->features, (u32 __user *) arg))
1807                         return -EFAULT;
1808                 break;
1809         case ATYIO_FEATW:
1810                 if (put_user(par->features, (u32 __user *) arg))
1811                         return -EFAULT;
1812                 break;
1813 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1814         default:
1815                 return -EINVAL;
1816         }
1817         return 0;
1818 }
1819
1820 static int atyfb_sync(struct fb_info *info)
1821 {
1822         struct atyfb_par *par = (struct atyfb_par *) info->par;
1823
1824         if (par->blitter_may_be_busy)
1825                 wait_for_idle(par);
1826         return 0;
1827 }
1828
1829 #ifdef __sparc__
1830 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
1831 {
1832         struct atyfb_par *par = (struct atyfb_par *) info->par;
1833         unsigned int size, page, map_size = 0;
1834         unsigned long map_offset = 0;
1835         unsigned long off;
1836         int i;
1837
1838         if (!par->mmap_map)
1839                 return -ENXIO;
1840
1841         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1842                 return -EINVAL;
1843
1844         off = vma->vm_pgoff << PAGE_SHIFT;
1845         size = vma->vm_end - vma->vm_start;
1846
1847         /* To stop the swapper from even considering these pages. */
1848         vma->vm_flags |= (VM_IO | VM_RESERVED);
1849
1850         if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1851             ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1852                 off += 0x8000000000000000UL;
1853
1854         vma->vm_pgoff = off >> PAGE_SHIFT;      /* propagate off changes */
1855
1856         /* Each page, see which map applies */
1857         for (page = 0; page < size;) {
1858                 map_size = 0;
1859                 for (i = 0; par->mmap_map[i].size; i++) {
1860                         unsigned long start = par->mmap_map[i].voff;
1861                         unsigned long end = start + par->mmap_map[i].size;
1862                         unsigned long offset = off + page;
1863
1864                         if (start > offset)
1865                                 continue;
1866                         if (offset >= end)
1867                                 continue;
1868
1869                         map_size = par->mmap_map[i].size - (offset - start);
1870                         map_offset =
1871                             par->mmap_map[i].poff + (offset - start);
1872                         break;
1873                 }
1874                 if (!map_size) {
1875                         page += PAGE_SIZE;
1876                         continue;
1877                 }
1878                 if (page + map_size > size)
1879                         map_size = size - page;
1880
1881                 pgprot_val(vma->vm_page_prot) &=
1882                     ~(par->mmap_map[i].prot_mask);
1883                 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1884
1885                 if (remap_pfn_range(vma, vma->vm_start + page,
1886                         map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1887                         return -EAGAIN;
1888
1889                 page += map_size;
1890         }
1891
1892         if (!map_size)
1893                 return -EINVAL;
1894
1895         if (!par->mmaped)
1896                 par->mmaped = 1;
1897         return 0;
1898 }
1899
1900 static struct {
1901         u32 yoffset;
1902         u8 r[2][256];
1903         u8 g[2][256];
1904         u8 b[2][256];
1905 } atyfb_save;
1906
1907 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1908 {
1909         int i, tmp;
1910
1911         for (i = 0; i < 256; i++) {
1912                 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1913                 if (M64_HAS(EXTRA_BRIGHT))
1914                         tmp |= 0x2;
1915                 aty_st_8(DAC_CNTL, tmp, par);
1916                 aty_st_8(DAC_MASK, 0xff, par);
1917
1918                 writeb(i, &par->aty_cmap_regs->rindex);
1919                 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1920                 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1921                 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1922                 writeb(i, &par->aty_cmap_regs->windex);
1923                 writeb(atyfb_save.r[1 - enter][i],
1924                        &par->aty_cmap_regs->lut);
1925                 writeb(atyfb_save.g[1 - enter][i],
1926                        &par->aty_cmap_regs->lut);
1927                 writeb(atyfb_save.b[1 - enter][i],
1928                        &par->aty_cmap_regs->lut);
1929         }
1930 }
1931
1932 static void atyfb_palette(int enter)
1933 {
1934         struct atyfb_par *par;
1935         struct fb_info *info;
1936         int i;
1937
1938         for (i = 0; i < FB_MAX; i++) {
1939                 info = registered_fb[i];
1940                 if (info && info->fbops == &atyfb_ops) {
1941                         par = (struct atyfb_par *) info->par;
1942                         
1943                         atyfb_save_palette(par, enter);
1944                         if (enter) {
1945                                 atyfb_save.yoffset = info->var.yoffset;
1946                                 info->var.yoffset = 0;
1947                                 set_off_pitch(par, info);
1948                         } else {
1949                                 info->var.yoffset = atyfb_save.yoffset;
1950                                 set_off_pitch(par, info);
1951                         }
1952                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1953                         break;
1954                 }
1955         }
1956 }
1957 #endif /* __sparc__ */
1958
1959
1960
1961 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1962
1963 /* Power management routines. Those are used for PowerBook sleep.
1964  */
1965 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1966 {
1967         u32 pm;
1968         int timeout;
1969
1970         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1971         pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1972         aty_st_lcd(POWER_MANAGEMENT, pm, par);
1973         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1974
1975         timeout = 2000;
1976         if (sleep) {
1977                 /* Sleep */
1978                 pm &= ~PWR_MGT_ON;
1979                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1980                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1981                 udelay(10);
1982                 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1983                 pm |= SUSPEND_NOW;
1984                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1985                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1986                 udelay(10);
1987                 pm |= PWR_MGT_ON;
1988                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1989                 do {
1990                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1991                         mdelay(1);
1992                         if ((--timeout) == 0)
1993                                 break;
1994                 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
1995         } else {
1996                 /* Wakeup */
1997                 pm &= ~PWR_MGT_ON;
1998                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1999                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2000                 udelay(10);
2001                 pm &= ~SUSPEND_NOW;
2002                 pm |= (PWR_BLON | AUTO_PWR_UP);
2003                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2004                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2005                 udelay(10);
2006                 pm |= PWR_MGT_ON;
2007                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2008                 do {
2009                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2010                         mdelay(1);
2011                         if ((--timeout) == 0)
2012                                 break;
2013                 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2014         }
2015         mdelay(500);
2016
2017         return timeout ? 0 : -EIO;
2018 }
2019
2020 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2021 {
2022         struct fb_info *info = pci_get_drvdata(pdev);
2023         struct atyfb_par *par = (struct atyfb_par *) info->par;
2024
2025 #ifndef CONFIG_PPC_PMAC
2026         /* HACK ALERT ! Once I find a proper way to say to each driver
2027          * individually what will happen with it's PCI slot, I'll change
2028          * that. On laptops, the AGP slot is just unclocked, so D2 is
2029          * expected, while on desktops, the card is powered off
2030          */
2031         return 0;
2032 #endif /* CONFIG_PPC_PMAC */
2033
2034         if (state.event == pdev->dev.power.power_state.event)
2035                 return 0;
2036
2037         acquire_console_sem();
2038
2039         fb_set_suspend(info, 1);
2040
2041         /* Idle & reset engine */
2042         wait_for_idle(par);
2043         aty_reset_engine(par);
2044
2045         /* Blank display and LCD */
2046         atyfb_blank(FB_BLANK_POWERDOWN, info);
2047
2048         par->asleep = 1;
2049         par->lock_blank = 1;
2050
2051         /* Set chip to "suspend" mode */
2052         if (aty_power_mgmt(1, par)) {
2053                 par->asleep = 0;
2054                 par->lock_blank = 0;
2055                 atyfb_blank(FB_BLANK_UNBLANK, info);
2056                 fb_set_suspend(info, 0);
2057                 release_console_sem();
2058                 return -EIO;
2059         }
2060
2061         release_console_sem();
2062
2063         pdev->dev.power.power_state = state;
2064
2065         return 0;
2066 }
2067
2068 static int atyfb_pci_resume(struct pci_dev *pdev)
2069 {
2070         struct fb_info *info = pci_get_drvdata(pdev);
2071         struct atyfb_par *par = (struct atyfb_par *) info->par;
2072
2073         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2074                 return 0;
2075
2076         acquire_console_sem();
2077
2078         if (pdev->dev.power.power_state.event == 2)
2079                 aty_power_mgmt(0, par);
2080         par->asleep = 0;
2081
2082         /* Restore display */
2083         atyfb_set_par(info);
2084
2085         /* Refresh */
2086         fb_set_suspend(info, 0);
2087
2088         /* Unblank */
2089         par->lock_blank = 0;
2090         atyfb_blank(FB_BLANK_UNBLANK, info);
2091
2092         release_console_sem();
2093
2094         pdev->dev.power.power_state = PMSG_ON;
2095
2096         return 0;
2097 }
2098
2099 #endif /*  defined(CONFIG_PM) && defined(CONFIG_PCI) */
2100
2101 #ifdef CONFIG_PMAC_BACKLIGHT
2102
2103     /*
2104      *   LCD backlight control
2105      */
2106
2107 static int backlight_conv[] = {
2108         0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d,
2109         0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff
2110 };
2111
2112 static int aty_set_backlight_enable(int on, int level, void *data)
2113 {
2114         struct fb_info *info = (struct fb_info *) data;
2115         struct atyfb_par *par = (struct atyfb_par *) info->par;
2116         unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2117
2118         reg |= (BLMOD_EN | BIASMOD_EN);
2119         if (on && level > BACKLIGHT_OFF) {
2120                 reg &= ~BIAS_MOD_LEVEL_MASK;
2121                 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT);
2122         } else {
2123                 reg &= ~BIAS_MOD_LEVEL_MASK;
2124                 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT);
2125         }
2126         aty_st_lcd(LCD_MISC_CNTL, reg, par);
2127         return 0;
2128 }
2129
2130 static int aty_set_backlight_level(int level, void *data)
2131 {
2132         return aty_set_backlight_enable(1, level, data);
2133 }
2134
2135 static struct backlight_controller aty_backlight_controller = {
2136         aty_set_backlight_enable,
2137         aty_set_backlight_level
2138 };
2139 #endif /* CONFIG_PMAC_BACKLIGHT */
2140
2141 static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2142 {
2143         const int ragepro_tbl[] = {
2144                 44, 50, 55, 66, 75, 80, 100
2145         };
2146         const int ragexl_tbl[] = {
2147                 50, 66, 75, 83, 90, 95, 100, 105,
2148                 110, 115, 120, 125, 133, 143, 166
2149         };
2150         const int *refresh_tbl;
2151         int i, size;
2152
2153         if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2154                 refresh_tbl = ragexl_tbl;
2155                 size = sizeof(ragexl_tbl)/sizeof(int);
2156         } else {
2157                 refresh_tbl = ragepro_tbl;
2158                 size = sizeof(ragepro_tbl)/sizeof(int);
2159         }
2160
2161         for (i=0; i < size; i++) {
2162                 if (xclk < refresh_tbl[i])
2163                 break;
2164         }
2165         par->mem_refresh_rate = i;
2166 }
2167
2168     /*
2169      *  Initialisation
2170      */
2171
2172 static struct fb_info *fb_list = NULL;
2173
2174 static int __init aty_init(struct fb_info *info, const char *name)
2175 {
2176         struct atyfb_par *par = (struct atyfb_par *) info->par;
2177         const char *ramname = NULL, *xtal;
2178         int gtb_memsize;
2179         struct fb_var_screeninfo var;
2180         u8 pll_ref_div;
2181         u32 i;
2182 #if defined(CONFIG_PPC)
2183         int sense;
2184 #endif
2185
2186         init_waitqueue_head(&par->vblank.wait);
2187         spin_lock_init(&par->int_lock);
2188
2189         par->aty_cmap_regs =
2190             (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2191
2192 #ifdef CONFIG_PPC_PMAC
2193         /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2194          * and set the frequency manually. */
2195         if (machine_is_compatible("PowerBook2,1")) {
2196                 par->pll_limits.mclk = 70;
2197                 par->pll_limits.xclk = 53;
2198         }
2199 #endif
2200         if (pll)
2201                 par->pll_limits.pll_max = pll;
2202         if (mclk)
2203                 par->pll_limits.mclk = mclk;
2204         if (xclk)
2205                 par->pll_limits.xclk = xclk;
2206
2207         aty_calc_mem_refresh(par, par->pll_limits.xclk);
2208         par->pll_per = 1000000/par->pll_limits.pll_max;
2209         par->mclk_per = 1000000/par->pll_limits.mclk;
2210         par->xclk_per = 1000000/par->pll_limits.xclk;
2211
2212         par->ref_clk_per = 1000000000000ULL / 14318180;
2213         xtal = "14.31818";
2214
2215 #ifdef CONFIG_FB_ATY_GX
2216         if (!M64_HAS(INTEGRATED)) {
2217                 u32 stat0;
2218                 u8 dac_type, dac_subtype, clk_type;
2219                 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2220                 par->bus_type = (stat0 >> 0) & 0x07;
2221                 par->ram_type = (stat0 >> 3) & 0x07;
2222                 ramname = aty_gx_ram[par->ram_type];
2223                 /* FIXME: clockchip/RAMDAC probing? */
2224                 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2225 #ifdef CONFIG_ATARI
2226                 clk_type = CLK_ATI18818_1;
2227                 dac_type = (stat0 >> 9) & 0x07;
2228                 if (dac_type == 0x07)
2229                         dac_subtype = DAC_ATT20C408;
2230                 else
2231                         dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2232 #else
2233                 dac_type = DAC_IBMRGB514;
2234                 dac_subtype = DAC_IBMRGB514;
2235                 clk_type = CLK_IBMRGB514;
2236 #endif
2237                 switch (dac_subtype) {
2238                 case DAC_IBMRGB514:
2239                         par->dac_ops = &aty_dac_ibm514;
2240                         break;
2241                 case DAC_ATI68860_B:
2242                 case DAC_ATI68860_C:
2243                         par->dac_ops = &aty_dac_ati68860b;
2244                         break;
2245                 case DAC_ATT20C408:
2246                 case DAC_ATT21C498:
2247                         par->dac_ops = &aty_dac_att21c498;
2248                         break;
2249                 default:
2250                         PRINTKI("aty_init: DAC type not implemented yet!\n");
2251                         par->dac_ops = &aty_dac_unsupported;
2252                         break;
2253                 }
2254                 switch (clk_type) {
2255                 case CLK_ATI18818_1:
2256                         par->pll_ops = &aty_pll_ati18818_1;
2257                         break;
2258                 case CLK_STG1703:
2259                         par->pll_ops = &aty_pll_stg1703;
2260                         break;
2261                 case CLK_CH8398:
2262                         par->pll_ops = &aty_pll_ch8398;
2263                         break;
2264                 case CLK_ATT20C408:
2265                         par->pll_ops = &aty_pll_att20c408;
2266                         break;
2267                 case CLK_IBMRGB514:
2268                         par->pll_ops = &aty_pll_ibm514;
2269                         break;
2270                 default:
2271                         PRINTKI("aty_init: CLK type not implemented yet!");
2272                         par->pll_ops = &aty_pll_unsupported;
2273                         break;
2274                 }
2275         }
2276 #endif /* CONFIG_FB_ATY_GX */
2277 #ifdef CONFIG_FB_ATY_CT
2278         if (M64_HAS(INTEGRATED)) {
2279                 par->dac_ops = &aty_dac_ct;
2280                 par->pll_ops = &aty_pll_ct;
2281                 par->bus_type = PCI;
2282 #ifdef CONFIG_FB_ATY_XL_INIT
2283                 if (IS_XL(par->pci_id))
2284                         atyfb_xl_init(info);
2285 #endif
2286                 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2287                 ramname = aty_ct_ram[par->ram_type];
2288                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2289                 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2290                         par->pll_limits.mclk = 63;
2291         }
2292
2293         if (M64_HAS(GTB_DSP)
2294             && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2295                 int diff1, diff2;
2296                 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2297                 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2298                 if (diff1 < 0)
2299                         diff1 = -diff1;
2300                 if (diff2 < 0)
2301                         diff2 = -diff2;
2302                 if (diff2 < diff1) {
2303                         par->ref_clk_per = 1000000000000ULL / 29498928;
2304                         xtal = "29.498928";
2305                 }
2306         }
2307 #endif /* CONFIG_FB_ATY_CT */
2308
2309         /* save previous video mode */
2310         aty_get_crtc(par, &saved_crtc);
2311         if(par->pll_ops->get_pll)
2312                 par->pll_ops->get_pll(info, &saved_pll);
2313
2314         i = aty_ld_le32(MEM_CNTL, par);
2315         gtb_memsize = M64_HAS(GTB_DSP);
2316         if (gtb_memsize)
2317                 switch (i & 0xF) {      /* 0xF used instead of MEM_SIZE_ALIAS */
2318                 case MEM_SIZE_512K:
2319                         info->fix.smem_len = 0x80000;
2320                         break;
2321                 case MEM_SIZE_1M:
2322                         info->fix.smem_len = 0x100000;
2323                         break;
2324                 case MEM_SIZE_2M_GTB:
2325                         info->fix.smem_len = 0x200000;
2326                         break;
2327                 case MEM_SIZE_4M_GTB:
2328                         info->fix.smem_len = 0x400000;
2329                         break;
2330                 case MEM_SIZE_6M_GTB:
2331                         info->fix.smem_len = 0x600000;
2332                         break;
2333                 case MEM_SIZE_8M_GTB:
2334                         info->fix.smem_len = 0x800000;
2335                         break;
2336                 default:
2337                         info->fix.smem_len = 0x80000;
2338         } else
2339                 switch (i & MEM_SIZE_ALIAS) {
2340                 case MEM_SIZE_512K:
2341                         info->fix.smem_len = 0x80000;
2342                         break;
2343                 case MEM_SIZE_1M:
2344                         info->fix.smem_len = 0x100000;
2345                         break;
2346                 case MEM_SIZE_2M:
2347                         info->fix.smem_len = 0x200000;
2348                         break;
2349                 case MEM_SIZE_4M:
2350                         info->fix.smem_len = 0x400000;
2351                         break;
2352                 case MEM_SIZE_6M:
2353                         info->fix.smem_len = 0x600000;
2354                         break;
2355                 case MEM_SIZE_8M:
2356                         info->fix.smem_len = 0x800000;
2357                         break;
2358                 default:
2359                         info->fix.smem_len = 0x80000;
2360                 }
2361
2362         if (M64_HAS(MAGIC_VRAM_SIZE)) {
2363                 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2364                         info->fix.smem_len += 0x400000;
2365         }
2366
2367         if (vram) {
2368                 info->fix.smem_len = vram * 1024;
2369                 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2370                 if (info->fix.smem_len <= 0x80000)
2371                         i |= MEM_SIZE_512K;
2372                 else if (info->fix.smem_len <= 0x100000)
2373                         i |= MEM_SIZE_1M;
2374                 else if (info->fix.smem_len <= 0x200000)
2375                         i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2376                 else if (info->fix.smem_len <= 0x400000)
2377                         i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2378                 else if (info->fix.smem_len <= 0x600000)
2379                         i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2380                 else
2381                         i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2382                 aty_st_le32(MEM_CNTL, i, par);
2383         }
2384
2385         /*
2386          *  Reg Block 0 (CT-compatible block) is at mmio_start
2387          *  Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2388          */
2389         if (M64_HAS(GX)) {
2390                 info->fix.mmio_len = 0x400;
2391                 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2392         } else if (M64_HAS(CT)) {
2393                 info->fix.mmio_len = 0x400;
2394                 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2395         } else if (M64_HAS(VT)) {
2396                 info->fix.mmio_start -= 0x400;
2397                 info->fix.mmio_len = 0x800;
2398                 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2399         } else {/* GT */
2400                 info->fix.mmio_start -= 0x400;
2401                 info->fix.mmio_len = 0x800;
2402                 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2403         }
2404
2405         PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2406                info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2407                info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2408                par->pll_limits.mclk, par->pll_limits.xclk);
2409
2410 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2411         if (M64_HAS(INTEGRATED)) {
2412                 int i;
2413                 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2414                        "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2415                        "debug atyfb: %08x %08x %08x %08x     %08x      %08x   %08x   %08x\n"
2416                        "debug atyfb: PLL",
2417                         aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2418                         aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2419                         aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2420                         aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2421                 for (i = 0; i < 40; i++)
2422                         printk(" %02x", aty_ld_pll_ct(i, par));
2423                 printk("\n");
2424         }
2425 #endif
2426         if(par->pll_ops->init_pll)
2427                 par->pll_ops->init_pll(info, &par->pll);
2428
2429         /*
2430          *  Last page of 8 MB (4 MB on ISA) aperture is MMIO
2431          *  FIXME: we should use the auxiliary aperture instead so we can access
2432          *  the full 8 MB of video RAM on 8 MB boards
2433          */
2434
2435         if (!par->aux_start &&
2436                 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2437                 info->fix.smem_len -= GUI_RESERVE;
2438
2439         /*
2440          *  Disable register access through the linear aperture
2441          *  if the auxiliary aperture is used so we can access
2442          *  the full 8 MB of video RAM on 8 MB boards.
2443          */
2444         if (par->aux_start)
2445                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2446
2447 #ifdef CONFIG_MTRR
2448         par->mtrr_aper = -1;
2449         par->mtrr_reg = -1;
2450         if (!nomtrr) {
2451                 /* Cover the whole resource. */
2452                  par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2453                  if (par->mtrr_aper >= 0 && !par->aux_start) {
2454                         /* Make a hole for mmio. */
2455                         par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2456                                 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2457                         if (par->mtrr_reg < 0) {
2458                                 mtrr_del(par->mtrr_aper, 0, 0);
2459                                 par->mtrr_aper = -1;
2460                         }
2461                  }
2462         }
2463 #endif
2464
2465         info->fbops = &atyfb_ops;
2466         info->pseudo_palette = pseudo_palette;
2467         info->flags = FBINFO_FLAG_DEFAULT;
2468
2469 #ifdef CONFIG_PMAC_BACKLIGHT
2470         if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2471                 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2472                 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2473                            | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2474         } else if (M64_HAS(MOBIL_BUS))
2475                 register_backlight_controller(&aty_backlight_controller, info, "ati");
2476 #endif /* CONFIG_PMAC_BACKLIGHT */
2477
2478         memset(&var, 0, sizeof(var));
2479 #ifdef CONFIG_PPC
2480         if (_machine == _MACH_Pmac) {
2481                 /*
2482                  *  FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2483                  *         applies to all Mac video cards
2484                  */
2485                 if (mode) {
2486                         if (!mac_find_mode(&var, info, mode, 8))
2487                                 var = default_var;
2488                 } else {
2489                         if (default_vmode == VMODE_CHOOSE) {
2490                                 if (M64_HAS(G3_PB_1024x768))
2491                                         /* G3 PowerBook with 1024x768 LCD */
2492                                         default_vmode = VMODE_1024_768_60;
2493                                 else if (machine_is_compatible("iMac"))
2494                                         default_vmode = VMODE_1024_768_75;
2495                                 else if (machine_is_compatible
2496                                          ("PowerBook2,1"))
2497                                         /* iBook with 800x600 LCD */
2498                                         default_vmode = VMODE_800_600_60;
2499                                 else
2500                                         default_vmode = VMODE_640_480_67;
2501                                 sense = read_aty_sense(par);
2502                                 PRINTKI("monitor sense=%x, mode %d\n",
2503                                         sense,  mac_map_monitor_sense(sense));
2504                         }
2505                         if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2506                                 default_vmode = VMODE_640_480_60;
2507                         if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2508                                 default_cmode = CMODE_8;
2509                         if (mac_vmode_to_var(default_vmode, default_cmode, &var))
2510                                 var = default_var;
2511                 }
2512         } else
2513 #endif /* !CONFIG_PPC */
2514         if (
2515 #if defined(CONFIG_SPARC32) || defined(CONFIG_SPARC64)
2516            /* On Sparc, unless the user gave a specific mode
2517             * specification, use the PROM probed values in
2518             * default_var.
2519             */
2520             !mode ||
2521 #endif
2522             !fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2523                 var = default_var;
2524
2525         if (noaccel)
2526                 var.accel_flags &= ~FB_ACCELF_TEXT;
2527         else
2528                 var.accel_flags |= FB_ACCELF_TEXT;
2529
2530         if (comp_sync != -1) {
2531                 if (!comp_sync)
2532                         var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2533                 else
2534                         var.sync |= FB_SYNC_COMP_HIGH_ACT;
2535         }
2536
2537         if (var.yres == var.yres_virtual) {
2538                 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2539                 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2540                 if (var.yres_virtual < var.yres)
2541                         var.yres_virtual = var.yres;
2542         }
2543
2544         if (atyfb_check_var(&var, info)) {
2545                 PRINTKE("can't set default video mode\n");
2546                 goto aty_init_exit;
2547         }
2548
2549 #ifdef __sparc__
2550         atyfb_save_palette(par, 0);
2551 #endif
2552
2553 #ifdef CONFIG_FB_ATY_CT
2554         if (!noaccel && M64_HAS(INTEGRATED))
2555                 aty_init_cursor(info);
2556 #endif /* CONFIG_FB_ATY_CT */
2557         info->var = var;
2558
2559         fb_alloc_cmap(&info->cmap, 256, 0);
2560
2561         if (register_framebuffer(info) < 0)
2562                 goto aty_init_exit;
2563
2564         fb_list = info;
2565
2566         PRINTKI("fb%d: %s frame buffer device on %s\n",
2567                info->node, info->fix.id, name);
2568         return 0;
2569
2570 aty_init_exit:
2571         /* restore video mode */
2572         aty_set_crtc(par, &saved_crtc);
2573         par->pll_ops->set_pll(info, &saved_pll);
2574
2575 #ifdef CONFIG_MTRR
2576         if (par->mtrr_reg >= 0) {
2577             mtrr_del(par->mtrr_reg, 0, 0);
2578             par->mtrr_reg = -1;
2579         }
2580         if (par->mtrr_aper >= 0) {
2581             mtrr_del(par->mtrr_aper, 0, 0);
2582             par->mtrr_aper = -1;
2583         }
2584 #endif
2585         return -1;
2586 }
2587
2588 #ifdef CONFIG_ATARI
2589 static int __init store_video_par(char *video_str, unsigned char m64_num)
2590 {
2591         char *p;
2592         unsigned long vmembase, size, guiregbase;
2593
2594         PRINTKI("store_video_par() '%s' \n", video_str);
2595
2596         if (!(p = strsep(&video_str, ";")) || !*p)
2597                 goto mach64_invalid;
2598         vmembase = simple_strtoul(p, NULL, 0);
2599         if (!(p = strsep(&video_str, ";")) || !*p)
2600                 goto mach64_invalid;
2601         size = simple_strtoul(p, NULL, 0);
2602         if (!(p = strsep(&video_str, ";")) || !*p)
2603                 goto mach64_invalid;
2604         guiregbase = simple_strtoul(p, NULL, 0);
2605
2606         phys_vmembase[m64_num] = vmembase;
2607         phys_size[m64_num] = size;
2608         phys_guiregbase[m64_num] = guiregbase;
2609         PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2610                guiregbase);
2611         return 0;
2612
2613       mach64_invalid:
2614         phys_vmembase[m64_num] = 0;
2615         return -1;
2616 }
2617 #endif /* CONFIG_ATARI */
2618
2619     /*
2620      *  Blank the display.
2621      */
2622
2623 static int atyfb_blank(int blank, struct fb_info *info)
2624 {
2625         struct atyfb_par *par = (struct atyfb_par *) info->par;
2626         u8 gen_cntl;
2627
2628         if (par->lock_blank || par->asleep)
2629                 return 0;
2630
2631 #ifdef CONFIG_PMAC_BACKLIGHT
2632         if ((_machine == _MACH_Pmac) && blank)
2633                 set_backlight_enable(0);
2634 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2635         if (par->lcd_table && blank &&
2636             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2637                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2638                 pm &= ~PWR_BLON;
2639                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2640         }
2641 #endif
2642
2643         gen_cntl = aty_ld_8(CRTC_GEN_CNTL, par);
2644         switch (blank) {
2645                 case FB_BLANK_UNBLANK:
2646                         gen_cntl &= ~(0x4c);
2647                         break;
2648                 case FB_BLANK_NORMAL:
2649                         gen_cntl |= 0x40;
2650                         break;
2651                 case FB_BLANK_VSYNC_SUSPEND:
2652                         gen_cntl |= 0x8;
2653                         break;
2654                 case FB_BLANK_HSYNC_SUSPEND:
2655                         gen_cntl |= 0x4;
2656                         break;
2657                 case FB_BLANK_POWERDOWN:
2658                         gen_cntl |= 0x4c;
2659                         break;
2660         }
2661         aty_st_8(CRTC_GEN_CNTL, gen_cntl, par);
2662
2663 #ifdef CONFIG_PMAC_BACKLIGHT
2664         if ((_machine == _MACH_Pmac) && !blank)
2665                 set_backlight_enable(1);
2666 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2667         if (par->lcd_table && !blank &&
2668             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2669                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2670                 pm |= PWR_BLON;
2671                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2672         }
2673 #endif
2674
2675         return 0;
2676 }
2677
2678 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2679                        const struct atyfb_par *par)
2680 {
2681 #ifdef CONFIG_ATARI
2682         out_8(&par->aty_cmap_regs->windex, regno);
2683         out_8(&par->aty_cmap_regs->lut, red);
2684         out_8(&par->aty_cmap_regs->lut, green);
2685         out_8(&par->aty_cmap_regs->lut, blue);
2686 #else
2687         writeb(regno, &par->aty_cmap_regs->windex);
2688         writeb(red, &par->aty_cmap_regs->lut);
2689         writeb(green, &par->aty_cmap_regs->lut);
2690         writeb(blue, &par->aty_cmap_regs->lut);
2691 #endif
2692 }
2693
2694     /*
2695      *  Set a single color register. The values supplied are already
2696      *  rounded down to the hardware's capabilities (according to the
2697      *  entries in the var structure). Return != 0 for invalid regno.
2698      *  !! 4 & 8 =  PSEUDO, > 8 = DIRECTCOLOR
2699      */
2700
2701 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2702         u_int transp, struct fb_info *info)
2703 {
2704         struct atyfb_par *par = (struct atyfb_par *) info->par;
2705         int i, depth;
2706         u32 *pal = info->pseudo_palette;
2707
2708         depth = info->var.bits_per_pixel;
2709         if (depth == 16)
2710                 depth = (info->var.green.length == 5) ? 15 : 16;
2711
2712         if (par->asleep)
2713                 return 0;
2714
2715         if (regno > 255 ||
2716             (depth == 16 && regno > 63) ||
2717             (depth == 15 && regno > 31))
2718                 return 1;
2719
2720         red >>= 8;
2721         green >>= 8;
2722         blue >>= 8;
2723
2724         par->palette[regno].red = red;
2725         par->palette[regno].green = green;
2726         par->palette[regno].blue = blue;
2727
2728         if (regno < 16) {
2729                 switch (depth) {
2730                 case 15:
2731                         pal[regno] = (regno << 10) | (regno << 5) | regno;
2732                         break;
2733                 case 16:
2734                         pal[regno] = (regno << 11) | (regno << 5) | regno;
2735                         break;
2736                 case 24:
2737                         pal[regno] = (regno << 16) | (regno << 8) | regno;
2738                         break;
2739                 case 32:
2740                         i = (regno << 8) | regno;
2741                         pal[regno] = (i << 16) | i;
2742                         break;
2743                 }
2744         }
2745
2746         i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2747         if (M64_HAS(EXTRA_BRIGHT))
2748                 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2749         aty_st_8(DAC_CNTL, i, par);
2750         aty_st_8(DAC_MASK, 0xff, par);
2751
2752         if (M64_HAS(INTEGRATED)) {
2753                 if (depth == 16) {
2754                         if (regno < 32)
2755                                 aty_st_pal(regno << 3, red,
2756                                            par->palette[regno<<1].green,
2757                                            blue, par);
2758                         red = par->palette[regno>>1].red;
2759                         blue = par->palette[regno>>1].blue;
2760                         regno <<= 2;
2761                 } else if (depth == 15) {
2762                         regno <<= 3;
2763                         for(i = 0; i < 8; i++) {
2764                             aty_st_pal(regno + i, red, green, blue, par);
2765                         }
2766                 }
2767         }
2768         aty_st_pal(regno, red, green, blue, par);
2769
2770         return 0;
2771 }
2772
2773 #ifdef CONFIG_PCI
2774
2775 #ifdef __sparc__
2776
2777 extern void (*prom_palette) (int);
2778
2779 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2780                         struct fb_info *info, unsigned long addr)
2781 {
2782         extern int con_is_present(void);
2783
2784         struct atyfb_par *par = info->par;
2785         struct pcidev_cookie *pcp;
2786         char prop[128];
2787         int node, len, i, j, ret;
2788         u32 mem, chip_id;
2789
2790         /* Do not attach when we have a serial console. */
2791         if (!con_is_present())
2792                 return -ENXIO;
2793
2794         /*
2795          * Map memory-mapped registers.
2796          */
2797         par->ati_regbase = (void *)addr + 0x7ffc00UL;
2798         info->fix.mmio_start = addr + 0x7ffc00UL;
2799
2800         /*
2801          * Map in big-endian aperture.
2802          */
2803         info->screen_base = (char *) (addr + 0x800000UL);
2804         info->fix.smem_start = addr + 0x800000UL;
2805
2806         /*
2807          * Figure mmap addresses from PCI config space.
2808          * Split Framebuffer in big- and little-endian halfs.
2809          */
2810         for (i = 0; i < 6 && pdev->resource[i].start; i++)
2811                 /* nothing */ ;
2812         j = i + 4;
2813
2814         par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2815         if (!par->mmap_map) {
2816                 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2817                 return -ENOMEM;
2818         }
2819         memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2820
2821         for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2822                 struct resource *rp = &pdev->resource[i];
2823                 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2824                 unsigned long base;
2825                 u32 size, pbase;
2826
2827                 base = rp->start;
2828
2829                 io = (rp->flags & IORESOURCE_IO);
2830
2831                 size = rp->end - base + 1;
2832
2833                 pci_read_config_dword(pdev, breg, &pbase);
2834
2835                 if (io)
2836                         size &= ~1;
2837
2838                 /*
2839                  * Map the framebuffer a second time, this time without
2840                  * the braindead _PAGE_IE setting. This is used by the
2841                  * fixed Xserver, but we need to maintain the old mapping
2842                  * to stay compatible with older ones...
2843                  */
2844                 if (base == addr) {
2845                         par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2846                         par->mmap_map[j].poff = base & PAGE_MASK;
2847                         par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2848                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2849                         par->mmap_map[j].prot_flag = _PAGE_E;
2850                         j++;
2851                 }
2852
2853                 /*
2854                  * Here comes the old framebuffer mapping with _PAGE_IE
2855                  * set for the big endian half of the framebuffer...
2856                  */
2857                 if (base == addr) {
2858                         par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2859                         par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2860                         par->mmap_map[j].size = 0x800000;
2861                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2862                         par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2863                         size -= 0x800000;
2864                         j++;
2865                 }
2866
2867                 par->mmap_map[j].voff = pbase & PAGE_MASK;
2868                 par->mmap_map[j].poff = base & PAGE_MASK;
2869                 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2870                 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2871                 par->mmap_map[j].prot_flag = _PAGE_E;
2872                 j++;
2873         }
2874
2875         if((ret = correct_chipset(par)))
2876                 return ret;
2877
2878         if (IS_XL(pdev->device)) {
2879                 /*
2880                  * Fix PROMs idea of MEM_CNTL settings...
2881                  */
2882                 mem = aty_ld_le32(MEM_CNTL, par);
2883                 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2884                 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2885                         switch (mem & 0x0f) {
2886                         case 3:
2887                                 mem = (mem & ~(0x0f)) | 2;
2888                                 break;
2889                         case 7:
2890                                 mem = (mem & ~(0x0f)) | 3;
2891                                 break;
2892                         case 9:
2893                                 mem = (mem & ~(0x0f)) | 4;
2894                                 break;
2895                         case 11:
2896                                 mem = (mem & ~(0x0f)) | 5;
2897                                 break;
2898                         default:
2899                                 break;
2900                         }
2901                         if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2902                                 mem &= ~(0x00700000);
2903                 }
2904                 mem &= ~(0xcf80e000);   /* Turn off all undocumented bits. */
2905                 aty_st_le32(MEM_CNTL, mem, par);
2906         }
2907
2908         /*
2909          * If this is the console device, we will set default video
2910          * settings to what the PROM left us with.
2911          */
2912         node = prom_getchild(prom_root_node);
2913         node = prom_searchsiblings(node, "aliases");
2914         if (node) {
2915                 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2916                 if (len > 0) {
2917                         prop[len] = '\0';
2918                         node = prom_finddevice(prop);
2919                 } else
2920                         node = 0;
2921         }
2922
2923         pcp = pdev->sysdata;
2924         if (node == pcp->prom_node) {
2925                 struct fb_var_screeninfo *var = &default_var;
2926                 unsigned int N, P, Q, M, T, R;
2927                 u32 v_total, h_total;
2928                 struct crtc crtc;
2929                 u8 pll_regs[16];
2930                 u8 clock_cntl;
2931
2932                 crtc.vxres = prom_getintdefault(node, "width", 1024);
2933                 crtc.vyres = prom_getintdefault(node, "height", 768);
2934                 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
2935                 var->xoffset = var->yoffset = 0;
2936                 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
2937                 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
2938                 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
2939                 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
2940                 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2941                 aty_crtc_to_var(&crtc, var);
2942
2943                 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
2944                 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
2945
2946                 /*
2947                  * Read the PLL to figure actual Refresh Rate.
2948                  */
2949                 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
2950                 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
2951                 for (i = 0; i < 16; i++)
2952                         pll_regs[i] = aty_ld_pll_ct(i, par);
2953
2954                 /*
2955                  * PLL Reference Divider M:
2956                  */
2957                 M = pll_regs[2];
2958
2959                 /*
2960                  * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
2961                  */
2962                 N = pll_regs[7 + (clock_cntl & 3)];
2963
2964                 /*
2965                  * PLL Post Divider P (Dependant on CLOCK_CNTL):
2966                  */
2967                 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
2968
2969                 /*
2970                  * PLL Divider Q:
2971                  */
2972                 Q = N / P;
2973
2974                 /*
2975                  * Target Frequency:
2976                  *
2977                  *      T * M
2978                  * Q = -------
2979                  *      2 * R
2980                  *
2981                  * where R is XTALIN (= 14318 or 29498 kHz).
2982                  */
2983                 if (IS_XL(pdev->device))
2984                         R = 29498;
2985                 else
2986                         R = 14318;
2987
2988                 T = 2 * Q * R / M;
2989
2990                 default_var.pixclock = 1000000000 / T;
2991         }
2992
2993         return 0;
2994 }
2995
2996 #else /* __sparc__ */
2997
2998 #ifdef __i386__
2999 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3000 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3001 {
3002         u32 driv_inf_tab, sig;
3003         u16 lcd_ofs;
3004
3005         /* To support an LCD panel, we should know it's dimensions and
3006          *  it's desired pixel clock.
3007          * There are two ways to do it:
3008          *  - Check the startup video mode and calculate the panel
3009          *    size from it. This is unreliable.
3010          *  - Read it from the driver information table in the video BIOS.
3011         */
3012         /* Address of driver information table is at offset 0x78. */
3013         driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3014
3015         /* Check for the driver information table signature. */
3016         sig = (*(u32 *)driv_inf_tab);
3017         if ((sig == 0x54504c24) || /* Rage LT pro */
3018                 (sig == 0x544d5224) || /* Rage mobility */
3019                 (sig == 0x54435824) || /* Rage XC */
3020                 (sig == 0x544c5824)) { /* Rage XL */
3021                 PRINTKI("BIOS contains driver information table.\n");
3022                 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3023                 par->lcd_table = 0;
3024                 if (lcd_ofs != 0) {
3025                         par->lcd_table = bios_base + lcd_ofs;
3026                 }
3027         }
3028
3029         if (par->lcd_table != 0) {
3030                 char model[24];
3031                 char strbuf[16];
3032                 char refresh_rates_buf[100];
3033                 int id, tech, f, i, m, default_refresh_rate;
3034                 char *txtcolour;
3035                 char *txtmonitor;
3036                 char *txtdual;
3037                 char *txtformat;
3038                 u16 width, height, panel_type, refresh_rates;
3039                 u16 *lcdmodeptr;
3040                 u32 format;
3041                 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3042                 /* The most important information is the panel size at
3043                  * offset 25 and 27, but there's some other nice information
3044                  * which we print to the screen.
3045                  */
3046                 id = *(u8 *)par->lcd_table;
3047                 strncpy(model,(char *)par->lcd_table+1,24);
3048                 model[23]=0;
3049
3050                 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3051                 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3052                 panel_type = *(u16 *)(par->lcd_table+29);
3053                 if (panel_type & 1)
3054                         txtcolour = "colour";
3055                 else
3056                         txtcolour = "monochrome";
3057                 if (panel_type & 2)
3058                         txtdual = "dual (split) ";
3059                 else
3060                         txtdual = "";
3061                 tech = (panel_type>>2) & 63;
3062                 switch (tech) {
3063                 case 0:
3064                         txtmonitor = "passive matrix";
3065                         break;
3066                 case 1:
3067                         txtmonitor = "active matrix";
3068                         break;
3069                 case 2:
3070                         txtmonitor = "active addressed STN";
3071                         break;
3072                 case 3:
3073                         txtmonitor = "EL";
3074                         break;
3075                 case 4:
3076                         txtmonitor = "plasma";
3077                         break;
3078                 default:
3079                         txtmonitor = "unknown";
3080                 }
3081                 format = *(u32 *)(par->lcd_table+57);
3082                 if (tech == 0 || tech == 2) {
3083                         switch (format & 7) {
3084                         case 0:
3085                                 txtformat = "12 bit interface";
3086                                 break;
3087                         case 1:
3088                                 txtformat = "16 bit interface";
3089                                 break;
3090                         case 2:
3091                                 txtformat = "24 bit interface";
3092                                 break;
3093                         default:
3094                                 txtformat = "unkown format";
3095                         }
3096                 } else {
3097                         switch (format & 7) {
3098                         case 0:
3099                                 txtformat = "8 colours";
3100                                 break;
3101                         case 1:
3102                                 txtformat = "512 colours";
3103                                 break;
3104                         case 2:
3105                                 txtformat = "4096 colours";
3106                                 break;
3107                         case 4:
3108                                 txtformat = "262144 colours (LT mode)";
3109                                 break;
3110                         case 5:
3111                                 txtformat = "16777216 colours";
3112                                 break;
3113                         case 6:
3114                                 txtformat = "262144 colours (FDPI-2 mode)";
3115                                 break;
3116                         default:
3117                                 txtformat = "unkown format";
3118                         }
3119                 }
3120                 PRINTKI("%s%s %s monitor detected: %s\n",
3121                         txtdual ,txtcolour, txtmonitor, model);
3122                 PRINTKI("       id=%d, %dx%d pixels, %s\n",
3123                         id, width, height, txtformat);
3124                 refresh_rates_buf[0] = 0;
3125                 refresh_rates = *(u16 *)(par->lcd_table+62);
3126                 m = 1;
3127                 f = 0;
3128                 for (i=0;i<16;i++) {
3129                         if (refresh_rates & m) {
3130                                 if (f == 0) {
3131                                         sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3132                                         f++;
3133                                 } else {
3134                                         sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3135                                 }
3136                                 strcat(refresh_rates_buf,strbuf);
3137                         }
3138                         m = m << 1;
3139                 }
3140                 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3141                 PRINTKI("       supports refresh rates [%s], default %d Hz\n",
3142                         refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3143                 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3144                 /* We now need to determine the crtc parameters for the
3145                  * lcd monitor. This is tricky, because they are not stored
3146                  * individually in the BIOS. Instead, the BIOS contains a
3147                  * table of display modes that work for this monitor.
3148                  *
3149                  * The idea is that we search for a mode of the same dimensions
3150                  * as the dimensions of the lcd monitor. Say our lcd monitor
3151                  * is 800x600 pixels, we search for a 800x600 monitor.
3152                  * The CRTC parameters we find here are the ones that we need
3153                  * to use to simulate other resolutions on the lcd screen.
3154                  */
3155                 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3156                 while (*lcdmodeptr != 0) {
3157                         u32 modeptr;
3158                         u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3159                         modeptr = bios_base + *lcdmodeptr;
3160
3161                         mwidth = *((u16 *)(modeptr+0));
3162                         mheight = *((u16 *)(modeptr+2));
3163
3164                         if (mwidth == width && mheight == height) {
3165                                 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3166                                 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3167                                 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3168                                 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3169                                 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3170                                 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3171
3172                                 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3173                                 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3174                                 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3175                                 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3176
3177                                 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3178                                 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3179                                 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3180                                 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3181
3182                                 par->lcd_vtotal++;
3183                                 par->lcd_vdisp++;
3184                                 lcd_vsync_start++;
3185
3186                                 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3187                                 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3188                                 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3189                                 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3190                                 break;
3191                         }
3192
3193                         lcdmodeptr++;
3194                 }
3195                 if (*lcdmodeptr == 0) {
3196                         PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3197                         /* To do: Switch to CRT if possible. */
3198                 } else {
3199                         PRINTKI("       LCD CRTC parameters: %d.%d  %d %d %d %d  %d %d %d %d\n",
3200                                 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3201                                 par->lcd_hdisp,
3202                                 par->lcd_hdisp + par->lcd_right_margin,
3203                                 par->lcd_hdisp + par->lcd_right_margin
3204                                         + par->lcd_hsync_dly + par->lcd_hsync_len,
3205                                 par->lcd_htotal,
3206                                 par->lcd_vdisp,
3207                                 par->lcd_vdisp + par->lcd_lower_margin,
3208                                 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3209                                 par->lcd_vtotal);
3210                         PRINTKI("                          : %d %d %d %d %d %d %d %d %d\n",
3211                                 par->lcd_pixclock,
3212                                 par->lcd_hblank_len - (par->lcd_right_margin +
3213                                         par->lcd_hsync_dly + par->lcd_hsync_len),
3214                                 par->lcd_hdisp,
3215                                 par->lcd_right_margin,
3216                                 par->lcd_hsync_len,
3217                                 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3218                                 par->lcd_vdisp,
3219                                 par->lcd_lower_margin,
3220                                 par->lcd_vsync_len);
3221                 }
3222         }
3223 }
3224 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3225
3226 static int __devinit init_from_bios(struct atyfb_par *par)
3227 {
3228         u32 bios_base, rom_addr;
3229         int ret;
3230
3231         rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3232         bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3233
3234         /* The BIOS starts with 0xaa55. */
3235         if (*((u16 *)bios_base) == 0xaa55) {
3236
3237                 u8 *bios_ptr;
3238                 u16 rom_table_offset, freq_table_offset;
3239                 PLL_BLOCK_MACH64 pll_block;
3240
3241                 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3242
3243                 /* check for frequncy table */
3244                 bios_ptr = (u8*)bios_base;
3245                 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3246                 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3247                 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3248
3249                 PRINTKI("BIOS frequency table:\n");
3250                 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3251                         pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3252                         pll_block.ref_freq, pll_block.ref_divider);
3253                 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3254                         pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3255                         pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3256
3257                 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3258                 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3259                 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3260                 par->pll_limits.ref_div = pll_block.ref_divider;
3261                 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3262                 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3263                 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3264                 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3265 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3266                 aty_init_lcd(par, bios_base);
3267 #endif
3268                 ret = 0;
3269         } else {
3270                 PRINTKE("no BIOS frequency table found, use parameters\n");
3271                 ret = -ENXIO;
3272         }
3273         iounmap((void* __iomem )bios_base);
3274
3275         return ret;
3276 }
3277 #endif /* __i386__ */
3278
3279 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3280 {
3281         struct atyfb_par *par = info->par;
3282         u16 tmp;
3283         unsigned long raddr;
3284         struct resource *rrp;
3285         int ret = 0;
3286
3287         raddr = addr + 0x7ff000UL;
3288         rrp = &pdev->resource[2];
3289         if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3290                 par->aux_start = rrp->start;
3291                 par->aux_size = rrp->end - rrp->start + 1;
3292                 raddr = rrp->start;
3293                 PRINTKI("using auxiliary register aperture\n");
3294         }
3295
3296         info->fix.mmio_start = raddr;
3297         par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3298         if (par->ati_regbase == 0)
3299                 return -ENOMEM;
3300
3301         info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3302         par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3303
3304         /*
3305          * Enable memory-space accesses using config-space
3306          * command register.
3307          */
3308         pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3309         if (!(tmp & PCI_COMMAND_MEMORY)) {
3310                 tmp |= PCI_COMMAND_MEMORY;
3311                 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3312         }
3313 #ifdef __BIG_ENDIAN
3314         /* Use the big-endian aperture */
3315         addr += 0x800000;
3316 #endif
3317
3318         /* Map in frame buffer */
3319         info->fix.smem_start = addr;
3320         info->screen_base = ioremap(addr, 0x800000);
3321         if (info->screen_base == NULL) {
3322                 ret = -ENOMEM;
3323                 goto atyfb_setup_generic_fail;
3324         }
3325
3326         if((ret = correct_chipset(par)))
3327                 goto atyfb_setup_generic_fail;
3328 #ifdef __i386__
3329         if((ret = init_from_bios(par)))
3330                 goto atyfb_setup_generic_fail;
3331 #endif
3332         if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3333                 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3334         else
3335                 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3336
3337         /* according to ATI, we should use clock 3 for acelerated mode */
3338         par->clk_wr_offset = 3;
3339
3340         return 0;
3341
3342 atyfb_setup_generic_fail:
3343         iounmap(par->ati_regbase);
3344         par->ati_regbase = NULL;
3345         return ret;
3346 }
3347
3348 #endif /* !__sparc__ */
3349
3350 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3351 {
3352         unsigned long addr, res_start, res_size;
3353         struct fb_info *info;
3354         struct resource *rp;
3355         struct atyfb_par *par;
3356         int i, rc = -ENOMEM;
3357
3358         for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
3359                 if (pdev->device == aty_chips[i].pci_id)
3360                         break;
3361
3362         if (i < 0)
3363                 return -ENODEV;
3364
3365         /* Enable device in PCI config */
3366         if (pci_enable_device(pdev)) {
3367                 PRINTKE("Cannot enable PCI device\n");
3368                 return -ENXIO;
3369         }
3370
3371         /* Find which resource to use */
3372         rp = &pdev->resource[0];
3373         if (rp->flags & IORESOURCE_IO)
3374                 rp = &pdev->resource[1];
3375         addr = rp->start;
3376         if (!addr)
3377                 return -ENXIO;
3378
3379         /* Reserve space */
3380         res_start = rp->start;
3381         res_size = rp->end - rp->start + 1;
3382         if (!request_mem_region (res_start, res_size, "atyfb"))
3383                 return -EBUSY;
3384
3385         /* Allocate framebuffer */
3386         info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3387         if (!info) {
3388                 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3389                 return -ENOMEM;
3390         }
3391         par = info->par;
3392         info->fix = atyfb_fix;
3393         info->device = &pdev->dev;
3394         par->pci_id = aty_chips[i].pci_id;
3395         par->res_start = res_start;
3396         par->res_size = res_size;
3397         par->irq = pdev->irq;
3398
3399         /* Setup "info" structure */
3400 #ifdef __sparc__
3401         rc = atyfb_setup_sparc(pdev, info, addr);
3402 #else
3403         rc = atyfb_setup_generic(pdev, info, addr);
3404 #endif
3405         if (rc)
3406                 goto err_release_mem;
3407
3408         pci_set_drvdata(pdev, info);
3409
3410         /* Init chip & register framebuffer */
3411         if (aty_init(info, "PCI"))
3412                 goto err_release_io;
3413
3414 #ifdef __sparc__
3415         if (!prom_palette)
3416                 prom_palette = atyfb_palette;
3417
3418         /*
3419          * Add /dev/fb mmap values.
3420          */
3421         par->mmap_map[0].voff = 0x8000000000000000UL;
3422         par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3423         par->mmap_map[0].size = info->fix.smem_len;
3424         par->mmap_map[0].prot_mask = _PAGE_CACHE;
3425         par->mmap_map[0].prot_flag = _PAGE_E;
3426         par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3427         par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3428         par->mmap_map[1].size = PAGE_SIZE;
3429         par->mmap_map[1].prot_mask = _PAGE_CACHE;
3430         par->mmap_map[1].prot_flag = _PAGE_E;
3431 #endif /* __sparc__ */
3432
3433         return 0;
3434
3435 err_release_io:
3436 #ifdef __sparc__
3437         kfree(par->mmap_map);
3438 #else
3439         if (par->ati_regbase)
3440                 iounmap(par->ati_regbase);
3441         if (info->screen_base)
3442                 iounmap(info->screen_base);
3443 #endif
3444 err_release_mem:
3445         if (par->aux_start)
3446                 release_mem_region(par->aux_start, par->aux_size);
3447
3448         release_mem_region(par->res_start, par->res_size);
3449         framebuffer_release(info);
3450
3451         return rc;
3452 }
3453
3454 #endif /* CONFIG_PCI */
3455
3456 #ifdef CONFIG_ATARI
3457
3458 static int __devinit atyfb_atari_probe(void)
3459 {
3460         struct aty_par *par;
3461         struct fb_info *info;
3462         int m64_num;
3463         u32 clock_r;
3464
3465         for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3466                 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3467                     !phys_guiregbase[m64_num]) {
3468                     PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3469                         continue;
3470                 }
3471
3472                 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3473                 if (!info) {
3474                         PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3475                         return -ENOMEM;
3476                 }
3477                 par = info->par;
3478
3479                 info->fix = atyfb_fix;
3480
3481                 par->irq = (unsigned int) -1; /* something invalid */
3482
3483                 /*
3484                  *  Map the video memory (physical address given) to somewhere in the
3485                  *  kernel address space.
3486                  */
3487                 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3488                 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3489                 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3490                                                 0xFC00ul;
3491                 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3492
3493                 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3494                 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3495
3496                 switch (clock_r & 0x003F) {
3497                 case 0x12:
3498                         par->clk_wr_offset = 3; /*  */
3499                         break;
3500                 case 0x34:
3501                         par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3502                         break;
3503                 case 0x16:
3504                         par->clk_wr_offset = 1; /*  */
3505                         break;
3506                 case 0x38:
3507                         par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3508                         break;
3509                 }
3510
3511                 if (aty_init(info, "ISA bus")) {
3512                         framebuffer_release(info);
3513                         /* This is insufficient! kernel_map has added two large chunks!! */
3514                         return -ENXIO;
3515                 }
3516         }
3517 }
3518
3519 #endif /* CONFIG_ATARI */
3520
3521 static void __devexit atyfb_remove(struct fb_info *info)
3522 {
3523         struct atyfb_par *par = (struct atyfb_par *) info->par;
3524
3525         /* restore video mode */
3526         aty_set_crtc(par, &saved_crtc);
3527         par->pll_ops->set_pll(info, &saved_pll);
3528
3529         unregister_framebuffer(info);
3530
3531 #ifdef CONFIG_MTRR
3532         if (par->mtrr_reg >= 0) {
3533             mtrr_del(par->mtrr_reg, 0, 0);
3534             par->mtrr_reg = -1;
3535         }
3536         if (par->mtrr_aper >= 0) {
3537             mtrr_del(par->mtrr_aper, 0, 0);
3538             par->mtrr_aper = -1;
3539         }
3540 #endif
3541 #ifndef __sparc__
3542         if (par->ati_regbase)
3543                 iounmap(par->ati_regbase);
3544         if (info->screen_base)
3545                 iounmap(info->screen_base);
3546 #ifdef __BIG_ENDIAN
3547         if (info->sprite.addr)
3548                 iounmap(info->sprite.addr);
3549 #endif
3550 #endif
3551 #ifdef __sparc__
3552         kfree(par->mmap_map);
3553 #endif
3554         if (par->aux_start)
3555                 release_mem_region(par->aux_start, par->aux_size);
3556
3557         if (par->res_start)
3558                 release_mem_region(par->res_start, par->res_size);
3559
3560         framebuffer_release(info);
3561 }
3562
3563 #ifdef CONFIG_PCI
3564
3565 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3566 {
3567         struct fb_info *info = pci_get_drvdata(pdev);
3568
3569         atyfb_remove(info);
3570 }
3571
3572 /*
3573  * This driver uses its own matching table. That will be more difficult
3574  * to fix, so for now, we just match against any ATI ID and let the
3575  * probe() function find out what's up. That also mean we don't have
3576  * a module ID table though.
3577  */
3578 static struct pci_device_id atyfb_pci_tbl[] = {
3579         { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3580           PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3581         { 0, }
3582 };
3583
3584 static struct pci_driver atyfb_driver = {
3585         .name           = "atyfb",
3586         .id_table       = atyfb_pci_tbl,
3587         .probe          = atyfb_pci_probe,
3588         .remove         = __devexit_p(atyfb_pci_remove),
3589 #ifdef CONFIG_PM
3590         .suspend        = atyfb_pci_suspend,
3591         .resume         = atyfb_pci_resume,
3592 #endif /* CONFIG_PM */
3593 };
3594
3595 #endif /* CONFIG_PCI */
3596
3597 #ifndef MODULE
3598 static int __init atyfb_setup(char *options)
3599 {
3600         char *this_opt;
3601
3602         if (!options || !*options)
3603                 return 0;
3604
3605         while ((this_opt = strsep(&options, ",")) != NULL) {
3606                 if (!strncmp(this_opt, "noaccel", 7)) {
3607                         noaccel = 1;
3608 #ifdef CONFIG_MTRR
3609                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3610                         nomtrr = 1;
3611 #endif
3612                 } else if (!strncmp(this_opt, "vram:", 5))
3613                         vram = simple_strtoul(this_opt + 5, NULL, 0);
3614                 else if (!strncmp(this_opt, "pll:", 4))
3615                         pll = simple_strtoul(this_opt + 4, NULL, 0);
3616                 else if (!strncmp(this_opt, "mclk:", 5))
3617                         mclk = simple_strtoul(this_opt + 5, NULL, 0);
3618                 else if (!strncmp(this_opt, "xclk:", 5))
3619                         xclk = simple_strtoul(this_opt+5, NULL, 0);
3620                 else if (!strncmp(this_opt, "comp_sync:", 10))
3621                         comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3622 #ifdef CONFIG_PPC
3623                 else if (!strncmp(this_opt, "vmode:", 6)) {
3624                         unsigned int vmode =
3625                             simple_strtoul(this_opt + 6, NULL, 0);
3626                         if (vmode > 0 && vmode <= VMODE_MAX)
3627                                 default_vmode = vmode;
3628                 } else if (!strncmp(this_opt, "cmode:", 6)) {
3629                         unsigned int cmode =
3630                             simple_strtoul(this_opt + 6, NULL, 0);
3631                         switch (cmode) {
3632                         case 0:
3633                         case 8:
3634                                 default_cmode = CMODE_8;
3635                                 break;
3636                         case 15:
3637                         case 16:
3638                                 default_cmode = CMODE_16;
3639                                 break;
3640                         case 24:
3641                         case 32:
3642                                 default_cmode = CMODE_32;
3643                                 break;
3644                         }
3645                 }
3646 #endif
3647 #ifdef CONFIG_ATARI
3648                 /*
3649                  * Why do we need this silly Mach64 argument?
3650                  * We are already here because of mach64= so its redundant.
3651                  */
3652                 else if (MACH_IS_ATARI
3653                          && (!strncmp(this_opt, "Mach64:", 7))) {
3654                         static unsigned char m64_num;
3655                         static char mach64_str[80];
3656                         strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3657                         if (!store_video_par(mach64_str, m64_num)) {
3658                                 m64_num++;
3659                                 mach64_count = m64_num;
3660                         }
3661                 }
3662 #endif
3663                 else
3664                         mode = this_opt;
3665         }
3666         return 0;
3667 }
3668 #endif  /*  MODULE  */
3669
3670 static int __init atyfb_init(void)
3671 {
3672 #ifndef MODULE
3673     char *option = NULL;
3674
3675     if (fb_get_options("atyfb", &option))
3676         return -ENODEV;
3677     atyfb_setup(option);
3678 #endif
3679
3680 #ifdef CONFIG_PCI
3681     pci_register_driver(&atyfb_driver);
3682 #endif
3683 #ifdef CONFIG_ATARI
3684     atyfb_atari_probe();
3685 #endif
3686     return 0;
3687 }
3688
3689 static void __exit atyfb_exit(void)
3690 {
3691 #ifdef CONFIG_PCI
3692         pci_unregister_driver(&atyfb_driver);
3693 #endif
3694 }
3695
3696 module_init(atyfb_init);
3697 module_exit(atyfb_exit);
3698
3699 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3700 MODULE_LICENSE("GPL");
3701 module_param(noaccel, bool, 0);
3702 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3703 module_param(vram, int, 0);
3704 MODULE_PARM_DESC(vram, "int: override size of video ram");
3705 module_param(pll, int, 0);
3706 MODULE_PARM_DESC(pll, "int: override video clock");
3707 module_param(mclk, int, 0);
3708 MODULE_PARM_DESC(mclk, "int: override memory clock");
3709 module_param(xclk, int, 0);
3710 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3711 module_param(comp_sync, int, 0);
3712 MODULE_PARM_DESC(comp_sync,
3713                  "Set composite sync signal to low (0) or high (1)");
3714 module_param(mode, charp, 0);
3715 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3716 #ifdef CONFIG_MTRR
3717 module_param(nomtrr, bool, 0);
3718 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3719 #endif