git.oblomov.eu Git - linux-2.6/blob - drivers/net/irda/smsc-ircc2.c

   1 /*********************************************************************
   2  * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
   3  *
   4  * Description:   Driver for the SMC Infrared Communications Controller
   5  * Status:        Experimental.
   6  * Author:        Daniele Peri (peri@csai.unipa.it)
   7  * Created at:
   8  * Modified at:
   9  * Modified by:
  10  *
  11  *     Copyright (c) 2002      Daniele Peri
  12  *     All Rights Reserved.
  13  *     Copyright (c) 2002      Jean Tourrilhes
  14  *     Copyright (c) 2006      Linus Walleij
  15  *
  16  *
  17  * Based on smc-ircc.c:
  18  *
  19  *     Copyright (c) 2001      Stefani Seibold
  20  *     Copyright (c) 1999-2001 Dag Brattli
  21  *     Copyright (c) 1998-1999 Thomas Davis,
  22  *
  23  *      and irport.c:
  24  *
  25  *     Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
  26  *
  27  *
  28  *     This program is free software; you can redistribute it and/or
  29  *     modify it under the terms of the GNU General Public License as
  30  *     published by the Free Software Foundation; either version 2 of
  31  *     the License, or (at your option) any later version.
  32  *
  33  *     This program is distributed in the hope that it will be useful,
  34  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  35  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  36  *     GNU General Public License for more details.
  37  *
  38  *     You should have received a copy of the GNU General Public License
  39  *     along with this program; if not, write to the Free Software
  40  *     Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  41  *     MA 02111-1307 USA
  42  *
  43  ********************************************************************/
  44
  45 #include <linux/module.h>
  46 #include <linux/kernel.h>
  47 #include <linux/types.h>
  48 #include <linux/skbuff.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/ioport.h>
  51 #include <linux/delay.h>
  52 #include <linux/slab.h>
  53 #include <linux/init.h>
  54 #include <linux/rtnetlink.h>
  55 #include <linux/serial_reg.h>
  56 #include <linux/dma-mapping.h>
  57 #include <linux/pnp.h>
  58 #include <linux/platform_device.h>
  59
  60 #include <asm/io.h>
  61 #include <asm/dma.h>
  62 #include <asm/byteorder.h>
  63
  64 #include <linux/spinlock.h>
  65 #include <linux/pm.h>
  66 #ifdef CONFIG_PCI
  67 #include <linux/pci.h>
  68 #endif
  69
  70 #include <net/irda/wrapper.h>
  71 #include <net/irda/irda.h>
  72 #include <net/irda/irda_device.h>
  73
  74 #include "smsc-ircc2.h"
  75 #include "smsc-sio.h"
  76
  77
  78 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
  79 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
  80 MODULE_LICENSE("GPL");
  81
  82 static int smsc_nopnp = 1;
  83 module_param_named(nopnp, smsc_nopnp, bool, 0);
  84 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
  85
  86 #define DMA_INVAL 255
  87 static int ircc_dma = DMA_INVAL;
  88 module_param(ircc_dma, int, 0);
  89 MODULE_PARM_DESC(ircc_dma, "DMA channel");
  90
  91 #define IRQ_INVAL 255
  92 static int ircc_irq = IRQ_INVAL;
  93 module_param(ircc_irq, int, 0);
  94 MODULE_PARM_DESC(ircc_irq, "IRQ line");
  95
  96 static int ircc_fir;
  97 module_param(ircc_fir, int, 0);
  98 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
  99
 100 static int ircc_sir;
 101 module_param(ircc_sir, int, 0);
 102 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
 103
 104 static int ircc_cfg;
 105 module_param(ircc_cfg, int, 0);
 106 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
 107
 108 static int ircc_transceiver;
 109 module_param(ircc_transceiver, int, 0);
 110 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
 111
 112 /* Types */
 113
 114 #ifdef CONFIG_PCI
 115 struct smsc_ircc_subsystem_configuration {
 116         unsigned short vendor; /* PCI vendor ID */
 117         unsigned short device; /* PCI vendor ID */
 118         unsigned short subvendor; /* PCI subsystem vendor ID */
 119         unsigned short subdevice; /* PCI sybsystem device ID */
 120         unsigned short sir_io; /* I/O port for SIR */
 121         unsigned short fir_io; /* I/O port for FIR */
 122         unsigned char  fir_irq; /* FIR IRQ */
 123         unsigned char  fir_dma; /* FIR DMA */
 124         unsigned short cfg_base; /* I/O port for chip configuration */
 125         int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
 126         const char *name;       /* name shown as info */
 127 };
 128 #endif
 129
 130 struct smsc_transceiver {
 131         char *name;
 132         void (*set_for_speed)(int fir_base, u32 speed);
 133         int  (*probe)(int fir_base);
 134 };
 135
 136 struct smsc_chip {
 137         char *name;
 138         #if 0
 139         u8      type;
 140         #endif
 141         u16 flags;
 142         u8 devid;
 143         u8 rev;
 144 };
 145
 146 struct smsc_chip_address {
 147         unsigned int cfg_base;
 148         unsigned int type;
 149 };
 150
 151 /* Private data for each instance */
 152 struct smsc_ircc_cb {
 153         struct net_device *netdev;     /* Yes! we are some kind of netdevice */
 154         struct net_device_stats stats;
 155         struct irlap_cb    *irlap; /* The link layer we are binded to */
 156
 157         chipio_t io;               /* IrDA controller information */
 158         iobuff_t tx_buff;          /* Transmit buffer */
 159         iobuff_t rx_buff;          /* Receive buffer */
 160         dma_addr_t tx_buff_dma;
 161         dma_addr_t rx_buff_dma;
 162
 163         struct qos_info qos;       /* QoS capabilities for this device */
 164
 165         spinlock_t lock;           /* For serializing operations */
 166
 167         __u32 new_speed;
 168         __u32 flags;               /* Interface flags */
 169
 170         int tx_buff_offsets[10];   /* Offsets between frames in tx_buff */
 171         int tx_len;                /* Number of frames in tx_buff */
 172
 173         int transceiver;
 174         struct platform_device *pldev;
 175 };
 176
 177 /* Constants */
 178
 179 #define SMSC_IRCC2_DRIVER_NAME                  "smsc-ircc2"
 180
 181 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED        9600
 182 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER        1
 183 #define SMSC_IRCC2_C_NET_TIMEOUT                0
 184 #define SMSC_IRCC2_C_SIR_STOP                   0
 185
 186 static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
 187
 188 /* Prototypes */
 189
 190 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
 191 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
 192 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
 193 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
 194 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
 195 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
 196 static int  smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
 197 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
 198 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
 199 static int  smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
 200 static int  smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
 201 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
 202 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
 203 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
 204 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
 205 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
 206 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
 207 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
 208 #if SMSC_IRCC2_C_SIR_STOP
 209 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
 210 #endif
 211 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
 212 static int  smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
 213 static int  smsc_ircc_net_open(struct net_device *dev);
 214 static int  smsc_ircc_net_close(struct net_device *dev);
 215 static int  smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 216 #if SMSC_IRCC2_C_NET_TIMEOUT
 217 static void smsc_ircc_timeout(struct net_device *dev);
 218 #endif
 219 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
 220 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
 221 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
 222 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
 223 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
 224
 225 /* Probing */
 226 static int __init smsc_ircc_look_for_chips(void);
 227 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
 228 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
 229 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
 230 static int __init smsc_superio_fdc(unsigned short cfg_base);
 231 static int __init smsc_superio_lpc(unsigned short cfg_base);
 232 #ifdef CONFIG_PCI
 233 static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
 234 static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
 235 static void __init preconfigure_ali_port(struct pci_dev *dev,
 236                                          unsigned short port);
 237 static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
 238 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
 239                                                     unsigned short ircc_fir,
 240                                                     unsigned short ircc_sir,
 241                                                     unsigned char ircc_dma,
 242                                                     unsigned char ircc_irq);
 243 #endif
 244
 245 /* Transceivers specific functions */
 246
 247 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
 248 static int  smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
 249 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
 250 static int  smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
 251 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
 252 static int  smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
 253
 254 /* Power Management */
 255
 256 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
 257 static int smsc_ircc_resume(struct platform_device *dev);
 258
 259 static struct platform_driver smsc_ircc_driver = {
 260         .suspend        = smsc_ircc_suspend,
 261         .resume         = smsc_ircc_resume,
 262         .driver         = {
 263                 .name   = SMSC_IRCC2_DRIVER_NAME,
 264         },
 265 };
 266
 267 /* Transceivers for SMSC-ircc */
 268
 269 static struct smsc_transceiver smsc_transceivers[] =
 270 {
 271         { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
 272         { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
 273         { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
 274         { NULL, NULL }
 275 };
 276 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
 277
 278 /*  SMC SuperIO chipsets definitions */
 279
 280 #define KEY55_1 0       /* SuperIO Configuration mode with Key <0x55> */
 281 #define KEY55_2 1       /* SuperIO Configuration mode with Key <0x55,0x55> */
 282 #define NoIRDA  2       /* SuperIO Chip has no IRDA Port */
 283 #define SIR     0       /* SuperIO Chip has only slow IRDA */
 284 #define FIR     4       /* SuperIO Chip has fast IRDA */
 285 #define SERx4   8       /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
 286
 287 static struct smsc_chip __initdata fdc_chips_flat[] =
 288 {
 289         /* Base address 0x3f0 or 0x370 */
 290         { "37C44",      KEY55_1|NoIRDA,         0x00, 0x00 }, /* This chip cannot be detected */
 291         { "37C665GT",   KEY55_2|NoIRDA,         0x65, 0x01 },
 292         { "37C665GT",   KEY55_2|NoIRDA,         0x66, 0x01 },
 293         { "37C669",     KEY55_2|SIR|SERx4,      0x03, 0x02 },
 294         { "37C669",     KEY55_2|SIR|SERx4,      0x04, 0x02 }, /* ID? */
 295         { "37C78",      KEY55_2|NoIRDA,         0x78, 0x00 },
 296         { "37N769",     KEY55_1|FIR|SERx4,      0x28, 0x00 },
 297         { "37N869",     KEY55_1|FIR|SERx4,      0x29, 0x00 },
 298         { NULL }
 299 };
 300
 301 static struct smsc_chip __initdata fdc_chips_paged[] =
 302 {
 303         /* Base address 0x3f0 or 0x370 */
 304         { "37B72X",     KEY55_1|SIR|SERx4,      0x4c, 0x00 },
 305         { "37B77X",     KEY55_1|SIR|SERx4,      0x43, 0x00 },
 306         { "37B78X",     KEY55_1|SIR|SERx4,      0x44, 0x00 },
 307         { "37B80X",     KEY55_1|SIR|SERx4,      0x42, 0x00 },
 308         { "37C67X",     KEY55_1|FIR|SERx4,      0x40, 0x00 },
 309         { "37C93X",     KEY55_2|SIR|SERx4,      0x02, 0x01 },
 310         { "37C93XAPM",  KEY55_1|SIR|SERx4,      0x30, 0x01 },
 311         { "37C93XFR",   KEY55_2|FIR|SERx4,      0x03, 0x01 },
 312         { "37M707",     KEY55_1|SIR|SERx4,      0x42, 0x00 },
 313         { "37M81X",     KEY55_1|SIR|SERx4,      0x4d, 0x00 },
 314         { "37N958FR",   KEY55_1|FIR|SERx4,      0x09, 0x04 },
 315         { "37N971",     KEY55_1|FIR|SERx4,      0x0a, 0x00 },
 316         { "37N972",     KEY55_1|FIR|SERx4,      0x0b, 0x00 },
 317         { NULL }
 318 };
 319
 320 static struct smsc_chip __initdata lpc_chips_flat[] =
 321 {
 322         /* Base address 0x2E or 0x4E */
 323         { "47N227",     KEY55_1|FIR|SERx4,      0x5a, 0x00 },
 324         { "47N227",     KEY55_1|FIR|SERx4,      0x7a, 0x00 },
 325         { "47N267",     KEY55_1|FIR|SERx4,      0x5e, 0x00 },
 326         { NULL }
 327 };
 328
 329 static struct smsc_chip __initdata lpc_chips_paged[] =
 330 {
 331         /* Base address 0x2E or 0x4E */
 332         { "47B27X",     KEY55_1|SIR|SERx4,      0x51, 0x00 },
 333         { "47B37X",     KEY55_1|SIR|SERx4,      0x52, 0x00 },
 334         { "47M10X",     KEY55_1|SIR|SERx4,      0x59, 0x00 },
 335         { "47M120",     KEY55_1|NoIRDA|SERx4,   0x5c, 0x00 },
 336         { "47M13X",     KEY55_1|SIR|SERx4,      0x59, 0x00 },
 337         { "47M14X",     KEY55_1|SIR|SERx4,      0x5f, 0x00 },
 338         { "47N252",     KEY55_1|FIR|SERx4,      0x0e, 0x00 },
 339         { "47S42X",     KEY55_1|SIR|SERx4,      0x57, 0x00 },
 340         { NULL }
 341 };
 342
 343 #define SMSCSIO_TYPE_FDC        1
 344 #define SMSCSIO_TYPE_LPC        2
 345 #define SMSCSIO_TYPE_FLAT       4
 346 #define SMSCSIO_TYPE_PAGED      8
 347
 348 static struct smsc_chip_address __initdata possible_addresses[] =
 349 {
 350         { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 351         { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 352         { 0xe0,  SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 353         { 0x2e,  SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 354         { 0x4e,  SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 355         { 0, 0 }
 356 };
 357
 358 /* Globals */
 359
 360 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
 361 static unsigned short dev_count;
 362
 363 static inline void register_bank(int iobase, int bank)
 364 {
 365         outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
 366                iobase + IRCC_MASTER);
 367 }
 368
 369 /* PNP hotplug support */
 370 static const struct pnp_device_id smsc_ircc_pnp_table[] = {
 371         { .id = "SMCf010", .driver_data = 0 },
 372         /* and presumably others */
 373         { }
 374 };
 375 MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
 376
 377 static int pnp_driver_registered;
 378
 379 static int __init smsc_ircc_pnp_probe(struct pnp_dev *dev,
 380                                       const struct pnp_device_id *dev_id)
 381 {
 382         unsigned int firbase, sirbase;
 383         u8 dma, irq;
 384
 385         if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
 386               pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
 387                 return -EINVAL;
 388
 389         sirbase = pnp_port_start(dev, 0);
 390         firbase = pnp_port_start(dev, 1);
 391         dma = pnp_dma(dev, 0);
 392         irq = pnp_irq(dev, 0);
 393
 394         if (smsc_ircc_open(firbase, sirbase, dma, irq))
 395                 return -ENODEV;
 396
 397         return 0;
 398 }
 399
 400 static struct pnp_driver smsc_ircc_pnp_driver = {
 401         .name           = "smsc-ircc2",
 402         .id_table       = smsc_ircc_pnp_table,
 403         .probe          = smsc_ircc_pnp_probe,
 404 };
 405
 406
 407 /*******************************************************************************
 408  *
 409  *
 410  * SMSC-ircc stuff
 411  *
 412  *
 413  *******************************************************************************/
 414
 415 static int __init smsc_ircc_legacy_probe(void)
 416 {
 417         int ret = 0;
 418
 419 #ifdef CONFIG_PCI
 420         if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
 421                 /* Ignore errors from preconfiguration */
 422                 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
 423         }
 424 #endif
 425
 426         if (ircc_fir > 0 && ircc_sir > 0) {
 427                 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
 428                 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
 429
 430                 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
 431                         ret = -ENODEV;
 432         } else {
 433                 ret = -ENODEV;
 434
 435                 /* try user provided configuration register base address */
 436                 if (ircc_cfg > 0) {
 437                         IRDA_MESSAGE(" Overriding configuration address "
 438                                      "0x%04x\n", ircc_cfg);
 439                         if (!smsc_superio_fdc(ircc_cfg))
 440                                 ret = 0;
 441                         if (!smsc_superio_lpc(ircc_cfg))
 442                                 ret = 0;
 443                 }
 444
 445                 if (smsc_ircc_look_for_chips() > 0)
 446                         ret = 0;
 447         }
 448         return ret;
 449 }
 450
 451 /*
 452  * Function smsc_ircc_init ()
 453  *
 454  *    Initialize chip. Just try to find out how many chips we are dealing with
 455  *    and where they are
 456  */
 457 static int __init smsc_ircc_init(void)
 458 {
 459         int ret;
 460
 461         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 462
 463         ret = platform_driver_register(&smsc_ircc_driver);
 464         if (ret) {
 465                 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
 466                 return ret;
 467         }
 468
 469         dev_count = 0;
 470
 471         if (smsc_nopnp || !pnp_platform_devices ||
 472             ircc_cfg || ircc_fir || ircc_sir ||
 473             ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
 474                 ret = smsc_ircc_legacy_probe();
 475         } else {
 476                 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
 477                         pnp_driver_registered = 1;
 478         }
 479
 480         if (ret) {
 481                 if (pnp_driver_registered)
 482                         pnp_unregister_driver(&smsc_ircc_pnp_driver);
 483                 platform_driver_unregister(&smsc_ircc_driver);
 484         }
 485
 486         return ret;
 487 }
 488
 489 /*
 490  * Function smsc_ircc_open (firbase, sirbase, dma, irq)
 491  *
 492  *    Try to open driver instance
 493  *
 494  */
 495 static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
 496 {
 497         struct smsc_ircc_cb *self;
 498         struct net_device *dev;
 499         int err;
 500
 501         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 502
 503         err = smsc_ircc_present(fir_base, sir_base);
 504         if (err)
 505                 goto err_out;
 506
 507         err = -ENOMEM;
 508         if (dev_count >= ARRAY_SIZE(dev_self)) {
 509                 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
 510                 goto err_out1;
 511         }
 512
 513         /*
 514          *  Allocate new instance of the driver
 515          */
 516         dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
 517         if (!dev) {
 518                 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
 519                 goto err_out1;
 520         }
 521
 522         dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
 523 #if SMSC_IRCC2_C_NET_TIMEOUT
 524         dev->tx_timeout      = smsc_ircc_timeout;
 525         dev->watchdog_timeo  = HZ * 2;  /* Allow enough time for speed change */
 526 #endif
 527         dev->open            = smsc_ircc_net_open;
 528         dev->stop            = smsc_ircc_net_close;
 529         dev->do_ioctl        = smsc_ircc_net_ioctl;
 530         dev->get_stats       = smsc_ircc_net_get_stats;
 531
 532         self = netdev_priv(dev);
 533         self->netdev = dev;
 534
 535         /* Make ifconfig display some details */
 536         dev->base_addr = self->io.fir_base = fir_base;
 537         dev->irq = self->io.irq = irq;
 538
 539         /* Need to store self somewhere */
 540         dev_self[dev_count] = self;
 541         spin_lock_init(&self->lock);
 542
 543         self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
 544         self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
 545
 546         self->rx_buff.head =
 547                 dma_alloc_coherent(NULL, self->rx_buff.truesize,
 548                                    &self->rx_buff_dma, GFP_KERNEL);
 549         if (self->rx_buff.head == NULL) {
 550                 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
 551                            driver_name);
 552                 goto err_out2;
 553         }
 554
 555         self->tx_buff.head =
 556                 dma_alloc_coherent(NULL, self->tx_buff.truesize,
 557                                    &self->tx_buff_dma, GFP_KERNEL);
 558         if (self->tx_buff.head == NULL) {
 559                 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
 560                            driver_name);
 561                 goto err_out3;
 562         }
 563
 564         memset(self->rx_buff.head, 0, self->rx_buff.truesize);
 565         memset(self->tx_buff.head, 0, self->tx_buff.truesize);
 566
 567         self->rx_buff.in_frame = FALSE;
 568         self->rx_buff.state = OUTSIDE_FRAME;
 569         self->tx_buff.data = self->tx_buff.head;
 570         self->rx_buff.data = self->rx_buff.head;
 571
 572         smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
 573         smsc_ircc_setup_qos(self);
 574         smsc_ircc_init_chip(self);
 575
 576         if (ircc_transceiver > 0  &&
 577             ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
 578                 self->transceiver = ircc_transceiver;
 579         else
 580                 smsc_ircc_probe_transceiver(self);
 581
 582         err = register_netdev(self->netdev);
 583         if (err) {
 584                 IRDA_ERROR("%s, Network device registration failed!\n",
 585                            driver_name);
 586                 goto err_out4;
 587         }
 588
 589         self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
 590                                                       dev_count, NULL, 0);
 591         if (IS_ERR(self->pldev)) {
 592                 err = PTR_ERR(self->pldev);
 593                 goto err_out5;
 594         }
 595         platform_set_drvdata(self->pldev, self);
 596
 597         IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
 598         dev_count++;
 599
 600         return 0;
 601
 602  err_out5:
 603         unregister_netdev(self->netdev);
 604
 605  err_out4:
 606         dma_free_coherent(NULL, self->tx_buff.truesize,
 607                           self->tx_buff.head, self->tx_buff_dma);
 608  err_out3:
 609         dma_free_coherent(NULL, self->rx_buff.truesize,
 610                           self->rx_buff.head, self->rx_buff_dma);
 611  err_out2:
 612         free_netdev(self->netdev);
 613         dev_self[dev_count] = NULL;
 614  err_out1:
 615         release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
 616         release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
 617  err_out:
 618         return err;
 619 }
 620
 621 /*
 622  * Function smsc_ircc_present(fir_base, sir_base)
 623  *
 624  *    Check the smsc-ircc chip presence
 625  *
 626  */
 627 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
 628 {
 629         unsigned char low, high, chip, config, dma, irq, version;
 630
 631         if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
 632                             driver_name)) {
 633                 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
 634                              __FUNCTION__, fir_base);
 635                 goto out1;
 636         }
 637
 638         if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
 639                             driver_name)) {
 640                 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
 641                              __FUNCTION__, sir_base);
 642                 goto out2;
 643         }
 644
 645         register_bank(fir_base, 3);
 646
 647         high    = inb(fir_base + IRCC_ID_HIGH);
 648         low     = inb(fir_base + IRCC_ID_LOW);
 649         chip    = inb(fir_base + IRCC_CHIP_ID);
 650         version = inb(fir_base + IRCC_VERSION);
 651         config  = inb(fir_base + IRCC_INTERFACE);
 652         dma     = config & IRCC_INTERFACE_DMA_MASK;
 653         irq     = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
 654
 655         if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
 656                 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
 657                              __FUNCTION__, fir_base);
 658                 goto out3;
 659         }
 660         IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
 661                      "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
 662                      chip & 0x0f, version, fir_base, sir_base, dma, irq);
 663
 664         return 0;
 665
 666  out3:
 667         release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
 668  out2:
 669         release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
 670  out1:
 671         return -ENODEV;
 672 }
 673
 674 /*
 675  * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
 676  *
 677  *    Setup I/O
 678  *
 679  */
 680 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
 681                                unsigned int fir_base, unsigned int sir_base,
 682                                u8 dma, u8 irq)
 683 {
 684         unsigned char config, chip_dma, chip_irq;
 685
 686         register_bank(fir_base, 3);
 687         config = inb(fir_base + IRCC_INTERFACE);
 688         chip_dma = config & IRCC_INTERFACE_DMA_MASK;
 689         chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
 690
 691         self->io.fir_base  = fir_base;
 692         self->io.sir_base  = sir_base;
 693         self->io.fir_ext   = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
 694         self->io.sir_ext   = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
 695         self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
 696         self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
 697
 698         if (irq != IRQ_INVAL) {
 699                 if (irq != chip_irq)
 700                         IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
 701                                      driver_name, chip_irq, irq);
 702                 self->io.irq = irq;
 703         } else
 704                 self->io.irq = chip_irq;
 705
 706         if (dma != DMA_INVAL) {
 707                 if (dma != chip_dma)
 708                         IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
 709                                      driver_name, chip_dma, dma);
 710                 self->io.dma = dma;
 711         } else
 712                 self->io.dma = chip_dma;
 713
 714 }
 715
 716 /*
 717  * Function smsc_ircc_setup_qos(self)
 718  *
 719  *    Setup qos
 720  *
 721  */
 722 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
 723 {
 724         /* Initialize QoS for this device */
 725         irda_init_max_qos_capabilies(&self->qos);
 726
 727         self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
 728                 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
 729
 730         self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
 731         self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
 732         irda_qos_bits_to_value(&self->qos);
 733 }
 734
 735 /*
 736  * Function smsc_ircc_init_chip(self)
 737  *
 738  *    Init chip
 739  *
 740  */
 741 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
 742 {
 743         int iobase = self->io.fir_base;
 744
 745         register_bank(iobase, 0);
 746         outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
 747         outb(0x00, iobase + IRCC_MASTER);
 748
 749         register_bank(iobase, 1);
 750         outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
 751              iobase + IRCC_SCE_CFGA);
 752
 753 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
 754         outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
 755              iobase + IRCC_SCE_CFGB);
 756 #else
 757         outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
 758              iobase + IRCC_SCE_CFGB);
 759 #endif
 760         (void) inb(iobase + IRCC_FIFO_THRESHOLD);
 761         outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
 762
 763         register_bank(iobase, 4);
 764         outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
 765
 766         register_bank(iobase, 0);
 767         outb(0, iobase + IRCC_LCR_A);
 768
 769         smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
 770
 771         /* Power on device */
 772         outb(0x00, iobase + IRCC_MASTER);
 773 }
 774
 775 /*
 776  * Function smsc_ircc_net_ioctl (dev, rq, cmd)
 777  *
 778  *    Process IOCTL commands for this device
 779  *
 780  */
 781 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 782 {
 783         struct if_irda_req *irq = (struct if_irda_req *) rq;
 784         struct smsc_ircc_cb *self;
 785         unsigned long flags;
 786         int ret = 0;
 787
 788         IRDA_ASSERT(dev != NULL, return -1;);
 789
 790         self = netdev_priv(dev);
 791
 792         IRDA_ASSERT(self != NULL, return -1;);
 793
 794         IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
 795
 796         switch (cmd) {
 797         case SIOCSBANDWIDTH: /* Set bandwidth */
 798                 if (!capable(CAP_NET_ADMIN))
 799                         ret = -EPERM;
 800                 else {
 801                         /* Make sure we are the only one touching
 802                          * self->io.speed and the hardware - Jean II */
 803                         spin_lock_irqsave(&self->lock, flags);
 804                         smsc_ircc_change_speed(self, irq->ifr_baudrate);
 805                         spin_unlock_irqrestore(&self->lock, flags);
 806                 }
 807                 break;
 808         case SIOCSMEDIABUSY: /* Set media busy */
 809                 if (!capable(CAP_NET_ADMIN)) {
 810                         ret = -EPERM;
 811                         break;
 812                 }
 813
 814                 irda_device_set_media_busy(self->netdev, TRUE);
 815                 break;
 816         case SIOCGRECEIVING: /* Check if we are receiving right now */
 817                 irq->ifr_receiving = smsc_ircc_is_receiving(self);
 818                 break;
 819         #if 0
 820         case SIOCSDTRRTS:
 821                 if (!capable(CAP_NET_ADMIN)) {
 822                         ret = -EPERM;
 823                         break;
 824                 }
 825                 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
 826                 break;
 827         #endif
 828         default:
 829                 ret = -EOPNOTSUPP;
 830         }
 831
 832         return ret;
 833 }
 834
 835 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
 836 {
 837         struct smsc_ircc_cb *self = netdev_priv(dev);
 838
 839         return &self->stats;
 840 }
 841
 842 #if SMSC_IRCC2_C_NET_TIMEOUT
 843 /*
 844  * Function smsc_ircc_timeout (struct net_device *dev)
 845  *
 846  *    The networking timeout management.
 847  *
 848  */
 849
 850 static void smsc_ircc_timeout(struct net_device *dev)
 851 {
 852         struct smsc_ircc_cb *self = netdev_priv(dev);
 853         unsigned long flags;
 854
 855         IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
 856                      dev->name, self->io.speed);
 857         spin_lock_irqsave(&self->lock, flags);
 858         smsc_ircc_sir_start(self);
 859         smsc_ircc_change_speed(self, self->io.speed);
 860         dev->trans_start = jiffies;
 861         netif_wake_queue(dev);
 862         spin_unlock_irqrestore(&self->lock, flags);
 863 }
 864 #endif
 865
 866 /*
 867  * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
 868  *
 869  *    Transmits the current frame until FIFO is full, then
 870  *    waits until the next transmit interrupt, and continues until the
 871  *    frame is transmitted.
 872  */
 873 int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
 874 {
 875         struct smsc_ircc_cb *self;
 876         unsigned long flags;
 877         s32 speed;
 878
 879         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 880
 881         IRDA_ASSERT(dev != NULL, return 0;);
 882
 883         self = netdev_priv(dev);
 884         IRDA_ASSERT(self != NULL, return 0;);
 885
 886         netif_stop_queue(dev);
 887
 888         /* Make sure test of self->io.speed & speed change are atomic */
 889         spin_lock_irqsave(&self->lock, flags);
 890
 891         /* Check if we need to change the speed */
 892         speed = irda_get_next_speed(skb);
 893         if (speed != self->io.speed && speed != -1) {
 894                 /* Check for empty frame */
 895                 if (!skb->len) {
 896                         /*
 897                          * We send frames one by one in SIR mode (no
 898                          * pipelining), so at this point, if we were sending
 899                          * a previous frame, we just received the interrupt
 900                          * telling us it is finished (UART_IIR_THRI).
 901                          * Therefore, waiting for the transmitter to really
 902                          * finish draining the fifo won't take too long.
 903                          * And the interrupt handler is not expected to run.
 904                          * - Jean II */
 905                         smsc_ircc_sir_wait_hw_transmitter_finish(self);
 906                         smsc_ircc_change_speed(self, speed);
 907                         spin_unlock_irqrestore(&self->lock, flags);
 908                         dev_kfree_skb(skb);
 909                         return 0;
 910                 }
 911                 self->new_speed = speed;
 912         }
 913
 914         /* Init tx buffer */
 915         self->tx_buff.data = self->tx_buff.head;
 916
 917         /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
 918         self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
 919                                            self->tx_buff.truesize);
 920
 921         self->stats.tx_bytes += self->tx_buff.len;
 922
 923         /* Turn on transmit finished interrupt. Will fire immediately!  */
 924         outb(UART_IER_THRI, self->io.sir_base + UART_IER);
 925
 926         spin_unlock_irqrestore(&self->lock, flags);
 927
 928         dev_kfree_skb(skb);
 929
 930         return 0;
 931 }
 932
 933 /*
 934  * Function smsc_ircc_set_fir_speed (self, baud)
 935  *
 936  *    Change the speed of the device
 937  *
 938  */
 939 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
 940 {
 941         int fir_base, ir_mode, ctrl, fast;
 942
 943         IRDA_ASSERT(self != NULL, return;);
 944         fir_base = self->io.fir_base;
 945
 946         self->io.speed = speed;
 947
 948         switch (speed) {
 949         default:
 950         case 576000:
 951                 ir_mode = IRCC_CFGA_IRDA_HDLC;
 952                 ctrl = IRCC_CRC;
 953                 fast = 0;
 954                 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
 955                 break;
 956         case 1152000:
 957                 ir_mode = IRCC_CFGA_IRDA_HDLC;
 958                 ctrl = IRCC_1152 | IRCC_CRC;
 959                 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
 960                 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
 961                            __FUNCTION__);
 962                 break;
 963         case 4000000:
 964                 ir_mode = IRCC_CFGA_IRDA_4PPM;
 965                 ctrl = IRCC_CRC;
 966                 fast = IRCC_LCR_A_FAST;
 967                 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
 968                            __FUNCTION__);
 969                 break;
 970         }
 971         #if 0
 972         Now in tranceiver!
 973         /* This causes an interrupt */
 974         register_bank(fir_base, 0);
 975         outb((inb(fir_base + IRCC_LCR_A) &  0xbf) | fast, fir_base + IRCC_LCR_A);
 976         #endif
 977
 978         register_bank(fir_base, 1);
 979         outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
 980
 981         register_bank(fir_base, 4);
 982         outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
 983 }
 984
 985 /*
 986  * Function smsc_ircc_fir_start(self)
 987  *
 988  *    Change the speed of the device
 989  *
 990  */
 991 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
 992 {
 993         struct net_device *dev;
 994         int fir_base;
 995
 996         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 997
 998         IRDA_ASSERT(self != NULL, return;);
 999         dev = self->netdev;
1000         IRDA_ASSERT(dev != NULL, return;);
1001
1002         fir_base = self->io.fir_base;
1003
1004         /* Reset everything */
1005
1006         /* Install FIR transmit handler */
1007         dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
1008
1009         /* Clear FIFO */
1010         outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1011
1012         /* Enable interrupt */
1013         /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1014
1015         register_bank(fir_base, 1);
1016
1017         /* Select the TX/RX interface */
1018 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
1019         outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1020              fir_base + IRCC_SCE_CFGB);
1021 #else
1022         outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1023              fir_base + IRCC_SCE_CFGB);
1024 #endif
1025         (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1026
1027         /* Enable SCE interrupts */
1028         outb(0, fir_base + IRCC_MASTER);
1029         register_bank(fir_base, 0);
1030         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1031         outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1032 }
1033
1034 /*
1035  * Function smsc_ircc_fir_stop(self, baud)
1036  *
1037  *    Change the speed of the device
1038  *
1039  */
1040 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1041 {
1042         int fir_base;
1043
1044         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1045
1046         IRDA_ASSERT(self != NULL, return;);
1047
1048         fir_base = self->io.fir_base;
1049         register_bank(fir_base, 0);
1050         /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1051         outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1052 }
1053
1054
1055 /*
1056  * Function smsc_ircc_change_speed(self, baud)
1057  *
1058  *    Change the speed of the device
1059  *
1060  * This function *must* be called with spinlock held, because it may
1061  * be called from the irq handler. - Jean II
1062  */
1063 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1064 {
1065         struct net_device *dev;
1066         int last_speed_was_sir;
1067
1068         IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
1069
1070         IRDA_ASSERT(self != NULL, return;);
1071         dev = self->netdev;
1072
1073         last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1074
1075         #if 0
1076         /* Temp Hack */
1077         speed= 1152000;
1078         self->io.speed = speed;
1079         last_speed_was_sir = 0;
1080         smsc_ircc_fir_start(self);
1081         #endif
1082
1083         if (self->io.speed == 0)
1084                 smsc_ircc_sir_start(self);
1085
1086         #if 0
1087         if (!last_speed_was_sir) speed = self->io.speed;
1088         #endif
1089
1090         if (self->io.speed != speed)
1091                 smsc_ircc_set_transceiver_for_speed(self, speed);
1092
1093         self->io.speed = speed;
1094
1095         if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1096                 if (!last_speed_was_sir) {
1097                         smsc_ircc_fir_stop(self);
1098                         smsc_ircc_sir_start(self);
1099                 }
1100                 smsc_ircc_set_sir_speed(self, speed);
1101         } else {
1102                 if (last_speed_was_sir) {
1103                         #if SMSC_IRCC2_C_SIR_STOP
1104                         smsc_ircc_sir_stop(self);
1105                         #endif
1106                         smsc_ircc_fir_start(self);
1107                 }
1108                 smsc_ircc_set_fir_speed(self, speed);
1109
1110                 #if 0
1111                 self->tx_buff.len = 10;
1112                 self->tx_buff.data = self->tx_buff.head;
1113
1114                 smsc_ircc_dma_xmit(self, 4000);
1115                 #endif
1116                 /* Be ready for incoming frames */
1117                 smsc_ircc_dma_receive(self);
1118         }
1119
1120         netif_wake_queue(dev);
1121 }
1122
1123 /*
1124  * Function smsc_ircc_set_sir_speed (self, speed)
1125  *
1126  *    Set speed of IrDA port to specified baudrate
1127  *
1128  */
1129 void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1130 {
1131         int iobase;
1132         int fcr;    /* FIFO control reg */
1133         int lcr;    /* Line control reg */
1134         int divisor;
1135
1136         IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1137
1138         IRDA_ASSERT(self != NULL, return;);
1139         iobase = self->io.sir_base;
1140
1141         /* Update accounting for new speed */
1142         self->io.speed = speed;
1143
1144         /* Turn off interrupts */
1145         outb(0, iobase + UART_IER);
1146
1147         divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1148
1149         fcr = UART_FCR_ENABLE_FIFO;
1150
1151         /*
1152          * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1153          * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1154          * about this timeout since it will always be fast enough.
1155          */
1156         fcr |= self->io.speed < 38400 ?
1157                 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1158
1159         /* IrDA ports use 8N1 */
1160         lcr = UART_LCR_WLEN8;
1161
1162         outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1163         outb(divisor & 0xff,      iobase + UART_DLL); /* Set speed */
1164         outb(divisor >> 8,        iobase + UART_DLM);
1165         outb(lcr,                 iobase + UART_LCR); /* Set 8N1 */
1166         outb(fcr,                 iobase + UART_FCR); /* Enable FIFO's */
1167
1168         /* Turn on interrups */
1169         outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1170
1171         IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1172 }
1173
1174
1175 /*
1176  * Function smsc_ircc_hard_xmit_fir (skb, dev)
1177  *
1178  *    Transmit the frame!
1179  *
1180  */
1181 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1182 {
1183         struct smsc_ircc_cb *self;
1184         unsigned long flags;
1185         s32 speed;
1186         int mtt;
1187
1188         IRDA_ASSERT(dev != NULL, return 0;);
1189         self = netdev_priv(dev);
1190         IRDA_ASSERT(self != NULL, return 0;);
1191
1192         netif_stop_queue(dev);
1193
1194         /* Make sure test of self->io.speed & speed change are atomic */
1195         spin_lock_irqsave(&self->lock, flags);
1196
1197         /* Check if we need to change the speed after this frame */
1198         speed = irda_get_next_speed(skb);
1199         if (speed != self->io.speed && speed != -1) {
1200                 /* Check for empty frame */
1201                 if (!skb->len) {
1202                         /* Note : you should make sure that speed changes
1203                          * are not going to corrupt any outgoing frame.
1204                          * Look at nsc-ircc for the gory details - Jean II */
1205                         smsc_ircc_change_speed(self, speed);
1206                         spin_unlock_irqrestore(&self->lock, flags);
1207                         dev_kfree_skb(skb);
1208                         return 0;
1209                 }
1210
1211                 self->new_speed = speed;
1212         }
1213
1214         skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1215
1216         self->tx_buff.len = skb->len;
1217         self->tx_buff.data = self->tx_buff.head;
1218
1219         mtt = irda_get_mtt(skb);
1220         if (mtt) {
1221                 int bofs;
1222
1223                 /*
1224                  * Compute how many BOFs (STA or PA's) we need to waste the
1225                  * min turn time given the speed of the link.
1226                  */
1227                 bofs = mtt * (self->io.speed / 1000) / 8000;
1228                 if (bofs > 4095)
1229                         bofs = 4095;
1230
1231                 smsc_ircc_dma_xmit(self, bofs);
1232         } else {
1233                 /* Transmit frame */
1234                 smsc_ircc_dma_xmit(self, 0);
1235         }
1236
1237         spin_unlock_irqrestore(&self->lock, flags);
1238         dev_kfree_skb(skb);
1239
1240         return 0;
1241 }
1242
1243 /*
1244  * Function smsc_ircc_dma_xmit (self, bofs)
1245  *
1246  *    Transmit data using DMA
1247  *
1248  */
1249 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1250 {
1251         int iobase = self->io.fir_base;
1252         u8 ctrl;
1253
1254         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1255 #if 1
1256         /* Disable Rx */
1257         register_bank(iobase, 0);
1258         outb(0x00, iobase + IRCC_LCR_B);
1259 #endif
1260         register_bank(iobase, 1);
1261         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1262              iobase + IRCC_SCE_CFGB);
1263
1264         self->io.direction = IO_XMIT;
1265
1266         /* Set BOF additional count for generating the min turn time */
1267         register_bank(iobase, 4);
1268         outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1269         ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1270         outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1271
1272         /* Set max Tx frame size */
1273         outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1274         outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1275
1276         /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1277
1278         /* Enable burst mode chip Tx DMA */
1279         register_bank(iobase, 1);
1280         outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1281              IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1282
1283         /* Setup DMA controller (must be done after enabling chip DMA) */
1284         irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1285                        DMA_TX_MODE);
1286
1287         /* Enable interrupt */
1288
1289         register_bank(iobase, 0);
1290         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1291         outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1292
1293         /* Enable transmit */
1294         outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1295 }
1296
1297 /*
1298  * Function smsc_ircc_dma_xmit_complete (self)
1299  *
1300  *    The transfer of a frame in finished. This function will only be called
1301  *    by the interrupt handler
1302  *
1303  */
1304 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1305 {
1306         int iobase = self->io.fir_base;
1307
1308         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1309 #if 0
1310         /* Disable Tx */
1311         register_bank(iobase, 0);
1312         outb(0x00, iobase + IRCC_LCR_B);
1313 #endif
1314         register_bank(iobase, 1);
1315         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1316              iobase + IRCC_SCE_CFGB);
1317
1318         /* Check for underrun! */
1319         register_bank(iobase, 0);
1320         if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1321                 self->stats.tx_errors++;
1322                 self->stats.tx_fifo_errors++;
1323
1324                 /* Reset error condition */
1325                 register_bank(iobase, 0);
1326                 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1327                 outb(0x00, iobase + IRCC_MASTER);
1328         } else {
1329                 self->stats.tx_packets++;
1330                 self->stats.tx_bytes += self->tx_buff.len;
1331         }
1332
1333         /* Check if it's time to change the speed */
1334         if (self->new_speed) {
1335                 smsc_ircc_change_speed(self, self->new_speed);
1336                 self->new_speed = 0;
1337         }
1338
1339         netif_wake_queue(self->netdev);
1340 }
1341
1342 /*
1343  * Function smsc_ircc_dma_receive(self)
1344  *
1345  *    Get ready for receiving a frame. The device will initiate a DMA
1346  *    if it starts to receive a frame.
1347  *
1348  */
1349 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1350 {
1351         int iobase = self->io.fir_base;
1352 #if 0
1353         /* Turn off chip DMA */
1354         register_bank(iobase, 1);
1355         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1356              iobase + IRCC_SCE_CFGB);
1357 #endif
1358
1359         /* Disable Tx */
1360         register_bank(iobase, 0);
1361         outb(0x00, iobase + IRCC_LCR_B);
1362
1363         /* Turn off chip DMA */
1364         register_bank(iobase, 1);
1365         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1366              iobase + IRCC_SCE_CFGB);
1367
1368         self->io.direction = IO_RECV;
1369         self->rx_buff.data = self->rx_buff.head;
1370
1371         /* Set max Rx frame size */
1372         register_bank(iobase, 4);
1373         outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1374         outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1375
1376         /* Setup DMA controller */
1377         irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1378                        DMA_RX_MODE);
1379
1380         /* Enable burst mode chip Rx DMA */
1381         register_bank(iobase, 1);
1382         outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1383              IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1384
1385         /* Enable interrupt */
1386         register_bank(iobase, 0);
1387         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1388         outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1389
1390         /* Enable receiver */
1391         register_bank(iobase, 0);
1392         outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1393              iobase + IRCC_LCR_B);
1394
1395         return 0;
1396 }
1397
1398 /*
1399  * Function smsc_ircc_dma_receive_complete(self)
1400  *
1401  *    Finished with receiving frames
1402  *
1403  */
1404 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1405 {
1406         struct sk_buff *skb;
1407         int len, msgcnt, lsr;
1408         int iobase = self->io.fir_base;
1409
1410         register_bank(iobase, 0);
1411
1412         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1413 #if 0
1414         /* Disable Rx */
1415         register_bank(iobase, 0);
1416         outb(0x00, iobase + IRCC_LCR_B);
1417 #endif
1418         register_bank(iobase, 0);
1419         outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1420         lsr= inb(iobase + IRCC_LSR);
1421         msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1422
1423         IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1424                    get_dma_residue(self->io.dma));
1425
1426         len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1427
1428         /* Look for errors */
1429         if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1430                 self->stats.rx_errors++;
1431                 if (lsr & IRCC_LSR_FRAME_ERROR)
1432                         self->stats.rx_frame_errors++;
1433                 if (lsr & IRCC_LSR_CRC_ERROR)
1434                         self->stats.rx_crc_errors++;
1435                 if (lsr & IRCC_LSR_SIZE_ERROR)
1436                         self->stats.rx_length_errors++;
1437                 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1438                         self->stats.rx_length_errors++;
1439                 return;
1440         }
1441
1442         /* Remove CRC */
1443         len -= self->io.speed < 4000000 ? 2 : 4;
1444
1445         if (len < 2 || len > 2050) {
1446                 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1447                 return;
1448         }
1449         IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1450
1451         skb = dev_alloc_skb(len + 1);
1452         if (!skb) {
1453                 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1454                              __FUNCTION__);
1455                 return;
1456         }
1457         /* Make sure IP header gets aligned */
1458         skb_reserve(skb, 1);
1459
1460         memcpy(skb_put(skb, len), self->rx_buff.data, len);
1461         self->stats.rx_packets++;
1462         self->stats.rx_bytes += len;
1463
1464         skb->dev = self->netdev;
1465         skb_reset_mac_header(skb);
1466         skb->protocol = htons(ETH_P_IRDA);
1467         netif_rx(skb);
1468 }
1469
1470 /*
1471  * Function smsc_ircc_sir_receive (self)
1472  *
1473  *    Receive one frame from the infrared port
1474  *
1475  */
1476 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1477 {
1478         int boguscount = 0;
1479         int iobase;
1480
1481         IRDA_ASSERT(self != NULL, return;);
1482
1483         iobase = self->io.sir_base;
1484
1485         /*
1486          * Receive all characters in Rx FIFO, unwrap and unstuff them.
1487          * async_unwrap_char will deliver all found frames
1488          */
1489         do {
1490                 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1491                                   inb(iobase + UART_RX));
1492
1493                 /* Make sure we don't stay here to long */
1494                 if (boguscount++ > 32) {
1495                         IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1496                         break;
1497                 }
1498         } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1499 }
1500
1501
1502 /*
1503  * Function smsc_ircc_interrupt (irq, dev_id, regs)
1504  *
1505  *    An interrupt from the chip has arrived. Time to do some work
1506  *
1507  */
1508 static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
1509 {
1510         struct net_device *dev = dev_id;
1511         struct smsc_ircc_cb *self = netdev_priv(dev);
1512         int iobase, iir, lcra, lsr;
1513         irqreturn_t ret = IRQ_NONE;
1514
1515         /* Serialise the interrupt handler in various CPUs, stop Tx path */
1516         spin_lock(&self->lock);
1517
1518         /* Check if we should use the SIR interrupt handler */
1519         if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1520                 ret = smsc_ircc_interrupt_sir(dev);
1521                 goto irq_ret_unlock;
1522         }
1523
1524         iobase = self->io.fir_base;
1525
1526         register_bank(iobase, 0);
1527         iir = inb(iobase + IRCC_IIR);
1528         if (iir == 0)
1529                 goto irq_ret_unlock;
1530         ret = IRQ_HANDLED;
1531
1532         /* Disable interrupts */
1533         outb(0, iobase + IRCC_IER);
1534         lcra = inb(iobase + IRCC_LCR_A);
1535         lsr = inb(iobase + IRCC_LSR);
1536
1537         IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1538
1539         if (iir & IRCC_IIR_EOM) {
1540                 if (self->io.direction == IO_RECV)
1541                         smsc_ircc_dma_receive_complete(self);
1542                 else
1543                         smsc_ircc_dma_xmit_complete(self);
1544
1545                 smsc_ircc_dma_receive(self);
1546         }
1547
1548         if (iir & IRCC_IIR_ACTIVE_FRAME) {
1549                 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1550         }
1551
1552         /* Enable interrupts again */
1553
1554         register_bank(iobase, 0);
1555         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1556
1557  irq_ret_unlock:
1558         spin_unlock(&self->lock);
1559
1560         return ret;
1561 }
1562
1563 /*
1564  * Function irport_interrupt_sir (irq, dev_id)
1565  *
1566  *    Interrupt handler for SIR modes
1567  */
1568 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1569 {
1570         struct smsc_ircc_cb *self = netdev_priv(dev);
1571         int boguscount = 0;
1572         int iobase;
1573         int iir, lsr;
1574
1575         /* Already locked comming here in smsc_ircc_interrupt() */
1576         /*spin_lock(&self->lock);*/
1577
1578         iobase = self->io.sir_base;
1579
1580         iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1581         if (iir == 0)
1582                 return IRQ_NONE;
1583         while (iir) {
1584                 /* Clear interrupt */
1585                 lsr = inb(iobase + UART_LSR);
1586
1587                 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1588                             __FUNCTION__, iir, lsr, iobase);
1589
1590                 switch (iir) {
1591                 case UART_IIR_RLSI:
1592                         IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1593                         break;
1594                 case UART_IIR_RDI:
1595                         /* Receive interrupt */
1596                         smsc_ircc_sir_receive(self);
1597                         break;
1598                 case UART_IIR_THRI:
1599                         if (lsr & UART_LSR_THRE)
1600                                 /* Transmitter ready for data */
1601                                 smsc_ircc_sir_write_wakeup(self);
1602                         break;
1603                 default:
1604                         IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1605                                    __FUNCTION__, iir);
1606                         break;
1607                 }
1608
1609                 /* Make sure we don't stay here to long */
1610                 if (boguscount++ > 100)
1611                         break;
1612
1613                 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1614         }
1615         /*spin_unlock(&self->lock);*/
1616         return IRQ_HANDLED;
1617 }
1618
1619
1620 #if 0 /* unused */
1621 /*
1622  * Function ircc_is_receiving (self)
1623  *
1624  *    Return TRUE is we are currently receiving a frame
1625  *
1626  */
1627 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1628 {
1629         int status = FALSE;
1630         /* int iobase; */
1631
1632         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1633
1634         IRDA_ASSERT(self != NULL, return FALSE;);
1635
1636         IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1637                    get_dma_residue(self->io.dma));
1638
1639         status = (self->rx_buff.state != OUTSIDE_FRAME);
1640
1641         return status;
1642 }
1643 #endif /* unused */
1644
1645 static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1646 {
1647         int error;
1648
1649         error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1650                             self->netdev->name, self->netdev);
1651         if (error)
1652                 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1653                            __FUNCTION__, self->io.irq, error);
1654
1655         return error;
1656 }
1657
1658 static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1659 {
1660         unsigned long flags;
1661
1662         spin_lock_irqsave(&self->lock, flags);
1663
1664         self->io.speed = 0;
1665         smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1666
1667         spin_unlock_irqrestore(&self->lock, flags);
1668 }
1669
1670 static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1671 {
1672         int iobase = self->io.fir_base;
1673         unsigned long flags;
1674
1675         spin_lock_irqsave(&self->lock, flags);
1676
1677         register_bank(iobase, 0);
1678         outb(0, iobase + IRCC_IER);
1679         outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1680         outb(0x00, iobase + IRCC_MASTER);
1681
1682         spin_unlock_irqrestore(&self->lock, flags);
1683 }
1684
1685
1686 /*
1687  * Function smsc_ircc_net_open (dev)
1688  *
1689  *    Start the device
1690  *
1691  */
1692 static int smsc_ircc_net_open(struct net_device *dev)
1693 {
1694         struct smsc_ircc_cb *self;
1695         char hwname[16];
1696
1697         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1698
1699         IRDA_ASSERT(dev != NULL, return -1;);
1700         self = netdev_priv(dev);
1701         IRDA_ASSERT(self != NULL, return 0;);
1702
1703         if (self->io.suspended) {
1704                 IRDA_DEBUG(0, "%s(), device is suspended\n", __FUNCTION__);
1705                 return -EAGAIN;
1706         }
1707
1708         if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1709                         (void *) dev)) {
1710                 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1711                            __FUNCTION__, self->io.irq);
1712                 return -EAGAIN;
1713         }
1714
1715         smsc_ircc_start_interrupts(self);
1716
1717         /* Give self a hardware name */
1718         /* It would be cool to offer the chip revision here - Jean II */
1719         sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1720
1721         /*
1722          * Open new IrLAP layer instance, now that everything should be
1723          * initialized properly
1724          */
1725         self->irlap = irlap_open(dev, &self->qos, hwname);
1726
1727         /*
1728          * Always allocate the DMA channel after the IRQ,
1729          * and clean up on failure.
1730          */
1731         if (request_dma(self->io.dma, dev->name)) {
1732                 smsc_ircc_net_close(dev);
1733
1734                 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1735                              __FUNCTION__, self->io.dma);
1736                 return -EAGAIN;
1737         }
1738
1739         netif_start_queue(dev);
1740
1741         return 0;
1742 }
1743
1744 /*
1745  * Function smsc_ircc_net_close (dev)
1746  *
1747  *    Stop the device
1748  *
1749  */
1750 static int smsc_ircc_net_close(struct net_device *dev)
1751 {
1752         struct smsc_ircc_cb *self;
1753
1754         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1755
1756         IRDA_ASSERT(dev != NULL, return -1;);
1757         self = netdev_priv(dev);
1758         IRDA_ASSERT(self != NULL, return 0;);
1759
1760         /* Stop device */
1761         netif_stop_queue(dev);
1762
1763         /* Stop and remove instance of IrLAP */
1764         if (self->irlap)
1765                 irlap_close(self->irlap);
1766         self->irlap = NULL;
1767
1768         smsc_ircc_stop_interrupts(self);
1769
1770         /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1771         if (!self->io.suspended)
1772                 free_irq(self->io.irq, dev);
1773
1774         disable_dma(self->io.dma);
1775         free_dma(self->io.dma);
1776
1777         return 0;
1778 }
1779
1780 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1781 {
1782         struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1783
1784         if (!self->io.suspended) {
1785                 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1786
1787                 rtnl_lock();
1788                 if (netif_running(self->netdev)) {
1789                         netif_device_detach(self->netdev);
1790                         smsc_ircc_stop_interrupts(self);
1791                         free_irq(self->io.irq, self->netdev);
1792                         disable_dma(self->io.dma);
1793                 }
1794                 self->io.suspended = 1;
1795                 rtnl_unlock();
1796         }
1797
1798         return 0;
1799 }
1800
1801 static int smsc_ircc_resume(struct platform_device *dev)
1802 {
1803         struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1804
1805         if (self->io.suspended) {
1806                 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1807
1808                 rtnl_lock();
1809                 smsc_ircc_init_chip(self);
1810                 if (netif_running(self->netdev)) {
1811                         if (smsc_ircc_request_irq(self)) {
1812                                 /*
1813                                  * Don't fail resume process, just kill this
1814                                  * network interface
1815                                  */
1816                                 unregister_netdevice(self->netdev);
1817                         } else {
1818                                 enable_dma(self->io.dma);
1819                                 smsc_ircc_start_interrupts(self);
1820                                 netif_device_attach(self->netdev);
1821                         }
1822                 }
1823                 self->io.suspended = 0;
1824                 rtnl_unlock();
1825         }
1826         return 0;
1827 }
1828
1829 /*
1830  * Function smsc_ircc_close (self)
1831  *
1832  *    Close driver instance
1833  *
1834  */
1835 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1836 {
1837         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1838
1839         IRDA_ASSERT(self != NULL, return -1;);
1840
1841         platform_device_unregister(self->pldev);
1842
1843         /* Remove netdevice */
1844         unregister_netdev(self->netdev);
1845
1846         smsc_ircc_stop_interrupts(self);
1847
1848         /* Release the PORTS that this driver is using */
1849         IRDA_DEBUG(0, "%s(), releasing 0x%03x\n",  __FUNCTION__,
1850                    self->io.fir_base);
1851
1852         release_region(self->io.fir_base, self->io.fir_ext);
1853
1854         IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1855                    self->io.sir_base);
1856
1857         release_region(self->io.sir_base, self->io.sir_ext);
1858
1859         if (self->tx_buff.head)
1860                 dma_free_coherent(NULL, self->tx_buff.truesize,
1861                                   self->tx_buff.head, self->tx_buff_dma);
1862
1863         if (self->rx_buff.head)
1864                 dma_free_coherent(NULL, self->rx_buff.truesize,
1865                                   self->rx_buff.head, self->rx_buff_dma);
1866
1867         free_netdev(self->netdev);
1868
1869         return 0;
1870 }
1871
1872 static void __exit smsc_ircc_cleanup(void)
1873 {
1874         int i;
1875
1876         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1877
1878         for (i = 0; i < 2; i++) {
1879                 if (dev_self[i])
1880                         smsc_ircc_close(dev_self[i]);
1881         }
1882
1883         if (pnp_driver_registered)
1884                 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1885
1886         platform_driver_unregister(&smsc_ircc_driver);
1887 }
1888
1889 /*
1890  *      Start SIR operations
1891  *
1892  * This function *must* be called with spinlock held, because it may
1893  * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1894  */
1895 void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1896 {
1897         struct net_device *dev;
1898         int fir_base, sir_base;
1899
1900         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1901
1902         IRDA_ASSERT(self != NULL, return;);
1903         dev = self->netdev;
1904         IRDA_ASSERT(dev != NULL, return;);
1905         dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1906
1907         fir_base = self->io.fir_base;
1908         sir_base = self->io.sir_base;
1909
1910         /* Reset everything */
1911         outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1912
1913         #if SMSC_IRCC2_C_SIR_STOP
1914         /*smsc_ircc_sir_stop(self);*/
1915         #endif
1916
1917         register_bank(fir_base, 1);
1918         outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1919
1920         /* Initialize UART */
1921         outb(UART_LCR_WLEN8, sir_base + UART_LCR);  /* Reset DLAB */
1922         outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1923
1924         /* Turn on interrups */
1925         outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1926
1927         IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1928
1929         outb(0x00, fir_base + IRCC_MASTER);
1930 }
1931
1932 #if SMSC_IRCC2_C_SIR_STOP
1933 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1934 {
1935         int iobase;
1936
1937         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1938         iobase = self->io.sir_base;
1939
1940         /* Reset UART */
1941         outb(0, iobase + UART_MCR);
1942
1943         /* Turn off interrupts */
1944         outb(0, iobase + UART_IER);
1945 }
1946 #endif
1947
1948 /*
1949  * Function smsc_sir_write_wakeup (self)
1950  *
1951  *    Called by the SIR interrupt handler when there's room for more data.
1952  *    If we have more packets to send, we send them here.
1953  *
1954  */
1955 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1956 {
1957         int actual = 0;
1958         int iobase;
1959         int fcr;
1960
1961         IRDA_ASSERT(self != NULL, return;);
1962
1963         IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1964
1965         iobase = self->io.sir_base;
1966
1967         /* Finished with frame?  */
1968         if (self->tx_buff.len > 0)  {
1969                 /* Write data left in transmit buffer */
1970                 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1971                                       self->tx_buff.data, self->tx_buff.len);
1972                 self->tx_buff.data += actual;
1973                 self->tx_buff.len  -= actual;
1974         } else {
1975
1976         /*if (self->tx_buff.len ==0)  {*/
1977
1978                 /*
1979                  *  Now serial buffer is almost free & we can start
1980                  *  transmission of another packet. But first we must check
1981                  *  if we need to change the speed of the hardware
1982                  */
1983                 if (self->new_speed) {
1984                         IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1985                                    __FUNCTION__, self->new_speed);
1986                         smsc_ircc_sir_wait_hw_transmitter_finish(self);
1987                         smsc_ircc_change_speed(self, self->new_speed);
1988                         self->new_speed = 0;
1989                 } else {
1990                         /* Tell network layer that we want more frames */
1991                         netif_wake_queue(self->netdev);
1992                 }
1993                 self->stats.tx_packets++;
1994
1995                 if (self->io.speed <= 115200) {
1996                         /*
1997                          * Reset Rx FIFO to make sure that all reflected transmit data
1998                          * is discarded. This is needed for half duplex operation
1999                          */
2000                         fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2001                         fcr |= self->io.speed < 38400 ?
2002                                         UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
2003
2004                         outb(fcr, iobase + UART_FCR);
2005
2006                         /* Turn on receive interrupts */
2007                         outb(UART_IER_RDI, iobase + UART_IER);
2008                 }
2009         }
2010 }
2011
2012 /*
2013  * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2014  *
2015  *    Fill Tx FIFO with transmit data
2016  *
2017  */
2018 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2019 {
2020         int actual = 0;
2021
2022         /* Tx FIFO should be empty! */
2023         if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
2024                 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
2025                 return 0;
2026         }
2027
2028         /* Fill FIFO with current frame */
2029         while (fifo_size-- > 0 && actual < len) {
2030                 /* Transmit next byte */
2031                 outb(buf[actual], iobase + UART_TX);
2032                 actual++;
2033         }
2034         return actual;
2035 }
2036
2037 /*
2038  * Function smsc_ircc_is_receiving (self)
2039  *
2040  *    Returns true is we are currently receiving data
2041  *
2042  */
2043 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2044 {
2045         return (self->rx_buff.state != OUTSIDE_FRAME);
2046 }
2047
2048
2049 /*
2050  * Function smsc_ircc_probe_transceiver(self)
2051  *
2052  *    Tries to find the used Transceiver
2053  *
2054  */
2055 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2056 {
2057         unsigned int    i;
2058
2059         IRDA_ASSERT(self != NULL, return;);
2060
2061         for (i = 0; smsc_transceivers[i].name != NULL; i++)
2062                 if (smsc_transceivers[i].probe(self->io.fir_base)) {
2063                         IRDA_MESSAGE(" %s transceiver found\n",
2064                                      smsc_transceivers[i].name);
2065                         self->transceiver= i + 1;
2066                         return;
2067                 }
2068
2069         IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2070                      smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
2071
2072         self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
2073 }
2074
2075
2076 /*
2077  * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2078  *
2079  *    Set the transceiver according to the speed
2080  *
2081  */
2082 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2083 {
2084         unsigned int trx;
2085
2086         trx = self->transceiver;
2087         if (trx > 0)
2088                 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
2089 }
2090
2091 /*
2092  * Function smsc_ircc_wait_hw_transmitter_finish ()
2093  *
2094  *    Wait for the real end of HW transmission
2095  *
2096  * The UART is a strict FIFO, and we get called only when we have finished
2097  * pushing data to the FIFO, so the maximum amount of time we must wait
2098  * is only for the FIFO to drain out.
2099  *
2100  * We use a simple calibrated loop. We may need to adjust the loop
2101  * delay (udelay) to balance I/O traffic and latency. And we also need to
2102  * adjust the maximum timeout.
2103  * It would probably be better to wait for the proper interrupt,
2104  * but it doesn't seem to be available.
2105  *
2106  * We can't use jiffies or kernel timers because :
2107  * 1) We are called from the interrupt handler, which disable softirqs,
2108  * so jiffies won't be increased
2109  * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2110  * want to wait that long to detect stuck hardware.
2111  * Jean II
2112  */
2113
2114 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2115 {
2116         int iobase = self->io.sir_base;
2117         int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
2118
2119         /* Calibrated busy loop */
2120         while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
2121                 udelay(1);
2122
2123         if (count == 0)
2124                 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
2125 }
2126
2127
2128 /* PROBING
2129  *
2130  * REVISIT we can be told about the device by PNP, and should use that info
2131  * instead of probing hardware and creating a platform_device ...
2132  */
2133
2134 static int __init smsc_ircc_look_for_chips(void)
2135 {
2136         struct smsc_chip_address *address;
2137         char *type;
2138         unsigned int cfg_base, found;
2139
2140         found = 0;
2141         address = possible_addresses;
2142
2143         while (address->cfg_base) {
2144                 cfg_base = address->cfg_base;
2145
2146                 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
2147
2148                 if (address->type & SMSCSIO_TYPE_FDC) {
2149                         type = "FDC";
2150                         if (address->type & SMSCSIO_TYPE_FLAT)
2151                                 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2152                                         found++;
2153
2154                         if (address->type & SMSCSIO_TYPE_PAGED)
2155                                 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2156                                         found++;
2157                 }
2158                 if (address->type & SMSCSIO_TYPE_LPC) {
2159                         type = "LPC";
2160                         if (address->type & SMSCSIO_TYPE_FLAT)
2161                                 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2162                                         found++;
2163
2164                         if (address->type & SMSCSIO_TYPE_PAGED)
2165                                 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2166                                         found++;
2167                 }
2168                 address++;
2169         }
2170         return found;
2171 }
2172
2173 /*
2174  * Function smsc_superio_flat (chip, base, type)
2175  *
2176  *    Try to get configuration of a smc SuperIO chip with flat register model
2177  *
2178  */
2179 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2180 {
2181         unsigned short firbase, sirbase;
2182         u8 mode, dma, irq;
2183         int ret = -ENODEV;
2184
2185         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2186
2187         if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2188                 return ret;
2189
2190         outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2191         mode = inb(cfgbase + 1);
2192
2193         /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
2194
2195         if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2196                 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2197
2198         outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2199         sirbase = inb(cfgbase + 1) << 2;
2200
2201         /* FIR iobase */
2202         outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2203         firbase = inb(cfgbase + 1) << 3;
2204
2205         /* DMA */
2206         outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2207         dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2208
2209         /* IRQ */
2210         outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2211         irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2212
2213         IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2214
2215         if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2216                 ret = 0;
2217
2218         /* Exit configuration */
2219         outb(SMSCSIO_CFGEXITKEY, cfgbase);
2220
2221         return ret;
2222 }
2223
2224 /*
2225  * Function smsc_superio_paged (chip, base, type)
2226  *
2227  *    Try  to get configuration of a smc SuperIO chip with paged register model
2228  *
2229  */
2230 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2231 {
2232         unsigned short fir_io, sir_io;
2233         int ret = -ENODEV;
2234
2235         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2236
2237         if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2238                 return ret;
2239
2240         /* Select logical device (UART2) */
2241         outb(0x07, cfg_base);
2242         outb(0x05, cfg_base + 1);
2243
2244         /* SIR iobase */
2245         outb(0x60, cfg_base);
2246         sir_io = inb(cfg_base + 1) << 8;
2247         outb(0x61, cfg_base);
2248         sir_io |= inb(cfg_base + 1);
2249
2250         /* Read FIR base */
2251         outb(0x62, cfg_base);
2252         fir_io = inb(cfg_base + 1) << 8;
2253         outb(0x63, cfg_base);
2254         fir_io |= inb(cfg_base + 1);
2255         outb(0x2b, cfg_base); /* ??? */
2256
2257         if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2258                 ret = 0;
2259
2260         /* Exit configuration */
2261         outb(SMSCSIO_CFGEXITKEY, cfg_base);
2262
2263         return ret;
2264 }
2265
2266
2267 static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2268 {
2269         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2270
2271         outb(reg, cfg_base);
2272         return inb(cfg_base) != reg ? -1 : 0;
2273 }
2274
2275 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2276 {
2277         u8 devid, xdevid, rev;
2278
2279         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2280
2281         /* Leave configuration */
2282
2283         outb(SMSCSIO_CFGEXITKEY, cfg_base);
2284
2285         if (inb(cfg_base) == SMSCSIO_CFGEXITKEY)        /* not a smc superio chip */
2286                 return NULL;
2287
2288         outb(reg, cfg_base);
2289
2290         xdevid = inb(cfg_base + 1);
2291
2292         /* Enter configuration */
2293
2294         outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2295
2296         #if 0
2297         if (smsc_access(cfg_base,0x55)) /* send second key and check */
2298                 return NULL;
2299         #endif
2300
2301         /* probe device ID */
2302
2303         if (smsc_access(cfg_base, reg))
2304                 return NULL;
2305
2306         devid = inb(cfg_base + 1);
2307
2308         if (devid == 0 || devid == 0xff)        /* typical values for unused port */
2309                 return NULL;
2310
2311         /* probe revision ID */
2312
2313         if (smsc_access(cfg_base, reg + 1))
2314                 return NULL;
2315
2316         rev = inb(cfg_base + 1);
2317
2318         if (rev >= 128)                 /* i think this will make no sense */
2319                 return NULL;
2320
2321         if (devid == xdevid)            /* protection against false positives */
2322                 return NULL;
2323
2324         /* Check for expected device ID; are there others? */
2325
2326         while (chip->devid != devid) {
2327
2328                 chip++;
2329
2330                 if (chip->name == NULL)
2331                         return NULL;
2332         }
2333
2334         IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2335                      devid, rev, cfg_base, type, chip->name);
2336
2337         if (chip->rev > rev) {
2338                 IRDA_MESSAGE("Revision higher than expected\n");
2339                 return NULL;
2340         }
2341
2342         if (chip->flags & NoIRDA)
2343                 IRDA_MESSAGE("chipset does not support IRDA\n");
2344
2345         return chip;
2346 }
2347
2348 static int __init smsc_superio_fdc(unsigned short cfg_base)
2349 {
2350         int ret = -1;
2351
2352         if (!request_region(cfg_base, 2, driver_name)) {
2353                 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2354                              __FUNCTION__, cfg_base);
2355         } else {
2356                 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2357                     !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2358                         ret =  0;
2359
2360                 release_region(cfg_base, 2);
2361         }
2362
2363         return ret;
2364 }
2365
2366 static int __init smsc_superio_lpc(unsigned short cfg_base)
2367 {
2368         int ret = -1;
2369
2370         if (!request_region(cfg_base, 2, driver_name)) {
2371                 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2372                              __FUNCTION__, cfg_base);
2373         } else {
2374                 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2375                     !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2376                         ret = 0;
2377
2378                 release_region(cfg_base, 2);
2379         }
2380         return ret;
2381 }
2382
2383 /*
2384  * Look for some specific subsystem setups that need
2385  * pre-configuration not properly done by the BIOS (especially laptops)
2386  * This code is based in part on smcinit.c, tosh1800-smcinit.c
2387  * and tosh2450-smcinit.c. The table lists the device entries
2388  * for ISA bridges with an LPC (Low Pin Count) controller which
2389  * handles the communication with the SMSC device. After the LPC
2390  * controller is initialized through PCI, the SMSC device is initialized
2391  * through a dedicated port in the ISA port-mapped I/O area, this latter
2392  * area is used to configure the SMSC device with default
2393  * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2394  * used different sets of parameters and different control port
2395  * addresses making a subsystem device table necessary.
2396  */
2397 #ifdef CONFIG_PCI
2398 #define PCIID_VENDOR_INTEL 0x8086
2399 #define PCIID_VENDOR_ALI 0x10b9
2400 static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2401         /*
2402          * Subsystems needing entries:
2403          * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2404          * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2405          * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2406          */
2407         {
2408                 /* Guessed entry */
2409                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2410                 .device = 0x24cc,
2411                 .subvendor = 0x103c,
2412                 .subdevice = 0x08bc,
2413                 .sir_io = 0x02f8,
2414                 .fir_io = 0x0130,
2415                 .fir_irq = 0x05,
2416                 .fir_dma = 0x03,
2417                 .cfg_base = 0x004e,
2418                 .preconfigure = preconfigure_through_82801,
2419                 .name = "HP nx5000 family",
2420         },
2421         {
2422                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2423                 .device = 0x24cc,
2424                 .subvendor = 0x103c,
2425                 .subdevice = 0x088c,
2426                 /* Quite certain these are the same for nc8000 as for nc6000 */
2427                 .sir_io = 0x02f8,
2428                 .fir_io = 0x0130,
2429                 .fir_irq = 0x05,
2430                 .fir_dma = 0x03,
2431                 .cfg_base = 0x004e,
2432                 .preconfigure = preconfigure_through_82801,
2433                 .name = "HP nc8000 family",
2434         },
2435         {
2436                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2437                 .device = 0x24cc,
2438                 .subvendor = 0x103c,
2439                 .subdevice = 0x0890,
2440                 .sir_io = 0x02f8,
2441                 .fir_io = 0x0130,
2442                 .fir_irq = 0x05,
2443                 .fir_dma = 0x03,
2444                 .cfg_base = 0x004e,
2445                 .preconfigure = preconfigure_through_82801,
2446                 .name = "HP nc6000 family",
2447         },
2448         {
2449                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2450                 .device = 0x24cc,
2451                 .subvendor = 0x0e11,
2452                 .subdevice = 0x0860,
2453                 /* I assume these are the same for x1000 as for the others */
2454                 .sir_io = 0x02e8,
2455                 .fir_io = 0x02f8,
2456                 .fir_irq = 0x07,
2457                 .fir_dma = 0x03,
2458                 .cfg_base = 0x002e,
2459                 .preconfigure = preconfigure_through_82801,
2460                 .name = "Compaq x1000 family",
2461         },
2462         {
2463                 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2464                 .vendor = PCIID_VENDOR_INTEL,
2465                 .device = 0x24c0,
2466                 .subvendor = 0x1179,
2467                 .subdevice = 0xffff, /* 0xffff is "any" */
2468                 .sir_io = 0x03f8,
2469                 .fir_io = 0x0130,
2470                 .fir_irq = 0x07,
2471                 .fir_dma = 0x01,
2472                 .cfg_base = 0x002e,
2473                 .preconfigure = preconfigure_through_82801,
2474                 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2475         },
2476         {
2477                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */
2478                 .device = 0x248c,
2479                 .subvendor = 0x1179,
2480                 .subdevice = 0xffff, /* 0xffff is "any" */
2481                 .sir_io = 0x03f8,
2482                 .fir_io = 0x0130,
2483                 .fir_irq = 0x03,
2484                 .fir_dma = 0x03,
2485                 .cfg_base = 0x002e,
2486                 .preconfigure = preconfigure_through_82801,
2487                 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
2488         },
2489         {
2490                 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2491                 .vendor = PCIID_VENDOR_INTEL,
2492                 .device = 0x24cc,
2493                 .subvendor = 0x1179,
2494                 .subdevice = 0xffff, /* 0xffff is "any" */
2495                 .sir_io = 0x03f8,
2496                 .fir_io = 0x0130,
2497                 .fir_irq = 0x03,
2498                 .fir_dma = 0x03,
2499                 .cfg_base = 0x002e,
2500                 .preconfigure = preconfigure_through_82801,
2501                 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2502         },
2503         {
2504                 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2505                 .vendor = PCIID_VENDOR_ALI,
2506                 .device = 0x1533,
2507                 .subvendor = 0x1179,
2508                 .subdevice = 0xffff, /* 0xffff is "any" */
2509                 .sir_io = 0x02e8,
2510                 .fir_io = 0x02f8,
2511                 .fir_irq = 0x07,
2512                 .fir_dma = 0x03,
2513                 .cfg_base = 0x002e,
2514                 .preconfigure = preconfigure_through_ali,
2515                 .name = "Toshiba laptop with ALi ISA bridge",
2516         },
2517         { } // Terminator
2518 };
2519
2520
2521 /*
2522  * This sets up the basic SMSC parameters
2523  * (FIR port, SIR port, FIR DMA, FIR IRQ)
2524  * through the chip configuration port.
2525  */
2526 static int __init preconfigure_smsc_chip(struct
2527                                          smsc_ircc_subsystem_configuration
2528                                          *conf)
2529 {
2530         unsigned short iobase = conf->cfg_base;
2531         unsigned char tmpbyte;
2532
2533         outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2534         outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2535         tmpbyte = inb(iobase +1); // Read device ID
2536         IRDA_DEBUG(0,
2537                    "Detected Chip id: 0x%02x, setting up registers...\n",
2538                    tmpbyte);
2539
2540         /* Disable UART1 and set up SIR I/O port */
2541         outb(0x24, iobase);  // select CR24 - UART1 base addr
2542         outb(0x00, iobase + 1); // disable UART1
2543         outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase);  // select CR25 - UART2 base addr
2544         outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2545         tmpbyte = inb(iobase + 1);
2546         if (tmpbyte != (conf->sir_io >> 2) ) {
2547                 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2548                 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
2549                 return -ENXIO;
2550         }
2551
2552         /* Set up FIR IRQ channel for UART2 */
2553         outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2554         tmpbyte = inb(iobase + 1);
2555         tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2556         tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2557         outb(tmpbyte, iobase + 1);
2558         tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2559         if (tmpbyte != conf->fir_irq) {
2560                 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2561                 return -ENXIO;
2562         }
2563
2564         /* Set up FIR I/O port */
2565         outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase);  // CR2B - SCE (FIR) base addr
2566         outb((conf->fir_io >> 3), iobase + 1);
2567         tmpbyte = inb(iobase + 1);
2568         if (tmpbyte != (conf->fir_io >> 3) ) {
2569                 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2570                 return -ENXIO;
2571         }
2572
2573         /* Set up FIR DMA channel */
2574         outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase);  // CR2C - SCE (FIR) DMA select
2575         outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2576         tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2577         if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2578                 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2579                 return -ENXIO;
2580         }
2581
2582         outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase);  // CR0C - UART mode
2583         tmpbyte = inb(iobase + 1);
2584         tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2585                 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2586         outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2587
2588         outb(LPC47N227_APMBOOTDRIVE_REG, iobase);  // CR07 - Auto Pwr Mgt/boot drive sel
2589         tmpbyte = inb(iobase + 1);
2590         outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2591
2592         /* This one was not part of tosh1800 */
2593         outb(0x0a, iobase);  // CR0a - ecp fifo / ir mux
2594         tmpbyte = inb(iobase + 1);
2595         outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2596
2597         outb(LPC47N227_UART12POWER_REG, iobase);  // CR02 - UART 1,2 power
2598         tmpbyte = inb(iobase + 1);
2599         outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2600
2601         outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase);  // CR00 - FDC Power/valid config cycle
2602         tmpbyte = inb(iobase + 1);
2603         outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2604
2605         outb(LPC47N227_CFGEXITKEY, iobase);  // Exit configuration
2606
2607         return 0;
2608 }
2609
2610 /* 82801CAM generic registers */
2611 #define VID 0x00
2612 #define DID 0x02
2613 #define PIRQ_A_D_ROUT 0x60
2614 #define SIRQ_CNTL 0x64
2615 #define PIRQ_E_H_ROUT 0x68
2616 #define PCI_DMA_C 0x90
2617 /* LPC-specific registers */
2618 #define COM_DEC 0xe0
2619 #define GEN1_DEC 0xe4
2620 #define LPC_EN 0xe6
2621 #define GEN2_DEC 0xec
2622 /*
2623  * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2624  * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2625  * They all work the same way!
2626  */
2627 static int __init preconfigure_through_82801(struct pci_dev *dev,
2628                                              struct
2629                                              smsc_ircc_subsystem_configuration
2630                                              *conf)
2631 {
2632         unsigned short tmpword;
2633         unsigned char tmpbyte;
2634
2635         IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2636         /*
2637          * Select the range for the COMA COM port (SIR)
2638          * Register COM_DEC:
2639          * Bit 7: reserved
2640          * Bit 6-4, COMB decode range
2641          * Bit 3: reserved
2642          * Bit 2-0, COMA decode range
2643          *
2644          * Decode ranges:
2645          *   000 = 0x3f8-0x3ff (COM1)
2646          *   001 = 0x2f8-0x2ff (COM2)
2647          *   010 = 0x220-0x227
2648          *   011 = 0x228-0x22f
2649          *   100 = 0x238-0x23f
2650          *   101 = 0x2e8-0x2ef (COM4)
2651          *   110 = 0x338-0x33f
2652          *   111 = 0x3e8-0x3ef (COM3)
2653          */
2654         pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2655         tmpbyte &= 0xf8; /* mask COMA bits */
2656         switch(conf->sir_io) {
2657         case 0x3f8:
2658                 tmpbyte |= 0x00;
2659                 break;
2660         case 0x2f8:
2661                 tmpbyte |= 0x01;
2662                 break;
2663         case 0x220:
2664                 tmpbyte |= 0x02;
2665                 break;
2666         case 0x228:
2667                 tmpbyte |= 0x03;
2668                 break;
2669         case 0x238:
2670                 tmpbyte |= 0x04;
2671                 break;
2672         case 0x2e8:
2673                 tmpbyte |= 0x05;
2674                 break;
2675         case 0x338:
2676                 tmpbyte |= 0x06;
2677                 break;
2678         case 0x3e8:
2679                 tmpbyte |= 0x07;
2680                 break;
2681         default:
2682                 tmpbyte |= 0x01; /* COM2 default */
2683         }
2684         IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2685         pci_write_config_byte(dev, COM_DEC, tmpbyte);
2686
2687         /* Enable Low Pin Count interface */
2688         pci_read_config_word(dev, LPC_EN, &tmpword);
2689         /* These seem to be set up at all times,
2690          * just make sure it is properly set.
2691          */
2692         switch(conf->cfg_base) {
2693         case 0x04e:
2694                 tmpword |= 0x2000;
2695                 break;
2696         case 0x02e:
2697                 tmpword |= 0x1000;
2698                 break;
2699         case 0x062:
2700                 tmpword |= 0x0800;
2701                 break;
2702         case 0x060:
2703                 tmpword |= 0x0400;
2704                 break;
2705         default:
2706                 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2707                              conf->cfg_base);
2708                 break;
2709         }
2710         tmpword &= 0xfffd; /* disable LPC COMB */
2711         tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2712         IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
2713         pci_write_config_word(dev, LPC_EN, tmpword);
2714
2715         /*
2716          * Configure LPC DMA channel
2717          * PCI_DMA_C bits:
2718          * Bit 15-14: DMA channel 7 select
2719          * Bit 13-12: DMA channel 6 select
2720          * Bit 11-10: DMA channel 5 select
2721          * Bit 9-8:   Reserved
2722          * Bit 7-6:   DMA channel 3 select
2723          * Bit 5-4:   DMA channel 2 select
2724          * Bit 3-2:   DMA channel 1 select
2725          * Bit 1-0:   DMA channel 0 select
2726          *  00 = Reserved value
2727          *  01 = PC/PCI DMA
2728          *  10 = Reserved value
2729          *  11 = LPC I/F DMA
2730          */
2731         pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2732         switch(conf->fir_dma) {
2733         case 0x07:
2734                 tmpword |= 0xc000;
2735                 break;
2736         case 0x06:
2737                 tmpword |= 0x3000;
2738                 break;
2739         case 0x05:
2740                 tmpword |= 0x0c00;
2741                 break;
2742         case 0x03:
2743                 tmpword |= 0x00c0;
2744                 break;
2745         case 0x02:
2746                 tmpword |= 0x0030;
2747                 break;
2748         case 0x01:
2749                 tmpword |= 0x000c;
2750                 break;
2751         case 0x00:
2752                 tmpword |= 0x0003;
2753                 break;
2754         default:
2755                 break; /* do not change settings */
2756         }
2757         IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2758         pci_write_config_word(dev, PCI_DMA_C, tmpword);
2759
2760         /*
2761          * GEN2_DEC bits:
2762          * Bit 15-4: Generic I/O range
2763          * Bit 3-1: reserved (read as 0)
2764          * Bit 0: enable GEN2 range on LPC I/F
2765          */
2766         tmpword = conf->fir_io & 0xfff8;
2767         tmpword |= 0x0001;
2768         IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2769         pci_write_config_word(dev, GEN2_DEC, tmpword);
2770
2771         /* Pre-configure chip */
2772         return preconfigure_smsc_chip(conf);
2773 }
2774
2775 /*
2776  * Pre-configure a certain port on the ALi 1533 bridge.
2777  * This is based on reverse-engineering since ALi does not
2778  * provide any data sheet for the 1533 chip.
2779  */
2780 static void __init preconfigure_ali_port(struct pci_dev *dev,
2781                                          unsigned short port)
2782 {
2783         unsigned char reg;
2784         /* These bits obviously control the different ports */
2785         unsigned char mask;
2786         unsigned char tmpbyte;
2787
2788         switch(port) {
2789         case 0x0130:
2790         case 0x0178:
2791                 reg = 0xb0;
2792                 mask = 0x80;
2793                 break;
2794         case 0x03f8:
2795                 reg = 0xb4;
2796                 mask = 0x80;
2797                 break;
2798         case 0x02f8:
2799                 reg = 0xb4;
2800                 mask = 0x30;
2801                 break;
2802         case 0x02e8:
2803                 reg = 0xb4;
2804                 mask = 0x08;
2805                 break;
2806         default:
2807                 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2808                 return;
2809         }
2810
2811         pci_read_config_byte(dev, reg, &tmpbyte);
2812         /* Turn on the right bits */
2813         tmpbyte |= mask;
2814         pci_write_config_byte(dev, reg, tmpbyte);
2815         IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2816         return;
2817 }
2818
2819 static int __init preconfigure_through_ali(struct pci_dev *dev,
2820                                            struct
2821                                            smsc_ircc_subsystem_configuration
2822                                            *conf)
2823 {
2824         /* Configure the two ports on the ALi 1533 */
2825         preconfigure_ali_port(dev, conf->sir_io);
2826         preconfigure_ali_port(dev, conf->fir_io);
2827
2828         /* Pre-configure chip */
2829         return preconfigure_smsc_chip(conf);
2830 }
2831
2832 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2833                                                     unsigned short ircc_fir,
2834                                                     unsigned short ircc_sir,
2835                                                     unsigned char ircc_dma,
2836                                                     unsigned char ircc_irq)
2837 {
2838         struct pci_dev *dev = NULL;
2839         unsigned short ss_vendor = 0x0000;
2840         unsigned short ss_device = 0x0000;
2841         int ret = 0;
2842
2843         dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2844
2845         while (dev != NULL) {
2846                 struct smsc_ircc_subsystem_configuration *conf;
2847
2848                 /*
2849                  * Cache the subsystem vendor/device:
2850                  * some manufacturers fail to set this for all components,
2851                  * so we save it in case there is just 0x0000 0x0000 on the
2852                  * device we want to check.
2853                  */
2854                 if (dev->subsystem_vendor != 0x0000U) {
2855                         ss_vendor = dev->subsystem_vendor;
2856                         ss_device = dev->subsystem_device;
2857                 }
2858                 conf = subsystem_configurations;
2859                 for( ; conf->subvendor; conf++) {
2860                         if(conf->vendor == dev->vendor &&
2861                            conf->device == dev->device &&
2862                            conf->subvendor == ss_vendor &&
2863                            /* Sometimes these are cached values */
2864                            (conf->subdevice == ss_device ||
2865                             conf->subdevice == 0xffff)) {
2866                                 struct smsc_ircc_subsystem_configuration
2867                                         tmpconf;
2868
2869                                 memcpy(&tmpconf, conf,
2870                                        sizeof(struct smsc_ircc_subsystem_configuration));
2871
2872                                 /*
2873                                  * Override the default values with anything
2874                                  * passed in as parameter
2875                                  */
2876                                 if (ircc_cfg != 0)
2877                                         tmpconf.cfg_base = ircc_cfg;
2878                                 if (ircc_fir != 0)
2879                                         tmpconf.fir_io = ircc_fir;
2880                                 if (ircc_sir != 0)
2881                                         tmpconf.sir_io = ircc_sir;
2882                                 if (ircc_dma != DMA_INVAL)
2883                                         tmpconf.fir_dma = ircc_dma;
2884                                 if (ircc_irq != IRQ_INVAL)
2885                                         tmpconf.fir_irq = ircc_irq;
2886
2887                                 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2888                                 if (conf->preconfigure)
2889                                         ret = conf->preconfigure(dev, &tmpconf);
2890                                 else
2891                                         ret = -ENODEV;
2892                         }
2893                 }
2894                 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2895         }
2896
2897         return ret;
2898 }
2899 #endif // CONFIG_PCI
2900
2901 /************************************************
2902  *
2903  * Transceivers specific functions
2904  *
2905  ************************************************/
2906
2907
2908 /*
2909  * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2910  *
2911  *    Program transceiver through smsc-ircc ATC circuitry
2912  *
2913  */
2914
2915 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2916 {
2917         unsigned long jiffies_now, jiffies_timeout;
2918         u8 val;
2919
2920         jiffies_now = jiffies;
2921         jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2922
2923         /* ATC */
2924         register_bank(fir_base, 4);
2925         outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2926              fir_base + IRCC_ATC);
2927
2928         while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2929                 !time_after(jiffies, jiffies_timeout))
2930                 /* empty */;
2931
2932         if (val)
2933                 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
2934                              inb(fir_base + IRCC_ATC));
2935 }
2936
2937 /*
2938  * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2939  *
2940  *    Probe transceiver smsc-ircc ATC circuitry
2941  *
2942  */
2943
2944 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2945 {
2946         return 0;
2947 }
2948
2949 /*
2950  * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2951  *
2952  *    Set transceiver
2953  *
2954  */
2955
2956 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2957 {
2958         u8 fast_mode;
2959
2960         switch (speed) {
2961         default:
2962         case 576000 :
2963                 fast_mode = 0;
2964                 break;
2965         case 1152000 :
2966         case 4000000 :
2967                 fast_mode = IRCC_LCR_A_FAST;
2968                 break;
2969         }
2970         register_bank(fir_base, 0);
2971         outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2972 }
2973
2974 /*
2975  * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2976  *
2977  *    Probe transceiver
2978  *
2979  */
2980
2981 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2982 {
2983         return 0;
2984 }
2985
2986 /*
2987  * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2988  *
2989  *    Set transceiver
2990  *
2991  */
2992
2993 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2994 {
2995         u8 fast_mode;
2996
2997         switch (speed) {
2998         default:
2999         case 576000 :
3000                 fast_mode = 0;
3001                 break;
3002         case 1152000 :
3003         case 4000000 :
3004                 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3005                 break;
3006
3007         }
3008         /* This causes an interrupt */
3009         register_bank(fir_base, 0);
3010         outb((inb(fir_base + IRCC_LCR_A) &  0xbf) | fast_mode, fir_base + IRCC_LCR_A);
3011 }
3012
3013 /*
3014  * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3015  *
3016  *    Probe transceiver
3017  *
3018  */
3019
3020 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3021 {
3022         return 0;
3023 }
3024
3025
3026 module_init(smsc_ircc_init);
3027 module_exit(smsc_ircc_cleanup);