git.oblomov.eu Git - linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43 #include <net/ip.h>
  44
  45 #include <asm/system.h>
  46 #include <asm/io.h>
  47 #include <asm/byteorder.h>
  48 #include <asm/uaccess.h>
  49
  50 #ifdef CONFIG_SPARC
  51 #include <asm/idprom.h>
  52 #include <asm/prom.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #define TG3_TSO_SUPPORT 1
  62
  63 #include "tg3.h"
  64
  65 #define DRV_MODULE_NAME         "tg3"
  66 #define PFX DRV_MODULE_NAME     ": "
  67 #define DRV_MODULE_VERSION      "3.91"
  68 #define DRV_MODULE_RELDATE      "April 18, 2008"
  69
  70 #define TG3_DEF_MAC_MODE        0
  71 #define TG3_DEF_RX_MODE         0
  72 #define TG3_DEF_TX_MODE         0
  73 #define TG3_DEF_MSG_ENABLE        \
  74         (NETIF_MSG_DRV          | \
  75          NETIF_MSG_PROBE        | \
  76          NETIF_MSG_LINK         | \
  77          NETIF_MSG_TIMER        | \
  78          NETIF_MSG_IFDOWN       | \
  79          NETIF_MSG_IFUP         | \
  80          NETIF_MSG_RX_ERR       | \
  81          NETIF_MSG_TX_ERR)
  82
  83 /* length of time before we decide the hardware is borked,
  84  * and dev->tx_timeout() should be called to fix the problem
  85  */
  86 #define TG3_TX_TIMEOUT                  (5 * HZ)
  87
  88 /* hardware minimum and maximum for a single frame's data payload */
  89 #define TG3_MIN_MTU                     60
  90 #define TG3_MAX_MTU(tp) \
  91         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  92
  93 /* These numbers seem to be hard coded in the NIC firmware somehow.
  94  * You can't change the ring sizes, but you can change where you place
  95  * them in the NIC onboard memory.
  96  */
  97 #define TG3_RX_RING_SIZE                512
  98 #define TG3_DEF_RX_RING_PENDING         200
  99 #define TG3_RX_JUMBO_RING_SIZE          256
 100 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 101
 102 /* Do not place this n-ring entries value into the tp struct itself,
 103  * we really want to expose these constants to GCC so that modulo et
 104  * al.  operations are done with shifts and masks instead of with
 105  * hw multiply/modulo instructions.  Another solution would be to
 106  * replace things like '% foo' with '& (foo - 1)'.
 107  */
 108 #define TG3_RX_RCB_RING_SIZE(tp)        \
 109         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 110
 111 #define TG3_TX_RING_SIZE                512
 112 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 113
 114 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 115                                  TG3_RX_RING_SIZE)
 116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_JUMBO_RING_SIZE)
 118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 119                                    TG3_RX_RCB_RING_SIZE(tp))
 120 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 121                                  TG3_TX_RING_SIZE)
 122 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 123
 124 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 125 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 126
 127 /* minimum number of free TX descriptors required to wake up TX process */
 128 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 129
 130 /* number of ETHTOOL_GSTATS u64's */
 131 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 132
 133 #define TG3_NUM_TEST            6
 134
 135 static char version[] __devinitdata =
 136         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 137
 138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_MODULE_VERSION);
 142
 143 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 144 module_param(tg3_debug, int, 0);
 145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 146
 147 static struct pci_device_id tg3_pci_tbl[] = {
 148         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 213         {}
 214 };
 215
 216 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 217
 218 static const struct {
 219         const char string[ETH_GSTRING_LEN];
 220 } ethtool_stats_keys[TG3_NUM_STATS] = {
 221         { "rx_octets" },
 222         { "rx_fragments" },
 223         { "rx_ucast_packets" },
 224         { "rx_mcast_packets" },
 225         { "rx_bcast_packets" },
 226         { "rx_fcs_errors" },
 227         { "rx_align_errors" },
 228         { "rx_xon_pause_rcvd" },
 229         { "rx_xoff_pause_rcvd" },
 230         { "rx_mac_ctrl_rcvd" },
 231         { "rx_xoff_entered" },
 232         { "rx_frame_too_long_errors" },
 233         { "rx_jabbers" },
 234         { "rx_undersize_packets" },
 235         { "rx_in_length_errors" },
 236         { "rx_out_length_errors" },
 237         { "rx_64_or_less_octet_packets" },
 238         { "rx_65_to_127_octet_packets" },
 239         { "rx_128_to_255_octet_packets" },
 240         { "rx_256_to_511_octet_packets" },
 241         { "rx_512_to_1023_octet_packets" },
 242         { "rx_1024_to_1522_octet_packets" },
 243         { "rx_1523_to_2047_octet_packets" },
 244         { "rx_2048_to_4095_octet_packets" },
 245         { "rx_4096_to_8191_octet_packets" },
 246         { "rx_8192_to_9022_octet_packets" },
 247
 248         { "tx_octets" },
 249         { "tx_collisions" },
 250
 251         { "tx_xon_sent" },
 252         { "tx_xoff_sent" },
 253         { "tx_flow_control" },
 254         { "tx_mac_errors" },
 255         { "tx_single_collisions" },
 256         { "tx_mult_collisions" },
 257         { "tx_deferred" },
 258         { "tx_excessive_collisions" },
 259         { "tx_late_collisions" },
 260         { "tx_collide_2times" },
 261         { "tx_collide_3times" },
 262         { "tx_collide_4times" },
 263         { "tx_collide_5times" },
 264         { "tx_collide_6times" },
 265         { "tx_collide_7times" },
 266         { "tx_collide_8times" },
 267         { "tx_collide_9times" },
 268         { "tx_collide_10times" },
 269         { "tx_collide_11times" },
 270         { "tx_collide_12times" },
 271         { "tx_collide_13times" },
 272         { "tx_collide_14times" },
 273         { "tx_collide_15times" },
 274         { "tx_ucast_packets" },
 275         { "tx_mcast_packets" },
 276         { "tx_bcast_packets" },
 277         { "tx_carrier_sense_errors" },
 278         { "tx_discards" },
 279         { "tx_errors" },
 280
 281         { "dma_writeq_full" },
 282         { "dma_write_prioq_full" },
 283         { "rxbds_empty" },
 284         { "rx_discards" },
 285         { "rx_errors" },
 286         { "rx_threshold_hit" },
 287
 288         { "dma_readq_full" },
 289         { "dma_read_prioq_full" },
 290         { "tx_comp_queue_full" },
 291
 292         { "ring_set_send_prod_index" },
 293         { "ring_status_update" },
 294         { "nic_irqs" },
 295         { "nic_avoided_irqs" },
 296         { "nic_tx_threshold_hit" }
 297 };
 298
 299 static const struct {
 300         const char string[ETH_GSTRING_LEN];
 301 } ethtool_test_keys[TG3_NUM_TEST] = {
 302         { "nvram test     (online) " },
 303         { "link test      (online) " },
 304         { "register test  (offline)" },
 305         { "memory test    (offline)" },
 306         { "loopback test  (offline)" },
 307         { "interrupt test (offline)" },
 308 };
 309
 310 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 311 {
 312         writel(val, tp->regs + off);
 313 }
 314
 315 static u32 tg3_read32(struct tg3 *tp, u32 off)
 316 {
 317         return (readl(tp->regs + off));
 318 }
 319
 320 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 321 {
 322         writel(val, tp->aperegs + off);
 323 }
 324
 325 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 326 {
 327         return (readl(tp->aperegs + off));
 328 }
 329
 330 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 331 {
 332         unsigned long flags;
 333
 334         spin_lock_irqsave(&tp->indirect_lock, flags);
 335         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 336         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 337         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 338 }
 339
 340 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 341 {
 342         writel(val, tp->regs + off);
 343         readl(tp->regs + off);
 344 }
 345
 346 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 347 {
 348         unsigned long flags;
 349         u32 val;
 350
 351         spin_lock_irqsave(&tp->indirect_lock, flags);
 352         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 353         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 354         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 355         return val;
 356 }
 357
 358 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 359 {
 360         unsigned long flags;
 361
 362         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 363                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 364                                        TG3_64BIT_REG_LOW, val);
 365                 return;
 366         }
 367         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 368                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 369                                        TG3_64BIT_REG_LOW, val);
 370                 return;
 371         }
 372
 373         spin_lock_irqsave(&tp->indirect_lock, flags);
 374         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 375         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 376         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 377
 378         /* In indirect mode when disabling interrupts, we also need
 379          * to clear the interrupt bit in the GRC local ctrl register.
 380          */
 381         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 382             (val == 0x1)) {
 383                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 384                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 385         }
 386 }
 387
 388 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 389 {
 390         unsigned long flags;
 391         u32 val;
 392
 393         spin_lock_irqsave(&tp->indirect_lock, flags);
 394         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 395         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 396         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 397         return val;
 398 }
 399
 400 /* usec_wait specifies the wait time in usec when writing to certain registers
 401  * where it is unsafe to read back the register without some delay.
 402  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 403  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 404  */
 405 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 406 {
 407         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 408             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 409                 /* Non-posted methods */
 410                 tp->write32(tp, off, val);
 411         else {
 412                 /* Posted method */
 413                 tg3_write32(tp, off, val);
 414                 if (usec_wait)
 415                         udelay(usec_wait);
 416                 tp->read32(tp, off);
 417         }
 418         /* Wait again after the read for the posted method to guarantee that
 419          * the wait time is met.
 420          */
 421         if (usec_wait)
 422                 udelay(usec_wait);
 423 }
 424
 425 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 426 {
 427         tp->write32_mbox(tp, off, val);
 428         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 429             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 430                 tp->read32_mbox(tp, off);
 431 }
 432
 433 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 434 {
 435         void __iomem *mbox = tp->regs + off;
 436         writel(val, mbox);
 437         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 438                 writel(val, mbox);
 439         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 440                 readl(mbox);
 441 }
 442
 443 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 444 {
 445         return (readl(tp->regs + off + GRCMBOX_BASE));
 446 }
 447
 448 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 449 {
 450         writel(val, tp->regs + off + GRCMBOX_BASE);
 451 }
 452
 453 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 454 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 455 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 456 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 457 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 458
 459 #define tw32(reg,val)           tp->write32(tp, reg, val)
 460 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 461 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 462 #define tr32(reg)               tp->read32(tp, reg)
 463
 464 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 465 {
 466         unsigned long flags;
 467
 468         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 469             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 470                 return;
 471
 472         spin_lock_irqsave(&tp->indirect_lock, flags);
 473         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 474                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 475                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 476
 477                 /* Always leave this as zero. */
 478                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 479         } else {
 480                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 481                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 482
 483                 /* Always leave this as zero. */
 484                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 485         }
 486         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 487 }
 488
 489 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 490 {
 491         unsigned long flags;
 492
 493         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 494             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 495                 *val = 0;
 496                 return;
 497         }
 498
 499         spin_lock_irqsave(&tp->indirect_lock, flags);
 500         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 501                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 502                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 503
 504                 /* Always leave this as zero. */
 505                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 506         } else {
 507                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 508                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 509
 510                 /* Always leave this as zero. */
 511                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 512         }
 513         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 514 }
 515
 516 static void tg3_ape_lock_init(struct tg3 *tp)
 517 {
 518         int i;
 519
 520         /* Make sure the driver hasn't any stale locks. */
 521         for (i = 0; i < 8; i++)
 522                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 523                                 APE_LOCK_GRANT_DRIVER);
 524 }
 525
 526 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 527 {
 528         int i, off;
 529         int ret = 0;
 530         u32 status;
 531
 532         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 533                 return 0;
 534
 535         switch (locknum) {
 536                 case TG3_APE_LOCK_MEM:
 537                         break;
 538                 default:
 539                         return -EINVAL;
 540         }
 541
 542         off = 4 * locknum;
 543
 544         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 545
 546         /* Wait for up to 1 millisecond to acquire lock. */
 547         for (i = 0; i < 100; i++) {
 548                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 549                 if (status == APE_LOCK_GRANT_DRIVER)
 550                         break;
 551                 udelay(10);
 552         }
 553
 554         if (status != APE_LOCK_GRANT_DRIVER) {
 555                 /* Revoke the lock request. */
 556                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 557                                 APE_LOCK_GRANT_DRIVER);
 558
 559                 ret = -EBUSY;
 560         }
 561
 562         return ret;
 563 }
 564
 565 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 566 {
 567         int off;
 568
 569         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 570                 return;
 571
 572         switch (locknum) {
 573                 case TG3_APE_LOCK_MEM:
 574                         break;
 575                 default:
 576                         return;
 577         }
 578
 579         off = 4 * locknum;
 580         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 581 }
 582
 583 static void tg3_disable_ints(struct tg3 *tp)
 584 {
 585         tw32(TG3PCI_MISC_HOST_CTRL,
 586              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 587         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 588 }
 589
 590 static inline void tg3_cond_int(struct tg3 *tp)
 591 {
 592         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 593             (tp->hw_status->status & SD_STATUS_UPDATED))
 594                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 595         else
 596                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 597                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 598 }
 599
 600 static void tg3_enable_ints(struct tg3 *tp)
 601 {
 602         tp->irq_sync = 0;
 603         wmb();
 604
 605         tw32(TG3PCI_MISC_HOST_CTRL,
 606              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 607         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 608                        (tp->last_tag << 24));
 609         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 610                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 611                                (tp->last_tag << 24));
 612         tg3_cond_int(tp);
 613 }
 614
 615 static inline unsigned int tg3_has_work(struct tg3 *tp)
 616 {
 617         struct tg3_hw_status *sblk = tp->hw_status;
 618         unsigned int work_exists = 0;
 619
 620         /* check for phy events */
 621         if (!(tp->tg3_flags &
 622               (TG3_FLAG_USE_LINKCHG_REG |
 623                TG3_FLAG_POLL_SERDES))) {
 624                 if (sblk->status & SD_STATUS_LINK_CHG)
 625                         work_exists = 1;
 626         }
 627         /* check for RX/TX work to do */
 628         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 629             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 630                 work_exists = 1;
 631
 632         return work_exists;
 633 }
 634
 635 /* tg3_restart_ints
 636  *  similar to tg3_enable_ints, but it accurately determines whether there
 637  *  is new work pending and can return without flushing the PIO write
 638  *  which reenables interrupts
 639  */
 640 static void tg3_restart_ints(struct tg3 *tp)
 641 {
 642         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 643                      tp->last_tag << 24);
 644         mmiowb();
 645
 646         /* When doing tagged status, this work check is unnecessary.
 647          * The last_tag we write above tells the chip which piece of
 648          * work we've completed.
 649          */
 650         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 651             tg3_has_work(tp))
 652                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 653                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 654 }
 655
 656 static inline void tg3_netif_stop(struct tg3 *tp)
 657 {
 658         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 659         napi_disable(&tp->napi);
 660         netif_tx_disable(tp->dev);
 661 }
 662
 663 static inline void tg3_netif_start(struct tg3 *tp)
 664 {
 665         netif_wake_queue(tp->dev);
 666         /* NOTE: unconditional netif_wake_queue is only appropriate
 667          * so long as all callers are assured to have free tx slots
 668          * (such as after tg3_init_hw)
 669          */
 670         napi_enable(&tp->napi);
 671         tp->hw_status->status |= SD_STATUS_UPDATED;
 672         tg3_enable_ints(tp);
 673 }
 674
 675 static void tg3_switch_clocks(struct tg3 *tp)
 676 {
 677         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 678         u32 orig_clock_ctrl;
 679
 680         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 681             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 682                 return;
 683
 684         orig_clock_ctrl = clock_ctrl;
 685         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 686                        CLOCK_CTRL_CLKRUN_OENABLE |
 687                        0x1f);
 688         tp->pci_clock_ctrl = clock_ctrl;
 689
 690         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 691                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 692                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 693                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 694                 }
 695         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 696                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 697                             clock_ctrl |
 698                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 699                             40);
 700                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 701                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 702                             40);
 703         }
 704         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 705 }
 706
 707 #define PHY_BUSY_LOOPS  5000
 708
 709 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 710 {
 711         u32 frame_val;
 712         unsigned int loops;
 713         int ret;
 714
 715         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 716                 tw32_f(MAC_MI_MODE,
 717                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 718                 udelay(80);
 719         }
 720
 721         *val = 0x0;
 722
 723         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 724                       MI_COM_PHY_ADDR_MASK);
 725         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 726                       MI_COM_REG_ADDR_MASK);
 727         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 728
 729         tw32_f(MAC_MI_COM, frame_val);
 730
 731         loops = PHY_BUSY_LOOPS;
 732         while (loops != 0) {
 733                 udelay(10);
 734                 frame_val = tr32(MAC_MI_COM);
 735
 736                 if ((frame_val & MI_COM_BUSY) == 0) {
 737                         udelay(5);
 738                         frame_val = tr32(MAC_MI_COM);
 739                         break;
 740                 }
 741                 loops -= 1;
 742         }
 743
 744         ret = -EBUSY;
 745         if (loops != 0) {
 746                 *val = frame_val & MI_COM_DATA_MASK;
 747                 ret = 0;
 748         }
 749
 750         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 751                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 752                 udelay(80);
 753         }
 754
 755         return ret;
 756 }
 757
 758 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 759 {
 760         u32 frame_val;
 761         unsigned int loops;
 762         int ret;
 763
 764         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 765             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 766                 return 0;
 767
 768         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 769                 tw32_f(MAC_MI_MODE,
 770                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 771                 udelay(80);
 772         }
 773
 774         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 775                       MI_COM_PHY_ADDR_MASK);
 776         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 777                       MI_COM_REG_ADDR_MASK);
 778         frame_val |= (val & MI_COM_DATA_MASK);
 779         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 780
 781         tw32_f(MAC_MI_COM, frame_val);
 782
 783         loops = PHY_BUSY_LOOPS;
 784         while (loops != 0) {
 785                 udelay(10);
 786                 frame_val = tr32(MAC_MI_COM);
 787                 if ((frame_val & MI_COM_BUSY) == 0) {
 788                         udelay(5);
 789                         frame_val = tr32(MAC_MI_COM);
 790                         break;
 791                 }
 792                 loops -= 1;
 793         }
 794
 795         ret = -EBUSY;
 796         if (loops != 0)
 797                 ret = 0;
 798
 799         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 800                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 801                 udelay(80);
 802         }
 803
 804         return ret;
 805 }
 806
 807 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
 808 {
 809         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
 810         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
 811 }
 812
 813 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
 814 {
 815         u32 phy;
 816
 817         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
 818             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
 819                 return;
 820
 821         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 822                 u32 ephy;
 823
 824                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
 825                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
 826                                      ephy | MII_TG3_EPHY_SHADOW_EN);
 827                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
 828                                 if (enable)
 829                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
 830                                 else
 831                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
 832                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
 833                         }
 834                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
 835                 }
 836         } else {
 837                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
 838                       MII_TG3_AUXCTL_SHDWSEL_MISC;
 839                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
 840                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
 841                         if (enable)
 842                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
 843                         else
 844                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
 845                         phy |= MII_TG3_AUXCTL_MISC_WREN;
 846                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
 847                 }
 848         }
 849 }
 850
 851 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 852 {
 853         u32 val;
 854
 855         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 856                 return;
 857
 858         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 859             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 860                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 861                              (val | (1 << 15) | (1 << 4)));
 862 }
 863
 864 static int tg3_bmcr_reset(struct tg3 *tp)
 865 {
 866         u32 phy_control;
 867         int limit, err;
 868
 869         /* OK, reset it, and poll the BMCR_RESET bit until it
 870          * clears or we time out.
 871          */
 872         phy_control = BMCR_RESET;
 873         err = tg3_writephy(tp, MII_BMCR, phy_control);
 874         if (err != 0)
 875                 return -EBUSY;
 876
 877         limit = 5000;
 878         while (limit--) {
 879                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 880                 if (err != 0)
 881                         return -EBUSY;
 882
 883                 if ((phy_control & BMCR_RESET) == 0) {
 884                         udelay(40);
 885                         break;
 886                 }
 887                 udelay(10);
 888         }
 889         if (limit <= 0)
 890                 return -EBUSY;
 891
 892         return 0;
 893 }
 894
 895 static void tg3_phy_apply_otp(struct tg3 *tp)
 896 {
 897         u32 otp, phy;
 898
 899         if (!tp->phy_otp)
 900                 return;
 901
 902         otp = tp->phy_otp;
 903
 904         /* Enable SM_DSP clock and tx 6dB coding. */
 905         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
 906               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
 907               MII_TG3_AUXCTL_ACTL_TX_6DB;
 908         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
 909
 910         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
 911         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
 912         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
 913
 914         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
 915               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
 916         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
 917
 918         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
 919         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
 920         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
 921
 922         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
 923         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
 924
 925         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
 926         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
 927
 928         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
 929               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
 930         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
 931
 932         /* Turn off SM_DSP clock. */
 933         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
 934               MII_TG3_AUXCTL_ACTL_TX_6DB;
 935         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
 936 }
 937
 938 static int tg3_wait_macro_done(struct tg3 *tp)
 939 {
 940         int limit = 100;
 941
 942         while (limit--) {
 943                 u32 tmp32;
 944
 945                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 946                         if ((tmp32 & 0x1000) == 0)
 947                                 break;
 948                 }
 949         }
 950         if (limit <= 0)
 951                 return -EBUSY;
 952
 953         return 0;
 954 }
 955
 956 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 957 {
 958         static const u32 test_pat[4][6] = {
 959         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 960         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 961         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 962         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 963         };
 964         int chan;
 965
 966         for (chan = 0; chan < 4; chan++) {
 967                 int i;
 968
 969                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 970                              (chan * 0x2000) | 0x0200);
 971                 tg3_writephy(tp, 0x16, 0x0002);
 972
 973                 for (i = 0; i < 6; i++)
 974                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 975                                      test_pat[chan][i]);
 976
 977                 tg3_writephy(tp, 0x16, 0x0202);
 978                 if (tg3_wait_macro_done(tp)) {
 979                         *resetp = 1;
 980                         return -EBUSY;
 981                 }
 982
 983                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 984                              (chan * 0x2000) | 0x0200);
 985                 tg3_writephy(tp, 0x16, 0x0082);
 986                 if (tg3_wait_macro_done(tp)) {
 987                         *resetp = 1;
 988                         return -EBUSY;
 989                 }
 990
 991                 tg3_writephy(tp, 0x16, 0x0802);
 992                 if (tg3_wait_macro_done(tp)) {
 993                         *resetp = 1;
 994                         return -EBUSY;
 995                 }
 996
 997                 for (i = 0; i < 6; i += 2) {
 998                         u32 low, high;
 999
1000                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1001                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1002                             tg3_wait_macro_done(tp)) {
1003                                 *resetp = 1;
1004                                 return -EBUSY;
1005                         }
1006                         low &= 0x7fff;
1007                         high &= 0x000f;
1008                         if (low != test_pat[chan][i] ||
1009                             high != test_pat[chan][i+1]) {
1010                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1011                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1012                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1013
1014                                 return -EBUSY;
1015                         }
1016                 }
1017         }
1018
1019         return 0;
1020 }
1021
1022 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1023 {
1024         int chan;
1025
1026         for (chan = 0; chan < 4; chan++) {
1027                 int i;
1028
1029                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1030                              (chan * 0x2000) | 0x0200);
1031                 tg3_writephy(tp, 0x16, 0x0002);
1032                 for (i = 0; i < 6; i++)
1033                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1034                 tg3_writephy(tp, 0x16, 0x0202);
1035                 if (tg3_wait_macro_done(tp))
1036                         return -EBUSY;
1037         }
1038
1039         return 0;
1040 }
1041
1042 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1043 {
1044         u32 reg32, phy9_orig;
1045         int retries, do_phy_reset, err;
1046
1047         retries = 10;
1048         do_phy_reset = 1;
1049         do {
1050                 if (do_phy_reset) {
1051                         err = tg3_bmcr_reset(tp);
1052                         if (err)
1053                                 return err;
1054                         do_phy_reset = 0;
1055                 }
1056
1057                 /* Disable transmitter and interrupt.  */
1058                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1059                         continue;
1060
1061                 reg32 |= 0x3000;
1062                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1063
1064                 /* Set full-duplex, 1000 mbps.  */
1065                 tg3_writephy(tp, MII_BMCR,
1066                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1067
1068                 /* Set to master mode.  */
1069                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1070                         continue;
1071
1072                 tg3_writephy(tp, MII_TG3_CTRL,
1073                              (MII_TG3_CTRL_AS_MASTER |
1074                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1075
1076                 /* Enable SM_DSP_CLOCK and 6dB.  */
1077                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1078
1079                 /* Block the PHY control access.  */
1080                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1081                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1082
1083                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1084                 if (!err)
1085                         break;
1086         } while (--retries);
1087
1088         err = tg3_phy_reset_chanpat(tp);
1089         if (err)
1090                 return err;
1091
1092         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1093         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1094
1095         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1096         tg3_writephy(tp, 0x16, 0x0000);
1097
1098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1099             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1100                 /* Set Extended packet length bit for jumbo frames */
1101                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1102         }
1103         else {
1104                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1105         }
1106
1107         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1108
1109         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1110                 reg32 &= ~0x3000;
1111                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1112         } else if (!err)
1113                 err = -EBUSY;
1114
1115         return err;
1116 }
1117
1118 static void tg3_link_report(struct tg3 *);
1119
1120 /* This will reset the tigon3 PHY if there is no valid
1121  * link unless the FORCE argument is non-zero.
1122  */
1123 static int tg3_phy_reset(struct tg3 *tp)
1124 {
1125         u32 cpmuctrl;
1126         u32 phy_status;
1127         int err;
1128
1129         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1130                 u32 val;
1131
1132                 val = tr32(GRC_MISC_CFG);
1133                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1134                 udelay(40);
1135         }
1136         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1137         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1138         if (err != 0)
1139                 return -EBUSY;
1140
1141         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1142                 netif_carrier_off(tp->dev);
1143                 tg3_link_report(tp);
1144         }
1145
1146         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1147             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1148             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1149                 err = tg3_phy_reset_5703_4_5(tp);
1150                 if (err)
1151                         return err;
1152                 goto out;
1153         }
1154
1155         cpmuctrl = 0;
1156         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1157             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1158                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1159                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1160                         tw32(TG3_CPMU_CTRL,
1161                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1162         }
1163
1164         err = tg3_bmcr_reset(tp);
1165         if (err)
1166                 return err;
1167
1168         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1169                 u32 phy;
1170
1171                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1172                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1173
1174                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1175         }
1176
1177         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1178                 u32 val;
1179
1180                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1181                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1182                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1183                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1184                         udelay(40);
1185                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1186                 }
1187
1188                 /* Disable GPHY autopowerdown. */
1189                 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1190                              MII_TG3_MISC_SHDW_WREN |
1191                              MII_TG3_MISC_SHDW_APD_SEL |
1192                              MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1193         }
1194
1195         tg3_phy_apply_otp(tp);
1196
1197 out:
1198         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1199                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1200                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1201                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1202                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1203                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1204                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1205         }
1206         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1207                 tg3_writephy(tp, 0x1c, 0x8d68);
1208                 tg3_writephy(tp, 0x1c, 0x8d68);
1209         }
1210         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1211                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1212                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1213                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1214                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1215                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1216                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1217                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1218                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1219         }
1220         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1221                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1222                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1223                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1224                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1225                         tg3_writephy(tp, MII_TG3_TEST1,
1226                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1227                 } else
1228                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1229                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1230         }
1231         /* Set Extended packet length bit (bit 14) on all chips that */
1232         /* support jumbo frames */
1233         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1234                 /* Cannot do read-modify-write on 5401 */
1235                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1236         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1237                 u32 phy_reg;
1238
1239                 /* Set bit 14 with read-modify-write to preserve other bits */
1240                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1241                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1242                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1243         }
1244
1245         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1246          * jumbo frames transmission.
1247          */
1248         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1249                 u32 phy_reg;
1250
1251                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1252                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1253                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1254         }
1255
1256         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1257                 /* adjust output voltage */
1258                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1259         }
1260
1261         tg3_phy_toggle_automdix(tp, 1);
1262         tg3_phy_set_wirespeed(tp);
1263         return 0;
1264 }
1265
1266 static void tg3_frob_aux_power(struct tg3 *tp)
1267 {
1268         struct tg3 *tp_peer = tp;
1269
1270         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1271                 return;
1272
1273         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1274             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1275                 struct net_device *dev_peer;
1276
1277                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1278                 /* remove_one() may have been run on the peer. */
1279                 if (!dev_peer)
1280                         tp_peer = tp;
1281                 else
1282                         tp_peer = netdev_priv(dev_peer);
1283         }
1284
1285         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1286             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1287             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1288             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1289                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1290                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1291                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1292                                     (GRC_LCLCTRL_GPIO_OE0 |
1293                                      GRC_LCLCTRL_GPIO_OE1 |
1294                                      GRC_LCLCTRL_GPIO_OE2 |
1295                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1296                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1297                                     100);
1298                 } else {
1299                         u32 no_gpio2;
1300                         u32 grc_local_ctrl = 0;
1301
1302                         if (tp_peer != tp &&
1303                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1304                                 return;
1305
1306                         /* Workaround to prevent overdrawing Amps. */
1307                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1308                             ASIC_REV_5714) {
1309                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1310                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1311                                             grc_local_ctrl, 100);
1312                         }
1313
1314                         /* On 5753 and variants, GPIO2 cannot be used. */
1315                         no_gpio2 = tp->nic_sram_data_cfg &
1316                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1317
1318                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1319                                          GRC_LCLCTRL_GPIO_OE1 |
1320                                          GRC_LCLCTRL_GPIO_OE2 |
1321                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1322                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1323                         if (no_gpio2) {
1324                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1325                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1326                         }
1327                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1328                                                     grc_local_ctrl, 100);
1329
1330                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1331
1332                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1333                                                     grc_local_ctrl, 100);
1334
1335                         if (!no_gpio2) {
1336                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1337                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1338                                             grc_local_ctrl, 100);
1339                         }
1340                 }
1341         } else {
1342                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1343                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1344                         if (tp_peer != tp &&
1345                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1346                                 return;
1347
1348                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1349                                     (GRC_LCLCTRL_GPIO_OE1 |
1350                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1351
1352                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1353                                     GRC_LCLCTRL_GPIO_OE1, 100);
1354
1355                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1356                                     (GRC_LCLCTRL_GPIO_OE1 |
1357                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1358                 }
1359         }
1360 }
1361
1362 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1363 {
1364         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1365                 return 1;
1366         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1367                 if (speed != SPEED_10)
1368                         return 1;
1369         } else if (speed == SPEED_10)
1370                 return 1;
1371
1372         return 0;
1373 }
1374
1375 static int tg3_setup_phy(struct tg3 *, int);
1376
1377 #define RESET_KIND_SHUTDOWN     0
1378 #define RESET_KIND_INIT         1
1379 #define RESET_KIND_SUSPEND      2
1380
1381 static void tg3_write_sig_post_reset(struct tg3 *, int);
1382 static int tg3_halt_cpu(struct tg3 *, u32);
1383 static int tg3_nvram_lock(struct tg3 *);
1384 static void tg3_nvram_unlock(struct tg3 *);
1385
1386 static void tg3_power_down_phy(struct tg3 *tp)
1387 {
1388         u32 val;
1389
1390         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1391                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1392                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1393                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1394
1395                         sg_dig_ctrl |=
1396                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1397                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1398                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1399                 }
1400                 return;
1401         }
1402
1403         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1404                 tg3_bmcr_reset(tp);
1405                 val = tr32(GRC_MISC_CFG);
1406                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1407                 udelay(40);
1408                 return;
1409         } else {
1410                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1411                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1412                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1413         }
1414
1415         /* The PHY should not be powered down on some chips because
1416          * of bugs.
1417          */
1418         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1419             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1420             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1421              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1422                 return;
1423
1424         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1425                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1426                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1427                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1428                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1429         }
1430
1431         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1432 }
1433
1434 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1435 {
1436         u32 misc_host_ctrl;
1437         u16 power_control, power_caps;
1438         int pm = tp->pm_cap;
1439
1440         /* Make sure register accesses (indirect or otherwise)
1441          * will function correctly.
1442          */
1443         pci_write_config_dword(tp->pdev,
1444                                TG3PCI_MISC_HOST_CTRL,
1445                                tp->misc_host_ctrl);
1446
1447         pci_read_config_word(tp->pdev,
1448                              pm + PCI_PM_CTRL,
1449                              &power_control);
1450         power_control |= PCI_PM_CTRL_PME_STATUS;
1451         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1452         switch (state) {
1453         case PCI_D0:
1454                 power_control |= 0;
1455                 pci_write_config_word(tp->pdev,
1456                                       pm + PCI_PM_CTRL,
1457                                       power_control);
1458                 udelay(100);    /* Delay after power state change */
1459
1460                 /* Switch out of Vaux if it is a NIC */
1461                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1462                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1463
1464                 return 0;
1465
1466         case PCI_D1:
1467                 power_control |= 1;
1468                 break;
1469
1470         case PCI_D2:
1471                 power_control |= 2;
1472                 break;
1473
1474         case PCI_D3hot:
1475                 power_control |= 3;
1476                 break;
1477
1478         default:
1479                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1480                        "requested.\n",
1481                        tp->dev->name, state);
1482                 return -EINVAL;
1483         };
1484
1485         power_control |= PCI_PM_CTRL_PME_ENABLE;
1486
1487         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1488         tw32(TG3PCI_MISC_HOST_CTRL,
1489              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1490
1491         if (tp->link_config.phy_is_low_power == 0) {
1492                 tp->link_config.phy_is_low_power = 1;
1493                 tp->link_config.orig_speed = tp->link_config.speed;
1494                 tp->link_config.orig_duplex = tp->link_config.duplex;
1495                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1496         }
1497
1498         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1499                 tp->link_config.speed = SPEED_10;
1500                 tp->link_config.duplex = DUPLEX_HALF;
1501                 tp->link_config.autoneg = AUTONEG_ENABLE;
1502                 tg3_setup_phy(tp, 0);
1503         }
1504
1505         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1506                 u32 val;
1507
1508                 val = tr32(GRC_VCPU_EXT_CTRL);
1509                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1510         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1511                 int i;
1512                 u32 val;
1513
1514                 for (i = 0; i < 200; i++) {
1515                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1516                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1517                                 break;
1518                         msleep(1);
1519                 }
1520         }
1521         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1522                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1523                                                      WOL_DRV_STATE_SHUTDOWN |
1524                                                      WOL_DRV_WOL |
1525                                                      WOL_SET_MAGIC_PKT);
1526
1527         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1528
1529         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1530                 u32 mac_mode;
1531
1532                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1533                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1534                         udelay(40);
1535
1536                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1537                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1538                         else
1539                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1540
1541                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1542                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1543                             ASIC_REV_5700) {
1544                                 u32 speed = (tp->tg3_flags &
1545                                              TG3_FLAG_WOL_SPEED_100MB) ?
1546                                              SPEED_100 : SPEED_10;
1547                                 if (tg3_5700_link_polarity(tp, speed))
1548                                         mac_mode |= MAC_MODE_LINK_POLARITY;
1549                                 else
1550                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
1551                         }
1552                 } else {
1553                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1554                 }
1555
1556                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1557                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1558
1559                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1560                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1561                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1562
1563                 tw32_f(MAC_MODE, mac_mode);
1564                 udelay(100);
1565
1566                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1567                 udelay(10);
1568         }
1569
1570         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1571             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1572              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1573                 u32 base_val;
1574
1575                 base_val = tp->pci_clock_ctrl;
1576                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1577                              CLOCK_CTRL_TXCLK_DISABLE);
1578
1579                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1580                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1581         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1582                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
1583                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1584                 /* do nothing */
1585         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1586                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1587                 u32 newbits1, newbits2;
1588
1589                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1590                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1591                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1592                                     CLOCK_CTRL_TXCLK_DISABLE |
1593                                     CLOCK_CTRL_ALTCLK);
1594                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1595                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1596                         newbits1 = CLOCK_CTRL_625_CORE;
1597                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1598                 } else {
1599                         newbits1 = CLOCK_CTRL_ALTCLK;
1600                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1601                 }
1602
1603                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1604                             40);
1605
1606                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1607                             40);
1608
1609                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1610                         u32 newbits3;
1611
1612                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1613                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1614                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1615                                             CLOCK_CTRL_TXCLK_DISABLE |
1616                                             CLOCK_CTRL_44MHZ_CORE);
1617                         } else {
1618                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1619                         }
1620
1621                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1622                                     tp->pci_clock_ctrl | newbits3, 40);
1623                 }
1624         }
1625
1626         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1627             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
1628             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
1629                 tg3_power_down_phy(tp);
1630
1631         tg3_frob_aux_power(tp);
1632
1633         /* Workaround for unstable PLL clock */
1634         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1635             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1636                 u32 val = tr32(0x7d00);
1637
1638                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1639                 tw32(0x7d00, val);
1640                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1641                         int err;
1642
1643                         err = tg3_nvram_lock(tp);
1644                         tg3_halt_cpu(tp, RX_CPU_BASE);
1645                         if (!err)
1646                                 tg3_nvram_unlock(tp);
1647                 }
1648         }
1649
1650         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1651
1652         /* Finally, set the new power state. */
1653         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1654         udelay(100);    /* Delay after power state change */
1655
1656         return 0;
1657 }
1658
1659 static void tg3_link_report(struct tg3 *tp)
1660 {
1661         if (!netif_carrier_ok(tp->dev)) {
1662                 if (netif_msg_link(tp))
1663                         printk(KERN_INFO PFX "%s: Link is down.\n",
1664                                tp->dev->name);
1665         } else if (netif_msg_link(tp)) {
1666                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1667                        tp->dev->name,
1668                        (tp->link_config.active_speed == SPEED_1000 ?
1669                         1000 :
1670                         (tp->link_config.active_speed == SPEED_100 ?
1671                          100 : 10)),
1672                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1673                         "full" : "half"));
1674
1675                 printk(KERN_INFO PFX
1676                        "%s: Flow control is %s for TX and %s for RX.\n",
1677                        tp->dev->name,
1678                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1679                        "on" : "off",
1680                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1681                        "on" : "off");
1682         }
1683 }
1684
1685 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1686 {
1687         u16 miireg;
1688
1689         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1690                 miireg = ADVERTISE_PAUSE_CAP;
1691         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1692                 miireg = ADVERTISE_PAUSE_ASYM;
1693         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1694                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1695         else
1696                 miireg = 0;
1697
1698         return miireg;
1699 }
1700
1701 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1702 {
1703         u16 miireg;
1704
1705         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1706                 miireg = ADVERTISE_1000XPAUSE;
1707         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1708                 miireg = ADVERTISE_1000XPSE_ASYM;
1709         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1710                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1711         else
1712                 miireg = 0;
1713
1714         return miireg;
1715 }
1716
1717 static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1718 {
1719         u8 cap = 0;
1720
1721         if (lcladv & ADVERTISE_PAUSE_CAP) {
1722                 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1723                         if (rmtadv & LPA_PAUSE_CAP)
1724                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1725                         else if (rmtadv & LPA_PAUSE_ASYM)
1726                                 cap = TG3_FLOW_CTRL_RX;
1727                 } else {
1728                         if (rmtadv & LPA_PAUSE_CAP)
1729                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1730                 }
1731         } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1732                 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1733                         cap = TG3_FLOW_CTRL_TX;
1734         }
1735
1736         return cap;
1737 }
1738
1739 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1740 {
1741         u8 cap = 0;
1742
1743         if (lcladv & ADVERTISE_1000XPAUSE) {
1744                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1745                         if (rmtadv & LPA_1000XPAUSE)
1746                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1747                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1748                                 cap = TG3_FLOW_CTRL_RX;
1749                 } else {
1750                         if (rmtadv & LPA_1000XPAUSE)
1751                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1752                 }
1753         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1754                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1755                         cap = TG3_FLOW_CTRL_TX;
1756         }
1757
1758         return cap;
1759 }
1760
1761 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1762 {
1763         u8 new_tg3_flags = 0;
1764         u32 old_rx_mode = tp->rx_mode;
1765         u32 old_tx_mode = tp->tx_mode;
1766
1767         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1768             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1769                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1770                         new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv,
1771                                                                    remote_adv);
1772                 else
1773                         new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv,
1774                                                                    remote_adv);
1775         } else {
1776                 new_tg3_flags = tp->link_config.flowctrl;
1777         }
1778
1779         tp->link_config.active_flowctrl = new_tg3_flags;
1780
1781         if (new_tg3_flags & TG3_FLOW_CTRL_RX)
1782                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1783         else
1784                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1785
1786         if (old_rx_mode != tp->rx_mode) {
1787                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1788         }
1789
1790         if (new_tg3_flags & TG3_FLOW_CTRL_TX)
1791                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1792         else
1793                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1794
1795         if (old_tx_mode != tp->tx_mode) {
1796                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1797         }
1798 }
1799
1800 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1801 {
1802         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1803         case MII_TG3_AUX_STAT_10HALF:
1804                 *speed = SPEED_10;
1805                 *duplex = DUPLEX_HALF;
1806                 break;
1807
1808         case MII_TG3_AUX_STAT_10FULL:
1809                 *speed = SPEED_10;
1810                 *duplex = DUPLEX_FULL;
1811                 break;
1812
1813         case MII_TG3_AUX_STAT_100HALF:
1814                 *speed = SPEED_100;
1815                 *duplex = DUPLEX_HALF;
1816                 break;
1817
1818         case MII_TG3_AUX_STAT_100FULL:
1819                 *speed = SPEED_100;
1820                 *duplex = DUPLEX_FULL;
1821                 break;
1822
1823         case MII_TG3_AUX_STAT_1000HALF:
1824                 *speed = SPEED_1000;
1825                 *duplex = DUPLEX_HALF;
1826                 break;
1827
1828         case MII_TG3_AUX_STAT_1000FULL:
1829                 *speed = SPEED_1000;
1830                 *duplex = DUPLEX_FULL;
1831                 break;
1832
1833         default:
1834                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1835                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1836                                  SPEED_10;
1837                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1838                                   DUPLEX_HALF;
1839                         break;
1840                 }
1841                 *speed = SPEED_INVALID;
1842                 *duplex = DUPLEX_INVALID;
1843                 break;
1844         };
1845 }
1846
1847 static void tg3_phy_copper_begin(struct tg3 *tp)
1848 {
1849         u32 new_adv;
1850         int i;
1851
1852         if (tp->link_config.phy_is_low_power) {
1853                 /* Entering low power mode.  Disable gigabit and
1854                  * 100baseT advertisements.
1855                  */
1856                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1857
1858                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1859                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1860                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1861                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1862
1863                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1864         } else if (tp->link_config.speed == SPEED_INVALID) {
1865                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1866                         tp->link_config.advertising &=
1867                                 ~(ADVERTISED_1000baseT_Half |
1868                                   ADVERTISED_1000baseT_Full);
1869
1870                 new_adv = ADVERTISE_CSMA;
1871                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1872                         new_adv |= ADVERTISE_10HALF;
1873                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1874                         new_adv |= ADVERTISE_10FULL;
1875                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1876                         new_adv |= ADVERTISE_100HALF;
1877                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1878                         new_adv |= ADVERTISE_100FULL;
1879
1880                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1881
1882                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1883
1884                 if (tp->link_config.advertising &
1885                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1886                         new_adv = 0;
1887                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1888                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1889                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1890                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1891                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1892                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1893                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1894                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1895                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1896                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1897                 } else {
1898                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1899                 }
1900         } else {
1901                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1902                 new_adv |= ADVERTISE_CSMA;
1903
1904                 /* Asking for a specific link mode. */
1905                 if (tp->link_config.speed == SPEED_1000) {
1906                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1907
1908                         if (tp->link_config.duplex == DUPLEX_FULL)
1909                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1910                         else
1911                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1912                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1913                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1914                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1915                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1916                 } else {
1917                         if (tp->link_config.speed == SPEED_100) {
1918                                 if (tp->link_config.duplex == DUPLEX_FULL)
1919                                         new_adv |= ADVERTISE_100FULL;
1920                                 else
1921                                         new_adv |= ADVERTISE_100HALF;
1922                         } else {
1923                                 if (tp->link_config.duplex == DUPLEX_FULL)
1924                                         new_adv |= ADVERTISE_10FULL;
1925                                 else
1926                                         new_adv |= ADVERTISE_10HALF;
1927                         }
1928                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1929
1930                         new_adv = 0;
1931                 }
1932
1933                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1934         }
1935
1936         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1937             tp->link_config.speed != SPEED_INVALID) {
1938                 u32 bmcr, orig_bmcr;
1939
1940                 tp->link_config.active_speed = tp->link_config.speed;
1941                 tp->link_config.active_duplex = tp->link_config.duplex;
1942
1943                 bmcr = 0;
1944                 switch (tp->link_config.speed) {
1945                 default:
1946                 case SPEED_10:
1947                         break;
1948
1949                 case SPEED_100:
1950                         bmcr |= BMCR_SPEED100;
1951                         break;
1952
1953                 case SPEED_1000:
1954                         bmcr |= TG3_BMCR_SPEED1000;
1955                         break;
1956                 };
1957
1958                 if (tp->link_config.duplex == DUPLEX_FULL)
1959                         bmcr |= BMCR_FULLDPLX;
1960
1961                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1962                     (bmcr != orig_bmcr)) {
1963                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1964                         for (i = 0; i < 1500; i++) {
1965                                 u32 tmp;
1966
1967                                 udelay(10);
1968                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1969                                     tg3_readphy(tp, MII_BMSR, &tmp))
1970                                         continue;
1971                                 if (!(tmp & BMSR_LSTATUS)) {
1972                                         udelay(40);
1973                                         break;
1974                                 }
1975                         }
1976                         tg3_writephy(tp, MII_BMCR, bmcr);
1977                         udelay(40);
1978                 }
1979         } else {
1980                 tg3_writephy(tp, MII_BMCR,
1981                              BMCR_ANENABLE | BMCR_ANRESTART);
1982         }
1983 }
1984
1985 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1986 {
1987         int err;
1988
1989         /* Turn off tap power management. */
1990         /* Set Extended packet length bit */
1991         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1992
1993         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1994         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1995
1996         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1997         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1998
1999         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2000         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2001
2002         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2003         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2004
2005         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2006         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2007
2008         udelay(40);
2009
2010         return err;
2011 }
2012
2013 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2014 {
2015         u32 adv_reg, all_mask = 0;
2016
2017         if (mask & ADVERTISED_10baseT_Half)
2018                 all_mask |= ADVERTISE_10HALF;
2019         if (mask & ADVERTISED_10baseT_Full)
2020                 all_mask |= ADVERTISE_10FULL;
2021         if (mask & ADVERTISED_100baseT_Half)
2022                 all_mask |= ADVERTISE_100HALF;
2023         if (mask & ADVERTISED_100baseT_Full)
2024                 all_mask |= ADVERTISE_100FULL;
2025
2026         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2027                 return 0;
2028
2029         if ((adv_reg & all_mask) != all_mask)
2030                 return 0;
2031         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2032                 u32 tg3_ctrl;
2033
2034                 all_mask = 0;
2035                 if (mask & ADVERTISED_1000baseT_Half)
2036                         all_mask |= ADVERTISE_1000HALF;
2037                 if (mask & ADVERTISED_1000baseT_Full)
2038                         all_mask |= ADVERTISE_1000FULL;
2039
2040                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2041                         return 0;
2042
2043                 if ((tg3_ctrl & all_mask) != all_mask)
2044                         return 0;
2045         }
2046         return 1;
2047 }
2048
2049 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2050 {
2051         u32 curadv, reqadv;
2052
2053         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2054                 return 1;
2055
2056         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2057         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2058
2059         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2060                 if (curadv != reqadv)
2061                         return 0;
2062
2063                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2064                         tg3_readphy(tp, MII_LPA, rmtadv);
2065         } else {
2066                 /* Reprogram the advertisement register, even if it
2067                  * does not affect the current link.  If the link
2068                  * gets renegotiated in the future, we can save an
2069                  * additional renegotiation cycle by advertising
2070                  * it correctly in the first place.
2071                  */
2072                 if (curadv != reqadv) {
2073                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2074                                      ADVERTISE_PAUSE_ASYM);
2075                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2076                 }
2077         }
2078
2079         return 1;
2080 }
2081
2082 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2083 {
2084         int current_link_up;
2085         u32 bmsr, dummy;
2086         u32 lcl_adv, rmt_adv;
2087         u16 current_speed;
2088         u8 current_duplex;
2089         int i, err;
2090
2091         tw32(MAC_EVENT, 0);
2092
2093         tw32_f(MAC_STATUS,
2094              (MAC_STATUS_SYNC_CHANGED |
2095               MAC_STATUS_CFG_CHANGED |
2096               MAC_STATUS_MI_COMPLETION |
2097               MAC_STATUS_LNKSTATE_CHANGED));
2098         udelay(40);
2099
2100         tp->mi_mode = MAC_MI_MODE_BASE;
2101         tw32_f(MAC_MI_MODE, tp->mi_mode);
2102         udelay(80);
2103
2104         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2105
2106         /* Some third-party PHYs need to be reset on link going
2107          * down.
2108          */
2109         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2110              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2111              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2112             netif_carrier_ok(tp->dev)) {
2113                 tg3_readphy(tp, MII_BMSR, &bmsr);
2114                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2115                     !(bmsr & BMSR_LSTATUS))
2116                         force_reset = 1;
2117         }
2118         if (force_reset)
2119                 tg3_phy_reset(tp);
2120
2121         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2122                 tg3_readphy(tp, MII_BMSR, &bmsr);
2123                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2124                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2125                         bmsr = 0;
2126
2127                 if (!(bmsr & BMSR_LSTATUS)) {
2128                         err = tg3_init_5401phy_dsp(tp);
2129                         if (err)
2130                                 return err;
2131
2132                         tg3_readphy(tp, MII_BMSR, &bmsr);
2133                         for (i = 0; i < 1000; i++) {
2134                                 udelay(10);
2135                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2136                                     (bmsr & BMSR_LSTATUS)) {
2137                                         udelay(40);
2138                                         break;
2139                                 }
2140                         }
2141
2142                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2143                             !(bmsr & BMSR_LSTATUS) &&
2144                             tp->link_config.active_speed == SPEED_1000) {
2145                                 err = tg3_phy_reset(tp);
2146                                 if (!err)
2147                                         err = tg3_init_5401phy_dsp(tp);
2148                                 if (err)
2149                                         return err;
2150                         }
2151                 }
2152         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2153                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2154                 /* 5701 {A0,B0} CRC bug workaround */
2155                 tg3_writephy(tp, 0x15, 0x0a75);
2156                 tg3_writephy(tp, 0x1c, 0x8c68);
2157                 tg3_writephy(tp, 0x1c, 0x8d68);
2158                 tg3_writephy(tp, 0x1c, 0x8c68);
2159         }
2160
2161         /* Clear pending interrupts... */
2162         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2163         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2164
2165         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2166                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2167         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2168                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2169
2170         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2171             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2172                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2173                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2174                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2175                 else
2176                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2177         }
2178
2179         current_link_up = 0;
2180         current_speed = SPEED_INVALID;
2181         current_duplex = DUPLEX_INVALID;
2182
2183         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2184                 u32 val;
2185
2186                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2187                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2188                 if (!(val & (1 << 10))) {
2189                         val |= (1 << 10);
2190                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2191                         goto relink;
2192                 }
2193         }
2194
2195         bmsr = 0;
2196         for (i = 0; i < 100; i++) {
2197                 tg3_readphy(tp, MII_BMSR, &bmsr);
2198                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2199                     (bmsr & BMSR_LSTATUS))
2200                         break;
2201                 udelay(40);
2202         }
2203
2204         if (bmsr & BMSR_LSTATUS) {
2205                 u32 aux_stat, bmcr;
2206
2207                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2208                 for (i = 0; i < 2000; i++) {
2209                         udelay(10);
2210                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2211                             aux_stat)
2212                                 break;
2213                 }
2214
2215                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2216                                              &current_speed,
2217                                              &current_duplex);
2218
2219                 bmcr = 0;
2220                 for (i = 0; i < 200; i++) {
2221                         tg3_readphy(tp, MII_BMCR, &bmcr);
2222                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
2223                                 continue;
2224                         if (bmcr && bmcr != 0x7fff)
2225                                 break;
2226                         udelay(10);
2227                 }
2228
2229                 lcl_adv = 0;
2230                 rmt_adv = 0;
2231
2232                 tp->link_config.active_speed = current_speed;
2233                 tp->link_config.active_duplex = current_duplex;
2234
2235                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2236                         if ((bmcr & BMCR_ANENABLE) &&
2237                             tg3_copper_is_advertising_all(tp,
2238                                                 tp->link_config.advertising)) {
2239                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2240                                                                   &rmt_adv))
2241                                         current_link_up = 1;
2242                         }
2243                 } else {
2244                         if (!(bmcr & BMCR_ANENABLE) &&
2245                             tp->link_config.speed == current_speed &&
2246                             tp->link_config.duplex == current_duplex &&
2247                             tp->link_config.flowctrl ==
2248                             tp->link_config.active_flowctrl) {
2249                                 current_link_up = 1;
2250                         }
2251                 }
2252
2253                 if (current_link_up == 1 &&
2254                     tp->link_config.active_duplex == DUPLEX_FULL)
2255                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2256         }
2257
2258 relink:
2259         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2260                 u32 tmp;
2261
2262                 tg3_phy_copper_begin(tp);
2263
2264                 tg3_readphy(tp, MII_BMSR, &tmp);
2265                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2266                     (tmp & BMSR_LSTATUS))
2267                         current_link_up = 1;
2268         }
2269
2270         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2271         if (current_link_up == 1) {
2272                 if (tp->link_config.active_speed == SPEED_100 ||
2273                     tp->link_config.active_speed == SPEED_10)
2274                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2275                 else
2276                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2277         } else
2278                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2279
2280         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2281         if (tp->link_config.active_duplex == DUPLEX_HALF)
2282                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2283
2284         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2285                 if (current_link_up == 1 &&
2286                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2287                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2288                 else
2289                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2290         }
2291
2292         /* ??? Without this setting Netgear GA302T PHY does not
2293          * ??? send/receive packets...
2294          */
2295         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2296             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2297                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2298                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2299                 udelay(80);
2300         }
2301
2302         tw32_f(MAC_MODE, tp->mac_mode);
2303         udelay(40);
2304
2305         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2306                 /* Polled via timer. */
2307                 tw32_f(MAC_EVENT, 0);
2308         } else {
2309                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2310         }
2311         udelay(40);
2312
2313         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2314             current_link_up == 1 &&
2315             tp->link_config.active_speed == SPEED_1000 &&
2316             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2317              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2318                 udelay(120);
2319                 tw32_f(MAC_STATUS,
2320                      (MAC_STATUS_SYNC_CHANGED |
2321                       MAC_STATUS_CFG_CHANGED));
2322                 udelay(40);
2323                 tg3_write_mem(tp,
2324                               NIC_SRAM_FIRMWARE_MBOX,
2325                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2326         }
2327
2328         if (current_link_up != netif_carrier_ok(tp->dev)) {
2329                 if (current_link_up)
2330                         netif_carrier_on(tp->dev);
2331                 else
2332                         netif_carrier_off(tp->dev);
2333                 tg3_link_report(tp);
2334         }
2335
2336         return 0;
2337 }
2338
2339 struct tg3_fiber_aneginfo {
2340         int state;
2341 #define ANEG_STATE_UNKNOWN              0
2342 #define ANEG_STATE_AN_ENABLE            1
2343 #define ANEG_STATE_RESTART_INIT         2
2344 #define ANEG_STATE_RESTART              3
2345 #define ANEG_STATE_DISABLE_LINK_OK      4
2346 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2347 #define ANEG_STATE_ABILITY_DETECT       6
2348 #define ANEG_STATE_ACK_DETECT_INIT      7
2349 #define ANEG_STATE_ACK_DETECT           8
2350 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2351 #define ANEG_STATE_COMPLETE_ACK         10
2352 #define ANEG_STATE_IDLE_DETECT_INIT     11
2353 #define ANEG_STATE_IDLE_DETECT          12
2354 #define ANEG_STATE_LINK_OK              13
2355 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2356 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2357
2358         u32 flags;
2359 #define MR_AN_ENABLE            0x00000001
2360 #define MR_RESTART_AN           0x00000002
2361 #define MR_AN_COMPLETE          0x00000004
2362 #define MR_PAGE_RX              0x00000008
2363 #define MR_NP_LOADED            0x00000010
2364 #define MR_TOGGLE_TX            0x00000020
2365 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2366 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2367 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2368 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2369 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2370 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2371 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2372 #define MR_TOGGLE_RX            0x00002000
2373 #define MR_NP_RX                0x00004000
2374
2375 #define MR_LINK_OK              0x80000000
2376
2377         unsigned long link_time, cur_time;
2378
2379         u32 ability_match_cfg;
2380         int ability_match_count;
2381
2382         char ability_match, idle_match, ack_match;
2383
2384         u32 txconfig, rxconfig;
2385 #define ANEG_CFG_NP             0x00000080
2386 #define ANEG_CFG_ACK            0x00000040
2387 #define ANEG_CFG_RF2            0x00000020
2388 #define ANEG_CFG_RF1            0x00000010
2389 #define ANEG_CFG_PS2            0x00000001
2390 #define ANEG_CFG_PS1            0x00008000
2391 #define ANEG_CFG_HD             0x00004000
2392 #define ANEG_CFG_FD             0x00002000
2393 #define ANEG_CFG_INVAL          0x00001f06
2394
2395 };
2396 #define ANEG_OK         0
2397 #define ANEG_DONE       1
2398 #define ANEG_TIMER_ENAB 2
2399 #define ANEG_FAILED     -1
2400
2401 #define ANEG_STATE_SETTLE_TIME  10000
2402
2403 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2404                                    struct tg3_fiber_aneginfo *ap)
2405 {
2406         u16 flowctrl;
2407         unsigned long delta;
2408         u32 rx_cfg_reg;
2409         int ret;
2410
2411         if (ap->state == ANEG_STATE_UNKNOWN) {
2412                 ap->rxconfig = 0;
2413                 ap->link_time = 0;
2414                 ap->cur_time = 0;
2415                 ap->ability_match_cfg = 0;
2416                 ap->ability_match_count = 0;
2417                 ap->ability_match = 0;
2418                 ap->idle_match = 0;
2419                 ap->ack_match = 0;
2420         }
2421         ap->cur_time++;
2422
2423         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2424                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2425
2426                 if (rx_cfg_reg != ap->ability_match_cfg) {
2427                         ap->ability_match_cfg = rx_cfg_reg;
2428                         ap->ability_match = 0;
2429                         ap->ability_match_count = 0;
2430                 } else {
2431                         if (++ap->ability_match_count > 1) {
2432                                 ap->ability_match = 1;
2433                                 ap->ability_match_cfg = rx_cfg_reg;
2434                         }
2435                 }
2436                 if (rx_cfg_reg & ANEG_CFG_ACK)
2437                         ap->ack_match = 1;
2438                 else
2439                         ap->ack_match = 0;
2440
2441                 ap->idle_match = 0;
2442         } else {
2443                 ap->idle_match = 1;
2444                 ap->ability_match_cfg = 0;
2445                 ap->ability_match_count = 0;
2446                 ap->ability_match = 0;
2447                 ap->ack_match = 0;
2448
2449                 rx_cfg_reg = 0;
2450         }
2451
2452         ap->rxconfig = rx_cfg_reg;
2453         ret = ANEG_OK;
2454
2455         switch(ap->state) {
2456         case ANEG_STATE_UNKNOWN:
2457                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2458                         ap->state = ANEG_STATE_AN_ENABLE;
2459
2460                 /* fallthru */
2461         case ANEG_STATE_AN_ENABLE:
2462                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2463                 if (ap->flags & MR_AN_ENABLE) {
2464                         ap->link_time = 0;
2465                         ap->cur_time = 0;
2466                         ap->ability_match_cfg = 0;
2467                         ap->ability_match_count = 0;
2468                         ap->ability_match = 0;
2469                         ap->idle_match = 0;
2470                         ap->ack_match = 0;
2471
2472                         ap->state = ANEG_STATE_RESTART_INIT;
2473                 } else {
2474                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2475                 }
2476                 break;
2477
2478         case ANEG_STATE_RESTART_INIT:
2479                 ap->link_time = ap->cur_time;
2480                 ap->flags &= ~(MR_NP_LOADED);
2481                 ap->txconfig = 0;
2482                 tw32(MAC_TX_AUTO_NEG, 0);
2483                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2484                 tw32_f(MAC_MODE, tp->mac_mode);
2485                 udelay(40);
2486
2487                 ret = ANEG_TIMER_ENAB;
2488                 ap->state = ANEG_STATE_RESTART;
2489
2490                 /* fallthru */
2491         case ANEG_STATE_RESTART:
2492                 delta = ap->cur_time - ap->link_time;
2493                 if (delta > ANEG_STATE_SETTLE_TIME) {
2494                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2495                 } else {
2496                         ret = ANEG_TIMER_ENAB;
2497                 }
2498                 break;
2499
2500         case ANEG_STATE_DISABLE_LINK_OK:
2501                 ret = ANEG_DONE;
2502                 break;
2503
2504         case ANEG_STATE_ABILITY_DETECT_INIT:
2505                 ap->flags &= ~(MR_TOGGLE_TX);
2506                 ap->txconfig = ANEG_CFG_FD;
2507                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2508                 if (flowctrl & ADVERTISE_1000XPAUSE)
2509                         ap->txconfig |= ANEG_CFG_PS1;
2510                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2511                         ap->txconfig |= ANEG_CFG_PS2;
2512                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2513                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2514                 tw32_f(MAC_MODE, tp->mac_mode);
2515                 udelay(40);
2516
2517                 ap->state = ANEG_STATE_ABILITY_DETECT;
2518                 break;
2519
2520         case ANEG_STATE_ABILITY_DETECT:
2521                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2522                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2523                 }
2524                 break;
2525
2526         case ANEG_STATE_ACK_DETECT_INIT:
2527                 ap->txconfig |= ANEG_CFG_ACK;
2528                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2529                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2530                 tw32_f(MAC_MODE, tp->mac_mode);
2531                 udelay(40);
2532
2533                 ap->state = ANEG_STATE_ACK_DETECT;
2534
2535                 /* fallthru */
2536         case ANEG_STATE_ACK_DETECT:
2537                 if (ap->ack_match != 0) {
2538                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2539                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2540                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2541                         } else {
2542                                 ap->state = ANEG_STATE_AN_ENABLE;
2543                         }
2544                 } else if (ap->ability_match != 0 &&
2545                            ap->rxconfig == 0) {
2546                         ap->state = ANEG_STATE_AN_ENABLE;
2547                 }
2548                 break;
2549
2550         case ANEG_STATE_COMPLETE_ACK_INIT:
2551                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2552                         ret = ANEG_FAILED;
2553                         break;
2554                 }
2555                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2556                                MR_LP_ADV_HALF_DUPLEX |
2557                                MR_LP_ADV_SYM_PAUSE |
2558                                MR_LP_ADV_ASYM_PAUSE |
2559                                MR_LP_ADV_REMOTE_FAULT1 |
2560                                MR_LP_ADV_REMOTE_FAULT2 |
2561                                MR_LP_ADV_NEXT_PAGE |
2562                                MR_TOGGLE_RX |
2563                                MR_NP_RX);
2564                 if (ap->rxconfig & ANEG_CFG_FD)
2565                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2566                 if (ap->rxconfig & ANEG_CFG_HD)
2567                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2568                 if (ap->rxconfig & ANEG_CFG_PS1)
2569                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2570                 if (ap->rxconfig & ANEG_CFG_PS2)
2571                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2572                 if (ap->rxconfig & ANEG_CFG_RF1)
2573                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2574                 if (ap->rxconfig & ANEG_CFG_RF2)
2575                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2576                 if (ap->rxconfig & ANEG_CFG_NP)
2577                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2578
2579                 ap->link_time = ap->cur_time;
2580
2581                 ap->flags ^= (MR_TOGGLE_TX);
2582                 if (ap->rxconfig & 0x0008)
2583                         ap->flags |= MR_TOGGLE_RX;
2584                 if (ap->rxconfig & ANEG_CFG_NP)
2585                         ap->flags |= MR_NP_RX;
2586                 ap->flags |= MR_PAGE_RX;
2587
2588                 ap->state = ANEG_STATE_COMPLETE_ACK;
2589                 ret = ANEG_TIMER_ENAB;
2590                 break;
2591
2592         case ANEG_STATE_COMPLETE_ACK:
2593                 if (ap->ability_match != 0 &&
2594                     ap->rxconfig == 0) {
2595                         ap->state = ANEG_STATE_AN_ENABLE;
2596                         break;
2597                 }
2598                 delta = ap->cur_time - ap->link_time;
2599                 if (delta > ANEG_STATE_SETTLE_TIME) {
2600                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2601                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2602                         } else {
2603                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2604                                     !(ap->flags & MR_NP_RX)) {
2605                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2606                                 } else {
2607                                         ret = ANEG_FAILED;
2608                                 }
2609                         }
2610                 }
2611                 break;
2612
2613         case ANEG_STATE_IDLE_DETECT_INIT:
2614                 ap->link_time = ap->cur_time;
2615                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2616                 tw32_f(MAC_MODE, tp->mac_mode);
2617                 udelay(40);
2618
2619                 ap->state = ANEG_STATE_IDLE_DETECT;
2620                 ret = ANEG_TIMER_ENAB;
2621                 break;
2622
2623         case ANEG_STATE_IDLE_DETECT:
2624                 if (ap->ability_match != 0 &&
2625                     ap->rxconfig == 0) {
2626                         ap->state = ANEG_STATE_AN_ENABLE;
2627                         break;
2628                 }
2629                 delta = ap->cur_time - ap->link_time;
2630                 if (delta > ANEG_STATE_SETTLE_TIME) {
2631                         /* XXX another gem from the Broadcom driver :( */
2632                         ap->state = ANEG_STATE_LINK_OK;
2633                 }
2634                 break;
2635
2636         case ANEG_STATE_LINK_OK:
2637                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2638                 ret = ANEG_DONE;
2639                 break;
2640
2641         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2642                 /* ??? unimplemented */
2643                 break;
2644
2645         case ANEG_STATE_NEXT_PAGE_WAIT:
2646                 /* ??? unimplemented */
2647                 break;
2648
2649         default:
2650                 ret = ANEG_FAILED;
2651                 break;
2652         };
2653
2654         return ret;
2655 }
2656
2657 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
2658 {
2659         int res = 0;
2660         struct tg3_fiber_aneginfo aninfo;
2661         int status = ANEG_FAILED;
2662         unsigned int tick;
2663         u32 tmp;
2664
2665         tw32_f(MAC_TX_AUTO_NEG, 0);
2666
2667         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2668         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2669         udelay(40);
2670
2671         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2672         udelay(40);
2673
2674         memset(&aninfo, 0, sizeof(aninfo));
2675         aninfo.flags |= MR_AN_ENABLE;
2676         aninfo.state = ANEG_STATE_UNKNOWN;
2677         aninfo.cur_time = 0;
2678         tick = 0;
2679         while (++tick < 195000) {
2680                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2681                 if (status == ANEG_DONE || status == ANEG_FAILED)
2682                         break;
2683
2684                 udelay(1);
2685         }
2686
2687         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2688         tw32_f(MAC_MODE, tp->mac_mode);
2689         udelay(40);
2690
2691         *txflags = aninfo.txconfig;
2692         *rxflags = aninfo.flags;
2693
2694         if (status == ANEG_DONE &&
2695             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2696                              MR_LP_ADV_FULL_DUPLEX)))
2697                 res = 1;
2698
2699         return res;
2700 }
2701
2702 static void tg3_init_bcm8002(struct tg3 *tp)
2703 {
2704         u32 mac_status = tr32(MAC_STATUS);
2705         int i;
2706
2707         /* Reset when initting first time or we have a link. */
2708         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2709             !(mac_status & MAC_STATUS_PCS_SYNCED))
2710                 return;
2711
2712         /* Set PLL lock range. */
2713         tg3_writephy(tp, 0x16, 0x8007);
2714
2715         /* SW reset */
2716         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2717
2718         /* Wait for reset to complete. */
2719         /* XXX schedule_timeout() ... */
2720         for (i = 0; i < 500; i++)
2721                 udelay(10);
2722
2723         /* Config mode; select PMA/Ch 1 regs. */
2724         tg3_writephy(tp, 0x10, 0x8411);
2725
2726         /* Enable auto-lock and comdet, select txclk for tx. */
2727         tg3_writephy(tp, 0x11, 0x0a10);
2728
2729         tg3_writephy(tp, 0x18, 0x00a0);
2730         tg3_writephy(tp, 0x16, 0x41ff);
2731
2732         /* Assert and deassert POR. */
2733         tg3_writephy(tp, 0x13, 0x0400);
2734         udelay(40);
2735         tg3_writephy(tp, 0x13, 0x0000);
2736
2737         tg3_writephy(tp, 0x11, 0x0a50);
2738         udelay(40);
2739         tg3_writephy(tp, 0x11, 0x0a10);
2740
2741         /* Wait for signal to stabilize */
2742         /* XXX schedule_timeout() ... */
2743         for (i = 0; i < 15000; i++)
2744                 udelay(10);
2745
2746         /* Deselect the channel register so we can read the PHYID
2747          * later.
2748          */
2749         tg3_writephy(tp, 0x10, 0x8011);
2750 }
2751
2752 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2753 {
2754         u16 flowctrl;
2755         u32 sg_dig_ctrl, sg_dig_status;
2756         u32 serdes_cfg, expected_sg_dig_ctrl;
2757         int workaround, port_a;
2758         int current_link_up;
2759
2760         serdes_cfg = 0;
2761         expected_sg_dig_ctrl = 0;
2762         workaround = 0;
2763         port_a = 1;
2764         current_link_up = 0;
2765
2766         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2767             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2768                 workaround = 1;
2769                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2770                         port_a = 0;
2771
2772                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2773                 /* preserve bits 20-23 for voltage regulator */
2774                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2775         }
2776
2777         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2778
2779         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2780                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
2781                         if (workaround) {
2782                                 u32 val = serdes_cfg;
2783
2784                                 if (port_a)
2785                                         val |= 0xc010000;
2786                                 else
2787                                         val |= 0x4010000;
2788                                 tw32_f(MAC_SERDES_CFG, val);
2789                         }
2790
2791                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
2792                 }
2793                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2794                         tg3_setup_flow_control(tp, 0, 0);
2795                         current_link_up = 1;
2796                 }
2797                 goto out;
2798         }
2799
2800         /* Want auto-negotiation.  */
2801         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
2802
2803         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2804         if (flowctrl & ADVERTISE_1000XPAUSE)
2805                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
2806         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2807                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
2808
2809         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2810                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2811                     tp->serdes_counter &&
2812                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2813                                     MAC_STATUS_RCVD_CFG)) ==
2814                      MAC_STATUS_PCS_SYNCED)) {
2815                         tp->serdes_counter--;
2816                         current_link_up = 1;
2817                         goto out;
2818                 }
2819 restart_autoneg:
2820                 if (workaround)
2821                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2822                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
2823                 udelay(5);
2824                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2825
2826                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2827                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2828         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2829                                  MAC_STATUS_SIGNAL_DET)) {
2830                 sg_dig_status = tr32(SG_DIG_STATUS);
2831                 mac_status = tr32(MAC_STATUS);
2832
2833                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
2834                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2835                         u32 local_adv = 0, remote_adv = 0;
2836
2837                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
2838                                 local_adv |= ADVERTISE_1000XPAUSE;
2839                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
2840                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
2841
2842                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
2843                                 remote_adv |= LPA_1000XPAUSE;
2844                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
2845                                 remote_adv |= LPA_1000XPAUSE_ASYM;
2846
2847                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2848                         current_link_up = 1;
2849                         tp->serdes_counter = 0;
2850                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2851                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
2852                         if (tp->serdes_counter)
2853                                 tp->serdes_counter--;
2854                         else {
2855                                 if (workaround) {
2856                                         u32 val = serdes_cfg;
2857
2858                                         if (port_a)
2859                                                 val |= 0xc010000;
2860                                         else
2861                                                 val |= 0x4010000;
2862
2863                                         tw32_f(MAC_SERDES_CFG, val);
2864                                 }
2865
2866                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
2867                                 udelay(40);
2868
2869                                 /* Link parallel detection - link is up */
2870                                 /* only if we have PCS_SYNC and not */
2871                                 /* receiving config code words */
2872                                 mac_status = tr32(MAC_STATUS);
2873                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2874                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2875                                         tg3_setup_flow_control(tp, 0, 0);
2876                                         current_link_up = 1;
2877                                         tp->tg3_flags2 |=
2878                                                 TG3_FLG2_PARALLEL_DETECT;
2879                                         tp->serdes_counter =
2880                                                 SERDES_PARALLEL_DET_TIMEOUT;
2881                                 } else
2882                                         goto restart_autoneg;
2883                         }
2884                 }
2885         } else {
2886                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2887                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2888         }
2889
2890 out:
2891         return current_link_up;
2892 }
2893
2894 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2895 {
2896         int current_link_up = 0;
2897
2898         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2899                 goto out;
2900
2901         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2902                 u32 txflags, rxflags;
2903                 int i;
2904
2905                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
2906                         u32 local_adv = 0, remote_adv = 0;
2907
2908                         if (txflags & ANEG_CFG_PS1)
2909                                 local_adv |= ADVERTISE_1000XPAUSE;
2910                         if (txflags & ANEG_CFG_PS2)
2911                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
2912
2913                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
2914                                 remote_adv |= LPA_1000XPAUSE;
2915                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
2916                                 remote_adv |= LPA_1000XPAUSE_ASYM;
2917
2918                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2919
2920                         current_link_up = 1;
2921                 }
2922                 for (i = 0; i < 30; i++) {
2923                         udelay(20);
2924                         tw32_f(MAC_STATUS,
2925                                (MAC_STATUS_SYNC_CHANGED |
2926                                 MAC_STATUS_CFG_CHANGED));
2927                         udelay(40);
2928                         if ((tr32(MAC_STATUS) &
2929                              (MAC_STATUS_SYNC_CHANGED |
2930                               MAC_STATUS_CFG_CHANGED)) == 0)
2931                                 break;
2932                 }
2933
2934                 mac_status = tr32(MAC_STATUS);
2935                 if (current_link_up == 0 &&
2936                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2937                     !(mac_status & MAC_STATUS_RCVD_CFG))
2938                         current_link_up = 1;
2939         } else {
2940                 tg3_setup_flow_control(tp, 0, 0);
2941
2942                 /* Forcing 1000FD link up. */
2943                 current_link_up = 1;
2944
2945                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2946                 udelay(40);
2947
2948                 tw32_f(MAC_MODE, tp->mac_mode);
2949                 udelay(40);
2950         }
2951
2952 out:
2953         return current_link_up;
2954 }
2955
2956 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2957 {
2958         u32 orig_pause_cfg;
2959         u16 orig_active_speed;
2960         u8 orig_active_duplex;
2961         u32 mac_status;
2962         int current_link_up;
2963         int i;
2964
2965         orig_pause_cfg = tp->link_config.active_flowctrl;
2966         orig_active_speed = tp->link_config.active_speed;
2967         orig_active_duplex = tp->link_config.active_duplex;
2968
2969         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2970             netif_carrier_ok(tp->dev) &&
2971             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2972                 mac_status = tr32(MAC_STATUS);
2973                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2974                                MAC_STATUS_SIGNAL_DET |
2975                                MAC_STATUS_CFG_CHANGED |
2976                                MAC_STATUS_RCVD_CFG);
2977                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2978                                    MAC_STATUS_SIGNAL_DET)) {
2979                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2980                                             MAC_STATUS_CFG_CHANGED));
2981                         return 0;
2982                 }
2983         }
2984
2985         tw32_f(MAC_TX_AUTO_NEG, 0);
2986
2987         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2988         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2989         tw32_f(MAC_MODE, tp->mac_mode);
2990         udelay(40);
2991
2992         if (tp->phy_id == PHY_ID_BCM8002)
2993                 tg3_init_bcm8002(tp);
2994
2995         /* Enable link change event even when serdes polling.  */
2996         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2997         udelay(40);
2998
2999         current_link_up = 0;
3000         mac_status = tr32(MAC_STATUS);
3001
3002         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3003                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3004         else
3005                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3006
3007         tp->hw_status->status =
3008                 (SD_STATUS_UPDATED |
3009                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3010
3011         for (i = 0; i < 100; i++) {
3012                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3013                                     MAC_STATUS_CFG_CHANGED));
3014                 udelay(5);
3015                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3016                                          MAC_STATUS_CFG_CHANGED |
3017                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3018                         break;
3019         }
3020
3021         mac_status = tr32(MAC_STATUS);
3022         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3023                 current_link_up = 0;
3024                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3025                     tp->serdes_counter == 0) {
3026                         tw32_f(MAC_MODE, (tp->mac_mode |
3027                                           MAC_MODE_SEND_CONFIGS));
3028                         udelay(1);
3029                         tw32_f(MAC_MODE, tp->mac_mode);
3030                 }
3031         }
3032
3033         if (current_link_up == 1) {
3034                 tp->link_config.active_speed = SPEED_1000;
3035                 tp->link_config.active_duplex = DUPLEX_FULL;
3036                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3037                                     LED_CTRL_LNKLED_OVERRIDE |
3038                                     LED_CTRL_1000MBPS_ON));
3039         } else {
3040                 tp->link_config.active_speed = SPEED_INVALID;
3041                 tp->link_config.active_duplex = DUPLEX_INVALID;
3042                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3043                                     LED_CTRL_LNKLED_OVERRIDE |
3044                                     LED_CTRL_TRAFFIC_OVERRIDE));
3045         }
3046
3047         if (current_link_up != netif_carrier_ok(tp->dev)) {
3048                 if (current_link_up)
3049                         netif_carrier_on(tp->dev);
3050                 else
3051                         netif_carrier_off(tp->dev);
3052                 tg3_link_report(tp);
3053         } else {
3054                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3055                 if (orig_pause_cfg != now_pause_cfg ||
3056                     orig_active_speed != tp->link_config.active_speed ||
3057                     orig_active_duplex != tp->link_config.active_duplex)
3058                         tg3_link_report(tp);
3059         }
3060
3061         return 0;
3062 }
3063
3064 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3065 {
3066         int current_link_up, err = 0;
3067         u32 bmsr, bmcr;
3068         u16 current_speed;
3069         u8 current_duplex;
3070         u32 local_adv, remote_adv;
3071
3072         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3073         tw32_f(MAC_MODE, tp->mac_mode);
3074         udelay(40);
3075
3076         tw32(MAC_EVENT, 0);
3077
3078         tw32_f(MAC_STATUS,
3079              (MAC_STATUS_SYNC_CHANGED |
3080               MAC_STATUS_CFG_CHANGED |
3081               MAC_STATUS_MI_COMPLETION |
3082               MAC_STATUS_LNKSTATE_CHANGED));
3083         udelay(40);
3084
3085         if (force_reset)
3086                 tg3_phy_reset(tp);
3087
3088         current_link_up = 0;
3089         current_speed = SPEED_INVALID;
3090         current_duplex = DUPLEX_INVALID;
3091
3092         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3093         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3094         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3095                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3096                         bmsr |= BMSR_LSTATUS;
3097                 else
3098                         bmsr &= ~BMSR_LSTATUS;
3099         }
3100
3101         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3102
3103         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3104             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3105              tp->link_config.flowctrl == tp->link_config.active_flowctrl) {
3106                 /* do nothing, just check for link up at the end */
3107         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3108                 u32 adv, new_adv;
3109
3110                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3111                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3112                                   ADVERTISE_1000XPAUSE |
3113                                   ADVERTISE_1000XPSE_ASYM |
3114                                   ADVERTISE_SLCT);
3115
3116                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3117
3118                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3119                         new_adv |= ADVERTISE_1000XHALF;
3120                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3121                         new_adv |= ADVERTISE_1000XFULL;
3122
3123                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3124                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3125                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3126                         tg3_writephy(tp, MII_BMCR, bmcr);
3127
3128                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3129                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3130                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3131
3132                         return err;
3133                 }
3134         } else {
3135                 u32 new_bmcr;
3136
3137                 bmcr &= ~BMCR_SPEED1000;
3138                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3139
3140                 if (tp->link_config.duplex == DUPLEX_FULL)
3141                         new_bmcr |= BMCR_FULLDPLX;
3142
3143                 if (new_bmcr != bmcr) {
3144                         /* BMCR_SPEED1000 is a reserved bit that needs
3145                          * to be set on write.
3146                          */
3147                         new_bmcr |= BMCR_SPEED1000;
3148
3149                         /* Force a linkdown */
3150                         if (netif_carrier_ok(tp->dev)) {
3151                                 u32 adv;
3152
3153                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3154                                 adv &= ~(ADVERTISE_1000XFULL |
3155                                          ADVERTISE_1000XHALF |
3156                                          ADVERTISE_SLCT);
3157                                 tg3_writephy(tp, MII_ADVERTISE, adv);
3158                                 tg3_writephy(tp, MII_BMCR, bmcr |
3159                                                            BMCR_ANRESTART |
3160                                                            BMCR_ANENABLE);
3161                                 udelay(10);
3162                                 netif_carrier_off(tp->dev);
3163                         }
3164                         tg3_writephy(tp, MII_BMCR, new_bmcr);
3165                         bmcr = new_bmcr;
3166                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3167                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3168                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3169                             ASIC_REV_5714) {
3170                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3171                                         bmsr |= BMSR_LSTATUS;
3172                                 else
3173                                         bmsr &= ~BMSR_LSTATUS;
3174                         }
3175                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3176                 }
3177         }
3178
3179         if (bmsr & BMSR_LSTATUS) {
3180                 current_speed = SPEED_1000;
3181                 current_link_up = 1;
3182                 if (bmcr & BMCR_FULLDPLX)
3183                         current_duplex = DUPLEX_FULL;
3184                 else
3185                         current_duplex = DUPLEX_HALF;
3186
3187                 local_adv = 0;
3188                 remote_adv = 0;
3189
3190                 if (bmcr & BMCR_ANENABLE) {
3191                         u32 common;
3192
3193                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3194                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3195                         common = local_adv & remote_adv;
3196                         if (common & (ADVERTISE_1000XHALF |
3197                                       ADVERTISE_1000XFULL)) {
3198                                 if (common & ADVERTISE_1000XFULL)
3199                                         current_duplex = DUPLEX_FULL;
3200                                 else
3201                                         current_duplex = DUPLEX_HALF;
3202                         }
3203                         else
3204                                 current_link_up = 0;
3205                 }
3206         }
3207
3208         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3209                 tg3_setup_flow_control(tp, local_adv, remote_adv);
3210
3211         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3212         if (tp->link_config.active_duplex == DUPLEX_HALF)
3213                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3214
3215         tw32_f(MAC_MODE, tp->mac_mode);
3216         udelay(40);
3217
3218         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3219
3220         tp->link_config.active_speed = current_speed;
3221         tp->link_config.active_duplex = current_duplex;
3222
3223         if (current_link_up != netif_carrier_ok(tp->dev)) {
3224                 if (current_link_up)
3225                         netif_carrier_on(tp->dev);
3226                 else {
3227                         netif_carrier_off(tp->dev);
3228                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3229                 }
3230                 tg3_link_report(tp);
3231         }
3232         return err;
3233 }
3234
3235 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3236 {
3237         if (tp->serdes_counter) {
3238                 /* Give autoneg time to complete. */
3239                 tp->serdes_counter--;
3240                 return;
3241         }
3242         if (!netif_carrier_ok(tp->dev) &&
3243             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3244                 u32 bmcr;
3245
3246                 tg3_readphy(tp, MII_BMCR, &bmcr);
3247                 if (bmcr & BMCR_ANENABLE) {
3248                         u32 phy1, phy2;
3249
3250                         /* Select shadow register 0x1f */
3251                         tg3_writephy(tp, 0x1c, 0x7c00);
3252                         tg3_readphy(tp, 0x1c, &phy1);
3253
3254                         /* Select expansion interrupt status register */
3255                         tg3_writephy(tp, 0x17, 0x0f01);
3256                         tg3_readphy(tp, 0x15, &phy2);
3257                         tg3_readphy(tp, 0x15, &phy2);
3258
3259                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3260                                 /* We have signal detect and not receiving
3261                                  * config code words, link is up by parallel
3262                                  * detection.
3263                                  */
3264
3265                                 bmcr &= ~BMCR_ANENABLE;
3266                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3267                                 tg3_writephy(tp, MII_BMCR, bmcr);
3268                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3269                         }
3270                 }
3271         }
3272         else if (netif_carrier_ok(tp->dev) &&
3273                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3274                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3275                 u32 phy2;
3276
3277                 /* Select expansion interrupt status register */
3278                 tg3_writephy(tp, 0x17, 0x0f01);
3279                 tg3_readphy(tp, 0x15, &phy2);
3280                 if (phy2 & 0x20) {
3281                         u32 bmcr;
3282
3283                         /* Config code words received, turn on autoneg. */
3284                         tg3_readphy(tp, MII_BMCR, &bmcr);
3285                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3286
3287                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3288
3289                 }
3290         }
3291 }
3292
3293 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3294 {
3295         int err;
3296
3297         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3298                 err = tg3_setup_fiber_phy(tp, force_reset);
3299         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3300                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3301         } else {
3302                 err = tg3_setup_copper_phy(tp, force_reset);
3303         }
3304
3305         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3306             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3307                 u32 val, scale;
3308
3309                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3310                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3311                         scale = 65;
3312                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3313                         scale = 6;
3314                 else
3315                         scale = 12;
3316
3317                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3318                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3319                 tw32(GRC_MISC_CFG, val);
3320         }
3321
3322         if (tp->link_config.active_speed == SPEED_1000 &&
3323             tp->link_config.active_duplex == DUPLEX_HALF)
3324                 tw32(MAC_TX_LENGTHS,
3325                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3326                       (6 << TX_LENGTHS_IPG_SHIFT) |
3327                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3328         else
3329                 tw32(MAC_TX_LENGTHS,
3330                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3331                       (6 << TX_LENGTHS_IPG_SHIFT) |
3332                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3333
3334         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3335                 if (netif_carrier_ok(tp->dev)) {
3336                         tw32(HOSTCC_STAT_COAL_TICKS,
3337                              tp->coal.stats_block_coalesce_usecs);
3338                 } else {
3339                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3340                 }
3341         }
3342
3343         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3344                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3345                 if (!netif_carrier_ok(tp->dev))
3346                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3347                               tp->pwrmgmt_thresh;
3348                 else
3349                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3350                 tw32(PCIE_PWR_MGMT_THRESH, val);
3351         }
3352
3353         return err;
3354 }
3355
3356 /* This is called whenever we suspect that the system chipset is re-
3357  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3358  * is bogus tx completions. We try to recover by setting the
3359  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3360  * in the workqueue.
3361  */
3362 static void tg3_tx_recover(struct tg3 *tp)
3363 {
3364         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3365                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3366
3367         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3368                "mapped I/O cycles to the network device, attempting to "
3369                "recover. Please report the problem to the driver maintainer "
3370                "and include system chipset information.\n", tp->dev->name);
3371
3372         spin_lock(&tp->lock);
3373         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3374         spin_unlock(&tp->lock);
3375 }
3376
3377 static inline u32 tg3_tx_avail(struct tg3 *tp)
3378 {
3379         smp_mb();
3380         return (tp->tx_pending -
3381                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3382 }
3383
3384 /* Tigon3 never reports partial packet sends.  So we do not
3385  * need special logic to handle SKBs that have not had all
3386  * of their frags sent yet, like SunGEM does.
3387  */
3388 static void tg3_tx(struct tg3 *tp)
3389 {
3390         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3391         u32 sw_idx = tp->tx_cons;
3392
3393         while (sw_idx != hw_idx) {
3394                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3395                 struct sk_buff *skb = ri->skb;
3396                 int i, tx_bug = 0;
3397
3398                 if (unlikely(skb == NULL)) {
3399                         tg3_tx_recover(tp);
3400                         return;
3401                 }
3402
3403                 pci_unmap_single(tp->pdev,
3404                                  pci_unmap_addr(ri, mapping),
3405                                  skb_headlen(skb),
3406                                  PCI_DMA_TODEVICE);
3407
3408                 ri->skb = NULL;
3409
3410                 sw_idx = NEXT_TX(sw_idx);
3411
3412                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3413                         ri = &tp->tx_buffers[sw_idx];
3414                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3415                                 tx_bug = 1;
3416
3417                         pci_unmap_page(tp->pdev,
3418                                        pci_unmap_addr(ri, mapping),
3419                                        skb_shinfo(skb)->frags[i].size,
3420                                        PCI_DMA_TODEVICE);
3421
3422                         sw_idx = NEXT_TX(sw_idx);
3423                 }
3424
3425                 dev_kfree_skb(skb);
3426
3427                 if (unlikely(tx_bug)) {
3428                         tg3_tx_recover(tp);
3429                         return;
3430                 }
3431         }
3432
3433         tp->tx_cons = sw_idx;
3434
3435         /* Need to make the tx_cons update visible to tg3_start_xmit()
3436          * before checking for netif_queue_stopped().  Without the
3437          * memory barrier, there is a small possibility that tg3_start_xmit()
3438          * will miss it and cause the queue to be stopped forever.
3439          */
3440         smp_mb();
3441
3442         if (unlikely(netif_queue_stopped(tp->dev) &&
3443                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3444                 netif_tx_lock(tp->dev);
3445                 if (netif_queue_stopped(tp->dev) &&
3446                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3447                         netif_wake_queue(tp->dev);
3448                 netif_tx_unlock(tp->dev);
3449         }
3450 }
3451
3452 /* Returns size of skb allocated or < 0 on error.
3453  *
3454  * We only need to fill in the address because the other members
3455  * of the RX descriptor are invariant, see tg3_init_rings.
3456  *
3457  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3458  * posting buffers we only dirty the first cache line of the RX
3459  * descriptor (containing the address).  Whereas for the RX status
3460  * buffers the cpu only reads the last cacheline of the RX descriptor
3461  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3462  */
3463 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3464                             int src_idx, u32 dest_idx_unmasked)
3465 {
3466         struct tg3_rx_buffer_desc *desc;
3467         struct ring_info *map, *src_map;
3468         struct sk_buff *skb;
3469         dma_addr_t mapping;
3470         int skb_size, dest_idx;
3471
3472         src_map = NULL;
3473         switch (opaque_key) {
3474         case RXD_OPAQUE_RING_STD:
3475                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3476                 desc = &tp->rx_std[dest_idx];
3477                 map = &tp->rx_std_buffers[dest_idx];
3478                 if (src_idx >= 0)
3479                         src_map = &tp->rx_std_buffers[src_idx];
3480                 skb_size = tp->rx_pkt_buf_sz;
3481                 break;
3482
3483         case RXD_OPAQUE_RING_JUMBO:
3484                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3485                 desc = &tp->rx_jumbo[dest_idx];
3486                 map = &tp->rx_jumbo_buffers[dest_idx];
3487                 if (src_idx >= 0)
3488                         src_map = &tp->rx_jumbo_buffers[src_idx];
3489                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3490                 break;
3491
3492         default:
3493                 return -EINVAL;
3494         };
3495
3496         /* Do not overwrite any of the map or rp information
3497          * until we are sure we can commit to a new buffer.
3498          *
3499          * Callers depend upon this behavior and assume that
3500          * we leave everything unchanged if we fail.
3501          */
3502         skb = netdev_alloc_skb(tp->dev, skb_size);
3503         if (skb == NULL)
3504                 return -ENOMEM;
3505
3506         skb_reserve(skb, tp->rx_offset);
3507
3508         mapping = pci_map_single(tp->pdev, skb->data,
3509                                  skb_size - tp->rx_offset,
3510                                  PCI_DMA_FROMDEVICE);
3511
3512         map->skb = skb;
3513         pci_unmap_addr_set(map, mapping, mapping);
3514
3515         if (src_map != NULL)
3516                 src_map->skb = NULL;
3517
3518         desc->addr_hi = ((u64)mapping >> 32);
3519         desc->addr_lo = ((u64)mapping & 0xffffffff);
3520
3521         return skb_size;
3522 }
3523
3524 /* We only need to move over in the address because the other
3525  * members of the RX descriptor are invariant.  See notes above
3526  * tg3_alloc_rx_skb for full details.
3527  */
3528 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3529                            int src_idx, u32 dest_idx_unmasked)
3530 {
3531         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3532         struct ring_info *src_map, *dest_map;
3533         int dest_idx;
3534
3535         switch (opaque_key) {
3536         case RXD_OPAQUE_RING_STD:
3537                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3538                 dest_desc = &tp->rx_std[dest_idx];
3539                 dest_map = &tp->rx_std_buffers[dest_idx];
3540                 src_desc = &tp->rx_std[src_idx];
3541                 src_map = &tp->rx_std_buffers[src_idx];
3542                 break;
3543
3544         case RXD_OPAQUE_RING_JUMBO:
3545                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3546                 dest_desc = &tp->rx_jumbo[dest_idx];
3547                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3548                 src_desc = &tp->rx_jumbo[src_idx];
3549                 src_map = &tp->rx_jumbo_buffers[src_idx];
3550                 break;
3551
3552         default:
3553                 return;
3554         };
3555
3556         dest_map->skb = src_map->skb;
3557         pci_unmap_addr_set(dest_map, mapping,
3558                            pci_unmap_addr(src_map, mapping));
3559         dest_desc->addr_hi = src_desc->addr_hi;
3560         dest_desc->addr_lo = src_desc->addr_lo;
3561
3562         src_map->skb = NULL;
3563 }
3564
3565 #if TG3_VLAN_TAG_USED
3566 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3567 {
3568         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3569 }
3570 #endif
3571
3572 /* The RX ring scheme is composed of multiple rings which post fresh
3573  * buffers to the chip, and one special ring the chip uses to report
3574  * status back to the host.
3575  *
3576  * The special ring reports the status of received packets to the
3577  * host.  The chip does not write into the original descriptor the
3578  * RX buffer was obtained from.  The chip simply takes the original
3579  * descriptor as provided by the host, updates the status and length
3580  * field, then writes this into the next status ring entry.
3581  *
3582  * Each ring the host uses to post buffers to the chip is described
3583  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3584  * it is first placed into the on-chip ram.  When the packet's length
3585  * is known, it walks down the TG3_BDINFO entries to select the ring.
3586  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3587  * which is within the range of the new packet's length is chosen.
3588  *
3589  * The "separate ring for rx status" scheme may sound queer, but it makes
3590  * sense from a cache coherency perspective.  If only the host writes
3591  * to the buffer post rings, and only the chip writes to the rx status
3592  * rings, then cache lines never move beyond shared-modified state.
3593  * If both the host and chip were to write into the same ring, cache line
3594  * eviction could occur since both entities want it in an exclusive state.
3595  */
3596 static int tg3_rx(struct tg3 *tp, int budget)
3597 {
3598         u32 work_mask, rx_std_posted = 0;
3599         u32 sw_idx = tp->rx_rcb_ptr;
3600         u16 hw_idx;
3601         int received;
3602
3603         hw_idx = tp->hw_status->idx[0].rx_producer;
3604         /*
3605          * We need to order the read of hw_idx and the read of
3606          * the opaque cookie.
3607          */
3608         rmb();
3609         work_mask = 0;
3610         received = 0;
3611         while (sw_idx != hw_idx && budget > 0) {
3612                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3613                 unsigned int len;
3614                 struct sk_buff *skb;
3615                 dma_addr_t dma_addr;
3616                 u32 opaque_key, desc_idx, *post_ptr;
3617
3618                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3619                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3620                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3621                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3622                                                   mapping);
3623                         skb = tp->rx_std_buffers[desc_idx].skb;
3624                         post_ptr = &tp->rx_std_ptr;
3625                         rx_std_posted++;
3626                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3627                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3628                                                   mapping);
3629                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3630                         post_ptr = &tp->rx_jumbo_ptr;
3631                 }
3632                 else {
3633                         goto next_pkt_nopost;
3634                 }
3635
3636                 work_mask |= opaque_key;
3637
3638                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3639                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3640                 drop_it:
3641                         tg3_recycle_rx(tp, opaque_key,
3642                                        desc_idx, *post_ptr);
3643                 drop_it_no_recycle:
3644                         /* Other statistics kept track of by card. */
3645                         tp->net_stats.rx_dropped++;
3646                         goto next_pkt;
3647                 }
3648
3649                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3650
3651                 if (len > RX_COPY_THRESHOLD
3652                         && tp->rx_offset == 2
3653                         /* rx_offset != 2 iff this is a 5701 card running
3654                          * in PCI-X mode [see tg3_get_invariants()] */
3655                 ) {
3656                         int skb_size;
3657
3658                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3659                                                     desc_idx, *post_ptr);
3660                         if (skb_size < 0)
3661                                 goto drop_it;
3662
3663                         pci_unmap_single(tp->pdev, dma_addr,
3664                                          skb_size - tp->rx_offset,
3665                                          PCI_DMA_FROMDEVICE);
3666
3667                         skb_put(skb, len);
3668                 } else {
3669                         struct sk_buff *copy_skb;
3670
3671                         tg3_recycle_rx(tp, opaque_key,
3672                                        desc_idx, *post_ptr);
3673
3674                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3675                         if (copy_skb == NULL)
3676                                 goto drop_it_no_recycle;
3677
3678                         skb_reserve(copy_skb, 2);
3679                         skb_put(copy_skb, len);
3680                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3681                         skb_copy_from_linear_data(skb, copy_skb->data, len);
3682                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3683
3684                         /* We'll reuse the original ring buffer. */
3685                         skb = copy_skb;
3686                 }
3687
3688                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3689                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3690                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3691                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3692                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3693                 else
3694                         skb->ip_summed = CHECKSUM_NONE;
3695
3696                 skb->protocol = eth_type_trans(skb, tp->dev);
3697 #if TG3_VLAN_TAG_USED
3698                 if (tp->vlgrp != NULL &&
3699                     desc->type_flags & RXD_FLAG_VLAN) {
3700                         tg3_vlan_rx(tp, skb,
3701                                     desc->err_vlan & RXD_VLAN_MASK);
3702                 } else
3703 #endif
3704                         netif_receive_skb(skb);
3705
3706                 tp->dev->last_rx = jiffies;
3707                 received++;
3708                 budget--;
3709
3710 next_pkt:
3711                 (*post_ptr)++;
3712
3713                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3714                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3715
3716                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3717                                      TG3_64BIT_REG_LOW, idx);
3718                         work_mask &= ~RXD_OPAQUE_RING_STD;
3719                         rx_std_posted = 0;
3720                 }
3721 next_pkt_nopost:
3722                 sw_idx++;
3723                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3724
3725                 /* Refresh hw_idx to see if there is new work */
3726                 if (sw_idx == hw_idx) {
3727                         hw_idx = tp->hw_status->idx[0].rx_producer;
3728                         rmb();
3729                 }
3730         }
3731
3732         /* ACK the status ring. */
3733         tp->rx_rcb_ptr = sw_idx;
3734         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3735
3736         /* Refill RX ring(s). */
3737         if (work_mask & RXD_OPAQUE_RING_STD) {
3738                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3739                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3740                              sw_idx);
3741         }
3742         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3743                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3744                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3745                              sw_idx);
3746         }
3747         mmiowb();
3748
3749         return received;
3750 }
3751
3752 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
3753 {
3754         struct tg3_hw_status *sblk = tp->hw_status;
3755
3756         /* handle link change and other phy events */
3757         if (!(tp->tg3_flags &
3758               (TG3_FLAG_USE_LINKCHG_REG |
3759                TG3_FLAG_POLL_SERDES))) {
3760                 if (sblk->status & SD_STATUS_LINK_CHG) {
3761                         sblk->status = SD_STATUS_UPDATED |
3762                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3763                         spin_lock(&tp->lock);
3764                         tg3_setup_phy(tp, 0);
3765                         spin_unlock(&tp->lock);
3766                 }
3767         }
3768
3769         /* run TX completion thread */
3770         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3771                 tg3_tx(tp);
3772                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3773                         return work_done;
3774         }
3775
3776         /* run RX thread, within the bounds set by NAPI.
3777          * All RX "locking" is done by ensuring outside
3778          * code synchronizes with tg3->napi.poll()
3779          */
3780         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
3781                 work_done += tg3_rx(tp, budget - work_done);
3782
3783         return work_done;
3784 }
3785
3786 static int tg3_poll(struct napi_struct *napi, int budget)
3787 {
3788         struct tg3 *tp = container_of(napi, struct tg3, napi);
3789         int work_done = 0;
3790         struct tg3_hw_status *sblk = tp->hw_status;
3791
3792         while (1) {
3793                 work_done = tg3_poll_work(tp, work_done, budget);
3794
3795                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3796                         goto tx_recovery;
3797
3798                 if (unlikely(work_done >= budget))
3799                         break;
3800
3801                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3802                         /* tp->last_tag is used in tg3_restart_ints() below
3803                          * to tell the hw how much work has been processed,
3804                          * so we must read it before checking for more work.
3805                          */
3806                         tp->last_tag = sblk->status_tag;
3807                         rmb();
3808                 } else
3809                         sblk->status &= ~SD_STATUS_UPDATED;
3810
3811                 if (likely(!tg3_has_work(tp))) {
3812                         netif_rx_complete(tp->dev, napi);
3813                         tg3_restart_ints(tp);
3814                         break;
3815                 }
3816         }
3817
3818         return work_done;
3819
3820 tx_recovery:
3821         /* work_done is guaranteed to be less than budget. */
3822         netif_rx_complete(tp->dev, napi);
3823         schedule_work(&tp->reset_task);
3824         return work_done;
3825 }
3826
3827 static void tg3_irq_quiesce(struct tg3 *tp)
3828 {
3829         BUG_ON(tp->irq_sync);
3830
3831         tp->irq_sync = 1;
3832         smp_mb();
3833
3834         synchronize_irq(tp->pdev->irq);
3835 }
3836
3837 static inline int tg3_irq_sync(struct tg3 *tp)
3838 {
3839         return tp->irq_sync;
3840 }
3841
3842 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3843  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3844  * with as well.  Most of the time, this is not necessary except when
3845  * shutting down the device.
3846  */
3847 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3848 {
3849         spin_lock_bh(&tp->lock);
3850         if (irq_sync)
3851                 tg3_irq_quiesce(tp);
3852 }
3853
3854 static inline void tg3_full_unlock(struct tg3 *tp)
3855 {
3856         spin_unlock_bh(&tp->lock);
3857 }
3858
3859 /* One-shot MSI handler - Chip automatically disables interrupt
3860  * after sending MSI so driver doesn't have to do it.
3861  */
3862 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3863 {
3864         struct net_device *dev = dev_id;
3865         struct tg3 *tp = netdev_priv(dev);
3866
3867         prefetch(tp->hw_status);
3868         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3869
3870         if (likely(!tg3_irq_sync(tp)))
3871                 netif_rx_schedule(dev, &tp->napi);
3872
3873         return IRQ_HANDLED;
3874 }
3875
3876 /* MSI ISR - No need to check for interrupt sharing and no need to
3877  * flush status block and interrupt mailbox. PCI ordering rules
3878  * guarantee that MSI will arrive after the status block.
3879  */
3880 static irqreturn_t tg3_msi(int irq, void *dev_id)
3881 {
3882         struct net_device *dev = dev_id;
3883         struct tg3 *tp = netdev_priv(dev);
3884
3885         prefetch(tp->hw_status);
3886         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3887         /*
3888          * Writing any value to intr-mbox-0 clears PCI INTA# and
3889          * chip-internal interrupt pending events.
3890          * Writing non-zero to intr-mbox-0 additional tells the
3891          * NIC to stop sending us irqs, engaging "in-intr-handler"
3892          * event coalescing.
3893          */
3894         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3895         if (likely(!tg3_irq_sync(tp)))
3896                 netif_rx_schedule(dev, &tp->napi);
3897
3898         return IRQ_RETVAL(1);
3899 }
3900
3901 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3902 {
3903         struct net_device *dev = dev_id;
3904         struct tg3 *tp = netdev_priv(dev);
3905         struct tg3_hw_status *sblk = tp->hw_status;
3906         unsigned int handled = 1;
3907
3908         /* In INTx mode, it is possible for the interrupt to arrive at
3909          * the CPU before the status block posted prior to the interrupt.
3910          * Reading the PCI State register will confirm whether the
3911          * interrupt is ours and will flush the status block.
3912          */
3913         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3914                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3915                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3916                         handled = 0;
3917                         goto out;
3918                 }
3919         }
3920
3921         /*
3922          * Writing any value to intr-mbox-0 clears PCI INTA# and
3923          * chip-internal interrupt pending events.
3924          * Writing non-zero to intr-mbox-0 additional tells the
3925          * NIC to stop sending us irqs, engaging "in-intr-handler"
3926          * event coalescing.
3927          *
3928          * Flush the mailbox to de-assert the IRQ immediately to prevent
3929          * spurious interrupts.  The flush impacts performance but
3930          * excessive spurious interrupts can be worse in some cases.
3931          */
3932         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3933         if (tg3_irq_sync(tp))
3934                 goto out;
3935         sblk->status &= ~SD_STATUS_UPDATED;
3936         if (likely(tg3_has_work(tp))) {
3937                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3938                 netif_rx_schedule(dev, &tp->napi);
3939         } else {
3940                 /* No work, shared interrupt perhaps?  re-enable
3941                  * interrupts, and flush that PCI write
3942                  */
3943                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3944                                0x00000000);
3945         }
3946 out:
3947         return IRQ_RETVAL(handled);
3948 }
3949
3950 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3951 {
3952         struct net_device *dev = dev_id;
3953         struct tg3 *tp = netdev_priv(dev);
3954         struct tg3_hw_status *sblk = tp->hw_status;
3955         unsigned int handled = 1;
3956
3957         /* In INTx mode, it is possible for the interrupt to arrive at
3958          * the CPU before the status block posted prior to the interrupt.
3959          * Reading the PCI State register will confirm whether the
3960          * interrupt is ours and will flush the status block.
3961          */
3962         if (unlikely(sblk->status_tag == tp->last_tag)) {
3963                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3964                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3965                         handled = 0;
3966                         goto out;
3967                 }
3968         }
3969
3970         /*
3971          * writing any value to intr-mbox-0 clears PCI INTA# and
3972          * chip-internal interrupt pending events.
3973          * writing non-zero to intr-mbox-0 additional tells the
3974          * NIC to stop sending us irqs, engaging "in-intr-handler"
3975          * event coalescing.
3976          *
3977          * Flush the mailbox to de-assert the IRQ immediately to prevent
3978          * spurious interrupts.  The flush impacts performance but
3979          * excessive spurious interrupts can be worse in some cases.
3980          */
3981         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3982         if (tg3_irq_sync(tp))
3983                 goto out;
3984         if (netif_rx_schedule_prep(dev, &tp->napi)) {
3985                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3986                 /* Update last_tag to mark that this status has been
3987                  * seen. Because interrupt may be shared, we may be
3988                  * racing with tg3_poll(), so only update last_tag
3989                  * if tg3_poll() is not scheduled.
3990                  */
3991                 tp->last_tag = sblk->status_tag;
3992                 __netif_rx_schedule(dev, &tp->napi);
3993         }
3994 out:
3995         return IRQ_RETVAL(handled);
3996 }
3997
3998 /* ISR for interrupt test */
3999 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4000 {
4001         struct net_device *dev = dev_id;
4002         struct tg3 *tp = netdev_priv(dev);
4003         struct tg3_hw_status *sblk = tp->hw_status;
4004
4005         if ((sblk->status & SD_STATUS_UPDATED) ||
4006             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4007                 tg3_disable_ints(tp);
4008                 return IRQ_RETVAL(1);
4009         }
4010         return IRQ_RETVAL(0);
4011 }
4012
4013 static int tg3_init_hw(struct tg3 *, int);
4014 static int tg3_halt(struct tg3 *, int, int);
4015
4016 /* Restart hardware after configuration changes, self-test, etc.
4017  * Invoked with tp->lock held.
4018  */
4019 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4020 {
4021         int err;
4022
4023         err = tg3_init_hw(tp, reset_phy);
4024         if (err) {
4025                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4026                        "aborting.\n", tp->dev->name);
4027                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4028                 tg3_full_unlock(tp);
4029                 del_timer_sync(&tp->timer);
4030                 tp->irq_sync = 0;
4031                 napi_enable(&tp->napi);
4032                 dev_close(tp->dev);
4033                 tg3_full_lock(tp, 0);
4034         }
4035         return err;
4036 }
4037
4038 #ifdef CONFIG_NET_POLL_CONTROLLER
4039 static void tg3_poll_controller(struct net_device *dev)
4040 {
4041         struct tg3 *tp = netdev_priv(dev);
4042
4043         tg3_interrupt(tp->pdev->irq, dev);
4044 }
4045 #endif
4046
4047 static void tg3_reset_task(struct work_struct *work)
4048 {
4049         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4050         unsigned int restart_timer;
4051
4052         tg3_full_lock(tp, 0);
4053
4054         if (!netif_running(tp->dev)) {
4055                 tg3_full_unlock(tp);
4056                 return;
4057         }
4058
4059         tg3_full_unlock(tp);
4060
4061         tg3_netif_stop(tp);
4062
4063         tg3_full_lock(tp, 1);
4064
4065         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4066         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4067
4068         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4069                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4070                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4071                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4072                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4073         }
4074
4075         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4076         if (tg3_init_hw(tp, 1))
4077                 goto out;
4078
4079         tg3_netif_start(tp);
4080
4081         if (restart_timer)
4082                 mod_timer(&tp->timer, jiffies + 1);
4083
4084 out:
4085         tg3_full_unlock(tp);
4086 }
4087
4088 static void tg3_dump_short_state(struct tg3 *tp)
4089 {
4090         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4091                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4092         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4093                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4094 }
4095
4096 static void tg3_tx_timeout(struct net_device *dev)
4097 {
4098         struct tg3 *tp = netdev_priv(dev);
4099
4100         if (netif_msg_tx_err(tp)) {
4101                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4102                        dev->name);
4103                 tg3_dump_short_state(tp);
4104         }
4105
4106         schedule_work(&tp->reset_task);
4107 }
4108
4109 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4110 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4111 {
4112         u32 base = (u32) mapping & 0xffffffff;
4113
4114         return ((base > 0xffffdcc0) &&
4115                 (base + len + 8 < base));
4116 }
4117
4118 /* Test for DMA addresses > 40-bit */
4119 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4120                                           int len)
4121 {
4122 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4123         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4124                 return (((u64) mapping + len) > DMA_40BIT_MASK);
4125         return 0;
4126 #else
4127         return 0;
4128 #endif
4129 }
4130
4131 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4132
4133 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4134 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4135                                        u32 last_plus_one, u32 *start,
4136                                        u32 base_flags, u32 mss)
4137 {
4138         struct sk_buff *new_skb;
4139         dma_addr_t new_addr = 0;
4140         u32 entry = *start;
4141         int i, ret = 0;
4142
4143         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4144                 new_skb = skb_copy(skb, GFP_ATOMIC);
4145         else {
4146                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4147
4148                 new_skb = skb_copy_expand(skb,
4149                                           skb_headroom(skb) + more_headroom,
4150                                           skb_tailroom(skb), GFP_ATOMIC);
4151         }
4152
4153         if (!new_skb) {
4154                 ret = -1;
4155         } else {
4156                 /* New SKB is guaranteed to be linear. */
4157                 entry = *start;
4158                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4159                                           PCI_DMA_TODEVICE);
4160                 /* Make sure new skb does not cross any 4G boundaries.
4161                  * Drop the packet if it does.
4162                  */
4163                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4164                         ret = -1;
4165                         dev_kfree_skb(new_skb);
4166                         new_skb = NULL;
4167                 } else {
4168                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
4169                                     base_flags, 1 | (mss << 1));
4170                         *start = NEXT_TX(entry);
4171                 }
4172         }
4173
4174         /* Now clean up the sw ring entries. */
4175         i = 0;
4176         while (entry != last_plus_one) {
4177                 int len;
4178
4179                 if (i == 0)
4180                         len = skb_headlen(skb);
4181                 else
4182                         len = skb_shinfo(skb)->frags[i-1].size;
4183                 pci_unmap_single(tp->pdev,
4184                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4185                                  len, PCI_DMA_TODEVICE);
4186                 if (i == 0) {
4187                         tp->tx_buffers[entry].skb = new_skb;
4188                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4189                 } else {
4190                         tp->tx_buffers[entry].skb = NULL;
4191                 }
4192                 entry = NEXT_TX(entry);
4193                 i++;
4194         }
4195
4196         dev_kfree_skb(skb);
4197
4198         return ret;
4199 }
4200
4201 static void tg3_set_txd(struct tg3 *tp, int entry,
4202                         dma_addr_t mapping, int len, u32 flags,
4203                         u32 mss_and_is_end)
4204 {
4205         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4206         int is_end = (mss_and_is_end & 0x1);
4207         u32 mss = (mss_and_is_end >> 1);
4208         u32 vlan_tag = 0;
4209
4210         if (is_end)
4211                 flags |= TXD_FLAG_END;
4212         if (flags & TXD_FLAG_VLAN) {
4213                 vlan_tag = flags >> 16;
4214                 flags &= 0xffff;
4215         }
4216         vlan_tag |= (mss << TXD_MSS_SHIFT);
4217
4218         txd->addr_hi = ((u64) mapping >> 32);
4219         txd->addr_lo = ((u64) mapping & 0xffffffff);
4220         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4221         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4222 }
4223
4224 /* hard_start_xmit for devices that don't have any bugs and
4225  * support TG3_FLG2_HW_TSO_2 only.
4226  */
4227 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4228 {
4229         struct tg3 *tp = netdev_priv(dev);
4230         dma_addr_t mapping;
4231         u32 len, entry, base_flags, mss;
4232
4233         len = skb_headlen(skb);
4234
4235         /* We are running in BH disabled context with netif_tx_lock
4236          * and TX reclaim runs via tp->napi.poll inside of a software
4237          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4238          * no IRQ context deadlocks to worry about either.  Rejoice!
4239          */
4240         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4241                 if (!netif_queue_stopped(dev)) {
4242                         netif_stop_queue(dev);
4243
4244                         /* This is a hard error, log it. */
4245                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4246                                "queue awake!\n", dev->name);
4247                 }
4248                 return NETDEV_TX_BUSY;
4249         }
4250
4251         entry = tp->tx_prod;
4252         base_flags = 0;
4253         mss = 0;
4254         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4255                 int tcp_opt_len, ip_tcp_len;
4256
4257                 if (skb_header_cloned(skb) &&
4258                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4259                         dev_kfree_skb(skb);
4260                         goto out_unlock;
4261                 }
4262
4263                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4264                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4265                 else {
4266                         struct iphdr *iph = ip_hdr(skb);
4267
4268                         tcp_opt_len = tcp_optlen(skb);
4269                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4270
4271                         iph->check = 0;
4272                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4273                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
4274                 }
4275
4276                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4277                                TXD_FLAG_CPU_POST_DMA);
4278
4279                 tcp_hdr(skb)->check = 0;
4280
4281         }
4282         else if (skb->ip_summed == CHECKSUM_PARTIAL)
4283                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4284 #if TG3_VLAN_TAG_USED
4285         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4286                 base_flags |= (TXD_FLAG_VLAN |
4287                                (vlan_tx_tag_get(skb) << 16));
4288 #endif
4289
4290         /* Queue skb data, a.k.a. the main skb fragment. */
4291         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4292
4293         tp->tx_buffers[entry].skb = skb;
4294         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4295
4296         tg3_set_txd(tp, entry, mapping, len, base_flags,
4297                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4298
4299         entry = NEXT_TX(entry);
4300
4301         /* Now loop through additional data fragments, and queue them. */
4302         if (skb_shinfo(skb)->nr_frags > 0) {
4303                 unsigned int i, last;
4304
4305                 last = skb_shinfo(skb)->nr_frags - 1;
4306                 for (i = 0; i <= last; i++) {
4307                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4308
4309                         len = frag->size;
4310                         mapping = pci_map_page(tp->pdev,
4311                                                frag->page,
4312                                                frag->page_offset,
4313                                                len, PCI_DMA_TODEVICE);
4314
4315                         tp->tx_buffers[entry].skb = NULL;
4316                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4317
4318                         tg3_set_txd(tp, entry, mapping, len,
4319                                     base_flags, (i == last) | (mss << 1));
4320
4321                         entry = NEXT_TX(entry);
4322                 }
4323         }
4324
4325         /* Packets are ready, update Tx producer idx local and on card. */
4326         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4327
4328         tp->tx_prod = entry;
4329         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4330                 netif_stop_queue(dev);
4331                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4332                         netif_wake_queue(tp->dev);
4333         }
4334
4335 out_unlock:
4336         mmiowb();
4337
4338         dev->trans_start = jiffies;
4339
4340         return NETDEV_TX_OK;
4341 }
4342
4343 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4344
4345 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4346  * TSO header is greater than 80 bytes.
4347  */
4348 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4349 {
4350         struct sk_buff *segs, *nskb;
4351
4352         /* Estimate the number of fragments in the worst case */
4353         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4354                 netif_stop_queue(tp->dev);
4355                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4356                         return NETDEV_TX_BUSY;
4357
4358                 netif_wake_queue(tp->dev);
4359         }
4360
4361         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4362         if (unlikely(IS_ERR(segs)))
4363                 goto tg3_tso_bug_end;
4364
4365         do {
4366                 nskb = segs;
4367                 segs = segs->next;
4368                 nskb->next = NULL;
4369                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4370         } while (segs);
4371
4372 tg3_tso_bug_end:
4373         dev_kfree_skb(skb);
4374
4375         return NETDEV_TX_OK;
4376 }
4377
4378 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4379  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4380  */
4381 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4382 {
4383         struct tg3 *tp = netdev_priv(dev);
4384         dma_addr_t mapping;
4385         u32 len, entry, base_flags, mss;
4386         int would_hit_hwbug;
4387
4388         len = skb_headlen(skb);
4389
4390         /* We are running in BH disabled context with netif_tx_lock
4391          * and TX reclaim runs via tp->napi.poll inside of a software
4392          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4393          * no IRQ context deadlocks to worry about either.  Rejoice!
4394          */
4395         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4396                 if (!netif_queue_stopped(dev)) {
4397                         netif_stop_queue(dev);
4398
4399                         /* This is a hard error, log it. */
4400                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4401                                "queue awake!\n", dev->name);
4402                 }
4403                 return NETDEV_TX_BUSY;
4404         }
4405
4406         entry = tp->tx_prod;
4407         base_flags = 0;
4408         if (skb->ip_summed == CHECKSUM_PARTIAL)
4409                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4410         mss = 0;
4411         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4412                 struct iphdr *iph;
4413                 int tcp_opt_len, ip_tcp_len, hdr_len;
4414
4415                 if (skb_header_cloned(skb) &&
4416                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4417                         dev_kfree_skb(skb);
4418                         goto out_unlock;
4419                 }
4420
4421                 tcp_opt_len = tcp_optlen(skb);
4422                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4423
4424                 hdr_len = ip_tcp_len + tcp_opt_len;
4425                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4426                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4427                         return (tg3_tso_bug(tp, skb));
4428
4429                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4430                                TXD_FLAG_CPU_POST_DMA);
4431
4432                 iph = ip_hdr(skb);
4433                 iph->check = 0;
4434                 iph->tot_len = htons(mss + hdr_len);
4435                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4436                         tcp_hdr(skb)->check = 0;
4437                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4438                 } else
4439                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4440                                                                  iph->daddr, 0,
4441                                                                  IPPROTO_TCP,
4442                                                                  0);
4443
4444                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4445                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4446                         if (tcp_opt_len || iph->ihl > 5) {
4447                                 int tsflags;
4448
4449                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4450                                 mss |= (tsflags << 11);
4451                         }
4452                 } else {
4453                         if (tcp_opt_len || iph->ihl > 5) {
4454                                 int tsflags;
4455
4456                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4457                                 base_flags |= tsflags << 12;
4458                         }
4459                 }
4460         }
4461 #if TG3_VLAN_TAG_USED
4462         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4463                 base_flags |= (TXD_FLAG_VLAN |
4464                                (vlan_tx_tag_get(skb) << 16));
4465 #endif
4466
4467         /* Queue skb data, a.k.a. the main skb fragment. */
4468         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4469
4470         tp->tx_buffers[entry].skb = skb;
4471         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4472
4473         would_hit_hwbug = 0;
4474
4475         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4476                 would_hit_hwbug = 1;
4477         else if (tg3_4g_overflow_test(mapping, len))
4478                 would_hit_hwbug = 1;
4479
4480         tg3_set_txd(tp, entry, mapping, len, base_flags,
4481                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4482
4483         entry = NEXT_TX(entry);
4484
4485         /* Now loop through additional data fragments, and queue them. */
4486         if (skb_shinfo(skb)->nr_frags > 0) {
4487                 unsigned int i, last;
4488
4489                 last = skb_shinfo(skb)->nr_frags - 1;
4490                 for (i = 0; i <= last; i++) {
4491                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4492
4493                         len = frag->size;
4494                         mapping = pci_map_page(tp->pdev,
4495                                                frag->page,
4496                                                frag->page_offset,
4497                                                len, PCI_DMA_TODEVICE);
4498
4499                         tp->tx_buffers[entry].skb = NULL;
4500                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4501
4502                         if (tg3_4g_overflow_test(mapping, len))
4503                                 would_hit_hwbug = 1;
4504
4505                         if (tg3_40bit_overflow_test(tp, mapping, len))
4506                                 would_hit_hwbug = 1;
4507
4508                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4509                                 tg3_set_txd(tp, entry, mapping, len,
4510                                             base_flags, (i == last)|(mss << 1));
4511                         else
4512                                 tg3_set_txd(tp, entry, mapping, len,
4513                                             base_flags, (i == last));
4514
4515                         entry = NEXT_TX(entry);
4516                 }
4517         }
4518
4519         if (would_hit_hwbug) {
4520                 u32 last_plus_one = entry;
4521                 u32 start;
4522
4523                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4524                 start &= (TG3_TX_RING_SIZE - 1);
4525
4526                 /* If the workaround fails due to memory/mapping
4527                  * failure, silently drop this packet.
4528                  */
4529                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4530                                                 &start, base_flags, mss))
4531                         goto out_unlock;
4532
4533                 entry = start;
4534         }
4535
4536         /* Packets are ready, update Tx producer idx local and on card. */
4537         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4538
4539         tp->tx_prod = entry;
4540         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4541                 netif_stop_queue(dev);
4542                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4543                         netif_wake_queue(tp->dev);
4544         }
4545
4546 out_unlock:
4547         mmiowb();
4548
4549         dev->trans_start = jiffies;
4550
4551         return NETDEV_TX_OK;
4552 }
4553
4554 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4555                                int new_mtu)
4556 {
4557         dev->mtu = new_mtu;
4558
4559         if (new_mtu > ETH_DATA_LEN) {
4560                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4561                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4562                         ethtool_op_set_tso(dev, 0);
4563                 }
4564                 else
4565                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4566         } else {
4567                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4568                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4569                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4570         }
4571 }
4572
4573 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4574 {
4575         struct tg3 *tp = netdev_priv(dev);
4576         int err;
4577
4578         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4579                 return -EINVAL;
4580
4581         if (!netif_running(dev)) {
4582                 /* We'll just catch it later when the
4583                  * device is up'd.
4584                  */
4585                 tg3_set_mtu(dev, tp, new_mtu);
4586                 return 0;
4587         }
4588
4589         tg3_netif_stop(tp);
4590
4591         tg3_full_lock(tp, 1);
4592
4593         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4594
4595         tg3_set_mtu(dev, tp, new_mtu);
4596
4597         err = tg3_restart_hw(tp, 0);
4598
4599         if (!err)
4600                 tg3_netif_start(tp);
4601
4602         tg3_full_unlock(tp);
4603
4604         return err;
4605 }
4606
4607 /* Free up pending packets in all rx/tx rings.
4608  *
4609  * The chip has been shut down and the driver detached from
4610  * the networking, so no interrupts or new tx packets will
4611  * end up in the driver.  tp->{tx,}lock is not held and we are not
4612  * in an interrupt context and thus may sleep.
4613  */
4614 static void tg3_free_rings(struct tg3 *tp)
4615 {
4616         struct ring_info *rxp;
4617         int i;
4618
4619         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4620                 rxp = &tp->rx_std_buffers[i];
4621
4622                 if (rxp->skb == NULL)
4623                         continue;
4624                 pci_unmap_single(tp->pdev,
4625                                  pci_unmap_addr(rxp, mapping),
4626                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4627                                  PCI_DMA_FROMDEVICE);
4628                 dev_kfree_skb_any(rxp->skb);
4629                 rxp->skb = NULL;
4630         }
4631
4632         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4633                 rxp = &tp->rx_jumbo_buffers[i];
4634
4635                 if (rxp->skb == NULL)
4636                         continue;
4637                 pci_unmap_single(tp->pdev,
4638                                  pci_unmap_addr(rxp, mapping),
4639                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4640                                  PCI_DMA_FROMDEVICE);
4641                 dev_kfree_skb_any(rxp->skb);
4642                 rxp->skb = NULL;
4643         }
4644
4645         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4646                 struct tx_ring_info *txp;
4647                 struct sk_buff *skb;
4648                 int j;
4649
4650                 txp = &tp->tx_buffers[i];
4651                 skb = txp->skb;
4652
4653                 if (skb == NULL) {
4654                         i++;
4655                         continue;
4656                 }
4657
4658                 pci_unmap_single(tp->pdev,
4659                                  pci_unmap_addr(txp, mapping),
4660                                  skb_headlen(skb),
4661                                  PCI_DMA_TODEVICE);
4662                 txp->skb = NULL;
4663
4664                 i++;
4665
4666                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4667                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4668                         pci_unmap_page(tp->pdev,
4669                                        pci_unmap_addr(txp, mapping),
4670                                        skb_shinfo(skb)->frags[j].size,
4671                                        PCI_DMA_TODEVICE);
4672                         i++;
4673                 }
4674
4675                 dev_kfree_skb_any(skb);
4676         }
4677 }
4678
4679 /* Initialize tx/rx rings for packet processing.
4680  *
4681  * The chip has been shut down and the driver detached from
4682  * the networking, so no interrupts or new tx packets will
4683  * end up in the driver.  tp->{tx,}lock are held and thus
4684  * we may not sleep.
4685  */
4686 static int tg3_init_rings(struct tg3 *tp)
4687 {
4688         u32 i;
4689
4690         /* Free up all the SKBs. */
4691         tg3_free_rings(tp);
4692
4693         /* Zero out all descriptors. */
4694         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4695         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4696         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4697         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4698
4699         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4700         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4701             (tp->dev->mtu > ETH_DATA_LEN))
4702                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4703
4704         /* Initialize invariants of the rings, we only set this
4705          * stuff once.  This works because the card does not
4706          * write into the rx buffer posting rings.
4707          */
4708         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4709                 struct tg3_rx_buffer_desc *rxd;
4710
4711                 rxd = &tp->rx_std[i];
4712                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4713                         << RXD_LEN_SHIFT;
4714                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4715                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4716                                (i << RXD_OPAQUE_INDEX_SHIFT));
4717         }
4718
4719         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4720                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4721                         struct tg3_rx_buffer_desc *rxd;
4722
4723                         rxd = &tp->rx_jumbo[i];
4724                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4725                                 << RXD_LEN_SHIFT;
4726                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4727                                 RXD_FLAG_JUMBO;
4728                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4729                                (i << RXD_OPAQUE_INDEX_SHIFT));
4730                 }
4731         }
4732
4733         /* Now allocate fresh SKBs for each rx ring. */
4734         for (i = 0; i < tp->rx_pending; i++) {
4735                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4736                         printk(KERN_WARNING PFX
4737                                "%s: Using a smaller RX standard ring, "
4738                                "only %d out of %d buffers were allocated "
4739                                "successfully.\n",
4740                                tp->dev->name, i, tp->rx_pending);
4741                         if (i == 0)
4742                                 return -ENOMEM;
4743                         tp->rx_pending = i;
4744                         break;
4745                 }
4746         }
4747
4748         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4749                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4750                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4751                                              -1, i) < 0) {
4752                                 printk(KERN_WARNING PFX
4753                                        "%s: Using a smaller RX jumbo ring, "
4754                                        "only %d out of %d buffers were "
4755                                        "allocated successfully.\n",
4756                                        tp->dev->name, i, tp->rx_jumbo_pending);
4757                                 if (i == 0) {
4758                                         tg3_free_rings(tp);
4759                                         return -ENOMEM;
4760                                 }
4761                                 tp->rx_jumbo_pending = i;
4762                                 break;
4763                         }
4764                 }
4765         }
4766         return 0;
4767 }
4768
4769 /*
4770  * Must not be invoked with interrupt sources disabled and
4771  * the hardware shutdown down.
4772  */
4773 static void tg3_free_consistent(struct tg3 *tp)
4774 {
4775         kfree(tp->rx_std_buffers);
4776         tp->rx_std_buffers = NULL;
4777         if (tp->rx_std) {
4778                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4779                                     tp->rx_std, tp->rx_std_mapping);
4780                 tp->rx_std = NULL;
4781         }
4782         if (tp->rx_jumbo) {
4783                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4784                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4785                 tp->rx_jumbo = NULL;
4786         }
4787         if (tp->rx_rcb) {
4788                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4789                                     tp->rx_rcb, tp->rx_rcb_mapping);
4790                 tp->rx_rcb = NULL;
4791         }
4792         if (tp->tx_ring) {
4793                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4794                         tp->tx_ring, tp->tx_desc_mapping);
4795                 tp->tx_ring = NULL;
4796         }
4797         if (tp->hw_status) {
4798                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4799                                     tp->hw_status, tp->status_mapping);
4800                 tp->hw_status = NULL;
4801         }
4802         if (tp->hw_stats) {
4803                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4804                                     tp->hw_stats, tp->stats_mapping);
4805                 tp->hw_stats = NULL;
4806         }
4807 }
4808
4809 /*
4810  * Must not be invoked with interrupt sources disabled and
4811  * the hardware shutdown down.  Can sleep.
4812  */
4813 static int tg3_alloc_consistent(struct tg3 *tp)
4814 {
4815         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4816                                       (TG3_RX_RING_SIZE +
4817                                        TG3_RX_JUMBO_RING_SIZE)) +
4818                                      (sizeof(struct tx_ring_info) *
4819                                       TG3_TX_RING_SIZE),
4820                                      GFP_KERNEL);
4821         if (!tp->rx_std_buffers)
4822                 return -ENOMEM;
4823
4824         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4825         tp->tx_buffers = (struct tx_ring_info *)
4826                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4827
4828         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4829                                           &tp->rx_std_mapping);
4830         if (!tp->rx_std)
4831                 goto err_out;
4832
4833         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4834                                             &tp->rx_jumbo_mapping);
4835
4836         if (!tp->rx_jumbo)
4837                 goto err_out;
4838
4839         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4840                                           &tp->rx_rcb_mapping);
4841         if (!tp->rx_rcb)
4842                 goto err_out;
4843
4844         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4845                                            &tp->tx_desc_mapping);
4846         if (!tp->tx_ring)
4847                 goto err_out;
4848
4849         tp->hw_status = pci_alloc_consistent(tp->pdev,
4850                                              TG3_HW_STATUS_SIZE,
4851                                              &tp->status_mapping);
4852         if (!tp->hw_status)
4853                 goto err_out;
4854
4855         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4856                                             sizeof(struct tg3_hw_stats),
4857                                             &tp->stats_mapping);
4858         if (!tp->hw_stats)
4859                 goto err_out;
4860
4861         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4862         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4863
4864         return 0;
4865
4866 err_out:
4867         tg3_free_consistent(tp);
4868         return -ENOMEM;
4869 }
4870
4871 #define MAX_WAIT_CNT 1000
4872
4873 /* To stop a block, clear the enable bit and poll till it
4874  * clears.  tp->lock is held.
4875  */
4876 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4877 {
4878         unsigned int i;
4879         u32 val;
4880
4881         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4882                 switch (ofs) {
4883                 case RCVLSC_MODE:
4884                 case DMAC_MODE:
4885                 case MBFREE_MODE:
4886                 case BUFMGR_MODE:
4887                 case MEMARB_MODE:
4888                         /* We can't enable/disable these bits of the
4889                          * 5705/5750, just say success.
4890                          */
4891                         return 0;
4892
4893                 default:
4894                         break;
4895                 };
4896         }
4897
4898         val = tr32(ofs);
4899         val &= ~enable_bit;
4900         tw32_f(ofs, val);
4901
4902         for (i = 0; i < MAX_WAIT_CNT; i++) {
4903                 udelay(100);
4904                 val = tr32(ofs);
4905                 if ((val & enable_bit) == 0)
4906                         break;
4907         }
4908
4909         if (i == MAX_WAIT_CNT && !silent) {
4910                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4911                        "ofs=%lx enable_bit=%x\n",
4912                        ofs, enable_bit);
4913                 return -ENODEV;
4914         }
4915
4916         return 0;
4917 }
4918
4919 /* tp->lock is held. */
4920 static int tg3_abort_hw(struct tg3 *tp, int silent)
4921 {
4922         int i, err;
4923
4924         tg3_disable_ints(tp);
4925
4926         tp->rx_mode &= ~RX_MODE_ENABLE;
4927         tw32_f(MAC_RX_MODE, tp->rx_mode);
4928         udelay(10);
4929
4930         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4931         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4932         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4933         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4934         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4935         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4936
4937         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4938         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4939         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4940         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4941         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4942         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4943         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4944
4945         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4946         tw32_f(MAC_MODE, tp->mac_mode);
4947         udelay(40);
4948
4949         tp->tx_mode &= ~TX_MODE_ENABLE;
4950         tw32_f(MAC_TX_MODE, tp->tx_mode);
4951
4952         for (i = 0; i < MAX_WAIT_CNT; i++) {
4953                 udelay(100);
4954                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4955                         break;
4956         }
4957         if (i >= MAX_WAIT_CNT) {
4958                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4959                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4960                        tp->dev->name, tr32(MAC_TX_MODE));
4961                 err |= -ENODEV;
4962         }
4963
4964         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4965         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4966         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4967
4968         tw32(FTQ_RESET, 0xffffffff);
4969         tw32(FTQ_RESET, 0x00000000);
4970
4971         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4972         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4973
4974         if (tp->hw_status)
4975                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4976         if (tp->hw_stats)
4977                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4978
4979         return err;
4980 }
4981
4982 /* tp->lock is held. */
4983 static int tg3_nvram_lock(struct tg3 *tp)
4984 {
4985         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4986                 int i;
4987
4988                 if (tp->nvram_lock_cnt == 0) {
4989                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4990                         for (i = 0; i < 8000; i++) {
4991                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4992                                         break;
4993                                 udelay(20);
4994                         }
4995                         if (i == 8000) {
4996                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4997                                 return -ENODEV;
4998                         }
4999                 }
5000                 tp->nvram_lock_cnt++;
5001         }
5002         return 0;
5003 }
5004
5005 /* tp->lock is held. */
5006 static void tg3_nvram_unlock(struct tg3 *tp)
5007 {
5008         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5009                 if (tp->nvram_lock_cnt > 0)
5010                         tp->nvram_lock_cnt--;
5011                 if (tp->nvram_lock_cnt == 0)
5012                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5013         }
5014 }
5015
5016 /* tp->lock is held. */
5017 static void tg3_enable_nvram_access(struct tg3 *tp)
5018 {
5019         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5020             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5021                 u32 nvaccess = tr32(NVRAM_ACCESS);
5022
5023                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5024         }
5025 }
5026
5027 /* tp->lock is held. */
5028 static void tg3_disable_nvram_access(struct tg3 *tp)
5029 {
5030         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5031             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5032                 u32 nvaccess = tr32(NVRAM_ACCESS);
5033
5034                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5035         }
5036 }
5037
5038 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5039 {
5040         int i;
5041         u32 apedata;
5042
5043         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5044         if (apedata != APE_SEG_SIG_MAGIC)
5045                 return;
5046
5047         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5048         if (apedata != APE_FW_STATUS_READY)
5049                 return;
5050
5051         /* Wait for up to 1 millisecond for APE to service previous event. */
5052         for (i = 0; i < 10; i++) {
5053                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5054                         return;
5055
5056                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5057
5058                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5059                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5060                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5061
5062                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5063
5064                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5065                         break;
5066
5067                 udelay(100);
5068         }
5069
5070         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5071                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5072 }
5073
5074 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5075 {
5076         u32 event;
5077         u32 apedata;
5078
5079         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5080                 return;
5081
5082         switch (kind) {
5083                 case RESET_KIND_INIT:
5084                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5085                                         APE_HOST_SEG_SIG_MAGIC);
5086                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5087                                         APE_HOST_SEG_LEN_MAGIC);
5088                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5089                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5090                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5091                                         APE_HOST_DRIVER_ID_MAGIC);
5092                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5093                                         APE_HOST_BEHAV_NO_PHYLOCK);
5094
5095                         event = APE_EVENT_STATUS_STATE_START;
5096                         break;
5097                 case RESET_KIND_SHUTDOWN:
5098                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5099                         break;
5100                 case RESET_KIND_SUSPEND:
5101                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5102                         break;
5103                 default:
5104                         return;
5105         }
5106
5107         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5108
5109         tg3_ape_send_event(tp, event);
5110 }
5111
5112 /* tp->lock is held. */
5113 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5114 {
5115         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5116                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5117
5118         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5119                 switch (kind) {
5120                 case RESET_KIND_INIT:
5121                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5122                                       DRV_STATE_START);
5123                         break;
5124
5125                 case RESET_KIND_SHUTDOWN:
5126                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5127                                       DRV_STATE_UNLOAD);
5128                         break;
5129
5130                 case RESET_KIND_SUSPEND:
5131                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5132                                       DRV_STATE_SUSPEND);
5133                         break;
5134
5135                 default:
5136                         break;
5137                 };
5138         }
5139
5140         if (kind == RESET_KIND_INIT ||
5141             kind == RESET_KIND_SUSPEND)
5142                 tg3_ape_driver_state_change(tp, kind);
5143 }
5144
5145 /* tp->lock is held. */
5146 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5147 {
5148         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5149                 switch (kind) {
5150                 case RESET_KIND_INIT:
5151                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5152                                       DRV_STATE_START_DONE);
5153                         break;
5154
5155                 case RESET_KIND_SHUTDOWN:
5156                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5157                                       DRV_STATE_UNLOAD_DONE);
5158                         break;
5159
5160                 default:
5161                         break;
5162                 };
5163         }
5164
5165         if (kind == RESET_KIND_SHUTDOWN)
5166                 tg3_ape_driver_state_change(tp, kind);
5167 }
5168
5169 /* tp->lock is held. */
5170 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5171 {
5172         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5173                 switch (kind) {
5174                 case RESET_KIND_INIT:
5175                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5176                                       DRV_STATE_START);
5177                         break;
5178
5179                 case RESET_KIND_SHUTDOWN:
5180                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5181                                       DRV_STATE_UNLOAD);
5182                         break;
5183
5184                 case RESET_KIND_SUSPEND:
5185                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5186                                       DRV_STATE_SUSPEND);
5187                         break;
5188
5189                 default:
5190                         break;
5191                 };
5192         }
5193 }
5194
5195 static int tg3_poll_fw(struct tg3 *tp)
5196 {
5197         int i;
5198         u32 val;
5199
5200         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5201                 /* Wait up to 20ms for init done. */
5202                 for (i = 0; i < 200; i++) {
5203                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5204                                 return 0;
5205                         udelay(100);
5206                 }
5207                 return -ENODEV;
5208         }
5209
5210         /* Wait for firmware initialization to complete. */
5211         for (i = 0; i < 100000; i++) {
5212                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5213                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5214                         break;
5215                 udelay(10);
5216         }
5217
5218         /* Chip might not be fitted with firmware.  Some Sun onboard
5219          * parts are configured like that.  So don't signal the timeout
5220          * of the above loop as an error, but do report the lack of
5221          * running firmware once.
5222          */
5223         if (i >= 100000 &&
5224             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5225                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5226
5227                 printk(KERN_INFO PFX "%s: No firmware running.\n",
5228                        tp->dev->name);
5229         }
5230
5231         return 0;
5232 }
5233
5234 /* Save PCI command register before chip reset */
5235 static void tg3_save_pci_state(struct tg3 *tp)
5236 {
5237         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5238 }
5239
5240 /* Restore PCI state after chip reset */
5241 static void tg3_restore_pci_state(struct tg3 *tp)
5242 {
5243         u32 val;
5244
5245         /* Re-enable indirect register accesses. */
5246         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5247                                tp->misc_host_ctrl);
5248
5249         /* Set MAX PCI retry to zero. */
5250         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5251         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5252             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5253                 val |= PCISTATE_RETRY_SAME_DMA;
5254         /* Allow reads and writes to the APE register and memory space. */
5255         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5256                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5257                        PCISTATE_ALLOW_APE_SHMEM_WR;
5258         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5259
5260         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5261
5262         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5263                 pcie_set_readrq(tp->pdev, 4096);
5264         else {
5265                 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5266                                       tp->pci_cacheline_sz);
5267                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5268                                       tp->pci_lat_timer);
5269         }
5270
5271         /* Make sure PCI-X relaxed ordering bit is clear. */
5272         if (tp->pcix_cap) {
5273                 u16 pcix_cmd;
5274
5275                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5276                                      &pcix_cmd);
5277                 pcix_cmd &= ~PCI_X_CMD_ERO;
5278                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5279                                       pcix_cmd);
5280         }
5281
5282         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5283
5284                 /* Chip reset on 5780 will reset MSI enable bit,
5285                  * so need to restore it.
5286                  */
5287                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5288                         u16 ctrl;
5289
5290                         pci_read_config_word(tp->pdev,
5291                                              tp->msi_cap + PCI_MSI_FLAGS,
5292                                              &ctrl);
5293                         pci_write_config_word(tp->pdev,
5294                                               tp->msi_cap + PCI_MSI_FLAGS,
5295                                               ctrl | PCI_MSI_FLAGS_ENABLE);
5296                         val = tr32(MSGINT_MODE);
5297                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5298                 }
5299         }
5300 }
5301
5302 static void tg3_stop_fw(struct tg3 *);
5303
5304 /* tp->lock is held. */
5305 static int tg3_chip_reset(struct tg3 *tp)
5306 {
5307         u32 val;
5308         void (*write_op)(struct tg3 *, u32, u32);
5309         int err;
5310
5311         tg3_nvram_lock(tp);
5312
5313         /* No matching tg3_nvram_unlock() after this because
5314          * chip reset below will undo the nvram lock.
5315          */
5316         tp->nvram_lock_cnt = 0;
5317
5318         /* GRC_MISC_CFG core clock reset will clear the memory
5319          * enable bit in PCI register 4 and the MSI enable bit
5320          * on some chips, so we save relevant registers here.
5321          */
5322         tg3_save_pci_state(tp);
5323
5324         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5325             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5326             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5327             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5328             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
5329                 tw32(GRC_FASTBOOT_PC, 0);
5330
5331         /*
5332          * We must avoid the readl() that normally takes place.
5333          * It locks machines, causes machine checks, and other
5334          * fun things.  So, temporarily disable the 5701
5335          * hardware workaround, while we do the reset.
5336          */
5337         write_op = tp->write32;
5338         if (write_op == tg3_write_flush_reg32)
5339                 tp->write32 = tg3_write32;
5340
5341         /* Prevent the irq handler from reading or writing PCI registers
5342          * during chip reset when the memory enable bit in the PCI command
5343          * register may be cleared.  The chip does not generate interrupt
5344          * at this time, but the irq handler may still be called due to irq
5345          * sharing or irqpoll.
5346          */
5347         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
5348         if (tp->hw_status) {
5349                 tp->hw_status->status = 0;
5350                 tp->hw_status->status_tag = 0;
5351         }
5352         tp->last_tag = 0;
5353         smp_mb();
5354         synchronize_irq(tp->pdev->irq);
5355
5356         /* do the reset */
5357         val = GRC_MISC_CFG_CORECLK_RESET;
5358
5359         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5360                 if (tr32(0x7e2c) == 0x60) {
5361                         tw32(0x7e2c, 0x20);
5362                 }
5363                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5364                         tw32(GRC_MISC_CFG, (1 << 29));
5365                         val |= (1 << 29);
5366                 }
5367         }
5368
5369         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5370                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5371                 tw32(GRC_VCPU_EXT_CTRL,
5372                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5373         }
5374
5375         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5376                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5377         tw32(GRC_MISC_CFG, val);
5378
5379         /* restore 5701 hardware bug workaround write method */
5380         tp->write32 = write_op;
5381
5382         /* Unfortunately, we have to delay before the PCI read back.
5383          * Some 575X chips even will not respond to a PCI cfg access
5384          * when the reset command is given to the chip.
5385          *
5386          * How do these hardware designers expect things to work
5387          * properly if the PCI write is posted for a long period
5388          * of time?  It is always necessary to have some method by
5389          * which a register read back can occur to push the write
5390          * out which does the reset.
5391          *
5392          * For most tg3 variants the trick below was working.
5393          * Ho hum...
5394          */
5395         udelay(120);
5396
5397         /* Flush PCI posted writes.  The normal MMIO registers
5398          * are inaccessible at this time so this is the only
5399          * way to make this reliably (actually, this is no longer
5400          * the case, see above).  I tried to use indirect
5401          * register read/write but this upset some 5701 variants.
5402          */
5403         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5404
5405         udelay(120);
5406
5407         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5408                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5409                         int i;
5410                         u32 cfg_val;
5411
5412                         /* Wait for link training to complete.  */
5413                         for (i = 0; i < 5000; i++)
5414                                 udelay(100);
5415
5416                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5417                         pci_write_config_dword(tp->pdev, 0xc4,
5418                                                cfg_val | (1 << 15));
5419                 }
5420                 /* Set PCIE max payload size and clear error status.  */
5421                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5422         }
5423
5424         tg3_restore_pci_state(tp);
5425
5426         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5427
5428         val = 0;
5429         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5430                 val = tr32(MEMARB_MODE);
5431         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5432
5433         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5434                 tg3_stop_fw(tp);
5435                 tw32(0x5000, 0x400);
5436         }
5437
5438         tw32(GRC_MODE, tp->grc_mode);
5439
5440         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5441                 val = tr32(0xc4);
5442
5443                 tw32(0xc4, val | (1 << 15));
5444         }
5445
5446         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5447             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5448                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5449                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5450                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5451                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5452         }
5453
5454         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5455                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5456                 tw32_f(MAC_MODE, tp->mac_mode);
5457         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5458                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5459                 tw32_f(MAC_MODE, tp->mac_mode);
5460         } else
5461                 tw32_f(MAC_MODE, 0);
5462         udelay(40);
5463
5464         err = tg3_poll_fw(tp);
5465         if (err)
5466                 return err;
5467
5468         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5469             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5470                 val = tr32(0x7c00);
5471
5472                 tw32(0x7c00, val | (1 << 25));
5473         }
5474
5475         /* Reprobe ASF enable state.  */
5476         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5477         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5478         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5479         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5480                 u32 nic_cfg;
5481
5482                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5483                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5484                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5485                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5486                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5487                 }
5488         }
5489
5490         return 0;
5491 }
5492
5493 /* tp->lock is held. */
5494 static void tg3_stop_fw(struct tg3 *tp)
5495 {
5496         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5497            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5498                 u32 val;
5499                 int i;
5500
5501                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5502                 val = tr32(GRC_RX_CPU_EVENT);
5503                 val |= (1 << 14);
5504                 tw32(GRC_RX_CPU_EVENT, val);
5505
5506                 /* Wait for RX cpu to ACK the event.  */
5507                 for (i = 0; i < 100; i++) {
5508                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5509                                 break;
5510                         udelay(1);
5511                 }
5512         }
5513 }
5514
5515 /* tp->lock is held. */
5516 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5517 {
5518         int err;
5519
5520         tg3_stop_fw(tp);
5521
5522         tg3_write_sig_pre_reset(tp, kind);
5523
5524         tg3_abort_hw(tp, silent);
5525         err = tg3_chip_reset(tp);
5526
5527         tg3_write_sig_legacy(tp, kind);
5528         tg3_write_sig_post_reset(tp, kind);
5529
5530         if (err)
5531                 return err;
5532
5533         return 0;
5534 }
5535
5536 #define TG3_FW_RELEASE_MAJOR    0x0
5537 #define TG3_FW_RELASE_MINOR     0x0
5538 #define TG3_FW_RELEASE_FIX      0x0
5539 #define TG3_FW_START_ADDR       0x08000000
5540 #define TG3_FW_TEXT_ADDR        0x08000000
5541 #define TG3_FW_TEXT_LEN         0x9c0
5542 #define TG3_FW_RODATA_ADDR      0x080009c0
5543 #define TG3_FW_RODATA_LEN       0x60
5544 #define TG3_FW_DATA_ADDR        0x08000a40
5545 #define TG3_FW_DATA_LEN         0x20
5546 #define TG3_FW_SBSS_ADDR        0x08000a60
5547 #define TG3_FW_SBSS_LEN         0xc
5548 #define TG3_FW_BSS_ADDR         0x08000a70
5549 #define TG3_FW_BSS_LEN          0x10
5550
5551 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5552         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5553         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5554         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5555         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5556         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5557         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5558         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5559         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5560         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5561         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5562         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5563         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5564         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5565         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5566         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5567         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5568         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5569         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5570         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5571         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5572         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5573         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5574         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5575         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5576         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5577         0, 0, 0, 0, 0, 0,
5578         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5579         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5580         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5581         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5582         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5583         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5584         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5585         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5586         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5587         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5588         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5589         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5590         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5591         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5592         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5593         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5594         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5595         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5596         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5597         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5598         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5599         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5600         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5601         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5602         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5603         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5604         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5605         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5606         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5607         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5608         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5609         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5610         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5611         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5612         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5613         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5614         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5615         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5616         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5617         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5618         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5619         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5620         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5621         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5622         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5623         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5624         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5625         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5626         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5627         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5628         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5629         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5630         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5631         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5632         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5633         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5634         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5635         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5636         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5637         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5638         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5639         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5640         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5641         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5642         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5643 };
5644
5645 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5646         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5647         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5648         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5649         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5650         0x00000000
5651 };
5652
5653 #if 0 /* All zeros, don't eat up space with it. */
5654 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5655         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5656         0x00000000, 0x00000000, 0x00000000, 0x00000000
5657 };
5658 #endif
5659
5660 #define RX_CPU_SCRATCH_BASE     0x30000
5661 #define RX_CPU_SCRATCH_SIZE     0x04000
5662 #define TX_CPU_SCRATCH_BASE     0x34000
5663 #define TX_CPU_SCRATCH_SIZE     0x04000
5664
5665 /* tp->lock is held. */
5666 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5667 {
5668         int i;
5669
5670         BUG_ON(offset == TX_CPU_BASE &&
5671             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5672
5673         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5674                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5675
5676                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5677                 return 0;
5678         }
5679         if (offset == RX_CPU_BASE) {
5680                 for (i = 0; i < 10000; i++) {
5681                         tw32(offset + CPU_STATE, 0xffffffff);
5682                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5683                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5684                                 break;
5685                 }
5686
5687                 tw32(offset + CPU_STATE, 0xffffffff);
5688                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5689                 udelay(10);
5690         } else {
5691                 for (i = 0; i < 10000; i++) {
5692                         tw32(offset + CPU_STATE, 0xffffffff);
5693                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5694                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5695                                 break;
5696                 }
5697         }
5698
5699         if (i >= 10000) {
5700                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5701                        "and %s CPU\n",
5702                        tp->dev->name,
5703                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5704                 return -ENODEV;
5705         }
5706
5707         /* Clear firmware's nvram arbitration. */
5708         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5709                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5710         return 0;
5711 }
5712
5713 struct fw_info {
5714         unsigned int text_base;
5715         unsigned int text_len;
5716         const u32 *text_data;
5717         unsigned int rodata_base;
5718         unsigned int rodata_len;
5719         const u32 *rodata_data;
5720         unsigned int data_base;
5721         unsigned int data_len;
5722         const u32 *data_data;
5723 };
5724
5725 /* tp->lock is held. */
5726 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5727                                  int cpu_scratch_size, struct fw_info *info)
5728 {
5729         int err, lock_err, i;
5730         void (*write_op)(struct tg3 *, u32, u32);
5731
5732         if (cpu_base == TX_CPU_BASE &&
5733             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5734                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5735                        "TX cpu firmware on %s which is 5705.\n",
5736                        tp->dev->name);
5737                 return -EINVAL;
5738         }
5739
5740         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5741                 write_op = tg3_write_mem;
5742         else
5743                 write_op = tg3_write_indirect_reg32;
5744
5745         /* It is possible that bootcode is still loading at this point.
5746          * Get the nvram lock first before halting the cpu.
5747          */
5748         lock_err = tg3_nvram_lock(tp);
5749         err = tg3_halt_cpu(tp, cpu_base);
5750         if (!lock_err)
5751                 tg3_nvram_unlock(tp);
5752         if (err)
5753                 goto out;
5754
5755         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5756                 write_op(tp, cpu_scratch_base + i, 0);
5757         tw32(cpu_base + CPU_STATE, 0xffffffff);
5758         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5759         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5760                 write_op(tp, (cpu_scratch_base +
5761                               (info->text_base & 0xffff) +
5762                               (i * sizeof(u32))),
5763                          (info->text_data ?
5764                           info->text_data[i] : 0));
5765         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5766                 write_op(tp, (cpu_scratch_base +
5767                               (info->rodata_base & 0xffff) +
5768                               (i * sizeof(u32))),
5769                          (info->rodata_data ?
5770                           info->rodata_data[i] : 0));
5771         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5772                 write_op(tp, (cpu_scratch_base +
5773                               (info->data_base & 0xffff) +
5774                               (i * sizeof(u32))),
5775                          (info->data_data ?
5776                           info->data_data[i] : 0));
5777
5778         err = 0;
5779
5780 out:
5781         return err;
5782 }
5783
5784 /* tp->lock is held. */
5785 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5786 {
5787         struct fw_info info;
5788         int err, i;
5789
5790         info.text_base = TG3_FW_TEXT_ADDR;
5791         info.text_len = TG3_FW_TEXT_LEN;
5792         info.text_data = &tg3FwText[0];
5793         info.rodata_base = TG3_FW_RODATA_ADDR;
5794         info.rodata_len = TG3_FW_RODATA_LEN;
5795         info.rodata_data = &tg3FwRodata[0];
5796         info.data_base = TG3_FW_DATA_ADDR;
5797         info.data_len = TG3_FW_DATA_LEN;
5798         info.data_data = NULL;
5799
5800         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5801                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5802                                     &info);
5803         if (err)
5804                 return err;
5805
5806         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5807                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5808                                     &info);
5809         if (err)
5810                 return err;
5811
5812         /* Now startup only the RX cpu. */
5813         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5814         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5815
5816         for (i = 0; i < 5; i++) {
5817                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5818                         break;
5819                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5820                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5821                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5822                 udelay(1000);
5823         }
5824         if (i >= 5) {
5825                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5826                        "to set RX CPU PC, is %08x should be %08x\n",
5827                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5828                        TG3_FW_TEXT_ADDR);
5829                 return -ENODEV;
5830         }
5831         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5832         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5833
5834         return 0;
5835 }
5836
5837
5838 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5839 #define TG3_TSO_FW_RELASE_MINOR         0x6
5840 #define TG3_TSO_FW_RELEASE_FIX          0x0
5841 #define TG3_TSO_FW_START_ADDR           0x08000000
5842 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5843 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5844 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5845 #define TG3_TSO_FW_RODATA_LEN           0x60
5846 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5847 #define TG3_TSO_FW_DATA_LEN             0x30
5848 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5849 #define TG3_TSO_FW_SBSS_LEN             0x2c
5850 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5851 #define TG3_TSO_FW_BSS_LEN              0x894
5852
5853 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5854         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5855         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5856         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5857         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5858         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5859         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5860         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5861         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5862         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5863         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5864         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5865         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5866         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5867         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5868         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5869         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5870         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5871         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5872         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5873         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5874         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5875         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5876         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5877         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5878         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5879         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5880         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5881         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5882         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5883         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5884         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5885         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5886         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5887         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5888         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5889         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5890         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5891         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5892         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5893         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5894         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5895         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5896         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5897         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5898         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5899         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5900         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5901         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5902         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5903         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5904         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5905         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5906         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5907         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5908         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5909         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5910         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5911         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5912         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5913         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5914         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5915         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5916         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5917         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5918         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5919         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5920         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5921         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5922         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5923         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5924         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5925         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5926         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5927         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5928         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5929         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5930         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5931         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5932         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5933         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5934         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5935         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5936         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5937         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5938         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5939         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5940         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5941         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5942         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5943         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5944         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5945         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5946         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5947         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5948         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5949         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5950         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5951         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5952         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5953         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5954         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5955         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5956         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5957         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5958         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5959         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5960         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5961         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5962         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5963         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5964         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5965         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5966         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5967         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5968         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5969         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5970         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5971         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5972         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5973         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5974         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5975         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5976         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5977         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5978         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5979         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5980         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5981         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5982         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5983         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5984         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5985         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5986         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5987         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5988         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5989         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5990         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5991         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5992         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5993         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5994         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5995         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5996         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5997         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5998         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5999         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
6000         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
6001         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
6002         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
6003         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
6004         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
6005         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
6006         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
6007         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
6008         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
6009         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
6010         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
6011         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
6012         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
6013         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
6014         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
6015         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
6016         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
6017         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
6018         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
6019         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
6020         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
6021         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
6022         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
6023         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
6024         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
6025         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
6026         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
6027         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
6028         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
6029         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
6030         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
6031         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
6032         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
6033         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
6034         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
6035         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
6036         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
6037         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
6038         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
6039         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
6040         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
6041         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
6042         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
6043         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
6044         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
6045         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
6046         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
6047         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
6048         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
6049         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
6050         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
6051         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
6052         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
6053         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
6054         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
6055         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
6056         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
6057         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
6058         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
6059         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
6060         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
6061         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
6062         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
6063         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
6064         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
6065         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
6066         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
6067         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
6068         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
6069         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
6070         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
6071         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
6072         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
6073         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
6074         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6075         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
6076         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
6077         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
6078         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
6079         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
6080         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
6081         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
6082         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
6083         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
6084         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
6085         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
6086         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
6087         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
6088         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
6089         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
6090         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
6091         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6092         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
6093         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
6094         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
6095         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
6096         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
6097         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
6098         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
6099         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
6100         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
6101         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
6102         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6103         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6104         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6105         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6106         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6107         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6108         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6109         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6110         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6111         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6112         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6113         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6114         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6115         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6116         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6117         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6118         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6119         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6120         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6121         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6122         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6123         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6124         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6125         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6126         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6127         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6128         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6129         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6130         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6131         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6132         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6133         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6134         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6135         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6136         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6137         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6138 };
6139
6140 static const u32 tg3TsoFwRodata[] = {
6141         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6142         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6143         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6144         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6145         0x00000000,
6146 };
6147
6148 static const u32 tg3TsoFwData[] = {
6149         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6150         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6151         0x00000000,
6152 };
6153
6154 /* 5705 needs a special version of the TSO firmware.  */
6155 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
6156 #define TG3_TSO5_FW_RELASE_MINOR        0x2
6157 #define TG3_TSO5_FW_RELEASE_FIX         0x0
6158 #define TG3_TSO5_FW_START_ADDR          0x00010000
6159 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
6160 #define TG3_TSO5_FW_TEXT_LEN            0xe90
6161 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
6162 #define TG3_TSO5_FW_RODATA_LEN          0x50
6163 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
6164 #define TG3_TSO5_FW_DATA_LEN            0x20
6165 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
6166 #define TG3_TSO5_FW_SBSS_LEN            0x28
6167 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
6168 #define TG3_TSO5_FW_BSS_LEN             0x88
6169
6170 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
6171         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6172         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6173         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6174         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6175         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6176         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6177         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6178         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6179         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6180         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6181         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6182         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6183         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6184         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6185         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6186         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6187         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6188         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6189         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6190         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6191         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6192         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6193         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6194         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6195         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6196         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6197         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6198         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6199         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6200         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6201         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6202         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6203         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6204         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6205         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6206         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6207         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6208         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6209         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6210         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6211         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6212         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6213         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6214         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6215         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6216         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6217         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6218         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6219         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6220         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6221         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6222         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6223         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6224         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6225         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6226         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6227         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6228         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6229         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6230         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6231         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6232         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6233         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6234         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6235         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6236         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6237         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6238         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6239         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6240         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6241         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6242         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6243         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6244         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6245         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6246         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6247         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6248         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6249         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6250         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6251         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6252         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6253         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6254         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6255         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6256         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6257         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6258         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6259         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6260         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6261         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6262         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6263         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6264         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6265         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6266         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6267         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6268         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6269         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6270         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6271         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6272         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6273         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6274         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6275         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6276         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6277         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6278         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6279         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6280         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6281         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6282         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6283         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6284         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6285         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6286         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6287         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6288         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6289         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6290         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6291         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6292         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6293         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6294         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6295         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6296         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6297         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6298         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6299         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6300         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6301         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6302         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6303         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6304         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6305         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6306         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6307         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6308         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6309         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6310         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6311         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6312         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6313         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6314         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6315         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6316         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6317         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6318         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6319         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6320         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6321         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6322         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6323         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6324         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6325         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6326         0x00000000, 0x00000000, 0x00000000,
6327 };
6328
6329 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
6330         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6331         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6332         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6333         0x00000000, 0x00000000, 0x00000000,
6334 };
6335
6336 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
6337         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6338         0x00000000, 0x00000000, 0x00000000,
6339 };
6340
6341 /* tp->lock is held. */
6342 static int tg3_load_tso_firmware(struct tg3 *tp)
6343 {
6344         struct fw_info info;
6345         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6346         int err, i;
6347
6348         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6349                 return 0;
6350
6351         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6352                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6353                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6354                 info.text_data = &tg3Tso5FwText[0];
6355                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6356                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6357                 info.rodata_data = &tg3Tso5FwRodata[0];
6358                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6359                 info.data_len = TG3_TSO5_FW_DATA_LEN;
6360                 info.data_data = &tg3Tso5FwData[0];
6361                 cpu_base = RX_CPU_BASE;
6362                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6363                 cpu_scratch_size = (info.text_len +
6364                                     info.rodata_len +
6365                                     info.data_len +
6366                                     TG3_TSO5_FW_SBSS_LEN +
6367                                     TG3_TSO5_FW_BSS_LEN);
6368         } else {
6369                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6370                 info.text_len = TG3_TSO_FW_TEXT_LEN;
6371                 info.text_data = &tg3TsoFwText[0];
6372                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6373                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6374                 info.rodata_data = &tg3TsoFwRodata[0];
6375                 info.data_base = TG3_TSO_FW_DATA_ADDR;
6376                 info.data_len = TG3_TSO_FW_DATA_LEN;
6377                 info.data_data = &tg3TsoFwData[0];
6378                 cpu_base = TX_CPU_BASE;
6379                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6380                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6381         }
6382
6383         err = tg3_load_firmware_cpu(tp, cpu_base,
6384                                     cpu_scratch_base, cpu_scratch_size,
6385                                     &info);
6386         if (err)
6387                 return err;
6388
6389         /* Now startup the cpu. */
6390         tw32(cpu_base + CPU_STATE, 0xffffffff);
6391         tw32_f(cpu_base + CPU_PC,    info.text_base);
6392
6393         for (i = 0; i < 5; i++) {
6394                 if (tr32(cpu_base + CPU_PC) == info.text_base)
6395                         break;
6396                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6397                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6398                 tw32_f(cpu_base + CPU_PC,    info.text_base);
6399                 udelay(1000);
6400         }
6401         if (i >= 5) {
6402                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6403                        "to set CPU PC, is %08x should be %08x\n",
6404                        tp->dev->name, tr32(cpu_base + CPU_PC),
6405                        info.text_base);
6406                 return -ENODEV;
6407         }
6408         tw32(cpu_base + CPU_STATE, 0xffffffff);
6409         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6410         return 0;
6411 }
6412
6413
6414 /* tp->lock is held. */
6415 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6416 {
6417         u32 addr_high, addr_low;
6418         int i;
6419
6420         addr_high = ((tp->dev->dev_addr[0] << 8) |
6421                      tp->dev->dev_addr[1]);
6422         addr_low = ((tp->dev->dev_addr[2] << 24) |
6423                     (tp->dev->dev_addr[3] << 16) |
6424                     (tp->dev->dev_addr[4] <<  8) |
6425                     (tp->dev->dev_addr[5] <<  0));
6426         for (i = 0; i < 4; i++) {
6427                 if (i == 1 && skip_mac_1)
6428                         continue;
6429                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6430                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6431         }
6432
6433         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6434             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6435                 for (i = 0; i < 12; i++) {
6436                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6437                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6438                 }
6439         }
6440
6441         addr_high = (tp->dev->dev_addr[0] +
6442                      tp->dev->dev_addr[1] +
6443                      tp->dev->dev_addr[2] +
6444                      tp->dev->dev_addr[3] +
6445                      tp->dev->dev_addr[4] +
6446                      tp->dev->dev_addr[5]) &
6447                 TX_BACKOFF_SEED_MASK;
6448         tw32(MAC_TX_BACKOFF_SEED, addr_high);
6449 }
6450
6451 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6452 {
6453         struct tg3 *tp = netdev_priv(dev);
6454         struct sockaddr *addr = p;
6455         int err = 0, skip_mac_1 = 0;
6456
6457         if (!is_valid_ether_addr(addr->sa_data))
6458                 return -EINVAL;
6459
6460         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6461
6462         if (!netif_running(dev))
6463                 return 0;
6464
6465         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6466                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6467
6468                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6469                 addr0_low = tr32(MAC_ADDR_0_LOW);
6470                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6471                 addr1_low = tr32(MAC_ADDR_1_LOW);
6472
6473                 /* Skip MAC addr 1 if ASF is using it. */
6474                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6475                     !(addr1_high == 0 && addr1_low == 0))
6476                         skip_mac_1 = 1;
6477         }
6478         spin_lock_bh(&tp->lock);
6479         __tg3_set_mac_addr(tp, skip_mac_1);
6480         spin_unlock_bh(&tp->lock);
6481
6482         return err;
6483 }
6484
6485 /* tp->lock is held. */
6486 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6487                            dma_addr_t mapping, u32 maxlen_flags,
6488                            u32 nic_addr)
6489 {
6490         tg3_write_mem(tp,
6491                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6492                       ((u64) mapping >> 32));
6493         tg3_write_mem(tp,
6494                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6495                       ((u64) mapping & 0xffffffff));
6496         tg3_write_mem(tp,
6497                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6498                        maxlen_flags);
6499
6500         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6501                 tg3_write_mem(tp,
6502                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6503                               nic_addr);
6504 }
6505
6506 static void __tg3_set_rx_mode(struct net_device *);
6507 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6508 {
6509         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6510         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6511         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6512         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6513         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6514                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6515                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6516         }
6517         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6518         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6519         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6520                 u32 val = ec->stats_block_coalesce_usecs;
6521
6522                 if (!netif_carrier_ok(tp->dev))
6523                         val = 0;
6524
6525                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6526         }
6527 }
6528
6529 /* tp->lock is held. */
6530 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6531 {
6532         u32 val, rdmac_mode;
6533         int i, err, limit;
6534
6535         tg3_disable_ints(tp);
6536
6537         tg3_stop_fw(tp);
6538
6539         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6540
6541         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6542                 tg3_abort_hw(tp, 1);
6543         }
6544
6545         if (reset_phy)
6546                 tg3_phy_reset(tp);
6547
6548         err = tg3_chip_reset(tp);
6549         if (err)
6550                 return err;
6551
6552         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6553
6554         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
6555             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
6556                 val = tr32(TG3_CPMU_CTRL);
6557                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6558                 tw32(TG3_CPMU_CTRL, val);
6559
6560                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6561                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6562                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6563                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6564
6565                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6566                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6567                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6568                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6569
6570                 val = tr32(TG3_CPMU_HST_ACC);
6571                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6572                 val |= CPMU_HST_ACC_MACCLK_6_25;
6573                 tw32(TG3_CPMU_HST_ACC, val);
6574         }
6575
6576         /* This works around an issue with Athlon chipsets on
6577          * B3 tigon3 silicon.  This bit has no effect on any
6578          * other revision.  But do not set this on PCI Express
6579          * chips and don't even touch the clocks if the CPMU is present.
6580          */
6581         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6582                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6583                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6584                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6585         }
6586
6587         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6588             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6589                 val = tr32(TG3PCI_PCISTATE);
6590                 val |= PCISTATE_RETRY_SAME_DMA;
6591                 tw32(TG3PCI_PCISTATE, val);
6592         }
6593
6594         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6595                 /* Allow reads and writes to the
6596                  * APE register and memory space.
6597                  */
6598                 val = tr32(TG3PCI_PCISTATE);
6599                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6600                        PCISTATE_ALLOW_APE_SHMEM_WR;
6601                 tw32(TG3PCI_PCISTATE, val);
6602         }
6603
6604         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6605                 /* Enable some hw fixes.  */
6606                 val = tr32(TG3PCI_MSI_DATA);
6607                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6608                 tw32(TG3PCI_MSI_DATA, val);
6609         }
6610
6611         /* Descriptor ring init may make accesses to the
6612          * NIC SRAM area to setup the TX descriptors, so we
6613          * can only do this after the hardware has been
6614          * successfully reset.
6615          */
6616         err = tg3_init_rings(tp);
6617         if (err)
6618                 return err;
6619
6620         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6621             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6622                 /* This value is determined during the probe time DMA
6623                  * engine test, tg3_test_dma.
6624                  */
6625                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6626         }
6627
6628         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6629                           GRC_MODE_4X_NIC_SEND_RINGS |
6630                           GRC_MODE_NO_TX_PHDR_CSUM |
6631                           GRC_MODE_NO_RX_PHDR_CSUM);
6632         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6633
6634         /* Pseudo-header checksum is done by hardware logic and not
6635          * the offload processers, so make the chip do the pseudo-
6636          * header checksums on receive.  For transmit it is more
6637          * convenient to do the pseudo-header checksum in software
6638          * as Linux does that on transmit for us in all cases.
6639          */
6640         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6641
6642         tw32(GRC_MODE,
6643              tp->grc_mode |
6644              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6645
6646         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6647         val = tr32(GRC_MISC_CFG);
6648         val &= ~0xff;
6649         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6650         tw32(GRC_MISC_CFG, val);
6651
6652         /* Initialize MBUF/DESC pool. */
6653         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6654                 /* Do nothing.  */
6655         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6656                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6657                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6658                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6659                 else
6660                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6661                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6662                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6663         }
6664         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6665                 int fw_len;
6666
6667                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6668                           TG3_TSO5_FW_RODATA_LEN +
6669                           TG3_TSO5_FW_DATA_LEN +
6670                           TG3_TSO5_FW_SBSS_LEN +
6671                           TG3_TSO5_FW_BSS_LEN);
6672                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6673                 tw32(BUFMGR_MB_POOL_ADDR,
6674                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6675                 tw32(BUFMGR_MB_POOL_SIZE,
6676                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6677         }
6678
6679         if (tp->dev->mtu <= ETH_DATA_LEN) {
6680                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6681                      tp->bufmgr_config.mbuf_read_dma_low_water);
6682                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6683                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6684                 tw32(BUFMGR_MB_HIGH_WATER,
6685                      tp->bufmgr_config.mbuf_high_water);
6686         } else {
6687                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6688                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6689                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6690                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6691                 tw32(BUFMGR_MB_HIGH_WATER,
6692                      tp->bufmgr_config.mbuf_high_water_jumbo);
6693         }
6694         tw32(BUFMGR_DMA_LOW_WATER,
6695              tp->bufmgr_config.dma_low_water);
6696         tw32(BUFMGR_DMA_HIGH_WATER,
6697              tp->bufmgr_config.dma_high_water);
6698
6699         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6700         for (i = 0; i < 2000; i++) {
6701                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6702                         break;
6703                 udelay(10);
6704         }
6705         if (i >= 2000) {
6706                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6707                        tp->dev->name);
6708                 return -ENODEV;
6709         }
6710
6711         /* Setup replenish threshold. */
6712         val = tp->rx_pending / 8;
6713         if (val == 0)
6714                 val = 1;
6715         else if (val > tp->rx_std_max_post)
6716                 val = tp->rx_std_max_post;
6717         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6718                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6719                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6720
6721                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6722                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6723         }
6724
6725         tw32(RCVBDI_STD_THRESH, val);
6726
6727         /* Initialize TG3_BDINFO's at:
6728          *  RCVDBDI_STD_BD:     standard eth size rx ring
6729          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6730          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6731          *
6732          * like so:
6733          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6734          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6735          *                              ring attribute flags
6736          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6737          *
6738          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6739          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6740          *
6741          * The size of each ring is fixed in the firmware, but the location is
6742          * configurable.
6743          */
6744         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6745              ((u64) tp->rx_std_mapping >> 32));
6746         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6747              ((u64) tp->rx_std_mapping & 0xffffffff));
6748         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6749              NIC_SRAM_RX_BUFFER_DESC);
6750
6751         /* Don't even try to program the JUMBO/MINI buffer descriptor
6752          * configs on 5705.
6753          */
6754         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6755                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6756                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6757         } else {
6758                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6759                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6760
6761                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6762                      BDINFO_FLAGS_DISABLED);
6763
6764                 /* Setup replenish threshold. */
6765                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6766
6767                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6768                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6769                              ((u64) tp->rx_jumbo_mapping >> 32));
6770                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6771                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6772                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6773                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6774                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6775                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6776                 } else {
6777                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6778                              BDINFO_FLAGS_DISABLED);
6779                 }
6780
6781         }
6782
6783         /* There is only one send ring on 5705/5750, no need to explicitly
6784          * disable the others.
6785          */
6786         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6787                 /* Clear out send RCB ring in SRAM. */
6788                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6789                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6790                                       BDINFO_FLAGS_DISABLED);
6791         }
6792
6793         tp->tx_prod = 0;
6794         tp->tx_cons = 0;
6795         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6796         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6797
6798         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6799                        tp->tx_desc_mapping,
6800                        (TG3_TX_RING_SIZE <<
6801                         BDINFO_FLAGS_MAXLEN_SHIFT),
6802                        NIC_SRAM_TX_BUFFER_DESC);
6803
6804         /* There is only one receive return ring on 5705/5750, no need
6805          * to explicitly disable the others.
6806          */
6807         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6808                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6809                      i += TG3_BDINFO_SIZE) {
6810                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6811                                       BDINFO_FLAGS_DISABLED);
6812                 }
6813         }
6814
6815         tp->rx_rcb_ptr = 0;
6816         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6817
6818         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6819                        tp->rx_rcb_mapping,
6820                        (TG3_RX_RCB_RING_SIZE(tp) <<
6821                         BDINFO_FLAGS_MAXLEN_SHIFT),
6822                        0);
6823
6824         tp->rx_std_ptr = tp->rx_pending;
6825         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6826                      tp->rx_std_ptr);
6827
6828         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6829                                                 tp->rx_jumbo_pending : 0;
6830         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6831                      tp->rx_jumbo_ptr);
6832
6833         /* Initialize MAC address and backoff seed. */
6834         __tg3_set_mac_addr(tp, 0);
6835
6836         /* MTU + ethernet header + FCS + optional VLAN tag */
6837         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6838
6839         /* The slot time is changed by tg3_setup_phy if we
6840          * run at gigabit with half duplex.
6841          */
6842         tw32(MAC_TX_LENGTHS,
6843              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6844              (6 << TX_LENGTHS_IPG_SHIFT) |
6845              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6846
6847         /* Receive rules. */
6848         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6849         tw32(RCVLPC_CONFIG, 0x0181);
6850
6851         /* Calculate RDMAC_MODE setting early, we need it to determine
6852          * the RCVLPC_STATE_ENABLE mask.
6853          */
6854         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6855                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6856                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6857                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6858                       RDMAC_MODE_LNGREAD_ENAB);
6859
6860         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
6861                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
6862                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
6863                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
6864
6865         /* If statement applies to 5705 and 5750 PCI devices only */
6866         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6867              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6868             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6869                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6870                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6871                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6872                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6873                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6874                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6875                 }
6876         }
6877
6878         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6879                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6880
6881         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6882                 rdmac_mode |= (1 << 27);
6883
6884         /* Receive/send statistics. */
6885         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6886                 val = tr32(RCVLPC_STATS_ENABLE);
6887                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6888                 tw32(RCVLPC_STATS_ENABLE, val);
6889         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6890                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6891                 val = tr32(RCVLPC_STATS_ENABLE);
6892                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6893                 tw32(RCVLPC_STATS_ENABLE, val);
6894         } else {
6895                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6896         }
6897         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6898         tw32(SNDDATAI_STATSENAB, 0xffffff);
6899         tw32(SNDDATAI_STATSCTRL,
6900              (SNDDATAI_SCTRL_ENABLE |
6901               SNDDATAI_SCTRL_FASTUPD));
6902
6903         /* Setup host coalescing engine. */
6904         tw32(HOSTCC_MODE, 0);
6905         for (i = 0; i < 2000; i++) {
6906                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6907                         break;
6908                 udelay(10);
6909         }
6910
6911         __tg3_set_coalesce(tp, &tp->coal);
6912
6913         /* set status block DMA address */
6914         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6915              ((u64) tp->status_mapping >> 32));
6916         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6917              ((u64) tp->status_mapping & 0xffffffff));
6918
6919         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6920                 /* Status/statistics block address.  See tg3_timer,
6921                  * the tg3_periodic_fetch_stats call there, and
6922                  * tg3_get_stats to see how this works for 5705/5750 chips.
6923                  */
6924                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6925                      ((u64) tp->stats_mapping >> 32));
6926                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6927                      ((u64) tp->stats_mapping & 0xffffffff));
6928                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6929                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6930         }
6931
6932         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6933
6934         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6935         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6936         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6937                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6938
6939         /* Clear statistics/status block in chip, and status block in ram. */
6940         for (i = NIC_SRAM_STATS_BLK;
6941              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6942              i += sizeof(u32)) {
6943                 tg3_write_mem(tp, i, 0);
6944                 udelay(40);
6945         }
6946         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6947
6948         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6949                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6950                 /* reset to prevent losing 1st rx packet intermittently */
6951                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6952                 udelay(10);
6953         }
6954
6955         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6956                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6957         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6958             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6959             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
6960                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6961         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6962         udelay(40);
6963
6964         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6965          * If TG3_FLG2_IS_NIC is zero, we should read the
6966          * register to preserve the GPIO settings for LOMs. The GPIOs,
6967          * whether used as inputs or outputs, are set by boot code after
6968          * reset.
6969          */
6970         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6971                 u32 gpio_mask;
6972
6973                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6974                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6975                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6976
6977                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6978                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6979                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6980
6981                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6982                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6983
6984                 tp->grc_local_ctrl &= ~gpio_mask;
6985                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6986
6987                 /* GPIO1 must be driven high for eeprom write protect */
6988                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6989                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6990                                                GRC_LCLCTRL_GPIO_OUTPUT1);
6991         }
6992         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6993         udelay(100);
6994
6995         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6996         tp->last_tag = 0;
6997
6998         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6999                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7000                 udelay(40);
7001         }
7002
7003         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7004                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7005                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7006                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7007                WDMAC_MODE_LNGREAD_ENAB);
7008
7009         /* If statement applies to 5705 and 5750 PCI devices only */
7010         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7011              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7012             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7013                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7014                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7015                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7016                         /* nothing */
7017                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7018                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7019                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7020                         val |= WDMAC_MODE_RX_ACCEL;
7021                 }
7022         }
7023
7024         /* Enable host coalescing bug fix */
7025         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
7026             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
7027             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
7028             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761))
7029                 val |= (1 << 29);
7030
7031         tw32_f(WDMAC_MODE, val);
7032         udelay(40);
7033
7034         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7035                 u16 pcix_cmd;
7036
7037                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7038                                      &pcix_cmd);
7039                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7040                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7041                         pcix_cmd |= PCI_X_CMD_READ_2K;
7042                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7043                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7044                         pcix_cmd |= PCI_X_CMD_READ_2K;
7045                 }
7046                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7047                                       pcix_cmd);
7048         }
7049
7050         tw32_f(RDMAC_MODE, rdmac_mode);
7051         udelay(40);
7052
7053         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7054         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7055                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7056
7057         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7058                 tw32(SNDDATAC_MODE,
7059                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7060         else
7061                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7062
7063         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7064         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7065         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7066         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7067         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7068                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7069         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7070         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7071
7072         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7073                 err = tg3_load_5701_a0_firmware_fix(tp);
7074                 if (err)
7075                         return err;
7076         }
7077
7078         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7079                 err = tg3_load_tso_firmware(tp);
7080                 if (err)
7081                         return err;
7082         }
7083
7084         tp->tx_mode = TX_MODE_ENABLE;
7085         tw32_f(MAC_TX_MODE, tp->tx_mode);
7086         udelay(100);
7087
7088         tp->rx_mode = RX_MODE_ENABLE;
7089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7090             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7091                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7092
7093         tw32_f(MAC_RX_MODE, tp->rx_mode);
7094         udelay(10);
7095
7096         if (tp->link_config.phy_is_low_power) {
7097                 tp->link_config.phy_is_low_power = 0;
7098                 tp->link_config.speed = tp->link_config.orig_speed;
7099                 tp->link_config.duplex = tp->link_config.orig_duplex;
7100                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7101         }
7102
7103         tp->mi_mode = MAC_MI_MODE_BASE;
7104         tw32_f(MAC_MI_MODE, tp->mi_mode);
7105         udelay(80);
7106
7107         tw32(MAC_LED_CTRL, tp->led_ctrl);
7108
7109         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7110         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7111                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7112                 udelay(10);
7113         }
7114         tw32_f(MAC_RX_MODE, tp->rx_mode);
7115         udelay(10);
7116
7117         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7118                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7119                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7120                         /* Set drive transmission level to 1.2V  */
7121                         /* only if the signal pre-emphasis bit is not set  */
7122                         val = tr32(MAC_SERDES_CFG);
7123                         val &= 0xfffff000;
7124                         val |= 0x880;
7125                         tw32(MAC_SERDES_CFG, val);
7126                 }
7127                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7128                         tw32(MAC_SERDES_CFG, 0x616000);
7129         }
7130
7131         /* Prevent chip from dropping frames when flow control
7132          * is enabled.
7133          */
7134         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7135
7136         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7137             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7138                 /* Use hardware link auto-negotiation */
7139                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7140         }
7141
7142         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7143             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7144                 u32 tmp;
7145
7146                 tmp = tr32(SERDES_RX_CTRL);
7147                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7148                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7149                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7150                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7151         }
7152
7153         err = tg3_setup_phy(tp, 0);
7154         if (err)
7155                 return err;
7156
7157         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7158             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7159                 u32 tmp;
7160
7161                 /* Clear CRC stats. */
7162                 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7163                         tg3_writephy(tp, MII_TG3_TEST1,
7164                                      tmp | MII_TG3_TEST1_CRC_EN);
7165                         tg3_readphy(tp, 0x14, &tmp);
7166                 }
7167         }
7168
7169         __tg3_set_rx_mode(tp->dev);
7170
7171         /* Initialize receive rules. */
7172         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7173         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7174         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7175         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7176
7177         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7178             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7179                 limit = 8;
7180         else
7181                 limit = 16;
7182         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7183                 limit -= 4;
7184         switch (limit) {
7185         case 16:
7186                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7187         case 15:
7188                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7189         case 14:
7190                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7191         case 13:
7192                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7193         case 12:
7194                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7195         case 11:
7196                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7197         case 10:
7198                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7199         case 9:
7200                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7201         case 8:
7202                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7203         case 7:
7204                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7205         case 6:
7206                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7207         case 5:
7208                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7209         case 4:
7210                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7211         case 3:
7212                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7213         case 2:
7214         case 1:
7215
7216         default:
7217                 break;
7218         };
7219
7220         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7221                 /* Write our heartbeat update interval to APE. */
7222                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7223                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7224
7225         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7226
7227         return 0;
7228 }
7229
7230 /* Called at device open time to get the chip ready for
7231  * packet processing.  Invoked with tp->lock held.
7232  */
7233 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7234 {
7235         int err;
7236
7237         /* Force the chip into D0. */
7238         err = tg3_set_power_state(tp, PCI_D0);
7239         if (err)
7240                 goto out;
7241
7242         tg3_switch_clocks(tp);
7243
7244         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7245
7246         err = tg3_reset_hw(tp, reset_phy);
7247
7248 out:
7249         return err;
7250 }
7251
7252 #define TG3_STAT_ADD32(PSTAT, REG) \
7253 do {    u32 __val = tr32(REG); \
7254         (PSTAT)->low += __val; \
7255         if ((PSTAT)->low < __val) \
7256                 (PSTAT)->high += 1; \
7257 } while (0)
7258
7259 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7260 {
7261         struct tg3_hw_stats *sp = tp->hw_stats;
7262
7263         if (!netif_carrier_ok(tp->dev))
7264                 return;
7265
7266         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7267         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7268         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7269         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7270         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7271         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7272         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7273         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7274         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7275         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7276         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7277         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7278         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7279
7280         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7281         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7282         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7283         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7284         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7285         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7286         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7287         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7288         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7289         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7290         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7291         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7292         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7293         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7294
7295         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7296         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7297         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7298 }
7299
7300 static void tg3_timer(unsigned long __opaque)
7301 {
7302         struct tg3 *tp = (struct tg3 *) __opaque;
7303
7304         if (tp->irq_sync)
7305                 goto restart_timer;
7306
7307         spin_lock(&tp->lock);
7308
7309         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7310                 /* All of this garbage is because when using non-tagged
7311                  * IRQ status the mailbox/status_block protocol the chip
7312                  * uses with the cpu is race prone.
7313                  */
7314                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7315                         tw32(GRC_LOCAL_CTRL,
7316                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7317                 } else {
7318                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7319                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7320                 }
7321
7322                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7323                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7324                         spin_unlock(&tp->lock);
7325                         schedule_work(&tp->reset_task);
7326                         return;
7327                 }
7328         }
7329
7330         /* This part only runs once per second. */
7331         if (!--tp->timer_counter) {
7332                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7333                         tg3_periodic_fetch_stats(tp);
7334
7335                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7336                         u32 mac_stat;
7337                         int phy_event;
7338
7339                         mac_stat = tr32(MAC_STATUS);
7340
7341                         phy_event = 0;
7342                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7343                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7344                                         phy_event = 1;
7345                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7346                                 phy_event = 1;
7347
7348                         if (phy_event)
7349                                 tg3_setup_phy(tp, 0);
7350                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7351                         u32 mac_stat = tr32(MAC_STATUS);
7352                         int need_setup = 0;
7353
7354                         if (netif_carrier_ok(tp->dev) &&
7355                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7356                                 need_setup = 1;
7357                         }
7358                         if (! netif_carrier_ok(tp->dev) &&
7359                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7360                                          MAC_STATUS_SIGNAL_DET))) {
7361                                 need_setup = 1;
7362                         }
7363                         if (need_setup) {
7364                                 if (!tp->serdes_counter) {
7365                                         tw32_f(MAC_MODE,
7366                                              (tp->mac_mode &
7367                                               ~MAC_MODE_PORT_MODE_MASK));
7368                                         udelay(40);
7369                                         tw32_f(MAC_MODE, tp->mac_mode);
7370                                         udelay(40);
7371                                 }
7372                                 tg3_setup_phy(tp, 0);
7373                         }
7374                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7375                         tg3_serdes_parallel_detect(tp);
7376
7377                 tp->timer_counter = tp->timer_multiplier;
7378         }
7379
7380         /* Heartbeat is only sent once every 2 seconds.
7381          *
7382          * The heartbeat is to tell the ASF firmware that the host
7383          * driver is still alive.  In the event that the OS crashes,
7384          * ASF needs to reset the hardware to free up the FIFO space
7385          * that may be filled with rx packets destined for the host.
7386          * If the FIFO is full, ASF will no longer function properly.
7387          *
7388          * Unintended resets have been reported on real time kernels
7389          * where the timer doesn't run on time.  Netpoll will also have
7390          * same problem.
7391          *
7392          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7393          * to check the ring condition when the heartbeat is expiring
7394          * before doing the reset.  This will prevent most unintended
7395          * resets.
7396          */
7397         if (!--tp->asf_counter) {
7398                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7399                         u32 val;
7400
7401                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7402                                       FWCMD_NICDRV_ALIVE3);
7403                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7404                         /* 5 seconds timeout */
7405                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7406                         val = tr32(GRC_RX_CPU_EVENT);
7407                         val |= (1 << 14);
7408                         tw32(GRC_RX_CPU_EVENT, val);
7409                 }
7410                 tp->asf_counter = tp->asf_multiplier;
7411         }
7412
7413         spin_unlock(&tp->lock);
7414
7415 restart_timer:
7416         tp->timer.expires = jiffies + tp->timer_offset;
7417         add_timer(&tp->timer);
7418 }
7419
7420 static int tg3_request_irq(struct tg3 *tp)
7421 {
7422         irq_handler_t fn;
7423         unsigned long flags;
7424         struct net_device *dev = tp->dev;
7425
7426         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7427                 fn = tg3_msi;
7428                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7429                         fn = tg3_msi_1shot;
7430                 flags = IRQF_SAMPLE_RANDOM;
7431         } else {
7432                 fn = tg3_interrupt;
7433                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7434                         fn = tg3_interrupt_tagged;
7435                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7436         }
7437         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7438 }
7439
7440 static int tg3_test_interrupt(struct tg3 *tp)
7441 {
7442         struct net_device *dev = tp->dev;
7443         int err, i, intr_ok = 0;
7444
7445         if (!netif_running(dev))
7446                 return -ENODEV;
7447
7448         tg3_disable_ints(tp);
7449
7450         free_irq(tp->pdev->irq, dev);
7451
7452         err = request_irq(tp->pdev->irq, tg3_test_isr,
7453                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7454         if (err)
7455                 return err;
7456
7457         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7458         tg3_enable_ints(tp);
7459
7460         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7461                HOSTCC_MODE_NOW);
7462
7463         for (i = 0; i < 5; i++) {
7464                 u32 int_mbox, misc_host_ctrl;
7465
7466                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7467                                         TG3_64BIT_REG_LOW);
7468                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7469
7470                 if ((int_mbox != 0) ||
7471                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7472                         intr_ok = 1;
7473                         break;
7474                 }
7475
7476                 msleep(10);
7477         }
7478
7479         tg3_disable_ints(tp);
7480
7481         free_irq(tp->pdev->irq, dev);
7482
7483         err = tg3_request_irq(tp);
7484
7485         if (err)
7486                 return err;
7487
7488         if (intr_ok)
7489                 return 0;
7490
7491         return -EIO;
7492 }
7493
7494 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7495  * successfully restored
7496  */
7497 static int tg3_test_msi(struct tg3 *tp)
7498 {
7499         struct net_device *dev = tp->dev;
7500         int err;
7501         u16 pci_cmd;
7502
7503         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7504                 return 0;
7505
7506         /* Turn off SERR reporting in case MSI terminates with Master
7507          * Abort.
7508          */
7509         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7510         pci_write_config_word(tp->pdev, PCI_COMMAND,
7511                               pci_cmd & ~PCI_COMMAND_SERR);
7512
7513         err = tg3_test_interrupt(tp);
7514
7515         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7516
7517         if (!err)
7518                 return 0;
7519
7520         /* other failures */
7521         if (err != -EIO)
7522                 return err;
7523
7524         /* MSI test failed, go back to INTx mode */
7525         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7526                "switching to INTx mode. Please report this failure to "
7527                "the PCI maintainer and include system chipset information.\n",
7528                        tp->dev->name);
7529
7530         free_irq(tp->pdev->irq, dev);
7531         pci_disable_msi(tp->pdev);
7532
7533         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7534
7535         err = tg3_request_irq(tp);
7536         if (err)
7537                 return err;
7538
7539         /* Need to reset the chip because the MSI cycle may have terminated
7540          * with Master Abort.
7541          */
7542         tg3_full_lock(tp, 1);
7543
7544         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7545         err = tg3_init_hw(tp, 1);
7546
7547         tg3_full_unlock(tp);
7548
7549         if (err)
7550                 free_irq(tp->pdev->irq, dev);
7551
7552         return err;
7553 }
7554
7555 static int tg3_open(struct net_device *dev)
7556 {
7557         struct tg3 *tp = netdev_priv(dev);
7558         int err;
7559
7560         netif_carrier_off(tp->dev);
7561
7562         tg3_full_lock(tp, 0);
7563
7564         err = tg3_set_power_state(tp, PCI_D0);
7565         if (err) {
7566                 tg3_full_unlock(tp);
7567                 return err;
7568         }
7569
7570         tg3_disable_ints(tp);
7571         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7572
7573         tg3_full_unlock(tp);
7574
7575         /* The placement of this call is tied
7576          * to the setup and use of Host TX descriptors.
7577          */
7578         err = tg3_alloc_consistent(tp);
7579         if (err)
7580                 return err;
7581
7582         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7583                 /* All MSI supporting chips should support tagged
7584                  * status.  Assert that this is the case.
7585                  */
7586                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7587                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7588                                "Not using MSI.\n", tp->dev->name);
7589                 } else if (pci_enable_msi(tp->pdev) == 0) {
7590                         u32 msi_mode;
7591
7592                         msi_mode = tr32(MSGINT_MODE);
7593                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7594                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7595                 }
7596         }
7597         err = tg3_request_irq(tp);
7598
7599         if (err) {
7600                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7601                         pci_disable_msi(tp->pdev);
7602                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7603                 }
7604                 tg3_free_consistent(tp);
7605                 return err;
7606         }
7607
7608         napi_enable(&tp->napi);
7609
7610         tg3_full_lock(tp, 0);
7611
7612         err = tg3_init_hw(tp, 1);
7613         if (err) {
7614                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7615                 tg3_free_rings(tp);
7616         } else {
7617                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7618                         tp->timer_offset = HZ;
7619                 else
7620                         tp->timer_offset = HZ / 10;
7621
7622                 BUG_ON(tp->timer_offset > HZ);
7623                 tp->timer_counter = tp->timer_multiplier =
7624                         (HZ / tp->timer_offset);
7625                 tp->asf_counter = tp->asf_multiplier =
7626                         ((HZ / tp->timer_offset) * 2);
7627
7628                 init_timer(&tp->timer);
7629                 tp->timer.expires = jiffies + tp->timer_offset;
7630                 tp->timer.data = (unsigned long) tp;
7631                 tp->timer.function = tg3_timer;
7632         }
7633
7634         tg3_full_unlock(tp);
7635
7636         if (err) {
7637                 napi_disable(&tp->napi);
7638                 free_irq(tp->pdev->irq, dev);
7639                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7640                         pci_disable_msi(tp->pdev);
7641                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7642                 }
7643                 tg3_free_consistent(tp);
7644                 return err;
7645         }
7646
7647         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7648                 err = tg3_test_msi(tp);
7649
7650                 if (err) {
7651                         tg3_full_lock(tp, 0);
7652
7653                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7654                                 pci_disable_msi(tp->pdev);
7655                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7656                         }
7657                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7658                         tg3_free_rings(tp);
7659                         tg3_free_consistent(tp);
7660
7661                         tg3_full_unlock(tp);
7662
7663                         napi_disable(&tp->napi);
7664
7665                         return err;
7666                 }
7667
7668                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7669                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7670                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7671
7672                                 tw32(PCIE_TRANSACTION_CFG,
7673                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7674                         }
7675                 }
7676         }
7677
7678         tg3_full_lock(tp, 0);
7679
7680         add_timer(&tp->timer);
7681         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7682         tg3_enable_ints(tp);
7683
7684         tg3_full_unlock(tp);
7685
7686         netif_start_queue(dev);
7687
7688         return 0;
7689 }
7690
7691 #if 0
7692 /*static*/ void tg3_dump_state(struct tg3 *tp)
7693 {
7694         u32 val32, val32_2, val32_3, val32_4, val32_5;
7695         u16 val16;
7696         int i;
7697
7698         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7699         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7700         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7701                val16, val32);
7702
7703         /* MAC block */
7704         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7705                tr32(MAC_MODE), tr32(MAC_STATUS));
7706         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7707                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7708         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7709                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7710         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7711                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7712
7713         /* Send data initiator control block */
7714         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7715                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7716         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7717                tr32(SNDDATAI_STATSCTRL));
7718
7719         /* Send data completion control block */
7720         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7721
7722         /* Send BD ring selector block */
7723         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7724                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7725
7726         /* Send BD initiator control block */
7727         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7728                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7729
7730         /* Send BD completion control block */
7731         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7732
7733         /* Receive list placement control block */
7734         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7735                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7736         printk("       RCVLPC_STATSCTRL[%08x]\n",
7737                tr32(RCVLPC_STATSCTRL));
7738
7739         /* Receive data and receive BD initiator control block */
7740         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7741                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7742
7743         /* Receive data completion control block */
7744         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7745                tr32(RCVDCC_MODE));
7746
7747         /* Receive BD initiator control block */
7748         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7749                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7750
7751         /* Receive BD completion control block */
7752         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7753                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7754
7755         /* Receive list selector control block */
7756         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7757                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7758
7759         /* Mbuf cluster free block */
7760         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7761                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7762
7763         /* Host coalescing control block */
7764         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7765                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7766         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7767                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7768                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7769         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7770                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7771                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7772         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7773                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7774         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7775                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7776
7777         /* Memory arbiter control block */
7778         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7779                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7780
7781         /* Buffer manager control block */
7782         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7783                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7784         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7785                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7786         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7787                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7788                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7789                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7790
7791         /* Read DMA control block */
7792         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7793                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7794
7795         /* Write DMA control block */
7796         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7797                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7798
7799         /* DMA completion block */
7800         printk("DEBUG: DMAC_MODE[%08x]\n",
7801                tr32(DMAC_MODE));
7802
7803         /* GRC block */
7804         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7805                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7806         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7807                tr32(GRC_LOCAL_CTRL));
7808
7809         /* TG3_BDINFOs */
7810         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7811                tr32(RCVDBDI_JUMBO_BD + 0x0),
7812                tr32(RCVDBDI_JUMBO_BD + 0x4),
7813                tr32(RCVDBDI_JUMBO_BD + 0x8),
7814                tr32(RCVDBDI_JUMBO_BD + 0xc));
7815         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7816                tr32(RCVDBDI_STD_BD + 0x0),
7817                tr32(RCVDBDI_STD_BD + 0x4),
7818                tr32(RCVDBDI_STD_BD + 0x8),
7819                tr32(RCVDBDI_STD_BD + 0xc));
7820         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7821                tr32(RCVDBDI_MINI_BD + 0x0),
7822                tr32(RCVDBDI_MINI_BD + 0x4),
7823                tr32(RCVDBDI_MINI_BD + 0x8),
7824                tr32(RCVDBDI_MINI_BD + 0xc));
7825
7826         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7827         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7828         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7829         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7830         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7831                val32, val32_2, val32_3, val32_4);
7832
7833         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7834         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7835         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7836         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7837         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7838                val32, val32_2, val32_3, val32_4);
7839
7840         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7841         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7842         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7843         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7844         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7845         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7846                val32, val32_2, val32_3, val32_4, val32_5);
7847
7848         /* SW status block */
7849         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7850                tp->hw_status->status,
7851                tp->hw_status->status_tag,
7852                tp->hw_status->rx_jumbo_consumer,
7853                tp->hw_status->rx_consumer,
7854                tp->hw_status->rx_mini_consumer,
7855                tp->hw_status->idx[0].rx_producer,
7856                tp->hw_status->idx[0].tx_consumer);
7857
7858         /* SW statistics block */
7859         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7860                ((u32 *)tp->hw_stats)[0],
7861                ((u32 *)tp->hw_stats)[1],
7862                ((u32 *)tp->hw_stats)[2],
7863                ((u32 *)tp->hw_stats)[3]);
7864
7865         /* Mailboxes */
7866         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7867                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7868                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7869                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7870                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7871
7872         /* NIC side send descriptors. */
7873         for (i = 0; i < 6; i++) {
7874                 unsigned long txd;
7875
7876                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7877                         + (i * sizeof(struct tg3_tx_buffer_desc));
7878                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7879                        i,
7880                        readl(txd + 0x0), readl(txd + 0x4),
7881                        readl(txd + 0x8), readl(txd + 0xc));
7882         }
7883
7884         /* NIC side RX descriptors. */
7885         for (i = 0; i < 6; i++) {
7886                 unsigned long rxd;
7887
7888                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7889                         + (i * sizeof(struct tg3_rx_buffer_desc));
7890                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7891                        i,
7892                        readl(rxd + 0x0), readl(rxd + 0x4),
7893                        readl(rxd + 0x8), readl(rxd + 0xc));
7894                 rxd += (4 * sizeof(u32));
7895                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7896                        i,
7897                        readl(rxd + 0x0), readl(rxd + 0x4),
7898                        readl(rxd + 0x8), readl(rxd + 0xc));
7899         }
7900
7901         for (i = 0; i < 6; i++) {
7902                 unsigned long rxd;
7903
7904                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7905                         + (i * sizeof(struct tg3_rx_buffer_desc));
7906                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7907                        i,
7908                        readl(rxd + 0x0), readl(rxd + 0x4),
7909                        readl(rxd + 0x8), readl(rxd + 0xc));
7910                 rxd += (4 * sizeof(u32));
7911                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7912                        i,
7913                        readl(rxd + 0x0), readl(rxd + 0x4),
7914                        readl(rxd + 0x8), readl(rxd + 0xc));
7915         }
7916 }
7917 #endif
7918
7919 static struct net_device_stats *tg3_get_stats(struct net_device *);
7920 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7921
7922 static int tg3_close(struct net_device *dev)
7923 {
7924         struct tg3 *tp = netdev_priv(dev);
7925
7926         napi_disable(&tp->napi);
7927         cancel_work_sync(&tp->reset_task);
7928
7929         netif_stop_queue(dev);
7930
7931         del_timer_sync(&tp->timer);
7932
7933         tg3_full_lock(tp, 1);
7934 #if 0
7935         tg3_dump_state(tp);
7936 #endif
7937
7938         tg3_disable_ints(tp);
7939
7940         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7941         tg3_free_rings(tp);
7942         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7943
7944         tg3_full_unlock(tp);
7945
7946         free_irq(tp->pdev->irq, dev);
7947         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7948                 pci_disable_msi(tp->pdev);
7949                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7950         }
7951
7952         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7953                sizeof(tp->net_stats_prev));
7954         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7955                sizeof(tp->estats_prev));
7956
7957         tg3_free_consistent(tp);
7958
7959         tg3_set_power_state(tp, PCI_D3hot);
7960
7961         netif_carrier_off(tp->dev);
7962
7963         return 0;
7964 }
7965
7966 static inline unsigned long get_stat64(tg3_stat64_t *val)
7967 {
7968         unsigned long ret;
7969
7970 #if (BITS_PER_LONG == 32)
7971         ret = val->low;
7972 #else
7973         ret = ((u64)val->high << 32) | ((u64)val->low);
7974 #endif
7975         return ret;
7976 }
7977
7978 static unsigned long calc_crc_errors(struct tg3 *tp)
7979 {
7980         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7981
7982         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7983             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7984              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7985                 u32 val;
7986
7987                 spin_lock_bh(&tp->lock);
7988                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7989                         tg3_writephy(tp, MII_TG3_TEST1,
7990                                      val | MII_TG3_TEST1_CRC_EN);
7991                         tg3_readphy(tp, 0x14, &val);
7992                 } else
7993                         val = 0;
7994                 spin_unlock_bh(&tp->lock);
7995
7996                 tp->phy_crc_errors += val;
7997
7998                 return tp->phy_crc_errors;
7999         }
8000
8001         return get_stat64(&hw_stats->rx_fcs_errors);
8002 }
8003
8004 #define ESTAT_ADD(member) \
8005         estats->member =        old_estats->member + \
8006                                 get_stat64(&hw_stats->member)
8007
8008 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8009 {
8010         struct tg3_ethtool_stats *estats = &tp->estats;
8011         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8012         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8013
8014         if (!hw_stats)
8015                 return old_estats;
8016
8017         ESTAT_ADD(rx_octets);
8018         ESTAT_ADD(rx_fragments);
8019         ESTAT_ADD(rx_ucast_packets);
8020         ESTAT_ADD(rx_mcast_packets);
8021         ESTAT_ADD(rx_bcast_packets);
8022         ESTAT_ADD(rx_fcs_errors);
8023         ESTAT_ADD(rx_align_errors);
8024         ESTAT_ADD(rx_xon_pause_rcvd);
8025         ESTAT_ADD(rx_xoff_pause_rcvd);
8026         ESTAT_ADD(rx_mac_ctrl_rcvd);
8027         ESTAT_ADD(rx_xoff_entered);
8028         ESTAT_ADD(rx_frame_too_long_errors);
8029         ESTAT_ADD(rx_jabbers);
8030         ESTAT_ADD(rx_undersize_packets);
8031         ESTAT_ADD(rx_in_length_errors);
8032         ESTAT_ADD(rx_out_length_errors);
8033         ESTAT_ADD(rx_64_or_less_octet_packets);
8034         ESTAT_ADD(rx_65_to_127_octet_packets);
8035         ESTAT_ADD(rx_128_to_255_octet_packets);
8036         ESTAT_ADD(rx_256_to_511_octet_packets);
8037         ESTAT_ADD(rx_512_to_1023_octet_packets);
8038         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8039         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8040         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8041         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8042         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8043
8044         ESTAT_ADD(tx_octets);
8045         ESTAT_ADD(tx_collisions);
8046         ESTAT_ADD(tx_xon_sent);
8047         ESTAT_ADD(tx_xoff_sent);
8048         ESTAT_ADD(tx_flow_control);
8049         ESTAT_ADD(tx_mac_errors);
8050         ESTAT_ADD(tx_single_collisions);
8051         ESTAT_ADD(tx_mult_collisions);
8052         ESTAT_ADD(tx_deferred);
8053         ESTAT_ADD(tx_excessive_collisions);
8054         ESTAT_ADD(tx_late_collisions);
8055         ESTAT_ADD(tx_collide_2times);
8056         ESTAT_ADD(tx_collide_3times);
8057         ESTAT_ADD(tx_collide_4times);
8058         ESTAT_ADD(tx_collide_5times);
8059         ESTAT_ADD(tx_collide_6times);
8060         ESTAT_ADD(tx_collide_7times);
8061         ESTAT_ADD(tx_collide_8times);
8062         ESTAT_ADD(tx_collide_9times);
8063         ESTAT_ADD(tx_collide_10times);
8064         ESTAT_ADD(tx_collide_11times);
8065         ESTAT_ADD(tx_collide_12times);
8066         ESTAT_ADD(tx_collide_13times);
8067         ESTAT_ADD(tx_collide_14times);
8068         ESTAT_ADD(tx_collide_15times);
8069         ESTAT_ADD(tx_ucast_packets);
8070         ESTAT_ADD(tx_mcast_packets);
8071         ESTAT_ADD(tx_bcast_packets);
8072         ESTAT_ADD(tx_carrier_sense_errors);
8073         ESTAT_ADD(tx_discards);
8074         ESTAT_ADD(tx_errors);
8075
8076         ESTAT_ADD(dma_writeq_full);
8077         ESTAT_ADD(dma_write_prioq_full);
8078         ESTAT_ADD(rxbds_empty);
8079         ESTAT_ADD(rx_discards);
8080         ESTAT_ADD(rx_errors);
8081         ESTAT_ADD(rx_threshold_hit);
8082
8083         ESTAT_ADD(dma_readq_full);
8084         ESTAT_ADD(dma_read_prioq_full);
8085         ESTAT_ADD(tx_comp_queue_full);
8086
8087         ESTAT_ADD(ring_set_send_prod_index);
8088         ESTAT_ADD(ring_status_update);
8089         ESTAT_ADD(nic_irqs);
8090         ESTAT_ADD(nic_avoided_irqs);
8091         ESTAT_ADD(nic_tx_threshold_hit);
8092
8093         return estats;
8094 }
8095
8096 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8097 {
8098         struct tg3 *tp = netdev_priv(dev);
8099         struct net_device_stats *stats = &tp->net_stats;
8100         struct net_device_stats *old_stats = &tp->net_stats_prev;
8101         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8102
8103         if (!hw_stats)
8104                 return old_stats;
8105
8106         stats->rx_packets = old_stats->rx_packets +
8107                 get_stat64(&hw_stats->rx_ucast_packets) +
8108                 get_stat64(&hw_stats->rx_mcast_packets) +
8109                 get_stat64(&hw_stats->rx_bcast_packets);
8110
8111         stats->tx_packets = old_stats->tx_packets +
8112                 get_stat64(&hw_stats->tx_ucast_packets) +
8113                 get_stat64(&hw_stats->tx_mcast_packets) +
8114                 get_stat64(&hw_stats->tx_bcast_packets);
8115
8116         stats->rx_bytes = old_stats->rx_bytes +
8117                 get_stat64(&hw_stats->rx_octets);
8118         stats->tx_bytes = old_stats->tx_bytes +
8119                 get_stat64(&hw_stats->tx_octets);
8120
8121         stats->rx_errors = old_stats->rx_errors +
8122                 get_stat64(&hw_stats->rx_errors);
8123         stats->tx_errors = old_stats->tx_errors +
8124                 get_stat64(&hw_stats->tx_errors) +
8125                 get_stat64(&hw_stats->tx_mac_errors) +
8126                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8127                 get_stat64(&hw_stats->tx_discards);
8128
8129         stats->multicast = old_stats->multicast +
8130                 get_stat64(&hw_stats->rx_mcast_packets);
8131         stats->collisions = old_stats->collisions +
8132                 get_stat64(&hw_stats->tx_collisions);
8133
8134         stats->rx_length_errors = old_stats->rx_length_errors +
8135                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8136                 get_stat64(&hw_stats->rx_undersize_packets);
8137
8138         stats->rx_over_errors = old_stats->rx_over_errors +
8139                 get_stat64(&hw_stats->rxbds_empty);
8140         stats->rx_frame_errors = old_stats->rx_frame_errors +
8141                 get_stat64(&hw_stats->rx_align_errors);
8142         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8143                 get_stat64(&hw_stats->tx_discards);
8144         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8145                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8146
8147         stats->rx_crc_errors = old_stats->rx_crc_errors +
8148                 calc_crc_errors(tp);
8149
8150         stats->rx_missed_errors = old_stats->rx_missed_errors +
8151                 get_stat64(&hw_stats->rx_discards);
8152
8153         return stats;
8154 }
8155
8156 static inline u32 calc_crc(unsigned char *buf, int len)
8157 {
8158         u32 reg;
8159         u32 tmp;
8160         int j, k;
8161
8162         reg = 0xffffffff;
8163
8164         for (j = 0; j < len; j++) {
8165                 reg ^= buf[j];
8166
8167                 for (k = 0; k < 8; k++) {
8168                         tmp = reg & 0x01;
8169
8170                         reg >>= 1;
8171
8172                         if (tmp) {
8173                                 reg ^= 0xedb88320;
8174                         }
8175                 }
8176         }
8177
8178         return ~reg;
8179 }
8180
8181 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8182 {
8183         /* accept or reject all multicast frames */
8184         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8185         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8186         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8187         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8188 }
8189
8190 static void __tg3_set_rx_mode(struct net_device *dev)
8191 {
8192         struct tg3 *tp = netdev_priv(dev);
8193         u32 rx_mode;
8194
8195         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8196                                   RX_MODE_KEEP_VLAN_TAG);
8197
8198         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8199          * flag clear.
8200          */
8201 #if TG3_VLAN_TAG_USED
8202         if (!tp->vlgrp &&
8203             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8204                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8205 #else
8206         /* By definition, VLAN is disabled always in this
8207          * case.
8208          */
8209         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8210                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8211 #endif
8212
8213         if (dev->flags & IFF_PROMISC) {
8214                 /* Promiscuous mode. */
8215                 rx_mode |= RX_MODE_PROMISC;
8216         } else if (dev->flags & IFF_ALLMULTI) {
8217                 /* Accept all multicast. */
8218                 tg3_set_multi (tp, 1);
8219         } else if (dev->mc_count < 1) {
8220                 /* Reject all multicast. */
8221                 tg3_set_multi (tp, 0);
8222         } else {
8223                 /* Accept one or more multicast(s). */
8224                 struct dev_mc_list *mclist;
8225                 unsigned int i;
8226                 u32 mc_filter[4] = { 0, };
8227                 u32 regidx;
8228                 u32 bit;
8229                 u32 crc;
8230
8231                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8232                      i++, mclist = mclist->next) {
8233
8234                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8235                         bit = ~crc & 0x7f;
8236                         regidx = (bit & 0x60) >> 5;
8237                         bit &= 0x1f;
8238                         mc_filter[regidx] |= (1 << bit);
8239                 }
8240
8241                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8242                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8243                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8244                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8245         }
8246
8247         if (rx_mode != tp->rx_mode) {
8248                 tp->rx_mode = rx_mode;
8249                 tw32_f(MAC_RX_MODE, rx_mode);
8250                 udelay(10);
8251         }
8252 }
8253
8254 static void tg3_set_rx_mode(struct net_device *dev)
8255 {
8256         struct tg3 *tp = netdev_priv(dev);
8257
8258         if (!netif_running(dev))
8259                 return;
8260
8261         tg3_full_lock(tp, 0);
8262         __tg3_set_rx_mode(dev);
8263         tg3_full_unlock(tp);
8264 }
8265
8266 #define TG3_REGDUMP_LEN         (32 * 1024)
8267
8268 static int tg3_get_regs_len(struct net_device *dev)
8269 {
8270         return TG3_REGDUMP_LEN;
8271 }
8272
8273 static void tg3_get_regs(struct net_device *dev,
8274                 struct ethtool_regs *regs, void *_p)
8275 {
8276         u32 *p = _p;
8277         struct tg3 *tp = netdev_priv(dev);
8278         u8 *orig_p = _p;
8279         int i;
8280
8281         regs->version = 0;
8282
8283         memset(p, 0, TG3_REGDUMP_LEN);
8284
8285         if (tp->link_config.phy_is_low_power)
8286                 return;
8287
8288         tg3_full_lock(tp, 0);
8289
8290 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8291 #define GET_REG32_LOOP(base,len)                \
8292 do {    p = (u32 *)(orig_p + (base));           \
8293         for (i = 0; i < len; i += 4)            \
8294                 __GET_REG32((base) + i);        \
8295 } while (0)
8296 #define GET_REG32_1(reg)                        \
8297 do {    p = (u32 *)(orig_p + (reg));            \
8298         __GET_REG32((reg));                     \
8299 } while (0)
8300
8301         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8302         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8303         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8304         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8305         GET_REG32_1(SNDDATAC_MODE);
8306         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8307         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8308         GET_REG32_1(SNDBDC_MODE);
8309         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8310         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8311         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8312         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8313         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8314         GET_REG32_1(RCVDCC_MODE);
8315         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8316         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8317         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8318         GET_REG32_1(MBFREE_MODE);
8319         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8320         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8321         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8322         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8323         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8324         GET_REG32_1(RX_CPU_MODE);
8325         GET_REG32_1(RX_CPU_STATE);
8326         GET_REG32_1(RX_CPU_PGMCTR);
8327         GET_REG32_1(RX_CPU_HWBKPT);
8328         GET_REG32_1(TX_CPU_MODE);
8329         GET_REG32_1(TX_CPU_STATE);
8330         GET_REG32_1(TX_CPU_PGMCTR);
8331         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8332         GET_REG32_LOOP(FTQ_RESET, 0x120);
8333         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8334         GET_REG32_1(DMAC_MODE);
8335         GET_REG32_LOOP(GRC_MODE, 0x4c);
8336         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8337                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8338
8339 #undef __GET_REG32
8340 #undef GET_REG32_LOOP
8341 #undef GET_REG32_1
8342
8343         tg3_full_unlock(tp);
8344 }
8345
8346 static int tg3_get_eeprom_len(struct net_device *dev)
8347 {
8348         struct tg3 *tp = netdev_priv(dev);
8349
8350         return tp->nvram_size;
8351 }
8352
8353 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
8354 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
8355 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
8356
8357 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8358 {
8359         struct tg3 *tp = netdev_priv(dev);
8360         int ret;
8361         u8  *pd;
8362         u32 i, offset, len, b_offset, b_count;
8363         __le32 val;
8364
8365         if (tp->link_config.phy_is_low_power)
8366                 return -EAGAIN;
8367
8368         offset = eeprom->offset;
8369         len = eeprom->len;
8370         eeprom->len = 0;
8371
8372         eeprom->magic = TG3_EEPROM_MAGIC;
8373
8374         if (offset & 3) {
8375                 /* adjustments to start on required 4 byte boundary */
8376                 b_offset = offset & 3;
8377                 b_count = 4 - b_offset;
8378                 if (b_count > len) {
8379                         /* i.e. offset=1 len=2 */
8380                         b_count = len;
8381                 }
8382                 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
8383                 if (ret)
8384                         return ret;
8385                 memcpy(data, ((char*)&val) + b_offset, b_count);
8386                 len -= b_count;
8387                 offset += b_count;
8388                 eeprom->len += b_count;
8389         }
8390
8391         /* read bytes upto the last 4 byte boundary */
8392         pd = &data[eeprom->len];
8393         for (i = 0; i < (len - (len & 3)); i += 4) {
8394                 ret = tg3_nvram_read_le(tp, offset + i, &val);
8395                 if (ret) {
8396                         eeprom->len += i;
8397                         return ret;
8398                 }
8399                 memcpy(pd + i, &val, 4);
8400         }
8401         eeprom->len += i;
8402
8403         if (len & 3) {
8404                 /* read last bytes not ending on 4 byte boundary */
8405                 pd = &data[eeprom->len];
8406                 b_count = len & 3;
8407                 b_offset = offset + len - b_count;
8408                 ret = tg3_nvram_read_le(tp, b_offset, &val);
8409                 if (ret)
8410                         return ret;
8411                 memcpy(pd, &val, b_count);
8412                 eeprom->len += b_count;
8413         }
8414         return 0;
8415 }
8416
8417 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8418
8419 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8420 {
8421         struct tg3 *tp = netdev_priv(dev);
8422         int ret;
8423         u32 offset, len, b_offset, odd_len;
8424         u8 *buf;
8425         __le32 start, end;
8426
8427         if (tp->link_config.phy_is_low_power)
8428                 return -EAGAIN;
8429
8430         if (eeprom->magic != TG3_EEPROM_MAGIC)
8431                 return -EINVAL;
8432
8433         offset = eeprom->offset;
8434         len = eeprom->len;
8435
8436         if ((b_offset = (offset & 3))) {
8437                 /* adjustments to start on required 4 byte boundary */
8438                 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
8439                 if (ret)
8440                         return ret;
8441                 len += b_offset;
8442                 offset &= ~3;
8443                 if (len < 4)
8444                         len = 4;
8445         }
8446
8447         odd_len = 0;
8448         if (len & 3) {
8449                 /* adjustments to end on required 4 byte boundary */
8450                 odd_len = 1;
8451                 len = (len + 3) & ~3;
8452                 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
8453                 if (ret)
8454                         return ret;
8455         }
8456
8457         buf = data;
8458         if (b_offset || odd_len) {
8459                 buf = kmalloc(len, GFP_KERNEL);
8460                 if (!buf)
8461                         return -ENOMEM;
8462                 if (b_offset)
8463                         memcpy(buf, &start, 4);
8464                 if (odd_len)
8465                         memcpy(buf+len-4, &end, 4);
8466                 memcpy(buf + b_offset, data, eeprom->len);
8467         }
8468
8469         ret = tg3_nvram_write_block(tp, offset, len, buf);
8470
8471         if (buf != data)
8472                 kfree(buf);
8473
8474         return ret;
8475 }
8476
8477 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8478 {
8479         struct tg3 *tp = netdev_priv(dev);
8480
8481         cmd->supported = (SUPPORTED_Autoneg);
8482
8483         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8484                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8485                                    SUPPORTED_1000baseT_Full);
8486
8487         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8488                 cmd->supported |= (SUPPORTED_100baseT_Half |
8489                                   SUPPORTED_100baseT_Full |
8490                                   SUPPORTED_10baseT_Half |
8491                                   SUPPORTED_10baseT_Full |
8492                                   SUPPORTED_TP);
8493                 cmd->port = PORT_TP;
8494         } else {
8495                 cmd->supported |= SUPPORTED_FIBRE;
8496                 cmd->port = PORT_FIBRE;
8497         }
8498
8499         cmd->advertising = tp->link_config.advertising;
8500         if (netif_running(dev)) {
8501                 cmd->speed = tp->link_config.active_speed;
8502                 cmd->duplex = tp->link_config.active_duplex;
8503         }
8504         cmd->phy_address = PHY_ADDR;
8505         cmd->transceiver = 0;
8506         cmd->autoneg = tp->link_config.autoneg;
8507         cmd->maxtxpkt = 0;
8508         cmd->maxrxpkt = 0;
8509         return 0;
8510 }
8511
8512 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8513 {
8514         struct tg3 *tp = netdev_priv(dev);
8515
8516         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8517                 /* These are the only valid advertisement bits allowed.  */
8518                 if (cmd->autoneg == AUTONEG_ENABLE &&
8519                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8520                                           ADVERTISED_1000baseT_Full |
8521                                           ADVERTISED_Autoneg |
8522                                           ADVERTISED_FIBRE)))
8523                         return -EINVAL;
8524                 /* Fiber can only do SPEED_1000.  */
8525                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8526                          (cmd->speed != SPEED_1000))
8527                         return -EINVAL;
8528         /* Copper cannot force SPEED_1000.  */
8529         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8530                    (cmd->speed == SPEED_1000))
8531                 return -EINVAL;
8532         else if ((cmd->speed == SPEED_1000) &&
8533                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8534                 return -EINVAL;
8535
8536         tg3_full_lock(tp, 0);
8537
8538         tp->link_config.autoneg = cmd->autoneg;
8539         if (cmd->autoneg == AUTONEG_ENABLE) {
8540                 tp->link_config.advertising = (cmd->advertising |
8541                                               ADVERTISED_Autoneg);
8542                 tp->link_config.speed = SPEED_INVALID;
8543                 tp->link_config.duplex = DUPLEX_INVALID;
8544         } else {
8545                 tp->link_config.advertising = 0;
8546                 tp->link_config.speed = cmd->speed;
8547                 tp->link_config.duplex = cmd->duplex;
8548         }
8549
8550         tp->link_config.orig_speed = tp->link_config.speed;
8551         tp->link_config.orig_duplex = tp->link_config.duplex;
8552         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8553
8554         if (netif_running(dev))
8555                 tg3_setup_phy(tp, 1);
8556
8557         tg3_full_unlock(tp);
8558
8559         return 0;
8560 }
8561
8562 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8563 {
8564         struct tg3 *tp = netdev_priv(dev);
8565
8566         strcpy(info->driver, DRV_MODULE_NAME);
8567         strcpy(info->version, DRV_MODULE_VERSION);
8568         strcpy(info->fw_version, tp->fw_ver);
8569         strcpy(info->bus_info, pci_name(tp->pdev));
8570 }
8571
8572 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8573 {
8574         struct tg3 *tp = netdev_priv(dev);
8575
8576         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8577                 wol->supported = WAKE_MAGIC;
8578         else
8579                 wol->supported = 0;
8580         wol->wolopts = 0;
8581         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8582                 wol->wolopts = WAKE_MAGIC;
8583         memset(&wol->sopass, 0, sizeof(wol->sopass));
8584 }
8585
8586 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8587 {
8588         struct tg3 *tp = netdev_priv(dev);
8589
8590         if (wol->wolopts & ~WAKE_MAGIC)
8591                 return -EINVAL;
8592         if ((wol->wolopts & WAKE_MAGIC) &&
8593             !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8594                 return -EINVAL;
8595
8596         spin_lock_bh(&tp->lock);
8597         if (wol->wolopts & WAKE_MAGIC)
8598                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8599         else
8600                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8601         spin_unlock_bh(&tp->lock);
8602
8603         return 0;
8604 }
8605
8606 static u32 tg3_get_msglevel(struct net_device *dev)
8607 {
8608         struct tg3 *tp = netdev_priv(dev);
8609         return tp->msg_enable;
8610 }
8611
8612 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8613 {
8614         struct tg3 *tp = netdev_priv(dev);
8615         tp->msg_enable = value;
8616 }
8617
8618 static int tg3_set_tso(struct net_device *dev, u32 value)
8619 {
8620         struct tg3 *tp = netdev_priv(dev);
8621
8622         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8623                 if (value)
8624                         return -EINVAL;
8625                 return 0;
8626         }
8627         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8628             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8629                 if (value) {
8630                         dev->features |= NETIF_F_TSO6;
8631                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8632                                 dev->features |= NETIF_F_TSO_ECN;
8633                 } else
8634                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
8635         }
8636         return ethtool_op_set_tso(dev, value);
8637 }
8638
8639 static int tg3_nway_reset(struct net_device *dev)
8640 {
8641         struct tg3 *tp = netdev_priv(dev);
8642         u32 bmcr;
8643         int r;
8644
8645         if (!netif_running(dev))
8646                 return -EAGAIN;
8647
8648         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8649                 return -EINVAL;
8650
8651         spin_lock_bh(&tp->lock);
8652         r = -EINVAL;
8653         tg3_readphy(tp, MII_BMCR, &bmcr);
8654         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8655             ((bmcr & BMCR_ANENABLE) ||
8656              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8657                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8658                                            BMCR_ANENABLE);
8659                 r = 0;
8660         }
8661         spin_unlock_bh(&tp->lock);
8662
8663         return r;
8664 }
8665
8666 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8667 {
8668         struct tg3 *tp = netdev_priv(dev);
8669
8670         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8671         ering->rx_mini_max_pending = 0;
8672         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8673                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8674         else
8675                 ering->rx_jumbo_max_pending = 0;
8676
8677         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8678
8679         ering->rx_pending = tp->rx_pending;
8680         ering->rx_mini_pending = 0;
8681         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8682                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8683         else
8684                 ering->rx_jumbo_pending = 0;
8685
8686         ering->tx_pending = tp->tx_pending;
8687 }
8688
8689 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8690 {
8691         struct tg3 *tp = netdev_priv(dev);
8692         int irq_sync = 0, err = 0;
8693
8694         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8695             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8696             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8697             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8698             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8699              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8700                 return -EINVAL;
8701
8702         if (netif_running(dev)) {
8703                 tg3_netif_stop(tp);
8704                 irq_sync = 1;
8705         }
8706
8707         tg3_full_lock(tp, irq_sync);
8708
8709         tp->rx_pending = ering->rx_pending;
8710
8711         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8712             tp->rx_pending > 63)
8713                 tp->rx_pending = 63;
8714         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8715         tp->tx_pending = ering->tx_pending;
8716
8717         if (netif_running(dev)) {
8718                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8719                 err = tg3_restart_hw(tp, 1);
8720                 if (!err)
8721                         tg3_netif_start(tp);
8722         }
8723
8724         tg3_full_unlock(tp);
8725
8726         return err;
8727 }
8728
8729 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8730 {
8731         struct tg3 *tp = netdev_priv(dev);
8732
8733         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8734
8735         if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX)
8736                 epause->rx_pause = 1;
8737         else
8738                 epause->rx_pause = 0;
8739
8740         if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX)
8741                 epause->tx_pause = 1;
8742         else
8743                 epause->tx_pause = 0;
8744 }
8745
8746 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8747 {
8748         struct tg3 *tp = netdev_priv(dev);
8749         int irq_sync = 0, err = 0;
8750
8751         if (netif_running(dev)) {
8752                 tg3_netif_stop(tp);
8753                 irq_sync = 1;
8754         }
8755
8756         tg3_full_lock(tp, irq_sync);
8757
8758         if (epause->autoneg)
8759                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8760         else
8761                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8762         if (epause->rx_pause)
8763                 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
8764         else
8765                 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
8766         if (epause->tx_pause)
8767                 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
8768         else
8769                 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
8770
8771         if (netif_running(dev)) {
8772                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8773                 err = tg3_restart_hw(tp, 1);
8774                 if (!err)
8775                         tg3_netif_start(tp);
8776         }
8777
8778         tg3_full_unlock(tp);
8779
8780         return err;
8781 }
8782
8783 static u32 tg3_get_rx_csum(struct net_device *dev)
8784 {
8785         struct tg3 *tp = netdev_priv(dev);
8786         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8787 }
8788
8789 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8790 {
8791         struct tg3 *tp = netdev_priv(dev);
8792
8793         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8794                 if (data != 0)
8795                         return -EINVAL;
8796                 return 0;
8797         }
8798
8799         spin_lock_bh(&tp->lock);
8800         if (data)
8801                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8802         else
8803                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8804         spin_unlock_bh(&tp->lock);
8805
8806         return 0;
8807 }
8808
8809 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8810 {
8811         struct tg3 *tp = netdev_priv(dev);
8812
8813         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8814                 if (data != 0)
8815                         return -EINVAL;
8816                 return 0;
8817         }
8818
8819         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8820             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
8821             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8822             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8823                 ethtool_op_set_tx_ipv6_csum(dev, data);
8824         else
8825                 ethtool_op_set_tx_csum(dev, data);
8826
8827         return 0;
8828 }
8829
8830 static int tg3_get_sset_count (struct net_device *dev, int sset)
8831 {
8832         switch (sset) {
8833         case ETH_SS_TEST:
8834                 return TG3_NUM_TEST;
8835         case ETH_SS_STATS:
8836                 return TG3_NUM_STATS;
8837         default:
8838                 return -EOPNOTSUPP;
8839         }
8840 }
8841
8842 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8843 {
8844         switch (stringset) {
8845         case ETH_SS_STATS:
8846                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8847                 break;
8848         case ETH_SS_TEST:
8849                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8850                 break;
8851         default:
8852                 WARN_ON(1);     /* we need a WARN() */
8853                 break;
8854         }
8855 }
8856
8857 static int tg3_phys_id(struct net_device *dev, u32 data)
8858 {
8859         struct tg3 *tp = netdev_priv(dev);
8860         int i;
8861
8862         if (!netif_running(tp->dev))
8863                 return -EAGAIN;
8864
8865         if (data == 0)
8866                 data = UINT_MAX / 2;
8867
8868         for (i = 0; i < (data * 2); i++) {
8869                 if ((i % 2) == 0)
8870                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8871                                            LED_CTRL_1000MBPS_ON |
8872                                            LED_CTRL_100MBPS_ON |
8873                                            LED_CTRL_10MBPS_ON |
8874                                            LED_CTRL_TRAFFIC_OVERRIDE |
8875                                            LED_CTRL_TRAFFIC_BLINK |
8876                                            LED_CTRL_TRAFFIC_LED);
8877
8878                 else
8879                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8880                                            LED_CTRL_TRAFFIC_OVERRIDE);
8881
8882                 if (msleep_interruptible(500))
8883                         break;
8884         }
8885         tw32(MAC_LED_CTRL, tp->led_ctrl);
8886         return 0;
8887 }
8888
8889 static void tg3_get_ethtool_stats (struct net_device *dev,
8890                                    struct ethtool_stats *estats, u64 *tmp_stats)
8891 {
8892         struct tg3 *tp = netdev_priv(dev);
8893         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8894 }
8895
8896 #define NVRAM_TEST_SIZE 0x100
8897 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
8898 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
8899 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
8900 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8901 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8902
8903 static int tg3_test_nvram(struct tg3 *tp)
8904 {
8905         u32 csum, magic;
8906         __le32 *buf;
8907         int i, j, k, err = 0, size;
8908
8909         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8910                 return -EIO;
8911
8912         if (magic == TG3_EEPROM_MAGIC)
8913                 size = NVRAM_TEST_SIZE;
8914         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8915                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
8916                     TG3_EEPROM_SB_FORMAT_1) {
8917                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
8918                         case TG3_EEPROM_SB_REVISION_0:
8919                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
8920                                 break;
8921                         case TG3_EEPROM_SB_REVISION_2:
8922                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
8923                                 break;
8924                         case TG3_EEPROM_SB_REVISION_3:
8925                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
8926                                 break;
8927                         default:
8928                                 return 0;
8929                         }
8930                 } else
8931                         return 0;
8932         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8933                 size = NVRAM_SELFBOOT_HW_SIZE;
8934         else
8935                 return -EIO;
8936
8937         buf = kmalloc(size, GFP_KERNEL);
8938         if (buf == NULL)
8939                 return -ENOMEM;
8940
8941         err = -EIO;
8942         for (i = 0, j = 0; i < size; i += 4, j++) {
8943                 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
8944                         break;
8945         }
8946         if (i < size)
8947                 goto out;
8948
8949         /* Selfboot format */
8950         magic = swab32(le32_to_cpu(buf[0]));
8951         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
8952             TG3_EEPROM_MAGIC_FW) {
8953                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8954
8955                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
8956                     TG3_EEPROM_SB_REVISION_2) {
8957                         /* For rev 2, the csum doesn't include the MBA. */
8958                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
8959                                 csum8 += buf8[i];
8960                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
8961                                 csum8 += buf8[i];
8962                 } else {
8963                         for (i = 0; i < size; i++)
8964                                 csum8 += buf8[i];
8965                 }
8966
8967                 if (csum8 == 0) {
8968                         err = 0;
8969                         goto out;
8970                 }
8971
8972                 err = -EIO;
8973                 goto out;
8974         }
8975
8976         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
8977             TG3_EEPROM_MAGIC_HW) {
8978                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8979                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8980                 u8 *buf8 = (u8 *) buf;
8981
8982                 /* Separate the parity bits and the data bytes.  */
8983                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8984                         if ((i == 0) || (i == 8)) {
8985                                 int l;
8986                                 u8 msk;
8987
8988                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8989                                         parity[k++] = buf8[i] & msk;
8990                                 i++;
8991                         }
8992                         else if (i == 16) {
8993                                 int l;
8994                                 u8 msk;
8995
8996                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8997                                         parity[k++] = buf8[i] & msk;
8998                                 i++;
8999
9000                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9001                                         parity[k++] = buf8[i] & msk;
9002                                 i++;
9003                         }
9004                         data[j++] = buf8[i];
9005                 }
9006
9007                 err = -EIO;
9008                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9009                         u8 hw8 = hweight8(data[i]);
9010
9011                         if ((hw8 & 0x1) && parity[i])
9012                                 goto out;
9013                         else if (!(hw8 & 0x1) && !parity[i])
9014                                 goto out;
9015                 }
9016                 err = 0;
9017                 goto out;
9018         }
9019
9020         /* Bootstrap checksum at offset 0x10 */
9021         csum = calc_crc((unsigned char *) buf, 0x10);
9022         if(csum != le32_to_cpu(buf[0x10/4]))
9023                 goto out;
9024
9025         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9026         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9027         if (csum != le32_to_cpu(buf[0xfc/4]))
9028                  goto out;
9029
9030         err = 0;
9031
9032 out:
9033         kfree(buf);
9034         return err;
9035 }
9036
9037 #define TG3_SERDES_TIMEOUT_SEC  2
9038 #define TG3_COPPER_TIMEOUT_SEC  6
9039
9040 static int tg3_test_link(struct tg3 *tp)
9041 {
9042         int i, max;
9043
9044         if (!netif_running(tp->dev))
9045                 return -ENODEV;
9046
9047         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9048                 max = TG3_SERDES_TIMEOUT_SEC;
9049         else
9050                 max = TG3_COPPER_TIMEOUT_SEC;
9051
9052         for (i = 0; i < max; i++) {
9053                 if (netif_carrier_ok(tp->dev))
9054                         return 0;
9055
9056                 if (msleep_interruptible(1000))
9057                         break;
9058         }
9059
9060         return -EIO;
9061 }
9062
9063 /* Only test the commonly used registers */
9064 static int tg3_test_registers(struct tg3 *tp)
9065 {
9066         int i, is_5705, is_5750;
9067         u32 offset, read_mask, write_mask, val, save_val, read_val;
9068         static struct {
9069                 u16 offset;
9070                 u16 flags;
9071 #define TG3_FL_5705     0x1
9072 #define TG3_FL_NOT_5705 0x2
9073 #define TG3_FL_NOT_5788 0x4
9074 #define TG3_FL_NOT_5750 0x8
9075                 u32 read_mask;
9076                 u32 write_mask;
9077         } reg_tbl[] = {
9078                 /* MAC Control Registers */
9079                 { MAC_MODE, TG3_FL_NOT_5705,
9080                         0x00000000, 0x00ef6f8c },
9081                 { MAC_MODE, TG3_FL_5705,
9082                         0x00000000, 0x01ef6b8c },
9083                 { MAC_STATUS, TG3_FL_NOT_5705,
9084                         0x03800107, 0x00000000 },
9085                 { MAC_STATUS, TG3_FL_5705,
9086                         0x03800100, 0x00000000 },
9087                 { MAC_ADDR_0_HIGH, 0x0000,
9088                         0x00000000, 0x0000ffff },
9089                 { MAC_ADDR_0_LOW, 0x0000,
9090                         0x00000000, 0xffffffff },
9091                 { MAC_RX_MTU_SIZE, 0x0000,
9092                         0x00000000, 0x0000ffff },
9093                 { MAC_TX_MODE, 0x0000,
9094                         0x00000000, 0x00000070 },
9095                 { MAC_TX_LENGTHS, 0x0000,
9096                         0x00000000, 0x00003fff },
9097                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9098                         0x00000000, 0x000007fc },
9099                 { MAC_RX_MODE, TG3_FL_5705,
9100                         0x00000000, 0x000007dc },
9101                 { MAC_HASH_REG_0, 0x0000,
9102                         0x00000000, 0xffffffff },
9103                 { MAC_HASH_REG_1, 0x0000,
9104                         0x00000000, 0xffffffff },
9105                 { MAC_HASH_REG_2, 0x0000,
9106                         0x00000000, 0xffffffff },
9107                 { MAC_HASH_REG_3, 0x0000,
9108                         0x00000000, 0xffffffff },
9109
9110                 /* Receive Data and Receive BD Initiator Control Registers. */
9111                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9112                         0x00000000, 0xffffffff },
9113                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9114                         0x00000000, 0xffffffff },
9115                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9116                         0x00000000, 0x00000003 },
9117                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9118                         0x00000000, 0xffffffff },
9119                 { RCVDBDI_STD_BD+0, 0x0000,
9120                         0x00000000, 0xffffffff },
9121                 { RCVDBDI_STD_BD+4, 0x0000,
9122                         0x00000000, 0xffffffff },
9123                 { RCVDBDI_STD_BD+8, 0x0000,
9124                         0x00000000, 0xffff0002 },
9125                 { RCVDBDI_STD_BD+0xc, 0x0000,
9126                         0x00000000, 0xffffffff },
9127
9128                 /* Receive BD Initiator Control Registers. */
9129                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9130                         0x00000000, 0xffffffff },
9131                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9132                         0x00000000, 0x000003ff },
9133                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9134                         0x00000000, 0xffffffff },
9135
9136                 /* Host Coalescing Control Registers. */
9137                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9138                         0x00000000, 0x00000004 },
9139                 { HOSTCC_MODE, TG3_FL_5705,
9140                         0x00000000, 0x000000f6 },
9141                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9142                         0x00000000, 0xffffffff },
9143                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9144                         0x00000000, 0x000003ff },
9145                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9146                         0x00000000, 0xffffffff },
9147                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9148                         0x00000000, 0x000003ff },
9149                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9150                         0x00000000, 0xffffffff },
9151                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9152                         0x00000000, 0x000000ff },
9153                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9154                         0x00000000, 0xffffffff },
9155                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9156                         0x00000000, 0x000000ff },
9157                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9158                         0x00000000, 0xffffffff },
9159                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9160                         0x00000000, 0xffffffff },
9161                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9162                         0x00000000, 0xffffffff },
9163                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9164                         0x00000000, 0x000000ff },
9165                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9166                         0x00000000, 0xffffffff },
9167                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9168                         0x00000000, 0x000000ff },
9169                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9170                         0x00000000, 0xffffffff },
9171                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9172                         0x00000000, 0xffffffff },
9173                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9174                         0x00000000, 0xffffffff },
9175                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9176                         0x00000000, 0xffffffff },
9177                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9178                         0x00000000, 0xffffffff },
9179                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9180                         0xffffffff, 0x00000000 },
9181                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9182                         0xffffffff, 0x00000000 },
9183
9184                 /* Buffer Manager Control Registers. */
9185                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9186                         0x00000000, 0x007fff80 },
9187                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9188                         0x00000000, 0x007fffff },
9189                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9190                         0x00000000, 0x0000003f },
9191                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9192                         0x00000000, 0x000001ff },
9193                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9194                         0x00000000, 0x000001ff },
9195                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9196                         0xffffffff, 0x00000000 },
9197                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9198                         0xffffffff, 0x00000000 },
9199
9200                 /* Mailbox Registers */
9201                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9202                         0x00000000, 0x000001ff },
9203                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9204                         0x00000000, 0x000001ff },
9205                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9206                         0x00000000, 0x000007ff },
9207                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9208                         0x00000000, 0x000001ff },
9209
9210                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9211         };
9212
9213         is_5705 = is_5750 = 0;
9214         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9215                 is_5705 = 1;
9216                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9217                         is_5750 = 1;
9218         }
9219
9220         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9221                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9222                         continue;
9223
9224                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9225                         continue;
9226
9227                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9228                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9229                         continue;
9230
9231                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9232                         continue;
9233
9234                 offset = (u32) reg_tbl[i].offset;
9235                 read_mask = reg_tbl[i].read_mask;
9236                 write_mask = reg_tbl[i].write_mask;
9237
9238                 /* Save the original register content */
9239                 save_val = tr32(offset);
9240
9241                 /* Determine the read-only value. */
9242                 read_val = save_val & read_mask;
9243
9244                 /* Write zero to the register, then make sure the read-only bits
9245                  * are not changed and the read/write bits are all zeros.
9246                  */
9247                 tw32(offset, 0);
9248
9249                 val = tr32(offset);
9250
9251                 /* Test the read-only and read/write bits. */
9252                 if (((val & read_mask) != read_val) || (val & write_mask))
9253                         goto out;
9254
9255                 /* Write ones to all the bits defined by RdMask and WrMask, then
9256                  * make sure the read-only bits are not changed and the
9257                  * read/write bits are all ones.
9258                  */
9259                 tw32(offset, read_mask | write_mask);
9260
9261                 val = tr32(offset);
9262
9263                 /* Test the read-only bits. */
9264                 if ((val & read_mask) != read_val)
9265                         goto out;
9266
9267                 /* Test the read/write bits. */
9268                 if ((val & write_mask) != write_mask)
9269                         goto out;
9270
9271                 tw32(offset, save_val);
9272         }
9273
9274         return 0;
9275
9276 out:
9277         if (netif_msg_hw(tp))
9278                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9279                        offset);
9280         tw32(offset, save_val);
9281         return -EIO;
9282 }
9283
9284 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9285 {
9286         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9287         int i;
9288         u32 j;
9289
9290         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9291                 for (j = 0; j < len; j += 4) {
9292                         u32 val;
9293
9294                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9295                         tg3_read_mem(tp, offset + j, &val);
9296                         if (val != test_pattern[i])
9297                                 return -EIO;
9298                 }
9299         }
9300         return 0;
9301 }
9302
9303 static int tg3_test_memory(struct tg3 *tp)
9304 {
9305         static struct mem_entry {
9306                 u32 offset;
9307                 u32 len;
9308         } mem_tbl_570x[] = {
9309                 { 0x00000000, 0x00b50},
9310                 { 0x00002000, 0x1c000},
9311                 { 0xffffffff, 0x00000}
9312         }, mem_tbl_5705[] = {
9313                 { 0x00000100, 0x0000c},
9314                 { 0x00000200, 0x00008},
9315                 { 0x00004000, 0x00800},
9316                 { 0x00006000, 0x01000},
9317                 { 0x00008000, 0x02000},
9318                 { 0x00010000, 0x0e000},
9319                 { 0xffffffff, 0x00000}
9320         }, mem_tbl_5755[] = {
9321                 { 0x00000200, 0x00008},
9322                 { 0x00004000, 0x00800},
9323                 { 0x00006000, 0x00800},
9324                 { 0x00008000, 0x02000},
9325                 { 0x00010000, 0x0c000},
9326                 { 0xffffffff, 0x00000}
9327         }, mem_tbl_5906[] = {
9328                 { 0x00000200, 0x00008},
9329                 { 0x00004000, 0x00400},
9330                 { 0x00006000, 0x00400},
9331                 { 0x00008000, 0x01000},
9332                 { 0x00010000, 0x01000},
9333                 { 0xffffffff, 0x00000}
9334         };
9335         struct mem_entry *mem_tbl;
9336         int err = 0;
9337         int i;
9338
9339         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9340                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9341                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9342                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9343                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9344                         mem_tbl = mem_tbl_5755;
9345                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9346                         mem_tbl = mem_tbl_5906;
9347                 else
9348                         mem_tbl = mem_tbl_5705;
9349         } else
9350                 mem_tbl = mem_tbl_570x;
9351
9352         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9353                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9354                     mem_tbl[i].len)) != 0)
9355                         break;
9356         }
9357
9358         return err;
9359 }
9360
9361 #define TG3_MAC_LOOPBACK        0
9362 #define TG3_PHY_LOOPBACK        1
9363
9364 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9365 {
9366         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9367         u32 desc_idx;
9368         struct sk_buff *skb, *rx_skb;
9369         u8 *tx_data;
9370         dma_addr_t map;
9371         int num_pkts, tx_len, rx_len, i, err;
9372         struct tg3_rx_buffer_desc *desc;
9373
9374         if (loopback_mode == TG3_MAC_LOOPBACK) {
9375                 /* HW errata - mac loopback fails in some cases on 5780.
9376                  * Normal traffic and PHY loopback are not affected by
9377                  * errata.
9378                  */
9379                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9380                         return 0;
9381
9382                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9383                            MAC_MODE_PORT_INT_LPBACK;
9384                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9385                         mac_mode |= MAC_MODE_LINK_POLARITY;
9386                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9387                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9388                 else
9389                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9390                 tw32(MAC_MODE, mac_mode);
9391         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9392                 u32 val;
9393
9394                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9395                         u32 phytest;
9396
9397                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9398                                 u32 phy;
9399
9400                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9401                                              phytest | MII_TG3_EPHY_SHADOW_EN);
9402                                 if (!tg3_readphy(tp, 0x1b, &phy))
9403                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
9404                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9405                         }
9406                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9407                 } else
9408                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9409
9410                 tg3_phy_toggle_automdix(tp, 0);
9411
9412                 tg3_writephy(tp, MII_BMCR, val);
9413                 udelay(40);
9414
9415                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9416                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9417                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9418                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9419                 } else
9420                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9421
9422                 /* reset to prevent losing 1st rx packet intermittently */
9423                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9424                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9425                         udelay(10);
9426                         tw32_f(MAC_RX_MODE, tp->rx_mode);
9427                 }
9428                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9429                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9430                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9431                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9432                                 mac_mode |= MAC_MODE_LINK_POLARITY;
9433                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
9434                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9435                 }
9436                 tw32(MAC_MODE, mac_mode);
9437         }
9438         else
9439                 return -EINVAL;
9440
9441         err = -EIO;
9442
9443         tx_len = 1514;
9444         skb = netdev_alloc_skb(tp->dev, tx_len);
9445         if (!skb)
9446                 return -ENOMEM;
9447
9448         tx_data = skb_put(skb, tx_len);
9449         memcpy(tx_data, tp->dev->dev_addr, 6);
9450         memset(tx_data + 6, 0x0, 8);
9451
9452         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9453
9454         for (i = 14; i < tx_len; i++)
9455                 tx_data[i] = (u8) (i & 0xff);
9456
9457         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9458
9459         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9460              HOSTCC_MODE_NOW);
9461
9462         udelay(10);
9463
9464         rx_start_idx = tp->hw_status->idx[0].rx_producer;
9465
9466         num_pkts = 0;
9467
9468         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9469
9470         tp->tx_prod++;
9471         num_pkts++;
9472
9473         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9474                      tp->tx_prod);
9475         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9476
9477         udelay(10);
9478
9479         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
9480         for (i = 0; i < 25; i++) {
9481                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9482                        HOSTCC_MODE_NOW);
9483
9484                 udelay(10);
9485
9486                 tx_idx = tp->hw_status->idx[0].tx_consumer;
9487                 rx_idx = tp->hw_status->idx[0].rx_producer;
9488                 if ((tx_idx == tp->tx_prod) &&
9489                     (rx_idx == (rx_start_idx + num_pkts)))
9490                         break;
9491         }
9492
9493         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9494         dev_kfree_skb(skb);
9495
9496         if (tx_idx != tp->tx_prod)
9497                 goto out;
9498
9499         if (rx_idx != rx_start_idx + num_pkts)
9500                 goto out;
9501
9502         desc = &tp->rx_rcb[rx_start_idx];
9503         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9504         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9505         if (opaque_key != RXD_OPAQUE_RING_STD)
9506                 goto out;
9507
9508         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9509             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9510                 goto out;
9511
9512         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9513         if (rx_len != tx_len)
9514                 goto out;
9515
9516         rx_skb = tp->rx_std_buffers[desc_idx].skb;
9517
9518         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9519         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9520
9521         for (i = 14; i < tx_len; i++) {
9522                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9523                         goto out;
9524         }
9525         err = 0;
9526
9527         /* tg3_free_rings will unmap and free the rx_skb */
9528 out:
9529         return err;
9530 }
9531
9532 #define TG3_MAC_LOOPBACK_FAILED         1
9533 #define TG3_PHY_LOOPBACK_FAILED         2
9534 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
9535                                          TG3_PHY_LOOPBACK_FAILED)
9536
9537 static int tg3_test_loopback(struct tg3 *tp)
9538 {
9539         int err = 0;
9540         u32 cpmuctrl = 0;
9541
9542         if (!netif_running(tp->dev))
9543                 return TG3_LOOPBACK_FAILED;
9544
9545         err = tg3_reset_hw(tp, 1);
9546         if (err)
9547                 return TG3_LOOPBACK_FAILED;
9548
9549         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9550             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
9551                 int i;
9552                 u32 status;
9553
9554                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9555
9556                 /* Wait for up to 40 microseconds to acquire lock. */
9557                 for (i = 0; i < 4; i++) {
9558                         status = tr32(TG3_CPMU_MUTEX_GNT);
9559                         if (status == CPMU_MUTEX_GNT_DRIVER)
9560                                 break;
9561                         udelay(10);
9562                 }
9563
9564                 if (status != CPMU_MUTEX_GNT_DRIVER)
9565                         return TG3_LOOPBACK_FAILED;
9566
9567                 /* Turn off link-based power management. */
9568                 cpmuctrl = tr32(TG3_CPMU_CTRL);
9569                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9570                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX)
9571                         tw32(TG3_CPMU_CTRL,
9572                              cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9573                                           CPMU_CTRL_LINK_AWARE_MODE));
9574                 else
9575                         tw32(TG3_CPMU_CTRL,
9576                              cpmuctrl & ~CPMU_CTRL_LINK_AWARE_MODE);
9577         }
9578
9579         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9580                 err |= TG3_MAC_LOOPBACK_FAILED;
9581
9582         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9583             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
9584                 tw32(TG3_CPMU_CTRL, cpmuctrl);
9585
9586                 /* Release the mutex */
9587                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9588         }
9589
9590         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9591                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9592                         err |= TG3_PHY_LOOPBACK_FAILED;
9593         }
9594
9595         return err;
9596 }
9597
9598 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9599                           u64 *data)
9600 {
9601         struct tg3 *tp = netdev_priv(dev);
9602
9603         if (tp->link_config.phy_is_low_power)
9604                 tg3_set_power_state(tp, PCI_D0);
9605
9606         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9607
9608         if (tg3_test_nvram(tp) != 0) {
9609                 etest->flags |= ETH_TEST_FL_FAILED;
9610                 data[0] = 1;
9611         }
9612         if (tg3_test_link(tp) != 0) {
9613                 etest->flags |= ETH_TEST_FL_FAILED;
9614                 data[1] = 1;
9615         }
9616         if (etest->flags & ETH_TEST_FL_OFFLINE) {
9617                 int err, irq_sync = 0;
9618
9619                 if (netif_running(dev)) {
9620                         tg3_netif_stop(tp);
9621                         irq_sync = 1;
9622                 }
9623
9624                 tg3_full_lock(tp, irq_sync);
9625
9626                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9627                 err = tg3_nvram_lock(tp);
9628                 tg3_halt_cpu(tp, RX_CPU_BASE);
9629                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9630                         tg3_halt_cpu(tp, TX_CPU_BASE);
9631                 if (!err)
9632                         tg3_nvram_unlock(tp);
9633
9634                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9635                         tg3_phy_reset(tp);
9636
9637                 if (tg3_test_registers(tp) != 0) {
9638                         etest->flags |= ETH_TEST_FL_FAILED;
9639                         data[2] = 1;
9640                 }
9641                 if (tg3_test_memory(tp) != 0) {
9642                         etest->flags |= ETH_TEST_FL_FAILED;
9643                         data[3] = 1;
9644                 }
9645                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9646                         etest->flags |= ETH_TEST_FL_FAILED;
9647
9648                 tg3_full_unlock(tp);
9649
9650                 if (tg3_test_interrupt(tp) != 0) {
9651                         etest->flags |= ETH_TEST_FL_FAILED;
9652                         data[5] = 1;
9653                 }
9654
9655                 tg3_full_lock(tp, 0);
9656
9657                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9658                 if (netif_running(dev)) {
9659                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9660                         if (!tg3_restart_hw(tp, 1))
9661                                 tg3_netif_start(tp);
9662                 }
9663
9664                 tg3_full_unlock(tp);
9665         }
9666         if (tp->link_config.phy_is_low_power)
9667                 tg3_set_power_state(tp, PCI_D3hot);
9668
9669 }
9670
9671 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9672 {
9673         struct mii_ioctl_data *data = if_mii(ifr);
9674         struct tg3 *tp = netdev_priv(dev);
9675         int err;
9676
9677         switch(cmd) {
9678         case SIOCGMIIPHY:
9679                 data->phy_id = PHY_ADDR;
9680
9681                 /* fallthru */
9682         case SIOCGMIIREG: {
9683                 u32 mii_regval;
9684
9685                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9686                         break;                  /* We have no PHY */
9687
9688                 if (tp->link_config.phy_is_low_power)
9689                         return -EAGAIN;
9690
9691                 spin_lock_bh(&tp->lock);
9692                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9693                 spin_unlock_bh(&tp->lock);
9694
9695                 data->val_out = mii_regval;
9696
9697                 return err;
9698         }
9699
9700         case SIOCSMIIREG:
9701                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9702                         break;                  /* We have no PHY */
9703
9704                 if (!capable(CAP_NET_ADMIN))
9705                         return -EPERM;
9706
9707                 if (tp->link_config.phy_is_low_power)
9708                         return -EAGAIN;
9709
9710                 spin_lock_bh(&tp->lock);
9711                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9712                 spin_unlock_bh(&tp->lock);
9713
9714                 return err;
9715
9716         default:
9717                 /* do nothing */
9718                 break;
9719         }
9720         return -EOPNOTSUPP;
9721 }
9722
9723 #if TG3_VLAN_TAG_USED
9724 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9725 {
9726         struct tg3 *tp = netdev_priv(dev);
9727
9728         if (netif_running(dev))
9729                 tg3_netif_stop(tp);
9730
9731         tg3_full_lock(tp, 0);
9732
9733         tp->vlgrp = grp;
9734
9735         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9736         __tg3_set_rx_mode(dev);
9737
9738         if (netif_running(dev))
9739                 tg3_netif_start(tp);
9740
9741         tg3_full_unlock(tp);
9742 }
9743 #endif
9744
9745 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9746 {
9747         struct tg3 *tp = netdev_priv(dev);
9748
9749         memcpy(ec, &tp->coal, sizeof(*ec));
9750         return 0;
9751 }
9752
9753 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9754 {
9755         struct tg3 *tp = netdev_priv(dev);
9756         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9757         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9758
9759         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9760                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9761                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9762                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9763                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9764         }
9765
9766         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9767             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9768             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9769             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9770             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9771             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9772             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9773             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9774             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9775             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9776                 return -EINVAL;
9777
9778         /* No rx interrupts will be generated if both are zero */
9779         if ((ec->rx_coalesce_usecs == 0) &&
9780             (ec->rx_max_coalesced_frames == 0))
9781                 return -EINVAL;
9782
9783         /* No tx interrupts will be generated if both are zero */
9784         if ((ec->tx_coalesce_usecs == 0) &&
9785             (ec->tx_max_coalesced_frames == 0))
9786                 return -EINVAL;
9787
9788         /* Only copy relevant parameters, ignore all others. */
9789         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9790         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9791         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9792         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9793         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9794         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9795         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9796         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9797         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9798
9799         if (netif_running(dev)) {
9800                 tg3_full_lock(tp, 0);
9801                 __tg3_set_coalesce(tp, &tp->coal);
9802                 tg3_full_unlock(tp);
9803         }
9804         return 0;
9805 }
9806
9807 static const struct ethtool_ops tg3_ethtool_ops = {
9808         .get_settings           = tg3_get_settings,
9809         .set_settings           = tg3_set_settings,
9810         .get_drvinfo            = tg3_get_drvinfo,
9811         .get_regs_len           = tg3_get_regs_len,
9812         .get_regs               = tg3_get_regs,
9813         .get_wol                = tg3_get_wol,
9814         .set_wol                = tg3_set_wol,
9815         .get_msglevel           = tg3_get_msglevel,
9816         .set_msglevel           = tg3_set_msglevel,
9817         .nway_reset             = tg3_nway_reset,
9818         .get_link               = ethtool_op_get_link,
9819         .get_eeprom_len         = tg3_get_eeprom_len,
9820         .get_eeprom             = tg3_get_eeprom,
9821         .set_eeprom             = tg3_set_eeprom,
9822         .get_ringparam          = tg3_get_ringparam,
9823         .set_ringparam          = tg3_set_ringparam,
9824         .get_pauseparam         = tg3_get_pauseparam,
9825         .set_pauseparam         = tg3_set_pauseparam,
9826         .get_rx_csum            = tg3_get_rx_csum,
9827         .set_rx_csum            = tg3_set_rx_csum,
9828         .set_tx_csum            = tg3_set_tx_csum,
9829         .set_sg                 = ethtool_op_set_sg,
9830         .set_tso                = tg3_set_tso,
9831         .self_test              = tg3_self_test,
9832         .get_strings            = tg3_get_strings,
9833         .phys_id                = tg3_phys_id,
9834         .get_ethtool_stats      = tg3_get_ethtool_stats,
9835         .get_coalesce           = tg3_get_coalesce,
9836         .set_coalesce           = tg3_set_coalesce,
9837         .get_sset_count         = tg3_get_sset_count,
9838 };
9839
9840 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9841 {
9842         u32 cursize, val, magic;
9843
9844         tp->nvram_size = EEPROM_CHIP_SIZE;
9845
9846         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9847                 return;
9848
9849         if ((magic != TG3_EEPROM_MAGIC) &&
9850             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9851             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9852                 return;
9853
9854         /*
9855          * Size the chip by reading offsets at increasing powers of two.
9856          * When we encounter our validation signature, we know the addressing
9857          * has wrapped around, and thus have our chip size.
9858          */
9859         cursize = 0x10;
9860
9861         while (cursize < tp->nvram_size) {
9862                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9863                         return;
9864
9865                 if (val == magic)
9866                         break;
9867
9868                 cursize <<= 1;
9869         }
9870
9871         tp->nvram_size = cursize;
9872 }
9873
9874 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9875 {
9876         u32 val;
9877
9878         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9879                 return;
9880
9881         /* Selfboot format */
9882         if (val != TG3_EEPROM_MAGIC) {
9883                 tg3_get_eeprom_size(tp);
9884                 return;
9885         }
9886
9887         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9888                 if (val != 0) {
9889                         tp->nvram_size = (val >> 16) * 1024;
9890                         return;
9891                 }
9892         }
9893         tp->nvram_size = 0x80000;
9894 }
9895
9896 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9897 {
9898         u32 nvcfg1;
9899
9900         nvcfg1 = tr32(NVRAM_CFG1);
9901         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9902                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9903         }
9904         else {
9905                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9906                 tw32(NVRAM_CFG1, nvcfg1);
9907         }
9908
9909         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9910             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9911                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9912                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9913                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9914                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9915                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9916                                 break;
9917                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9918                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9919                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9920                                 break;
9921                         case FLASH_VENDOR_ATMEL_EEPROM:
9922                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9923                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9924                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9925                                 break;
9926                         case FLASH_VENDOR_ST:
9927                                 tp->nvram_jedecnum = JEDEC_ST;
9928                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9929                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9930                                 break;
9931                         case FLASH_VENDOR_SAIFUN:
9932                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9933                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9934                                 break;
9935                         case FLASH_VENDOR_SST_SMALL:
9936                         case FLASH_VENDOR_SST_LARGE:
9937                                 tp->nvram_jedecnum = JEDEC_SST;
9938                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9939                                 break;
9940                 }
9941         }
9942         else {
9943                 tp->nvram_jedecnum = JEDEC_ATMEL;
9944                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9945                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9946         }
9947 }
9948
9949 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9950 {
9951         u32 nvcfg1;
9952
9953         nvcfg1 = tr32(NVRAM_CFG1);
9954
9955         /* NVRAM protection for TPM */
9956         if (nvcfg1 & (1 << 27))
9957                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9958
9959         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9960                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9961                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9962                         tp->nvram_jedecnum = JEDEC_ATMEL;
9963                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9964                         break;
9965                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9966                         tp->nvram_jedecnum = JEDEC_ATMEL;
9967                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9968                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9969                         break;
9970                 case FLASH_5752VENDOR_ST_M45PE10:
9971                 case FLASH_5752VENDOR_ST_M45PE20:
9972                 case FLASH_5752VENDOR_ST_M45PE40:
9973                         tp->nvram_jedecnum = JEDEC_ST;
9974                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9975                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9976                         break;
9977         }
9978
9979         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9980                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9981                         case FLASH_5752PAGE_SIZE_256:
9982                                 tp->nvram_pagesize = 256;
9983                                 break;
9984                         case FLASH_5752PAGE_SIZE_512:
9985                                 tp->nvram_pagesize = 512;
9986                                 break;
9987                         case FLASH_5752PAGE_SIZE_1K:
9988                                 tp->nvram_pagesize = 1024;
9989                                 break;
9990                         case FLASH_5752PAGE_SIZE_2K:
9991                                 tp->nvram_pagesize = 2048;
9992                                 break;
9993                         case FLASH_5752PAGE_SIZE_4K:
9994                                 tp->nvram_pagesize = 4096;
9995                                 break;
9996                         case FLASH_5752PAGE_SIZE_264:
9997                                 tp->nvram_pagesize = 264;
9998                                 break;
9999                 }
10000         }
10001         else {
10002                 /* For eeprom, set pagesize to maximum eeprom size */
10003                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10004
10005                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10006                 tw32(NVRAM_CFG1, nvcfg1);
10007         }
10008 }
10009
10010 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10011 {
10012         u32 nvcfg1, protect = 0;
10013
10014         nvcfg1 = tr32(NVRAM_CFG1);
10015
10016         /* NVRAM protection for TPM */
10017         if (nvcfg1 & (1 << 27)) {
10018                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10019                 protect = 1;
10020         }
10021
10022         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10023         switch (nvcfg1) {
10024                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10025                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10026                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10027                 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10028                         tp->nvram_jedecnum = JEDEC_ATMEL;
10029                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10030                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10031                         tp->nvram_pagesize = 264;
10032                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10033                             nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10034                                 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
10035                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10036                                 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
10037                         else
10038                                 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
10039                         break;
10040                 case FLASH_5752VENDOR_ST_M45PE10:
10041                 case FLASH_5752VENDOR_ST_M45PE20:
10042                 case FLASH_5752VENDOR_ST_M45PE40:
10043                         tp->nvram_jedecnum = JEDEC_ST;
10044                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10045                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10046                         tp->nvram_pagesize = 256;
10047                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10048                                 tp->nvram_size = (protect ? 0x10000 : 0x20000);
10049                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10050                                 tp->nvram_size = (protect ? 0x10000 : 0x40000);
10051                         else
10052                                 tp->nvram_size = (protect ? 0x20000 : 0x80000);
10053                         break;
10054         }
10055 }
10056
10057 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10058 {
10059         u32 nvcfg1;
10060
10061         nvcfg1 = tr32(NVRAM_CFG1);
10062
10063         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10064                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10065                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10066                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10067                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10068                         tp->nvram_jedecnum = JEDEC_ATMEL;
10069                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10070                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10071
10072                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10073                         tw32(NVRAM_CFG1, nvcfg1);
10074                         break;
10075                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10076                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10077                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10078                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10079                         tp->nvram_jedecnum = JEDEC_ATMEL;
10080                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10081                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10082                         tp->nvram_pagesize = 264;
10083                         break;
10084                 case FLASH_5752VENDOR_ST_M45PE10:
10085                 case FLASH_5752VENDOR_ST_M45PE20:
10086                 case FLASH_5752VENDOR_ST_M45PE40:
10087                         tp->nvram_jedecnum = JEDEC_ST;
10088                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10089                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10090                         tp->nvram_pagesize = 256;
10091                         break;
10092         }
10093 }
10094
10095 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10096 {
10097         u32 nvcfg1, protect = 0;
10098
10099         nvcfg1 = tr32(NVRAM_CFG1);
10100
10101         /* NVRAM protection for TPM */
10102         if (nvcfg1 & (1 << 27)) {
10103                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10104                 protect = 1;
10105         }
10106
10107         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10108         switch (nvcfg1) {
10109                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10110                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10111                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10112                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10113                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10114                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10115                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10116                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10117                         tp->nvram_jedecnum = JEDEC_ATMEL;
10118                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10119                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10120                         tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10121                         tp->nvram_pagesize = 256;
10122                         break;
10123                 case FLASH_5761VENDOR_ST_A_M45PE20:
10124                 case FLASH_5761VENDOR_ST_A_M45PE40:
10125                 case FLASH_5761VENDOR_ST_A_M45PE80:
10126                 case FLASH_5761VENDOR_ST_A_M45PE16:
10127                 case FLASH_5761VENDOR_ST_M_M45PE20:
10128                 case FLASH_5761VENDOR_ST_M_M45PE40:
10129                 case FLASH_5761VENDOR_ST_M_M45PE80:
10130                 case FLASH_5761VENDOR_ST_M_M45PE16:
10131                         tp->nvram_jedecnum = JEDEC_ST;
10132                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10133                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10134                         tp->nvram_pagesize = 256;
10135                         break;
10136         }
10137
10138         if (protect) {
10139                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10140         } else {
10141                 switch (nvcfg1) {
10142                         case FLASH_5761VENDOR_ATMEL_ADB161D:
10143                         case FLASH_5761VENDOR_ATMEL_MDB161D:
10144                         case FLASH_5761VENDOR_ST_A_M45PE16:
10145                         case FLASH_5761VENDOR_ST_M_M45PE16:
10146                                 tp->nvram_size = 0x100000;
10147                                 break;
10148                         case FLASH_5761VENDOR_ATMEL_ADB081D:
10149                         case FLASH_5761VENDOR_ATMEL_MDB081D:
10150                         case FLASH_5761VENDOR_ST_A_M45PE80:
10151                         case FLASH_5761VENDOR_ST_M_M45PE80:
10152                                 tp->nvram_size = 0x80000;
10153                                 break;
10154                         case FLASH_5761VENDOR_ATMEL_ADB041D:
10155                         case FLASH_5761VENDOR_ATMEL_MDB041D:
10156                         case FLASH_5761VENDOR_ST_A_M45PE40:
10157                         case FLASH_5761VENDOR_ST_M_M45PE40:
10158                                 tp->nvram_size = 0x40000;
10159                                 break;
10160                         case FLASH_5761VENDOR_ATMEL_ADB021D:
10161                         case FLASH_5761VENDOR_ATMEL_MDB021D:
10162                         case FLASH_5761VENDOR_ST_A_M45PE20:
10163                         case FLASH_5761VENDOR_ST_M_M45PE20:
10164                                 tp->nvram_size = 0x20000;
10165                                 break;
10166                 }
10167         }
10168 }
10169
10170 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10171 {
10172         tp->nvram_jedecnum = JEDEC_ATMEL;
10173         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10174         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10175 }
10176
10177 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10178 static void __devinit tg3_nvram_init(struct tg3 *tp)
10179 {
10180         tw32_f(GRC_EEPROM_ADDR,
10181              (EEPROM_ADDR_FSM_RESET |
10182               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10183                EEPROM_ADDR_CLKPERD_SHIFT)));
10184
10185         msleep(1);
10186
10187         /* Enable seeprom accesses. */
10188         tw32_f(GRC_LOCAL_CTRL,
10189              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10190         udelay(100);
10191
10192         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10193             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10194                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10195
10196                 if (tg3_nvram_lock(tp)) {
10197                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10198                                "tg3_nvram_init failed.\n", tp->dev->name);
10199                         return;
10200                 }
10201                 tg3_enable_nvram_access(tp);
10202
10203                 tp->nvram_size = 0;
10204
10205                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10206                         tg3_get_5752_nvram_info(tp);
10207                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10208                         tg3_get_5755_nvram_info(tp);
10209                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10210                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
10211                         tg3_get_5787_nvram_info(tp);
10212                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10213                         tg3_get_5761_nvram_info(tp);
10214                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10215                         tg3_get_5906_nvram_info(tp);
10216                 else
10217                         tg3_get_nvram_info(tp);
10218
10219                 if (tp->nvram_size == 0)
10220                         tg3_get_nvram_size(tp);
10221
10222                 tg3_disable_nvram_access(tp);
10223                 tg3_nvram_unlock(tp);
10224
10225         } else {
10226                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10227
10228                 tg3_get_eeprom_size(tp);
10229         }
10230 }
10231
10232 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10233                                         u32 offset, u32 *val)
10234 {
10235         u32 tmp;
10236         int i;
10237
10238         if (offset > EEPROM_ADDR_ADDR_MASK ||
10239             (offset % 4) != 0)
10240                 return -EINVAL;
10241
10242         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10243                                         EEPROM_ADDR_DEVID_MASK |
10244                                         EEPROM_ADDR_READ);
10245         tw32(GRC_EEPROM_ADDR,
10246              tmp |
10247              (0 << EEPROM_ADDR_DEVID_SHIFT) |
10248              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10249               EEPROM_ADDR_ADDR_MASK) |
10250              EEPROM_ADDR_READ | EEPROM_ADDR_START);
10251
10252         for (i = 0; i < 1000; i++) {
10253                 tmp = tr32(GRC_EEPROM_ADDR);
10254
10255                 if (tmp & EEPROM_ADDR_COMPLETE)
10256                         break;
10257                 msleep(1);
10258         }
10259         if (!(tmp & EEPROM_ADDR_COMPLETE))
10260                 return -EBUSY;
10261
10262         *val = tr32(GRC_EEPROM_DATA);
10263         return 0;
10264 }
10265
10266 #define NVRAM_CMD_TIMEOUT 10000
10267
10268 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10269 {
10270         int i;
10271
10272         tw32(NVRAM_CMD, nvram_cmd);
10273         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10274                 udelay(10);
10275                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10276                         udelay(10);
10277                         break;
10278                 }
10279         }
10280         if (i == NVRAM_CMD_TIMEOUT) {
10281                 return -EBUSY;
10282         }
10283         return 0;
10284 }
10285
10286 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10287 {
10288         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10289             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10290             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10291            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10292             (tp->nvram_jedecnum == JEDEC_ATMEL))
10293
10294                 addr = ((addr / tp->nvram_pagesize) <<
10295                         ATMEL_AT45DB0X1B_PAGE_POS) +
10296                        (addr % tp->nvram_pagesize);
10297
10298         return addr;
10299 }
10300
10301 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10302 {
10303         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10304             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10305             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10306            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10307             (tp->nvram_jedecnum == JEDEC_ATMEL))
10308
10309                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10310                         tp->nvram_pagesize) +
10311                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10312
10313         return addr;
10314 }
10315
10316 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10317 {
10318         int ret;
10319
10320         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10321                 return tg3_nvram_read_using_eeprom(tp, offset, val);
10322
10323         offset = tg3_nvram_phys_addr(tp, offset);
10324
10325         if (offset > NVRAM_ADDR_MSK)
10326                 return -EINVAL;
10327
10328         ret = tg3_nvram_lock(tp);
10329         if (ret)
10330                 return ret;
10331
10332         tg3_enable_nvram_access(tp);
10333
10334         tw32(NVRAM_ADDR, offset);
10335         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10336                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10337
10338         if (ret == 0)
10339                 *val = swab32(tr32(NVRAM_RDDATA));
10340
10341         tg3_disable_nvram_access(tp);
10342
10343         tg3_nvram_unlock(tp);
10344
10345         return ret;
10346 }
10347
10348 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
10349 {
10350         u32 v;
10351         int res = tg3_nvram_read(tp, offset, &v);
10352         if (!res)
10353                 *val = cpu_to_le32(v);
10354         return res;
10355 }
10356
10357 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10358 {
10359         int err;
10360         u32 tmp;
10361
10362         err = tg3_nvram_read(tp, offset, &tmp);
10363         *val = swab32(tmp);
10364         return err;
10365 }
10366
10367 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10368                                     u32 offset, u32 len, u8 *buf)
10369 {
10370         int i, j, rc = 0;
10371         u32 val;
10372
10373         for (i = 0; i < len; i += 4) {
10374                 u32 addr;
10375                 __le32 data;
10376
10377                 addr = offset + i;
10378
10379                 memcpy(&data, buf + i, 4);
10380
10381                 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
10382
10383                 val = tr32(GRC_EEPROM_ADDR);
10384                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10385
10386                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10387                         EEPROM_ADDR_READ);
10388                 tw32(GRC_EEPROM_ADDR, val |
10389                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10390                         (addr & EEPROM_ADDR_ADDR_MASK) |
10391                         EEPROM_ADDR_START |
10392                         EEPROM_ADDR_WRITE);
10393
10394                 for (j = 0; j < 1000; j++) {
10395                         val = tr32(GRC_EEPROM_ADDR);
10396
10397                         if (val & EEPROM_ADDR_COMPLETE)
10398                                 break;
10399                         msleep(1);
10400                 }
10401                 if (!(val & EEPROM_ADDR_COMPLETE)) {
10402                         rc = -EBUSY;
10403                         break;
10404                 }
10405         }
10406
10407         return rc;
10408 }
10409
10410 /* offset and length are dword aligned */
10411 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10412                 u8 *buf)
10413 {
10414         int ret = 0;
10415         u32 pagesize = tp->nvram_pagesize;
10416         u32 pagemask = pagesize - 1;
10417         u32 nvram_cmd;
10418         u8 *tmp;
10419
10420         tmp = kmalloc(pagesize, GFP_KERNEL);
10421         if (tmp == NULL)
10422                 return -ENOMEM;
10423
10424         while (len) {
10425                 int j;
10426                 u32 phy_addr, page_off, size;
10427
10428                 phy_addr = offset & ~pagemask;
10429
10430                 for (j = 0; j < pagesize; j += 4) {
10431                         if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
10432                                                 (__le32 *) (tmp + j))))
10433                                 break;
10434                 }
10435                 if (ret)
10436                         break;
10437
10438                 page_off = offset & pagemask;
10439                 size = pagesize;
10440                 if (len < size)
10441                         size = len;
10442
10443                 len -= size;
10444
10445                 memcpy(tmp + page_off, buf, size);
10446
10447                 offset = offset + (pagesize - page_off);
10448
10449                 tg3_enable_nvram_access(tp);
10450
10451                 /*
10452                  * Before we can erase the flash page, we need
10453                  * to issue a special "write enable" command.
10454                  */
10455                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10456
10457                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10458                         break;
10459
10460                 /* Erase the target page */
10461                 tw32(NVRAM_ADDR, phy_addr);
10462
10463                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10464                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10465
10466                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10467                         break;
10468
10469                 /* Issue another write enable to start the write. */
10470                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10471
10472                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10473                         break;
10474
10475                 for (j = 0; j < pagesize; j += 4) {
10476                         __be32 data;
10477
10478                         data = *((__be32 *) (tmp + j));
10479                         /* swab32(le32_to_cpu(data)), actually */
10480                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
10481
10482                         tw32(NVRAM_ADDR, phy_addr + j);
10483
10484                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10485                                 NVRAM_CMD_WR;
10486
10487                         if (j == 0)
10488                                 nvram_cmd |= NVRAM_CMD_FIRST;
10489                         else if (j == (pagesize - 4))
10490                                 nvram_cmd |= NVRAM_CMD_LAST;
10491
10492                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10493                                 break;
10494                 }
10495                 if (ret)
10496                         break;
10497         }
10498
10499         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10500         tg3_nvram_exec_cmd(tp, nvram_cmd);
10501
10502         kfree(tmp);
10503
10504         return ret;
10505 }
10506
10507 /* offset and length are dword aligned */
10508 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10509                 u8 *buf)
10510 {
10511         int i, ret = 0;
10512
10513         for (i = 0; i < len; i += 4, offset += 4) {
10514                 u32 page_off, phy_addr, nvram_cmd;
10515                 __be32 data;
10516
10517                 memcpy(&data, buf + i, 4);
10518                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10519
10520                 page_off = offset % tp->nvram_pagesize;
10521
10522                 phy_addr = tg3_nvram_phys_addr(tp, offset);
10523
10524                 tw32(NVRAM_ADDR, phy_addr);
10525
10526                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10527
10528                 if ((page_off == 0) || (i == 0))
10529                         nvram_cmd |= NVRAM_CMD_FIRST;
10530                 if (page_off == (tp->nvram_pagesize - 4))
10531                         nvram_cmd |= NVRAM_CMD_LAST;
10532
10533                 if (i == (len - 4))
10534                         nvram_cmd |= NVRAM_CMD_LAST;
10535
10536                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
10537                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
10538                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
10539                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
10540                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
10541                     (tp->nvram_jedecnum == JEDEC_ST) &&
10542                     (nvram_cmd & NVRAM_CMD_FIRST)) {
10543
10544                         if ((ret = tg3_nvram_exec_cmd(tp,
10545                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10546                                 NVRAM_CMD_DONE)))
10547
10548                                 break;
10549                 }
10550                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10551                         /* We always do complete word writes to eeprom. */
10552                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10553                 }
10554
10555                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10556                         break;
10557         }
10558         return ret;
10559 }
10560
10561 /* offset and length are dword aligned */
10562 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10563 {
10564         int ret;
10565
10566         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10567                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10568                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
10569                 udelay(40);
10570         }
10571
10572         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10573                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10574         }
10575         else {
10576                 u32 grc_mode;
10577
10578                 ret = tg3_nvram_lock(tp);
10579                 if (ret)
10580                         return ret;
10581
10582                 tg3_enable_nvram_access(tp);
10583                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10584                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
10585                         tw32(NVRAM_WRITE1, 0x406);
10586
10587                 grc_mode = tr32(GRC_MODE);
10588                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10589
10590                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10591                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10592
10593                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
10594                                 buf);
10595                 }
10596                 else {
10597                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10598                                 buf);
10599                 }
10600
10601                 grc_mode = tr32(GRC_MODE);
10602                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10603
10604                 tg3_disable_nvram_access(tp);
10605                 tg3_nvram_unlock(tp);
10606         }
10607
10608         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10609                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10610                 udelay(40);
10611         }
10612
10613         return ret;
10614 }
10615
10616 struct subsys_tbl_ent {
10617         u16 subsys_vendor, subsys_devid;
10618         u32 phy_id;
10619 };
10620
10621 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10622         /* Broadcom boards. */
10623         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10624         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10625         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10626         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
10627         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10628         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10629         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
10630         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10631         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10632         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10633         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10634
10635         /* 3com boards. */
10636         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10637         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10638         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
10639         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10640         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10641
10642         /* DELL boards. */
10643         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10644         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10645         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10646         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10647
10648         /* Compaq boards. */
10649         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10650         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10651         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
10652         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10653         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10654
10655         /* IBM boards. */
10656         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10657 };
10658
10659 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10660 {
10661         int i;
10662
10663         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10664                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10665                      tp->pdev->subsystem_vendor) &&
10666                     (subsys_id_to_phy_id[i].subsys_devid ==
10667                      tp->pdev->subsystem_device))
10668                         return &subsys_id_to_phy_id[i];
10669         }
10670         return NULL;
10671 }
10672
10673 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10674 {
10675         u32 val;
10676         u16 pmcsr;
10677
10678         /* On some early chips the SRAM cannot be accessed in D3hot state,
10679          * so need make sure we're in D0.
10680          */
10681         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10682         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10683         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10684         msleep(1);
10685
10686         /* Make sure register accesses (indirect or otherwise)
10687          * will function correctly.
10688          */
10689         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10690                                tp->misc_host_ctrl);
10691
10692         /* The memory arbiter has to be enabled in order for SRAM accesses
10693          * to succeed.  Normally on powerup the tg3 chip firmware will make
10694          * sure it is enabled, but other entities such as system netboot
10695          * code might disable it.
10696          */
10697         val = tr32(MEMARB_MODE);
10698         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10699
10700         tp->phy_id = PHY_ID_INVALID;
10701         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10702
10703         /* Assume an onboard device and WOL capable by default.  */
10704         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10705
10706         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10707                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10708                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10709                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10710                 }
10711                 val = tr32(VCPU_CFGSHDW);
10712                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
10713                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10714                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
10715                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
10716                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10717                 return;
10718         }
10719
10720         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10721         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10722                 u32 nic_cfg, led_cfg;
10723                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10724                 int eeprom_phy_serdes = 0;
10725
10726                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10727                 tp->nic_sram_data_cfg = nic_cfg;
10728
10729                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10730                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10731                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10732                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10733                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10734                     (ver > 0) && (ver < 0x100))
10735                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10736
10737                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10738                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10739                         eeprom_phy_serdes = 1;
10740
10741                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10742                 if (nic_phy_id != 0) {
10743                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10744                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10745
10746                         eeprom_phy_id  = (id1 >> 16) << 10;
10747                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
10748                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10749                 } else
10750                         eeprom_phy_id = 0;
10751
10752                 tp->phy_id = eeprom_phy_id;
10753                 if (eeprom_phy_serdes) {
10754                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10755                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10756                         else
10757                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10758                 }
10759
10760                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10761                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10762                                     SHASTA_EXT_LED_MODE_MASK);
10763                 else
10764                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10765
10766                 switch (led_cfg) {
10767                 default:
10768                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10769                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10770                         break;
10771
10772                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10773                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10774                         break;
10775
10776                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10777                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10778
10779                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10780                          * read on some older 5700/5701 bootcode.
10781                          */
10782                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10783                             ASIC_REV_5700 ||
10784                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10785                             ASIC_REV_5701)
10786                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10787
10788                         break;
10789
10790                 case SHASTA_EXT_LED_SHARED:
10791                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10792                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10793                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10794                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10795                                                  LED_CTRL_MODE_PHY_2);
10796                         break;
10797
10798                 case SHASTA_EXT_LED_MAC:
10799                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10800                         break;
10801
10802                 case SHASTA_EXT_LED_COMBO:
10803                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10804                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10805                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10806                                                  LED_CTRL_MODE_PHY_2);
10807                         break;
10808
10809                 };
10810
10811                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10812                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10813                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10814                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10815
10816                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
10817                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10818
10819                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10820                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10821                         if ((tp->pdev->subsystem_vendor ==
10822                              PCI_VENDOR_ID_ARIMA) &&
10823                             (tp->pdev->subsystem_device == 0x205a ||
10824                              tp->pdev->subsystem_device == 0x2063))
10825                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10826                 } else {
10827                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10828                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10829                 }
10830
10831                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10832                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10833                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10834                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10835                 }
10836                 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
10837                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
10838                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10839                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10840                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
10841
10842                 if (tp->tg3_flags & TG3_FLAG_WOL_CAP &&
10843                     nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)
10844                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10845
10846                 if (cfg2 & (1 << 17))
10847                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10848
10849                 /* serdes signal pre-emphasis in register 0x590 set by */
10850                 /* bootcode if bit 18 is set */
10851                 if (cfg2 & (1 << 18))
10852                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10853
10854                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10855                         u32 cfg3;
10856
10857                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10858                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10859                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10860                 }
10861         }
10862 }
10863
10864 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
10865 {
10866         int i;
10867         u32 val;
10868
10869         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
10870         tw32(OTP_CTRL, cmd);
10871
10872         /* Wait for up to 1 ms for command to execute. */
10873         for (i = 0; i < 100; i++) {
10874                 val = tr32(OTP_STATUS);
10875                 if (val & OTP_STATUS_CMD_DONE)
10876                         break;
10877                 udelay(10);
10878         }
10879
10880         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
10881 }
10882
10883 /* Read the gphy configuration from the OTP region of the chip.  The gphy
10884  * configuration is a 32-bit value that straddles the alignment boundary.
10885  * We do two 32-bit reads and then shift and merge the results.
10886  */
10887 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
10888 {
10889         u32 bhalf_otp, thalf_otp;
10890
10891         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
10892
10893         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
10894                 return 0;
10895
10896         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
10897
10898         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
10899                 return 0;
10900
10901         thalf_otp = tr32(OTP_READ_DATA);
10902
10903         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
10904
10905         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
10906                 return 0;
10907
10908         bhalf_otp = tr32(OTP_READ_DATA);
10909
10910         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
10911 }
10912
10913 static int __devinit tg3_phy_probe(struct tg3 *tp)
10914 {
10915         u32 hw_phy_id_1, hw_phy_id_2;
10916         u32 hw_phy_id, hw_phy_id_masked;
10917         int err;
10918
10919         /* Reading the PHY ID register can conflict with ASF
10920          * firwmare access to the PHY hardware.
10921          */
10922         err = 0;
10923         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
10924             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
10925                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10926         } else {
10927                 /* Now read the physical PHY_ID from the chip and verify
10928                  * that it is sane.  If it doesn't look good, we fall back
10929                  * to either the hard-coded table based PHY_ID and failing
10930                  * that the value found in the eeprom area.
10931                  */
10932                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10933                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10934
10935                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
10936                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10937                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
10938
10939                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10940         }
10941
10942         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10943                 tp->phy_id = hw_phy_id;
10944                 if (hw_phy_id_masked == PHY_ID_BCM8002)
10945                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10946                 else
10947                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10948         } else {
10949                 if (tp->phy_id != PHY_ID_INVALID) {
10950                         /* Do nothing, phy ID already set up in
10951                          * tg3_get_eeprom_hw_cfg().
10952                          */
10953                 } else {
10954                         struct subsys_tbl_ent *p;
10955
10956                         /* No eeprom signature?  Try the hardcoded
10957                          * subsys device table.
10958                          */
10959                         p = lookup_by_subsys(tp);
10960                         if (!p)
10961                                 return -ENODEV;
10962
10963                         tp->phy_id = p->phy_id;
10964                         if (!tp->phy_id ||
10965                             tp->phy_id == PHY_ID_BCM8002)
10966                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10967                 }
10968         }
10969
10970         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10971             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
10972             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10973                 u32 bmsr, adv_reg, tg3_ctrl, mask;
10974
10975                 tg3_readphy(tp, MII_BMSR, &bmsr);
10976                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10977                     (bmsr & BMSR_LSTATUS))
10978                         goto skip_phy_reset;
10979
10980                 err = tg3_phy_reset(tp);
10981                 if (err)
10982                         return err;
10983
10984                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10985                            ADVERTISE_100HALF | ADVERTISE_100FULL |
10986                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10987                 tg3_ctrl = 0;
10988                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10989                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10990                                     MII_TG3_CTRL_ADV_1000_FULL);
10991                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10992                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10993                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10994                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
10995                 }
10996
10997                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10998                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10999                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11000                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11001                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11002
11003                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11004                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11005
11006                         tg3_writephy(tp, MII_BMCR,
11007                                      BMCR_ANENABLE | BMCR_ANRESTART);
11008                 }
11009                 tg3_phy_set_wirespeed(tp);
11010
11011                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11012                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11013                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11014         }
11015
11016 skip_phy_reset:
11017         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11018                 err = tg3_init_5401phy_dsp(tp);
11019                 if (err)
11020                         return err;
11021         }
11022
11023         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11024                 err = tg3_init_5401phy_dsp(tp);
11025         }
11026
11027         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11028                 tp->link_config.advertising =
11029                         (ADVERTISED_1000baseT_Half |
11030                          ADVERTISED_1000baseT_Full |
11031                          ADVERTISED_Autoneg |
11032                          ADVERTISED_FIBRE);
11033         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11034                 tp->link_config.advertising &=
11035                         ~(ADVERTISED_1000baseT_Half |
11036                           ADVERTISED_1000baseT_Full);
11037
11038         return err;
11039 }
11040
11041 static void __devinit tg3_read_partno(struct tg3 *tp)
11042 {
11043         unsigned char vpd_data[256];
11044         unsigned int i;
11045         u32 magic;
11046
11047         if (tg3_nvram_read_swab(tp, 0x0, &magic))
11048                 goto out_not_found;
11049
11050         if (magic == TG3_EEPROM_MAGIC) {
11051                 for (i = 0; i < 256; i += 4) {
11052                         u32 tmp;
11053
11054                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11055                                 goto out_not_found;
11056
11057                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
11058                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
11059                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11060                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11061                 }
11062         } else {
11063                 int vpd_cap;
11064
11065                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11066                 for (i = 0; i < 256; i += 4) {
11067                         u32 tmp, j = 0;
11068                         __le32 v;
11069                         u16 tmp16;
11070
11071                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11072                                               i);
11073                         while (j++ < 100) {
11074                                 pci_read_config_word(tp->pdev, vpd_cap +
11075                                                      PCI_VPD_ADDR, &tmp16);
11076                                 if (tmp16 & 0x8000)
11077                                         break;
11078                                 msleep(1);
11079                         }
11080                         if (!(tmp16 & 0x8000))
11081                                 goto out_not_found;
11082
11083                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11084                                               &tmp);
11085                         v = cpu_to_le32(tmp);
11086                         memcpy(&vpd_data[i], &v, 4);
11087                 }
11088         }
11089
11090         /* Now parse and find the part number. */
11091         for (i = 0; i < 254; ) {
11092                 unsigned char val = vpd_data[i];
11093                 unsigned int block_end;
11094
11095                 if (val == 0x82 || val == 0x91) {
11096                         i = (i + 3 +
11097                              (vpd_data[i + 1] +
11098                               (vpd_data[i + 2] << 8)));
11099                         continue;
11100                 }
11101
11102                 if (val != 0x90)
11103                         goto out_not_found;
11104
11105                 block_end = (i + 3 +
11106                              (vpd_data[i + 1] +
11107                               (vpd_data[i + 2] << 8)));
11108                 i += 3;
11109
11110                 if (block_end > 256)
11111                         goto out_not_found;
11112
11113                 while (i < (block_end - 2)) {
11114                         if (vpd_data[i + 0] == 'P' &&
11115                             vpd_data[i + 1] == 'N') {
11116                                 int partno_len = vpd_data[i + 2];
11117
11118                                 i += 3;
11119                                 if (partno_len > 24 || (partno_len + i) > 256)
11120                                         goto out_not_found;
11121
11122                                 memcpy(tp->board_part_number,
11123                                        &vpd_data[i], partno_len);
11124
11125                                 /* Success. */
11126                                 return;
11127                         }
11128                         i += 3 + vpd_data[i + 2];
11129                 }
11130
11131                 /* Part number not found. */
11132                 goto out_not_found;
11133         }
11134
11135 out_not_found:
11136         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11137                 strcpy(tp->board_part_number, "BCM95906");
11138         else
11139                 strcpy(tp->board_part_number, "none");
11140 }
11141
11142 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11143 {
11144         u32 val;
11145
11146         if (tg3_nvram_read_swab(tp, offset, &val) ||
11147             (val & 0xfc000000) != 0x0c000000 ||
11148             tg3_nvram_read_swab(tp, offset + 4, &val) ||
11149             val != 0)
11150                 return 0;
11151
11152         return 1;
11153 }
11154
11155 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11156 {
11157         u32 val, offset, start;
11158         u32 ver_offset;
11159         int i, bcnt;
11160
11161         if (tg3_nvram_read_swab(tp, 0, &val))
11162                 return;
11163
11164         if (val != TG3_EEPROM_MAGIC)
11165                 return;
11166
11167         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11168             tg3_nvram_read_swab(tp, 0x4, &start))
11169                 return;
11170
11171         offset = tg3_nvram_logical_addr(tp, offset);
11172
11173         if (!tg3_fw_img_is_valid(tp, offset) ||
11174             tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
11175                 return;
11176
11177         offset = offset + ver_offset - start;
11178         for (i = 0; i < 16; i += 4) {
11179                 __le32 v;
11180                 if (tg3_nvram_read_le(tp, offset + i, &v))
11181                         return;
11182
11183                 memcpy(tp->fw_ver + i, &v, 4);
11184         }
11185
11186         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11187              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11188                 return;
11189
11190         for (offset = TG3_NVM_DIR_START;
11191              offset < TG3_NVM_DIR_END;
11192              offset += TG3_NVM_DIRENT_SIZE) {
11193                 if (tg3_nvram_read_swab(tp, offset, &val))
11194                         return;
11195
11196                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11197                         break;
11198         }
11199
11200         if (offset == TG3_NVM_DIR_END)
11201                 return;
11202
11203         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11204                 start = 0x08000000;
11205         else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11206                 return;
11207
11208         if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11209             !tg3_fw_img_is_valid(tp, offset) ||
11210             tg3_nvram_read_swab(tp, offset + 8, &val))
11211                 return;
11212
11213         offset += val - start;
11214
11215         bcnt = strlen(tp->fw_ver);
11216
11217         tp->fw_ver[bcnt++] = ',';
11218         tp->fw_ver[bcnt++] = ' ';
11219
11220         for (i = 0; i < 4; i++) {
11221                 __le32 v;
11222                 if (tg3_nvram_read_le(tp, offset, &v))
11223                         return;
11224
11225                 offset += sizeof(v);
11226
11227                 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11228                         memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
11229                         break;
11230                 }
11231
11232                 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11233                 bcnt += sizeof(v);
11234         }
11235
11236         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11237 }
11238
11239 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11240
11241 static int __devinit tg3_get_invariants(struct tg3 *tp)
11242 {
11243         static struct pci_device_id write_reorder_chipsets[] = {
11244                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11245                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11246                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11247                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11248                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11249                              PCI_DEVICE_ID_VIA_8385_0) },
11250                 { },
11251         };
11252         u32 misc_ctrl_reg;
11253         u32 cacheline_sz_reg;
11254         u32 pci_state_reg, grc_misc_cfg;
11255         u32 val;
11256         u16 pci_cmd;
11257         int err, pcie_cap;
11258
11259         /* Force memory write invalidate off.  If we leave it on,
11260          * then on 5700_BX chips we have to enable a workaround.
11261          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11262          * to match the cacheline size.  The Broadcom driver have this
11263          * workaround but turns MWI off all the times so never uses
11264          * it.  This seems to suggest that the workaround is insufficient.
11265          */
11266         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11267         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11268         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11269
11270         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11271          * has the register indirect write enable bit set before
11272          * we try to access any of the MMIO registers.  It is also
11273          * critical that the PCI-X hw workaround situation is decided
11274          * before that as well.
11275          */
11276         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11277                               &misc_ctrl_reg);
11278
11279         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11280                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11281         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11282                 u32 prod_id_asic_rev;
11283
11284                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11285                                       &prod_id_asic_rev);
11286                 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
11287         }
11288
11289         /* Wrong chip ID in 5752 A0. This code can be removed later
11290          * as A0 is not in production.
11291          */
11292         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11293                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11294
11295         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11296          * we need to disable memory and use config. cycles
11297          * only to access all registers. The 5702/03 chips
11298          * can mistakenly decode the special cycles from the
11299          * ICH chipsets as memory write cycles, causing corruption
11300          * of register and memory space. Only certain ICH bridges
11301          * will drive special cycles with non-zero data during the
11302          * address phase which can fall within the 5703's address
11303          * range. This is not an ICH bug as the PCI spec allows
11304          * non-zero address during special cycles. However, only
11305          * these ICH bridges are known to drive non-zero addresses
11306          * during special cycles.
11307          *
11308          * Since special cycles do not cross PCI bridges, we only
11309          * enable this workaround if the 5703 is on the secondary
11310          * bus of these ICH bridges.
11311          */
11312         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11313             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11314                 static struct tg3_dev_id {
11315                         u32     vendor;
11316                         u32     device;
11317                         u32     rev;
11318                 } ich_chipsets[] = {
11319                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11320                           PCI_ANY_ID },
11321                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11322                           PCI_ANY_ID },
11323                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11324                           0xa },
11325                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11326                           PCI_ANY_ID },
11327                         { },
11328                 };
11329                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11330                 struct pci_dev *bridge = NULL;
11331
11332                 while (pci_id->vendor != 0) {
11333                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11334                                                 bridge);
11335                         if (!bridge) {
11336                                 pci_id++;
11337                                 continue;
11338                         }
11339                         if (pci_id->rev != PCI_ANY_ID) {
11340                                 if (bridge->revision > pci_id->rev)
11341                                         continue;
11342                         }
11343                         if (bridge->subordinate &&
11344                             (bridge->subordinate->number ==
11345                              tp->pdev->bus->number)) {
11346
11347                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11348                                 pci_dev_put(bridge);
11349                                 break;
11350                         }
11351                 }
11352         }
11353
11354         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11355                 static struct tg3_dev_id {
11356                         u32     vendor;
11357                         u32     device;
11358                 } bridge_chipsets[] = {
11359                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11360                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11361                         { },
11362                 };
11363                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11364                 struct pci_dev *bridge = NULL;
11365
11366                 while (pci_id->vendor != 0) {
11367                         bridge = pci_get_device(pci_id->vendor,
11368                                                 pci_id->device,
11369                                                 bridge);
11370                         if (!bridge) {
11371                                 pci_id++;
11372                                 continue;
11373                         }
11374                         if (bridge->subordinate &&
11375                             (bridge->subordinate->number <=
11376                              tp->pdev->bus->number) &&
11377                             (bridge->subordinate->subordinate >=
11378                              tp->pdev->bus->number)) {
11379                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11380                                 pci_dev_put(bridge);
11381                                 break;
11382                         }
11383                 }
11384         }
11385
11386         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11387          * DMA addresses > 40-bit. This bridge may have other additional
11388          * 57xx devices behind it in some 4-port NIC designs for example.
11389          * Any tg3 device found behind the bridge will also need the 40-bit
11390          * DMA workaround.
11391          */
11392         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11393             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11394                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11395                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11396                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11397         }
11398         else {
11399                 struct pci_dev *bridge = NULL;
11400
11401                 do {
11402                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11403                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
11404                                                 bridge);
11405                         if (bridge && bridge->subordinate &&
11406                             (bridge->subordinate->number <=
11407                              tp->pdev->bus->number) &&
11408                             (bridge->subordinate->subordinate >=
11409                              tp->pdev->bus->number)) {
11410                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11411                                 pci_dev_put(bridge);
11412                                 break;
11413                         }
11414                 } while (bridge);
11415         }
11416
11417         /* Initialize misc host control in PCI block. */
11418         tp->misc_host_ctrl |= (misc_ctrl_reg &
11419                                MISC_HOST_CTRL_CHIPREV);
11420         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11421                                tp->misc_host_ctrl);
11422
11423         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11424                               &cacheline_sz_reg);
11425
11426         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
11427         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
11428         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
11429         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
11430
11431         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11432             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11433                 tp->pdev_peer = tg3_find_peer(tp);
11434
11435         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11436             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11437             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11438             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11439             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11440             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11441             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11442             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11443                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11444
11445         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11446             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11447                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11448
11449         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11450                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11451                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11452                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11453                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11454                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11455                      tp->pdev_peer == tp->pdev))
11456                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11457
11458                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11459                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11460                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11461                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11462                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11463                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11464                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
11465                 } else {
11466                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
11467                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11468                                 ASIC_REV_5750 &&
11469                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
11470                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
11471                 }
11472         }
11473
11474         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
11475             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
11476             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11477             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
11478             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
11479             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
11480             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
11481             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
11482                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11483
11484         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11485         if (pcie_cap != 0) {
11486                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11487
11488                 pcie_set_readrq(tp->pdev, 4096);
11489
11490                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11491                         u16 lnkctl;
11492
11493                         pci_read_config_word(tp->pdev,
11494                                              pcie_cap + PCI_EXP_LNKCTL,
11495                                              &lnkctl);
11496                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
11497                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11498                 }
11499         }
11500
11501         /* If we have an AMD 762 or VIA K8T800 chipset, write
11502          * reordering to the mailbox registers done by the host
11503          * controller can cause major troubles.  We read back from
11504          * every mailbox register write to force the writes to be
11505          * posted to the chip in order.
11506          */
11507         if (pci_dev_present(write_reorder_chipsets) &&
11508             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11509                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11510
11511         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11512             tp->pci_lat_timer < 64) {
11513                 tp->pci_lat_timer = 64;
11514
11515                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
11516                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
11517                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
11518                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
11519
11520                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11521                                        cacheline_sz_reg);
11522         }
11523
11524         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11525             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11526                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11527                 if (!tp->pcix_cap) {
11528                         printk(KERN_ERR PFX "Cannot find PCI-X "
11529                                             "capability, aborting.\n");
11530                         return -EIO;
11531                 }
11532         }
11533
11534         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11535                               &pci_state_reg);
11536
11537         if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
11538                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11539
11540                 /* If this is a 5700 BX chipset, and we are in PCI-X
11541                  * mode, enable register write workaround.
11542                  *
11543                  * The workaround is to use indirect register accesses
11544                  * for all chip writes not to mailbox registers.
11545                  */
11546                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
11547                         u32 pm_reg;
11548
11549                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11550
11551                         /* The chip can have it's power management PCI config
11552                          * space registers clobbered due to this bug.
11553                          * So explicitly force the chip into D0 here.
11554                          */
11555                         pci_read_config_dword(tp->pdev,
11556                                               tp->pm_cap + PCI_PM_CTRL,
11557                                               &pm_reg);
11558                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
11559                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
11560                         pci_write_config_dword(tp->pdev,
11561                                                tp->pm_cap + PCI_PM_CTRL,
11562                                                pm_reg);
11563
11564                         /* Also, force SERR#/PERR# in PCI command. */
11565                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11566                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
11567                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11568                 }
11569         }
11570
11571         /* 5700 BX chips need to have their TX producer index mailboxes
11572          * written twice to workaround a bug.
11573          */
11574         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
11575                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
11576
11577         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
11578                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
11579         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
11580                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
11581
11582         /* Chip-specific fixup from Broadcom driver */
11583         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
11584             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
11585                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
11586                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
11587         }
11588
11589         /* Default fast path register access methods */
11590         tp->read32 = tg3_read32;
11591         tp->write32 = tg3_write32;
11592         tp->read32_mbox = tg3_read32;
11593         tp->write32_mbox = tg3_write32;
11594         tp->write32_tx_mbox = tg3_write32;
11595         tp->write32_rx_mbox = tg3_write32;
11596
11597         /* Various workaround register access methods */
11598         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
11599                 tp->write32 = tg3_write_indirect_reg32;
11600         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11601                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
11602                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
11603                 /*
11604                  * Back to back register writes can cause problems on these
11605                  * chips, the workaround is to read back all reg writes
11606                  * except those to mailbox regs.
11607                  *
11608                  * See tg3_write_indirect_reg32().
11609                  */
11610                 tp->write32 = tg3_write_flush_reg32;
11611         }
11612
11613
11614         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
11615             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
11616                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11617                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
11618                         tp->write32_rx_mbox = tg3_write_flush_reg32;
11619         }
11620
11621         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
11622                 tp->read32 = tg3_read_indirect_reg32;
11623                 tp->write32 = tg3_write_indirect_reg32;
11624                 tp->read32_mbox = tg3_read_indirect_mbox;
11625                 tp->write32_mbox = tg3_write_indirect_mbox;
11626                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
11627                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
11628
11629                 iounmap(tp->regs);
11630                 tp->regs = NULL;
11631
11632                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11633                 pci_cmd &= ~PCI_COMMAND_MEMORY;
11634                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11635         }
11636         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11637                 tp->read32_mbox = tg3_read32_mbox_5906;
11638                 tp->write32_mbox = tg3_write32_mbox_5906;
11639                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
11640                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
11641         }
11642
11643         if (tp->write32 == tg3_write_indirect_reg32 ||
11644             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11645              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11646               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
11647                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
11648
11649         /* Get eeprom hw config before calling tg3_set_power_state().
11650          * In particular, the TG3_FLG2_IS_NIC flag must be
11651          * determined before calling tg3_set_power_state() so that
11652          * we know whether or not to switch out of Vaux power.
11653          * When the flag is set, it means that GPIO1 is used for eeprom
11654          * write protect and also implies that it is a LOM where GPIOs
11655          * are not used to switch power.
11656          */
11657         tg3_get_eeprom_hw_cfg(tp);
11658
11659         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
11660                 /* Allow reads and writes to the
11661                  * APE register and memory space.
11662                  */
11663                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
11664                                  PCISTATE_ALLOW_APE_SHMEM_WR;
11665                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
11666                                        pci_state_reg);
11667         }
11668
11669         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11670             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
11671                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
11672
11673                 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
11674                     tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
11675                     tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
11676                     tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
11677                         tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
11678         }
11679
11680         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
11681          * GPIO1 driven high will bring 5700's external PHY out of reset.
11682          * It is also used as eeprom write protect on LOMs.
11683          */
11684         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
11685         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11686             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
11687                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
11688                                        GRC_LCLCTRL_GPIO_OUTPUT1);
11689         /* Unused GPIO3 must be driven as output on 5752 because there
11690          * are no pull-up resistors on unused GPIO pins.
11691          */
11692         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11693                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
11694
11695         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11696                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
11697
11698         /* Force the chip into D0. */
11699         err = tg3_set_power_state(tp, PCI_D0);
11700         if (err) {
11701                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
11702                        pci_name(tp->pdev));
11703                 return err;
11704         }
11705
11706         /* 5700 B0 chips do not support checksumming correctly due
11707          * to hardware bugs.
11708          */
11709         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11710                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11711
11712         /* Derive initial jumbo mode from MTU assigned in
11713          * ether_setup() via the alloc_etherdev() call
11714          */
11715         if (tp->dev->mtu > ETH_DATA_LEN &&
11716             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11717                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
11718
11719         /* Determine WakeOnLan speed to use. */
11720         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11721             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11722             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
11723             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
11724                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
11725         } else {
11726                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
11727         }
11728
11729         /* A few boards don't want Ethernet@WireSpeed phy feature */
11730         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11731             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
11732              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
11733              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
11734             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
11735             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
11736                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
11737
11738         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
11739             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
11740                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
11741         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
11742                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
11743
11744         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11745                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11746                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11747                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11748                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
11749                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
11750                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
11751                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
11752                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
11753                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
11754                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
11755                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
11756         }
11757
11758         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11759             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
11760                 tp->phy_otp = tg3_read_otp_phycfg(tp);
11761                 if (tp->phy_otp == 0)
11762                         tp->phy_otp = TG3_OTP_DEFAULT;
11763         }
11764
11765         tp->coalesce_mode = 0;
11766         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
11767             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
11768                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
11769
11770         /* Initialize MAC MI mode, polling disabled. */
11771         tw32_f(MAC_MI_MODE, tp->mi_mode);
11772         udelay(80);
11773
11774         /* Initialize data/descriptor byte/word swapping. */
11775         val = tr32(GRC_MODE);
11776         val &= GRC_MODE_HOST_STACKUP;
11777         tw32(GRC_MODE, val | tp->grc_mode);
11778
11779         tg3_switch_clocks(tp);
11780
11781         /* Clear this out for sanity. */
11782         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
11783
11784         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11785                               &pci_state_reg);
11786         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
11787             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
11788                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
11789
11790                 if (chiprevid == CHIPREV_ID_5701_A0 ||
11791                     chiprevid == CHIPREV_ID_5701_B0 ||
11792                     chiprevid == CHIPREV_ID_5701_B2 ||
11793                     chiprevid == CHIPREV_ID_5701_B5) {
11794                         void __iomem *sram_base;
11795
11796                         /* Write some dummy words into the SRAM status block
11797                          * area, see if it reads back correctly.  If the return
11798                          * value is bad, force enable the PCIX workaround.
11799                          */
11800                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
11801
11802                         writel(0x00000000, sram_base);
11803                         writel(0x00000000, sram_base + 4);
11804                         writel(0xffffffff, sram_base + 4);
11805                         if (readl(sram_base) != 0x00000000)
11806                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11807                 }
11808         }
11809
11810         udelay(50);
11811         tg3_nvram_init(tp);
11812
11813         grc_misc_cfg = tr32(GRC_MISC_CFG);
11814         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
11815
11816         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11817             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
11818              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
11819                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
11820
11821         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
11822             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
11823                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
11824         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
11825                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
11826                                       HOSTCC_MODE_CLRTICK_TXBD);
11827
11828                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
11829                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11830                                        tp->misc_host_ctrl);
11831         }
11832
11833         /* these are limited to 10/100 only */
11834         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11835              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
11836             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11837              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11838              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
11839               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
11840               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
11841             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11842              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
11843               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
11844               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
11845             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11846                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
11847
11848         err = tg3_phy_probe(tp);
11849         if (err) {
11850                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
11851                        pci_name(tp->pdev), err);
11852                 /* ... but do not return immediately ... */
11853         }
11854
11855         tg3_read_partno(tp);
11856         tg3_read_fw_ver(tp);
11857
11858         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
11859                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11860         } else {
11861                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11862                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
11863                 else
11864                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11865         }
11866
11867         /* 5700 {AX,BX} chips have a broken status block link
11868          * change bit implementation, so we must use the
11869          * status register in those cases.
11870          */
11871         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11872                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
11873         else
11874                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
11875
11876         /* The led_ctrl is set during tg3_phy_probe, here we might
11877          * have to force the link status polling mechanism based
11878          * upon subsystem IDs.
11879          */
11880         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
11881             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11882             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
11883                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
11884                                   TG3_FLAG_USE_LINKCHG_REG);
11885         }
11886
11887         /* For all SERDES we poll the MAC status register. */
11888         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11889                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
11890         else
11891                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
11892
11893         /* All chips before 5787 can get confused if TX buffers
11894          * straddle the 4GB address boundary in some cases.
11895          */
11896         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11897             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11898             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11899             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11900             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11901                 tp->dev->hard_start_xmit = tg3_start_xmit;
11902         else
11903                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
11904
11905         tp->rx_offset = 2;
11906         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11907             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11908                 tp->rx_offset = 0;
11909
11910         tp->rx_std_max_post = TG3_RX_RING_SIZE;
11911
11912         /* Increment the rx prod index on the rx std ring by at most
11913          * 8 for these chips to workaround hw errata.
11914          */
11915         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11916             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11917             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11918                 tp->rx_std_max_post = 8;
11919
11920         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11921                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
11922                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
11923
11924         return err;
11925 }
11926
11927 #ifdef CONFIG_SPARC
11928 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11929 {
11930         struct net_device *dev = tp->dev;
11931         struct pci_dev *pdev = tp->pdev;
11932         struct device_node *dp = pci_device_to_OF_node(pdev);
11933         const unsigned char *addr;
11934         int len;
11935
11936         addr = of_get_property(dp, "local-mac-address", &len);
11937         if (addr && len == 6) {
11938                 memcpy(dev->dev_addr, addr, 6);
11939                 memcpy(dev->perm_addr, dev->dev_addr, 6);
11940                 return 0;
11941         }
11942         return -ENODEV;
11943 }
11944
11945 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11946 {
11947         struct net_device *dev = tp->dev;
11948
11949         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11950         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11951         return 0;
11952 }
11953 #endif
11954
11955 static int __devinit tg3_get_device_address(struct tg3 *tp)
11956 {
11957         struct net_device *dev = tp->dev;
11958         u32 hi, lo, mac_offset;
11959         int addr_ok = 0;
11960
11961 #ifdef CONFIG_SPARC
11962         if (!tg3_get_macaddr_sparc(tp))
11963                 return 0;
11964 #endif
11965
11966         mac_offset = 0x7c;
11967         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11968             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11969                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11970                         mac_offset = 0xcc;
11971                 if (tg3_nvram_lock(tp))
11972                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11973                 else
11974                         tg3_nvram_unlock(tp);
11975         }
11976         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11977                 mac_offset = 0x10;
11978
11979         /* First try to get it from MAC address mailbox. */
11980         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11981         if ((hi >> 16) == 0x484b) {
11982                 dev->dev_addr[0] = (hi >>  8) & 0xff;
11983                 dev->dev_addr[1] = (hi >>  0) & 0xff;
11984
11985                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11986                 dev->dev_addr[2] = (lo >> 24) & 0xff;
11987                 dev->dev_addr[3] = (lo >> 16) & 0xff;
11988                 dev->dev_addr[4] = (lo >>  8) & 0xff;
11989                 dev->dev_addr[5] = (lo >>  0) & 0xff;
11990
11991                 /* Some old bootcode may report a 0 MAC address in SRAM */
11992                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11993         }
11994         if (!addr_ok) {
11995                 /* Next, try NVRAM. */
11996                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11997                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11998                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
11999                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
12000                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
12001                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
12002                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
12003                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
12004                 }
12005                 /* Finally just fetch it out of the MAC control regs. */
12006                 else {
12007                         hi = tr32(MAC_ADDR_0_HIGH);
12008                         lo = tr32(MAC_ADDR_0_LOW);
12009
12010                         dev->dev_addr[5] = lo & 0xff;
12011                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12012                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12013                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12014                         dev->dev_addr[1] = hi & 0xff;
12015                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12016                 }
12017         }
12018
12019         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12020 #ifdef CONFIG_SPARC
12021                 if (!tg3_get_default_macaddr_sparc(tp))
12022                         return 0;
12023 #endif
12024                 return -EINVAL;
12025         }
12026         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12027         return 0;
12028 }
12029
12030 #define BOUNDARY_SINGLE_CACHELINE       1
12031 #define BOUNDARY_MULTI_CACHELINE        2
12032
12033 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12034 {
12035         int cacheline_size;
12036         u8 byte;
12037         int goal;
12038
12039         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12040         if (byte == 0)
12041                 cacheline_size = 1024;
12042         else
12043                 cacheline_size = (int) byte * 4;
12044
12045         /* On 5703 and later chips, the boundary bits have no
12046          * effect.
12047          */
12048         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12049             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12050             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12051                 goto out;
12052
12053 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12054         goal = BOUNDARY_MULTI_CACHELINE;
12055 #else
12056 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12057         goal = BOUNDARY_SINGLE_CACHELINE;
12058 #else
12059         goal = 0;
12060 #endif
12061 #endif
12062
12063         if (!goal)
12064                 goto out;
12065
12066         /* PCI controllers on most RISC systems tend to disconnect
12067          * when a device tries to burst across a cache-line boundary.
12068          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12069          *
12070          * Unfortunately, for PCI-E there are only limited
12071          * write-side controls for this, and thus for reads
12072          * we will still get the disconnects.  We'll also waste
12073          * these PCI cycles for both read and write for chips
12074          * other than 5700 and 5701 which do not implement the
12075          * boundary bits.
12076          */
12077         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12078             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12079                 switch (cacheline_size) {
12080                 case 16:
12081                 case 32:
12082                 case 64:
12083                 case 128:
12084                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12085                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12086                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12087                         } else {
12088                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12089                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12090                         }
12091                         break;
12092
12093                 case 256:
12094                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12095                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12096                         break;
12097
12098                 default:
12099                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12100                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12101                         break;
12102                 };
12103         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12104                 switch (cacheline_size) {
12105                 case 16:
12106                 case 32:
12107                 case 64:
12108                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12109                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12110                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12111                                 break;
12112                         }
12113                         /* fallthrough */
12114                 case 128:
12115                 default:
12116                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12117                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12118                         break;
12119                 };
12120         } else {
12121                 switch (cacheline_size) {
12122                 case 16:
12123                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12124                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12125                                         DMA_RWCTRL_WRITE_BNDRY_16);
12126                                 break;
12127                         }
12128                         /* fallthrough */
12129                 case 32:
12130                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12131                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12132                                         DMA_RWCTRL_WRITE_BNDRY_32);
12133                                 break;
12134                         }
12135                         /* fallthrough */
12136                 case 64:
12137                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12138                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12139                                         DMA_RWCTRL_WRITE_BNDRY_64);
12140                                 break;
12141                         }
12142                         /* fallthrough */
12143                 case 128:
12144                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12145                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12146                                         DMA_RWCTRL_WRITE_BNDRY_128);
12147                                 break;
12148                         }
12149                         /* fallthrough */
12150                 case 256:
12151                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12152                                 DMA_RWCTRL_WRITE_BNDRY_256);
12153                         break;
12154                 case 512:
12155                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12156                                 DMA_RWCTRL_WRITE_BNDRY_512);
12157                         break;
12158                 case 1024:
12159                 default:
12160                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12161                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12162                         break;
12163                 };
12164         }
12165
12166 out:
12167         return val;
12168 }
12169
12170 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12171 {
12172         struct tg3_internal_buffer_desc test_desc;
12173         u32 sram_dma_descs;
12174         int i, ret;
12175
12176         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12177
12178         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12179         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12180         tw32(RDMAC_STATUS, 0);
12181         tw32(WDMAC_STATUS, 0);
12182
12183         tw32(BUFMGR_MODE, 0);
12184         tw32(FTQ_RESET, 0);
12185
12186         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12187         test_desc.addr_lo = buf_dma & 0xffffffff;
12188         test_desc.nic_mbuf = 0x00002100;
12189         test_desc.len = size;
12190
12191         /*
12192          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12193          * the *second* time the tg3 driver was getting loaded after an
12194          * initial scan.
12195          *
12196          * Broadcom tells me:
12197          *   ...the DMA engine is connected to the GRC block and a DMA
12198          *   reset may affect the GRC block in some unpredictable way...
12199          *   The behavior of resets to individual blocks has not been tested.
12200          *
12201          * Broadcom noted the GRC reset will also reset all sub-components.
12202          */
12203         if (to_device) {
12204                 test_desc.cqid_sqid = (13 << 8) | 2;
12205
12206                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12207                 udelay(40);
12208         } else {
12209                 test_desc.cqid_sqid = (16 << 8) | 7;
12210
12211                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12212                 udelay(40);
12213         }
12214         test_desc.flags = 0x00000005;
12215
12216         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12217                 u32 val;
12218
12219                 val = *(((u32 *)&test_desc) + i);
12220                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12221                                        sram_dma_descs + (i * sizeof(u32)));
12222                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12223         }
12224         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12225
12226         if (to_device) {
12227                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12228         } else {
12229                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12230         }
12231
12232         ret = -ENODEV;
12233         for (i = 0; i < 40; i++) {
12234                 u32 val;
12235
12236                 if (to_device)
12237                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12238                 else
12239                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12240                 if ((val & 0xffff) == sram_dma_descs) {
12241                         ret = 0;
12242                         break;
12243                 }
12244
12245                 udelay(100);
12246         }
12247
12248         return ret;
12249 }
12250
12251 #define TEST_BUFFER_SIZE        0x2000
12252
12253 static int __devinit tg3_test_dma(struct tg3 *tp)
12254 {
12255         dma_addr_t buf_dma;
12256         u32 *buf, saved_dma_rwctrl;
12257         int ret;
12258
12259         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12260         if (!buf) {
12261                 ret = -ENOMEM;
12262                 goto out_nofree;
12263         }
12264
12265         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12266                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12267
12268         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12269
12270         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12271                 /* DMA read watermark not used on PCIE */
12272                 tp->dma_rwctrl |= 0x00180000;
12273         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12274                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12275                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12276                         tp->dma_rwctrl |= 0x003f0000;
12277                 else
12278                         tp->dma_rwctrl |= 0x003f000f;
12279         } else {
12280                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12281                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12282                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12283                         u32 read_water = 0x7;
12284
12285                         /* If the 5704 is behind the EPB bridge, we can
12286                          * do the less restrictive ONE_DMA workaround for
12287                          * better performance.
12288                          */
12289                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12290                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12291                                 tp->dma_rwctrl |= 0x8000;
12292                         else if (ccval == 0x6 || ccval == 0x7)
12293                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12294
12295                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12296                                 read_water = 4;
12297                         /* Set bit 23 to enable PCIX hw bug fix */
12298                         tp->dma_rwctrl |=
12299                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12300                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12301                                 (1 << 23);
12302                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12303                         /* 5780 always in PCIX mode */
12304                         tp->dma_rwctrl |= 0x00144000;
12305                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12306                         /* 5714 always in PCIX mode */
12307                         tp->dma_rwctrl |= 0x00148000;
12308                 } else {
12309                         tp->dma_rwctrl |= 0x001b000f;
12310                 }
12311         }
12312
12313         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12314             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12315                 tp->dma_rwctrl &= 0xfffffff0;
12316
12317         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12318             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12319                 /* Remove this if it causes problems for some boards. */
12320                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12321
12322                 /* On 5700/5701 chips, we need to set this bit.
12323                  * Otherwise the chip will issue cacheline transactions
12324                  * to streamable DMA memory with not all the byte
12325                  * enables turned on.  This is an error on several
12326                  * RISC PCI controllers, in particular sparc64.
12327                  *
12328                  * On 5703/5704 chips, this bit has been reassigned
12329                  * a different meaning.  In particular, it is used
12330                  * on those chips to enable a PCI-X workaround.
12331                  */
12332                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12333         }
12334
12335         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12336
12337 #if 0
12338         /* Unneeded, already done by tg3_get_invariants.  */
12339         tg3_switch_clocks(tp);
12340 #endif
12341
12342         ret = 0;
12343         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12344             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12345                 goto out;
12346
12347         /* It is best to perform DMA test with maximum write burst size
12348          * to expose the 5700/5701 write DMA bug.
12349          */
12350         saved_dma_rwctrl = tp->dma_rwctrl;
12351         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12352         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12353
12354         while (1) {
12355                 u32 *p = buf, i;
12356
12357                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12358                         p[i] = i;
12359
12360                 /* Send the buffer to the chip. */
12361                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12362                 if (ret) {
12363                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12364                         break;
12365                 }
12366
12367 #if 0
12368                 /* validate data reached card RAM correctly. */
12369                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12370                         u32 val;
12371                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
12372                         if (le32_to_cpu(val) != p[i]) {
12373                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
12374                                 /* ret = -ENODEV here? */
12375                         }
12376                         p[i] = 0;
12377                 }
12378 #endif
12379                 /* Now read it back. */
12380                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12381                 if (ret) {
12382                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12383
12384                         break;
12385                 }
12386
12387                 /* Verify it. */
12388                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12389                         if (p[i] == i)
12390                                 continue;
12391
12392                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12393                             DMA_RWCTRL_WRITE_BNDRY_16) {
12394                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12395                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12396                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12397                                 break;
12398                         } else {
12399                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12400                                 ret = -ENODEV;
12401                                 goto out;
12402                         }
12403                 }
12404
12405                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12406                         /* Success. */
12407                         ret = 0;
12408                         break;
12409                 }
12410         }
12411         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12412             DMA_RWCTRL_WRITE_BNDRY_16) {
12413                 static struct pci_device_id dma_wait_state_chipsets[] = {
12414                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12415                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12416                         { },
12417                 };
12418
12419                 /* DMA test passed without adjusting DMA boundary,
12420                  * now look for chipsets that are known to expose the
12421                  * DMA bug without failing the test.
12422                  */
12423                 if (pci_dev_present(dma_wait_state_chipsets)) {
12424                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12425                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12426                 }
12427                 else
12428                         /* Safe to use the calculated DMA boundary. */
12429                         tp->dma_rwctrl = saved_dma_rwctrl;
12430
12431                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12432         }
12433
12434 out:
12435         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12436 out_nofree:
12437         return ret;
12438 }
12439
12440 static void __devinit tg3_init_link_config(struct tg3 *tp)
12441 {
12442         tp->link_config.advertising =
12443                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12444                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12445                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12446                  ADVERTISED_Autoneg | ADVERTISED_MII);
12447         tp->link_config.speed = SPEED_INVALID;
12448         tp->link_config.duplex = DUPLEX_INVALID;
12449         tp->link_config.autoneg = AUTONEG_ENABLE;
12450         tp->link_config.active_speed = SPEED_INVALID;
12451         tp->link_config.active_duplex = DUPLEX_INVALID;
12452         tp->link_config.phy_is_low_power = 0;
12453         tp->link_config.orig_speed = SPEED_INVALID;
12454         tp->link_config.orig_duplex = DUPLEX_INVALID;
12455         tp->link_config.orig_autoneg = AUTONEG_INVALID;
12456 }
12457
12458 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12459 {
12460         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12461                 tp->bufmgr_config.mbuf_read_dma_low_water =
12462                         DEFAULT_MB_RDMA_LOW_WATER_5705;
12463                 tp->bufmgr_config.mbuf_mac_rx_low_water =
12464                         DEFAULT_MB_MACRX_LOW_WATER_5705;
12465                 tp->bufmgr_config.mbuf_high_water =
12466                         DEFAULT_MB_HIGH_WATER_5705;
12467                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12468                         tp->bufmgr_config.mbuf_mac_rx_low_water =
12469                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
12470                         tp->bufmgr_config.mbuf_high_water =
12471                                 DEFAULT_MB_HIGH_WATER_5906;
12472                 }
12473
12474                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12475                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12476                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12477                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12478                 tp->bufmgr_config.mbuf_high_water_jumbo =
12479                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12480         } else {
12481                 tp->bufmgr_config.mbuf_read_dma_low_water =
12482                         DEFAULT_MB_RDMA_LOW_WATER;
12483                 tp->bufmgr_config.mbuf_mac_rx_low_water =
12484                         DEFAULT_MB_MACRX_LOW_WATER;
12485                 tp->bufmgr_config.mbuf_high_water =
12486                         DEFAULT_MB_HIGH_WATER;
12487
12488                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12489                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12490                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12491                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12492                 tp->bufmgr_config.mbuf_high_water_jumbo =
12493                         DEFAULT_MB_HIGH_WATER_JUMBO;
12494         }
12495
12496         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12497         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12498 }
12499
12500 static char * __devinit tg3_phy_string(struct tg3 *tp)
12501 {
12502         switch (tp->phy_id & PHY_ID_MASK) {
12503         case PHY_ID_BCM5400:    return "5400";
12504         case PHY_ID_BCM5401:    return "5401";
12505         case PHY_ID_BCM5411:    return "5411";
12506         case PHY_ID_BCM5701:    return "5701";
12507         case PHY_ID_BCM5703:    return "5703";
12508         case PHY_ID_BCM5704:    return "5704";
12509         case PHY_ID_BCM5705:    return "5705";
12510         case PHY_ID_BCM5750:    return "5750";
12511         case PHY_ID_BCM5752:    return "5752";
12512         case PHY_ID_BCM5714:    return "5714";
12513         case PHY_ID_BCM5780:    return "5780";
12514         case PHY_ID_BCM5755:    return "5755";
12515         case PHY_ID_BCM5787:    return "5787";
12516         case PHY_ID_BCM5784:    return "5784";
12517         case PHY_ID_BCM5756:    return "5722/5756";
12518         case PHY_ID_BCM5906:    return "5906";
12519         case PHY_ID_BCM5761:    return "5761";
12520         case PHY_ID_BCM8002:    return "8002/serdes";
12521         case 0:                 return "serdes";
12522         default:                return "unknown";
12523         };
12524 }
12525
12526 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12527 {
12528         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12529                 strcpy(str, "PCI Express");
12530                 return str;
12531         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12532                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12533
12534                 strcpy(str, "PCIX:");
12535
12536                 if ((clock_ctrl == 7) ||
12537                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
12538                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
12539                         strcat(str, "133MHz");
12540                 else if (clock_ctrl == 0)
12541                         strcat(str, "33MHz");
12542                 else if (clock_ctrl == 2)
12543                         strcat(str, "50MHz");
12544                 else if (clock_ctrl == 4)
12545                         strcat(str, "66MHz");
12546                 else if (clock_ctrl == 6)
12547                         strcat(str, "100MHz");
12548         } else {
12549                 strcpy(str, "PCI:");
12550                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
12551                         strcat(str, "66MHz");
12552                 else
12553                         strcat(str, "33MHz");
12554         }
12555         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
12556                 strcat(str, ":32-bit");
12557         else
12558                 strcat(str, ":64-bit");
12559         return str;
12560 }
12561
12562 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
12563 {
12564         struct pci_dev *peer;
12565         unsigned int func, devnr = tp->pdev->devfn & ~7;
12566
12567         for (func = 0; func < 8; func++) {
12568                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
12569                 if (peer && peer != tp->pdev)
12570                         break;
12571                 pci_dev_put(peer);
12572         }
12573         /* 5704 can be configured in single-port mode, set peer to
12574          * tp->pdev in that case.
12575          */
12576         if (!peer) {
12577                 peer = tp->pdev;
12578                 return peer;
12579         }
12580
12581         /*
12582          * We don't need to keep the refcount elevated; there's no way
12583          * to remove one half of this device without removing the other
12584          */
12585         pci_dev_put(peer);
12586
12587         return peer;
12588 }
12589
12590 static void __devinit tg3_init_coal(struct tg3 *tp)
12591 {
12592         struct ethtool_coalesce *ec = &tp->coal;
12593
12594         memset(ec, 0, sizeof(*ec));
12595         ec->cmd = ETHTOOL_GCOALESCE;
12596         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
12597         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
12598         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
12599         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
12600         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
12601         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
12602         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
12603         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
12604         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
12605
12606         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
12607                                  HOSTCC_MODE_CLRTICK_TXBD)) {
12608                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
12609                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
12610                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
12611                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
12612         }
12613
12614         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12615                 ec->rx_coalesce_usecs_irq = 0;
12616                 ec->tx_coalesce_usecs_irq = 0;
12617                 ec->stats_block_coalesce_usecs = 0;
12618         }
12619 }
12620
12621 static int __devinit tg3_init_one(struct pci_dev *pdev,
12622                                   const struct pci_device_id *ent)
12623 {
12624         static int tg3_version_printed = 0;
12625         resource_size_t tg3reg_base;
12626         unsigned long tg3reg_len;
12627         struct net_device *dev;
12628         struct tg3 *tp;
12629         int err, pm_cap;
12630         char str[40];
12631         u64 dma_mask, persist_dma_mask;
12632         DECLARE_MAC_BUF(mac);
12633
12634         if (tg3_version_printed++ == 0)
12635                 printk(KERN_INFO "%s", version);
12636
12637         err = pci_enable_device(pdev);
12638         if (err) {
12639                 printk(KERN_ERR PFX "Cannot enable PCI device, "
12640                        "aborting.\n");
12641                 return err;
12642         }
12643
12644         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12645                 printk(KERN_ERR PFX "Cannot find proper PCI device "
12646                        "base address, aborting.\n");
12647                 err = -ENODEV;
12648                 goto err_out_disable_pdev;
12649         }
12650
12651         err = pci_request_regions(pdev, DRV_MODULE_NAME);
12652         if (err) {
12653                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
12654                        "aborting.\n");
12655                 goto err_out_disable_pdev;
12656         }
12657
12658         pci_set_master(pdev);
12659
12660         /* Find power-management capability. */
12661         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
12662         if (pm_cap == 0) {
12663                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
12664                        "aborting.\n");
12665                 err = -EIO;
12666                 goto err_out_free_res;
12667         }
12668
12669         tg3reg_base = pci_resource_start(pdev, 0);
12670         tg3reg_len = pci_resource_len(pdev, 0);
12671
12672         dev = alloc_etherdev(sizeof(*tp));
12673         if (!dev) {
12674                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
12675                 err = -ENOMEM;
12676                 goto err_out_free_res;
12677         }
12678
12679         SET_NETDEV_DEV(dev, &pdev->dev);
12680
12681 #if TG3_VLAN_TAG_USED
12682         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
12683         dev->vlan_rx_register = tg3_vlan_rx_register;
12684 #endif
12685
12686         tp = netdev_priv(dev);
12687         tp->pdev = pdev;
12688         tp->dev = dev;
12689         tp->pm_cap = pm_cap;
12690         tp->mac_mode = TG3_DEF_MAC_MODE;
12691         tp->rx_mode = TG3_DEF_RX_MODE;
12692         tp->tx_mode = TG3_DEF_TX_MODE;
12693         tp->mi_mode = MAC_MI_MODE_BASE;
12694         if (tg3_debug > 0)
12695                 tp->msg_enable = tg3_debug;
12696         else
12697                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
12698
12699         /* The word/byte swap controls here control register access byte
12700          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
12701          * setting below.
12702          */
12703         tp->misc_host_ctrl =
12704                 MISC_HOST_CTRL_MASK_PCI_INT |
12705                 MISC_HOST_CTRL_WORD_SWAP |
12706                 MISC_HOST_CTRL_INDIR_ACCESS |
12707                 MISC_HOST_CTRL_PCISTATE_RW;
12708
12709         /* The NONFRM (non-frame) byte/word swap controls take effect
12710          * on descriptor entries, anything which isn't packet data.
12711          *
12712          * The StrongARM chips on the board (one for tx, one for rx)
12713          * are running in big-endian mode.
12714          */
12715         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
12716                         GRC_MODE_WSWAP_NONFRM_DATA);
12717 #ifdef __BIG_ENDIAN
12718         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
12719 #endif
12720         spin_lock_init(&tp->lock);
12721         spin_lock_init(&tp->indirect_lock);
12722         INIT_WORK(&tp->reset_task, tg3_reset_task);
12723
12724         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
12725         if (!tp->regs) {
12726                 printk(KERN_ERR PFX "Cannot map device registers, "
12727                        "aborting.\n");
12728                 err = -ENOMEM;
12729                 goto err_out_free_dev;
12730         }
12731
12732         tg3_init_link_config(tp);
12733
12734         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
12735         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
12736         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
12737
12738         dev->open = tg3_open;
12739         dev->stop = tg3_close;
12740         dev->get_stats = tg3_get_stats;
12741         dev->set_multicast_list = tg3_set_rx_mode;
12742         dev->set_mac_address = tg3_set_mac_addr;
12743         dev->do_ioctl = tg3_ioctl;
12744         dev->tx_timeout = tg3_tx_timeout;
12745         netif_napi_add(dev, &tp->napi, tg3_poll, 64);
12746         dev->ethtool_ops = &tg3_ethtool_ops;
12747         dev->watchdog_timeo = TG3_TX_TIMEOUT;
12748         dev->change_mtu = tg3_change_mtu;
12749         dev->irq = pdev->irq;
12750 #ifdef CONFIG_NET_POLL_CONTROLLER
12751         dev->poll_controller = tg3_poll_controller;
12752 #endif
12753
12754         err = tg3_get_invariants(tp);
12755         if (err) {
12756                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
12757                        "aborting.\n");
12758                 goto err_out_iounmap;
12759         }
12760
12761         /* The EPB bridge inside 5714, 5715, and 5780 and any
12762          * device behind the EPB cannot support DMA addresses > 40-bit.
12763          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
12764          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
12765          * do DMA address check in tg3_start_xmit().
12766          */
12767         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
12768                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
12769         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
12770                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
12771 #ifdef CONFIG_HIGHMEM
12772                 dma_mask = DMA_64BIT_MASK;
12773 #endif
12774         } else
12775                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
12776
12777         /* Configure DMA attributes. */
12778         if (dma_mask > DMA_32BIT_MASK) {
12779                 err = pci_set_dma_mask(pdev, dma_mask);
12780                 if (!err) {
12781                         dev->features |= NETIF_F_HIGHDMA;
12782                         err = pci_set_consistent_dma_mask(pdev,
12783                                                           persist_dma_mask);
12784                         if (err < 0) {
12785                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
12786                                        "DMA for consistent allocations\n");
12787                                 goto err_out_iounmap;
12788                         }
12789                 }
12790         }
12791         if (err || dma_mask == DMA_32BIT_MASK) {
12792                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
12793                 if (err) {
12794                         printk(KERN_ERR PFX "No usable DMA configuration, "
12795                                "aborting.\n");
12796                         goto err_out_iounmap;
12797                 }
12798         }
12799
12800         tg3_init_bufmgr_config(tp);
12801
12802         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
12803                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
12804         }
12805         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12806             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12807             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
12808             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12809             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
12810                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
12811         } else {
12812                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
12813         }
12814
12815         /* TSO is on by default on chips that support hardware TSO.
12816          * Firmware TSO on older chips gives lower performance, so it
12817          * is off by default, but can be enabled using ethtool.
12818          */
12819         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
12820                 dev->features |= NETIF_F_TSO;
12821                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
12822                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
12823                         dev->features |= NETIF_F_TSO6;
12824                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12825                         dev->features |= NETIF_F_TSO_ECN;
12826         }
12827
12828
12829         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
12830             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
12831             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
12832                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
12833                 tp->rx_pending = 63;
12834         }
12835
12836         err = tg3_get_device_address(tp);
12837         if (err) {
12838                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
12839                        "aborting.\n");
12840                 goto err_out_iounmap;
12841         }
12842
12843         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12844                 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12845                         printk(KERN_ERR PFX "Cannot find proper PCI device "
12846                                "base address for APE, aborting.\n");
12847                         err = -ENODEV;
12848                         goto err_out_iounmap;
12849                 }
12850
12851                 tg3reg_base = pci_resource_start(pdev, 2);
12852                 tg3reg_len = pci_resource_len(pdev, 2);
12853
12854                 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
12855                 if (!tp->aperegs) {
12856                         printk(KERN_ERR PFX "Cannot map APE registers, "
12857                                "aborting.\n");
12858                         err = -ENOMEM;
12859                         goto err_out_iounmap;
12860                 }
12861
12862                 tg3_ape_lock_init(tp);
12863         }
12864
12865         /*
12866          * Reset chip in case UNDI or EFI driver did not shutdown
12867          * DMA self test will enable WDMAC and we'll see (spurious)
12868          * pending DMA on the PCI bus at that point.
12869          */
12870         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
12871             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
12872                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
12873                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12874         }
12875
12876         err = tg3_test_dma(tp);
12877         if (err) {
12878                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
12879                 goto err_out_apeunmap;
12880         }
12881
12882         /* Tigon3 can do ipv4 only... and some chips have buggy
12883          * checksumming.
12884          */
12885         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
12886                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12887                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12888                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12889                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12890                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12891                         dev->features |= NETIF_F_IPV6_CSUM;
12892
12893                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12894         } else
12895                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
12896
12897         /* flow control autonegotiation is default behavior */
12898         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12899         tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
12900
12901         tg3_init_coal(tp);
12902
12903         pci_set_drvdata(pdev, dev);
12904
12905         err = register_netdev(dev);
12906         if (err) {
12907                 printk(KERN_ERR PFX "Cannot register net device, "
12908                        "aborting.\n");
12909                 goto err_out_apeunmap;
12910         }
12911
12912         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] "
12913                "(%s) %s Ethernet %s\n",
12914                dev->name,
12915                tp->board_part_number,
12916                tp->pci_chip_rev_id,
12917                tg3_phy_string(tp),
12918                tg3_bus_string(tp, str),
12919                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12920                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
12921                  "10/100/1000Base-T")),
12922                print_mac(mac, dev->dev_addr));
12923
12924         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
12925                "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
12926                dev->name,
12927                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
12928                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
12929                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
12930                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
12931                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
12932                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
12933         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
12934                dev->name, tp->dma_rwctrl,
12935                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
12936                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
12937
12938         return 0;
12939
12940 err_out_apeunmap:
12941         if (tp->aperegs) {
12942                 iounmap(tp->aperegs);
12943                 tp->aperegs = NULL;
12944         }
12945
12946 err_out_iounmap:
12947         if (tp->regs) {
12948                 iounmap(tp->regs);
12949                 tp->regs = NULL;
12950         }
12951
12952 err_out_free_dev:
12953         free_netdev(dev);
12954
12955 err_out_free_res:
12956         pci_release_regions(pdev);
12957
12958 err_out_disable_pdev:
12959         pci_disable_device(pdev);
12960         pci_set_drvdata(pdev, NULL);
12961         return err;
12962 }
12963
12964 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12965 {
12966         struct net_device *dev = pci_get_drvdata(pdev);
12967
12968         if (dev) {
12969                 struct tg3 *tp = netdev_priv(dev);
12970
12971                 flush_scheduled_work();
12972                 unregister_netdev(dev);
12973                 if (tp->aperegs) {
12974                         iounmap(tp->aperegs);
12975                         tp->aperegs = NULL;
12976                 }
12977                 if (tp->regs) {
12978                         iounmap(tp->regs);
12979                         tp->regs = NULL;
12980                 }
12981                 free_netdev(dev);
12982                 pci_release_regions(pdev);
12983                 pci_disable_device(pdev);
12984                 pci_set_drvdata(pdev, NULL);
12985         }
12986 }
12987
12988 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12989 {
12990         struct net_device *dev = pci_get_drvdata(pdev);
12991         struct tg3 *tp = netdev_priv(dev);
12992         int err;
12993
12994         /* PCI register 4 needs to be saved whether netif_running() or not.
12995          * MSI address and data need to be saved if using MSI and
12996          * netif_running().
12997          */
12998         pci_save_state(pdev);
12999
13000         if (!netif_running(dev))
13001                 return 0;
13002
13003         flush_scheduled_work();
13004         tg3_netif_stop(tp);
13005
13006         del_timer_sync(&tp->timer);
13007
13008         tg3_full_lock(tp, 1);
13009         tg3_disable_ints(tp);
13010         tg3_full_unlock(tp);
13011
13012         netif_device_detach(dev);
13013
13014         tg3_full_lock(tp, 0);
13015         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13016         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13017         tg3_full_unlock(tp);
13018
13019         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
13020         if (err) {
13021                 tg3_full_lock(tp, 0);
13022
13023                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13024                 if (tg3_restart_hw(tp, 1))
13025                         goto out;
13026
13027                 tp->timer.expires = jiffies + tp->timer_offset;
13028                 add_timer(&tp->timer);
13029
13030                 netif_device_attach(dev);
13031                 tg3_netif_start(tp);
13032
13033 out:
13034                 tg3_full_unlock(tp);
13035         }
13036
13037         return err;
13038 }
13039
13040 static int tg3_resume(struct pci_dev *pdev)
13041 {
13042         struct net_device *dev = pci_get_drvdata(pdev);
13043         struct tg3 *tp = netdev_priv(dev);
13044         int err;
13045
13046         pci_restore_state(tp->pdev);
13047
13048         if (!netif_running(dev))
13049                 return 0;
13050
13051         err = tg3_set_power_state(tp, PCI_D0);
13052         if (err)
13053                 return err;
13054
13055         netif_device_attach(dev);
13056
13057         tg3_full_lock(tp, 0);
13058
13059         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13060         err = tg3_restart_hw(tp, 1);
13061         if (err)
13062                 goto out;
13063
13064         tp->timer.expires = jiffies + tp->timer_offset;
13065         add_timer(&tp->timer);
13066
13067         tg3_netif_start(tp);
13068
13069 out:
13070         tg3_full_unlock(tp);
13071
13072         return err;
13073 }
13074
13075 static struct pci_driver tg3_driver = {
13076         .name           = DRV_MODULE_NAME,
13077         .id_table       = tg3_pci_tbl,
13078         .probe          = tg3_init_one,
13079         .remove         = __devexit_p(tg3_remove_one),
13080         .suspend        = tg3_suspend,
13081         .resume         = tg3_resume
13082 };
13083
13084 static int __init tg3_init(void)
13085 {
13086         return pci_register_driver(&tg3_driver);
13087 }
13088
13089 static void __exit tg3_cleanup(void)
13090 {
13091         pci_unregister_driver(&tg3_driver);
13092 }
13093
13094 module_init(tg3_init);
13095 module_exit(tg3_cleanup);