git.oblomov.eu Git - linux-2.6/blob - drivers/ide/pci/serverworks.c

   1 /*
   2  * linux/drivers/ide/pci/serverworks.c          Version 0.8      25 Ebr 2003
   3  *
   4  * Copyright (C) 1998-2000 Michel Aubry
   5  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
   6  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   7  * Portions copyright (c) 2001 Sun Microsystems
   8  *
   9  *
  10  * RCC/ServerWorks IDE driver for Linux
  11  *
  12  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  13  *         supports UDMA mode 2 (33 MB/s)
  14  *
  15  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  16  *         all revisions support UDMA mode 4 (66 MB/s)
  17  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  18  *
  19  *         *** The CSB5 does not provide ANY register ***
  20  *         *** to detect 80-conductor cable presence. ***
  21  *
  22  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  23  *
  24  *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
  25  *   controller same as the CSB6. Single channel ATA100 only.
  26  *
  27  * Documentation:
  28  *      Available under NDA only. Errata info very hard to get.
  29  *
  30  */
  31
  32 #include <linux/types.h>
  33 #include <linux/module.h>
  34 #include <linux/kernel.h>
  35 #include <linux/ioport.h>
  36 #include <linux/pci.h>
  37 #include <linux/hdreg.h>
  38 #include <linux/ide.h>
  39 #include <linux/init.h>
  40 #include <linux/delay.h>
  41
  42 #include <asm/io.h>
  43
  44 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  45 #define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  46
  47 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  48  * can overrun their FIFOs when used with the CSB5 */
  49 static const char *svwks_bad_ata100[] = {
  50         "ST320011A",
  51         "ST340016A",
  52         "ST360021A",
  53         "ST380021A",
  54         NULL
  55 };
  56
  57 static u8 svwks_revision = 0;
  58 static struct pci_dev *isa_dev;
  59
  60 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  61 {
  62         while (*list)
  63                 if (!strcmp(*list++, drive->id->model))
  64                         return 1;
  65         return 0;
  66 }
  67
  68 static u8 svwks_udma_filter(ide_drive_t *drive)
  69 {
  70         struct pci_dev *dev     = HWIF(drive)->pci_dev;
  71         u8 mask = 0;
  72
  73         if (!svwks_revision)
  74                 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
  75
  76         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
  77                 return 0x1f;
  78         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  79                 u32 reg = 0;
  80                 if (isa_dev)
  81                         pci_read_config_dword(isa_dev, 0x64, &reg);
  82
  83                 /*
  84                  *      Don't enable UDMA on disk devices for the moment
  85                  */
  86                 if(drive->media == ide_disk)
  87                         return 0;
  88                 /* Check the OSB4 DMA33 enable bit */
  89                 return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
  90         } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
  91                 return 0x07;
  92         } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
  93                 u8 btr = 0, mode;
  94                 pci_read_config_byte(dev, 0x5A, &btr);
  95                 mode = btr & 0x3;
  96
  97                 /* If someone decides to do UDMA133 on CSB5 the same
  98                    issue will bite so be inclusive */
  99                 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
 100                         mode = 2;
 101
 102                 switch(mode) {
 103                 case 2:  mask = 0x1f; break;
 104                 case 1:  mask = 0x07; break;
 105                 default: mask = 0x00; break;
 106                 }
 107         }
 108         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 109              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 110             (!(PCI_FUNC(dev->devfn) & 1)))
 111                 mask = 0x1f;
 112
 113         return mask;
 114 }
 115
 116 static u8 svwks_csb_check (struct pci_dev *dev)
 117 {
 118         switch (dev->device) {
 119                 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 120                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 121                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 122                 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 123                         return 1;
 124                 default:
 125                         break;
 126         }
 127         return 0;
 128 }
 129 static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 130 {
 131         static const u8 udma_modes[]            = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
 132         static const u8 dma_modes[]             = { 0x77, 0x21, 0x20 };
 133         static const u8 pio_modes[]             = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 134         static const u8 drive_pci[]             = { 0x41, 0x40, 0x43, 0x42 };
 135         static const u8 drive_pci2[]            = { 0x45, 0x44, 0x47, 0x46 };
 136
 137         ide_hwif_t *hwif        = HWIF(drive);
 138         struct pci_dev *dev     = hwif->pci_dev;
 139         u8 speed;
 140         u8 pio                  = ide_get_best_pio_mode(drive, 255, 5, NULL);
 141         u8 unit                 = (drive->select.b.unit & 0x01);
 142         u8 csb5                 = svwks_csb_check(dev);
 143         u8 ultra_enable         = 0, ultra_timing = 0;
 144         u8 dma_timing           = 0, pio_timing = 0;
 145         u16 csb5_pio            = 0;
 146
 147         if (xferspeed == 255)   /* PIO auto-tuning */
 148                 speed = XFER_PIO_0 + pio;
 149         else
 150                 speed = ide_rate_filter(drive, xferspeed);
 151
 152         /* If we are about to put a disk into UDMA mode we screwed up.
 153            Our code assumes we never _ever_ do this on an OSB4 */
 154
 155         if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
 156                 drive->media == ide_disk && speed >= XFER_UDMA_0)
 157                         BUG();
 158
 159         pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
 160         pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
 161         pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
 162         pci_read_config_word(dev, 0x4A, &csb5_pio);
 163         pci_read_config_byte(dev, 0x54, &ultra_enable);
 164
 165         /* Per Specified Design by OEM, and ASIC Architect */
 166         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 167             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 168                 if (!drive->init_speed) {
 169                         u8 dma_stat = inb(hwif->dma_status);
 170
 171 dma_pio:
 172                         if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
 173                             ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
 174                                 drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
 175                                 return 0;
 176                         } else if ((dma_timing) &&
 177                                    ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
 178                                 u8 dmaspeed = dma_timing;
 179
 180                                 dma_timing &= ~0xFF;
 181                                 if ((dmaspeed & 0x20) == 0x20)
 182                                         dmaspeed = XFER_MW_DMA_2;
 183                                 else if ((dmaspeed & 0x21) == 0x21)
 184                                         dmaspeed = XFER_MW_DMA_1;
 185                                 else if ((dmaspeed & 0x77) == 0x77)
 186                                         dmaspeed = XFER_MW_DMA_0;
 187                                 else
 188                                         goto dma_pio;
 189                                 drive->current_speed = drive->init_speed = dmaspeed;
 190                                 return 0;
 191                         } else if (pio_timing) {
 192                                 u8 piospeed = pio_timing;
 193
 194                                 pio_timing &= ~0xFF;
 195                                 if ((piospeed & 0x20) == 0x20)
 196                                         piospeed = XFER_PIO_4;
 197                                 else if ((piospeed & 0x22) == 0x22)
 198                                         piospeed = XFER_PIO_3;
 199                                 else if ((piospeed & 0x34) == 0x34)
 200                                         piospeed = XFER_PIO_2;
 201                                 else if ((piospeed & 0x47) == 0x47)
 202                                         piospeed = XFER_PIO_1;
 203                                 else if ((piospeed & 0x5d) == 0x5d)
 204                                         piospeed = XFER_PIO_0;
 205                                 else
 206                                         goto oem_setup_failed;
 207                                 drive->current_speed = drive->init_speed = piospeed;
 208                                 return 0;
 209                         }
 210                 }
 211         }
 212
 213 oem_setup_failed:
 214
 215         pio_timing      &= ~0xFF;
 216         dma_timing      &= ~0xFF;
 217         ultra_timing    &= ~(0x0F << (4*unit));
 218         ultra_enable    &= ~(0x01 << drive->dn);
 219         csb5_pio        &= ~(0x0F << (4*drive->dn));
 220
 221         switch(speed) {
 222                 case XFER_PIO_4:
 223                 case XFER_PIO_3:
 224                 case XFER_PIO_2:
 225                 case XFER_PIO_1:
 226                 case XFER_PIO_0:
 227                         pio_timing |= pio_modes[speed - XFER_PIO_0];
 228                         csb5_pio   |= ((speed - XFER_PIO_0) << (4*drive->dn));
 229                         break;
 230
 231                 case XFER_MW_DMA_2:
 232                 case XFER_MW_DMA_1:
 233                 case XFER_MW_DMA_0:
 234                         pio_timing |= pio_modes[pio];
 235                         csb5_pio   |= (pio << (4*drive->dn));
 236                         dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
 237                         break;
 238
 239                 case XFER_UDMA_5:
 240                 case XFER_UDMA_4:
 241                 case XFER_UDMA_3:
 242                 case XFER_UDMA_2:
 243                 case XFER_UDMA_1:
 244                 case XFER_UDMA_0:
 245                         pio_timing   |= pio_modes[pio];
 246                         csb5_pio     |= (pio << (4*drive->dn));
 247                         dma_timing   |= dma_modes[2];
 248                         ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
 249                         ultra_enable |= (0x01 << drive->dn);
 250                 default:
 251                         break;
 252         }
 253
 254         pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
 255         if (csb5)
 256                 pci_write_config_word(dev, 0x4A, csb5_pio);
 257
 258         pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
 259         pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
 260         pci_write_config_byte(dev, 0x54, ultra_enable);
 261
 262         return (ide_config_drive_speed(drive, speed));
 263 }
 264
 265 static void config_chipset_for_pio (ide_drive_t *drive)
 266 {
 267         u16 eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
 268         u16 xfer_pio = drive->id->eide_pio_modes;
 269         u8 timing, speed, pio;
 270
 271         pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
 272
 273         if (xfer_pio > 4)
 274                 xfer_pio = 0;
 275
 276         if (drive->id->eide_pio_iordy > 0)
 277                 for (xfer_pio = 5;
 278                         xfer_pio>0 &&
 279                         drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
 280                         xfer_pio--);
 281         else
 282                 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
 283                            (drive->id->eide_pio_modes & 2) ? 0x04 :
 284                            (drive->id->eide_pio_modes & 1) ? 0x03 :
 285                            (drive->id->tPIO & 2) ? 0x02 :
 286                            (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
 287
 288         timing = (xfer_pio >= pio) ? xfer_pio : pio;
 289
 290         switch(timing) {
 291                 case 4: speed = XFER_PIO_4;break;
 292                 case 3: speed = XFER_PIO_3;break;
 293                 case 2: speed = XFER_PIO_2;break;
 294                 case 1: speed = XFER_PIO_1;break;
 295                 default:
 296                         speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
 297                         break;
 298         }
 299         (void) svwks_tune_chipset(drive, speed);
 300         drive->current_speed = speed;
 301 }
 302
 303 static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
 304 {
 305         if(pio == 255)
 306                 (void) svwks_tune_chipset(drive, 255);
 307         else
 308                 (void) svwks_tune_chipset(drive, (XFER_PIO_0 + pio));
 309 }
 310
 311 static int config_chipset_for_dma (ide_drive_t *drive)
 312 {
 313         u8 speed = ide_max_dma_mode(drive);
 314
 315         if (!(speed))
 316                 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
 317
 318         (void) svwks_tune_chipset(drive, speed);
 319         return ide_dma_enable(drive);
 320 }
 321
 322 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
 323 {
 324         drive->init_speed = 0;
 325
 326         if (ide_use_dma(drive) && config_chipset_for_dma(drive))
 327                 return 0;
 328
 329         if (ide_use_fast_pio(drive))
 330                 config_chipset_for_pio(drive);
 331
 332         return -1;
 333 }
 334
 335 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
 336 {
 337         unsigned int reg;
 338         u8 btr;
 339
 340         /* save revision id to determine DMA capability */
 341         pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
 342
 343         /* force Master Latency Timer value to 64 PCICLKs */
 344         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
 345
 346         /* OSB4 : South Bridge and IDE */
 347         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 348                 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 349                           PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 350                 if (isa_dev) {
 351                         pci_read_config_dword(isa_dev, 0x64, &reg);
 352                         reg &= ~0x00002000; /* disable 600ns interrupt mask */
 353                         if(!(reg & 0x00004000))
 354                                 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
 355                         reg |=  0x00004000; /* enable UDMA/33 support */
 356                         pci_write_config_dword(isa_dev, 0x64, reg);
 357                 }
 358         }
 359
 360         /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 361         else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 362                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 363                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 364
 365                 /* Third Channel Test */
 366                 if (!(PCI_FUNC(dev->devfn) & 1)) {
 367                         struct pci_dev * findev = NULL;
 368                         u32 reg4c = 0;
 369                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 370                                 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 371                         if (findev) {
 372                                 pci_read_config_dword(findev, 0x4C, &reg4c);
 373                                 reg4c &= ~0x000007FF;
 374                                 reg4c |=  0x00000040;
 375                                 reg4c |=  0x00000020;
 376                                 pci_write_config_dword(findev, 0x4C, reg4c);
 377                                 pci_dev_put(findev);
 378                         }
 379                         outb_p(0x06, 0x0c00);
 380                         dev->irq = inb_p(0x0c01);
 381                 } else {
 382                         struct pci_dev * findev = NULL;
 383                         u8 reg41 = 0;
 384
 385                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 386                                         PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 387                         if (findev) {
 388                                 pci_read_config_byte(findev, 0x41, &reg41);
 389                                 reg41 &= ~0x40;
 390                                 pci_write_config_byte(findev, 0x41, reg41);
 391                                 pci_dev_put(findev);
 392                         }
 393                         /*
 394                          * This is a device pin issue on CSB6.
 395                          * Since there will be a future raid mode,
 396                          * early versions of the chipset require the
 397                          * interrupt pin to be set, and it is a compatibility
 398                          * mode issue.
 399                          */
 400                         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 401                                 dev->irq = 0;
 402                 }
 403 //              pci_read_config_dword(dev, 0x40, &pioreg)
 404 //              pci_write_config_dword(dev, 0x40, 0x99999999);
 405 //              pci_read_config_dword(dev, 0x44, &dmareg);
 406 //              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
 407                 /* setup the UDMA Control register
 408                  *
 409                  * 1. clear bit 6 to enable DMA
 410                  * 2. enable DMA modes with bits 0-1
 411                  *      00 : legacy
 412                  *      01 : udma2
 413                  *      10 : udma2/udma4
 414                  *      11 : udma2/udma4/udma5
 415                  */
 416                 pci_read_config_byte(dev, 0x5A, &btr);
 417                 btr &= ~0x40;
 418                 if (!(PCI_FUNC(dev->devfn) & 1))
 419                         btr |= 0x2;
 420                 else
 421                         btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 422                 pci_write_config_byte(dev, 0x5A, btr);
 423         }
 424         /* Setup HT1000 SouthBridge Controller - Single Channel Only */
 425         else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
 426                 pci_read_config_byte(dev, 0x5A, &btr);
 427                 btr &= ~0x40;
 428                 btr |= 0x3;
 429                 pci_write_config_byte(dev, 0x5A, btr);
 430         }
 431
 432         return dev->irq;
 433 }
 434
 435 static unsigned int __devinit ata66_svwks_svwks (ide_hwif_t *hwif)
 436 {
 437         return 1;
 438 }
 439
 440 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 441  * of the subsystem device ID indicate presence of an 80-pin cable.
 442  * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 443  * Bit 15 set   = secondary IDE channel has 80-pin cable.
 444  * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 445  * Bit 14 set   = primary IDE channel has 80-pin cable.
 446  */
 447 static unsigned int __devinit ata66_svwks_dell (ide_hwif_t *hwif)
 448 {
 449         struct pci_dev *dev = hwif->pci_dev;
 450         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
 451             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 452             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
 453              dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
 454                 return ((1 << (hwif->channel + 14)) &
 455                         dev->subsystem_device) ? 1 : 0;
 456         return 0;
 457 }
 458
 459 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
 460  * detect issue by attaching the drives directly to the board.
 461  * This check follows the Dell precedent (how scary is that?!)
 462  *
 463  * WARNING: this only works on Alpine hardware!
 464  */
 465 static unsigned int __devinit ata66_svwks_cobalt (ide_hwif_t *hwif)
 466 {
 467         struct pci_dev *dev = hwif->pci_dev;
 468         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
 469             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 470             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
 471                 return ((1 << (hwif->channel + 14)) &
 472                         dev->subsystem_device) ? 1 : 0;
 473         return 0;
 474 }
 475
 476 static unsigned int __devinit ata66_svwks (ide_hwif_t *hwif)
 477 {
 478         struct pci_dev *dev = hwif->pci_dev;
 479
 480         /* Server Works */
 481         if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
 482                 return ata66_svwks_svwks (hwif);
 483
 484         /* Dell PowerEdge */
 485         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
 486                 return ata66_svwks_dell (hwif);
 487
 488         /* Cobalt Alpine */
 489         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
 490                 return ata66_svwks_cobalt (hwif);
 491
 492         /* Per Specified Design by OEM, and ASIC Architect */
 493         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 494             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
 495                 return 1;
 496
 497         return 0;
 498 }
 499
 500 static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
 501 {
 502         u8 dma_stat = 0;
 503
 504         if (!hwif->irq)
 505                 hwif->irq = hwif->channel ? 15 : 14;
 506
 507         hwif->tuneproc = &svwks_tune_drive;
 508         hwif->speedproc = &svwks_tune_chipset;
 509         hwif->udma_filter = &svwks_udma_filter;
 510
 511         hwif->atapi_dma = 1;
 512
 513         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
 514                 hwif->ultra_mask = 0x3f;
 515
 516         hwif->mwdma_mask = 0x07;
 517
 518         hwif->autodma = 0;
 519
 520         if (!hwif->dma_base) {
 521                 hwif->drives[0].autotune = 1;
 522                 hwif->drives[1].autotune = 1;
 523                 return;
 524         }
 525
 526         hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
 527         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 528                 if (!hwif->udma_four)
 529                         hwif->udma_four = ata66_svwks(hwif);
 530         }
 531         if (!noautodma)
 532                 hwif->autodma = 1;
 533
 534         dma_stat = inb(hwif->dma_status);
 535         hwif->drives[0].autodma = (dma_stat & 0x20);
 536         hwif->drives[1].autodma = (dma_stat & 0x40);
 537         hwif->drives[0].autotune = (!(dma_stat & 0x20));
 538         hwif->drives[1].autotune = (!(dma_stat & 0x40));
 539 }
 540
 541 static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
 542 {
 543         return ide_setup_pci_device(dev, d);
 544 }
 545
 546 static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
 547 {
 548         if (!(PCI_FUNC(dev->devfn) & 1)) {
 549                 d->bootable = NEVER_BOARD;
 550                 if (dev->resource[0].start == 0x01f1)
 551                         d->bootable = ON_BOARD;
 552         }
 553
 554         d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
 555                         dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
 556                        (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
 557
 558         return ide_setup_pci_device(dev, d);
 559 }
 560
 561 static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
 562         {       /* 0 */
 563                 .name           = "SvrWks OSB4",
 564                 .init_setup     = init_setup_svwks,
 565                 .init_chipset   = init_chipset_svwks,
 566                 .init_hwif      = init_hwif_svwks,
 567                 .channels       = 2,
 568                 .autodma        = AUTODMA,
 569                 .bootable       = ON_BOARD,
 570         },{     /* 1 */
 571                 .name           = "SvrWks CSB5",
 572                 .init_setup     = init_setup_svwks,
 573                 .init_chipset   = init_chipset_svwks,
 574                 .init_hwif      = init_hwif_svwks,
 575                 .channels       = 2,
 576                 .autodma        = AUTODMA,
 577                 .bootable       = ON_BOARD,
 578         },{     /* 2 */
 579                 .name           = "SvrWks CSB6",
 580                 .init_setup     = init_setup_csb6,
 581                 .init_chipset   = init_chipset_svwks,
 582                 .init_hwif      = init_hwif_svwks,
 583                 .channels       = 2,
 584                 .autodma        = AUTODMA,
 585                 .bootable       = ON_BOARD,
 586         },{     /* 3 */
 587                 .name           = "SvrWks CSB6",
 588                 .init_setup     = init_setup_csb6,
 589                 .init_chipset   = init_chipset_svwks,
 590                 .init_hwif      = init_hwif_svwks,
 591                 .channels       = 1,    /* 2 */
 592                 .autodma        = AUTODMA,
 593                 .bootable       = ON_BOARD,
 594         },{     /* 4 */
 595                 .name           = "SvrWks HT1000",
 596                 .init_setup     = init_setup_svwks,
 597                 .init_chipset   = init_chipset_svwks,
 598                 .init_hwif      = init_hwif_svwks,
 599                 .channels       = 1,    /* 2 */
 600                 .autodma        = AUTODMA,
 601                 .bootable       = ON_BOARD,
 602         }
 603 };
 604
 605 /**
 606  *      svwks_init_one  -       called when a OSB/CSB is found
 607  *      @dev: the svwks device
 608  *      @id: the matching pci id
 609  *
 610  *      Called when the PCI registration layer (or the IDE initialization)
 611  *      finds a device matching our IDE device tables.
 612  */
 613
 614 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 615 {
 616         ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
 617
 618         return d->init_setup(dev, d);
 619 }
 620
 621 static struct pci_device_id svwks_pci_tbl[] = {
 622         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 623         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 624         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 625         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 626         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 627         { 0, },
 628 };
 629 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
 630
 631 static struct pci_driver driver = {
 632         .name           = "Serverworks_IDE",
 633         .id_table       = svwks_pci_tbl,
 634         .probe          = svwks_init_one,
 635 };
 636
 637 static int __init svwks_ide_init(void)
 638 {
 639         return ide_pci_register_driver(&driver);
 640 }
 641
 642 module_init(svwks_ide_init);
 643
 644 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
 645 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
 646 MODULE_LICENSE("GPL");