git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/mthca/mthca_cq.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006 Cisco Systems, Inc. All rights reserved.
   5  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  *
  36  * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
  37  */
  38
  39 #include <linux/hardirq.h>
  40 #include <linux/sched.h>
  41
  42 #include <asm/io.h>
  43
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49
  50 enum {
  51         MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
  52 };
  53
  54 enum {
  55         MTHCA_CQ_ENTRY_SIZE = 0x20
  56 };
  57
  58 enum {
  59         MTHCA_ATOMIC_BYTE_LEN = 8
  60 };
  61
  62 /*
  63  * Must be packed because start is 64 bits but only aligned to 32 bits.
  64  */
  65 struct mthca_cq_context {
  66         __be32 flags;
  67         __be64 start;
  68         __be32 logsize_usrpage;
  69         __be32 error_eqn;       /* Tavor only */
  70         __be32 comp_eqn;
  71         __be32 pd;
  72         __be32 lkey;
  73         __be32 last_notified_index;
  74         __be32 solicit_producer_index;
  75         __be32 consumer_index;
  76         __be32 producer_index;
  77         __be32 cqn;
  78         __be32 ci_db;           /* Arbel only */
  79         __be32 state_db;        /* Arbel only */
  80         u32    reserved;
  81 } __attribute__((packed));
  82
  83 #define MTHCA_CQ_STATUS_OK          ( 0 << 28)
  84 #define MTHCA_CQ_STATUS_OVERFLOW    ( 9 << 28)
  85 #define MTHCA_CQ_STATUS_WRITE_FAIL  (10 << 28)
  86 #define MTHCA_CQ_FLAG_TR            ( 1 << 18)
  87 #define MTHCA_CQ_FLAG_OI            ( 1 << 17)
  88 #define MTHCA_CQ_STATE_DISARMED     ( 0 <<  8)
  89 #define MTHCA_CQ_STATE_ARMED        ( 1 <<  8)
  90 #define MTHCA_CQ_STATE_ARMED_SOL    ( 4 <<  8)
  91 #define MTHCA_EQ_STATE_FIRED        (10 <<  8)
  92
  93 enum {
  94         MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
  95 };
  96
  97 enum {
  98         SYNDROME_LOCAL_LENGTH_ERR        = 0x01,
  99         SYNDROME_LOCAL_QP_OP_ERR         = 0x02,
 100         SYNDROME_LOCAL_EEC_OP_ERR        = 0x03,
 101         SYNDROME_LOCAL_PROT_ERR          = 0x04,
 102         SYNDROME_WR_FLUSH_ERR            = 0x05,
 103         SYNDROME_MW_BIND_ERR             = 0x06,
 104         SYNDROME_BAD_RESP_ERR            = 0x10,
 105         SYNDROME_LOCAL_ACCESS_ERR        = 0x11,
 106         SYNDROME_REMOTE_INVAL_REQ_ERR    = 0x12,
 107         SYNDROME_REMOTE_ACCESS_ERR       = 0x13,
 108         SYNDROME_REMOTE_OP_ERR           = 0x14,
 109         SYNDROME_RETRY_EXC_ERR           = 0x15,
 110         SYNDROME_RNR_RETRY_EXC_ERR       = 0x16,
 111         SYNDROME_LOCAL_RDD_VIOL_ERR      = 0x20,
 112         SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
 113         SYNDROME_REMOTE_ABORTED_ERR      = 0x22,
 114         SYNDROME_INVAL_EECN_ERR          = 0x23,
 115         SYNDROME_INVAL_EEC_STATE_ERR     = 0x24
 116 };
 117
 118 struct mthca_cqe {
 119         __be32 my_qpn;
 120         __be32 my_ee;
 121         __be32 rqpn;
 122         __be16 sl_g_mlpath;
 123         __be16 rlid;
 124         __be32 imm_etype_pkey_eec;
 125         __be32 byte_cnt;
 126         __be32 wqe;
 127         u8     opcode;
 128         u8     is_send;
 129         u8     reserved;
 130         u8     owner;
 131 };
 132
 133 struct mthca_err_cqe {
 134         __be32 my_qpn;
 135         u32    reserved1[3];
 136         u8     syndrome;
 137         u8     vendor_err;
 138         __be16 db_cnt;
 139         u32    reserved2;
 140         __be32 wqe;
 141         u8     opcode;
 142         u8     reserved3[2];
 143         u8     owner;
 144 };
 145
 146 #define MTHCA_CQ_ENTRY_OWNER_SW      (0 << 7)
 147 #define MTHCA_CQ_ENTRY_OWNER_HW      (1 << 7)
 148
 149 #define MTHCA_TAVOR_CQ_DB_INC_CI       (1 << 24)
 150 #define MTHCA_TAVOR_CQ_DB_REQ_NOT      (2 << 24)
 151 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL  (3 << 24)
 152 #define MTHCA_TAVOR_CQ_DB_SET_CI       (4 << 24)
 153 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
 154
 155 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL  (1 << 24)
 156 #define MTHCA_ARBEL_CQ_DB_REQ_NOT      (2 << 24)
 157 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
 158
 159 static inline struct mthca_cqe *get_cqe_from_buf(struct mthca_cq_buf *buf,
 160                                                  int entry)
 161 {
 162         if (buf->is_direct)
 163                 return buf->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE);
 164         else
 165                 return buf->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf
 166                         + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE;
 167 }
 168
 169 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
 170 {
 171         return get_cqe_from_buf(&cq->buf, entry);
 172 }
 173
 174 static inline struct mthca_cqe *cqe_sw(struct mthca_cqe *cqe)
 175 {
 176         return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
 177 }
 178
 179 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
 180 {
 181         return cqe_sw(get_cqe(cq, cq->cons_index & cq->ibcq.cqe));
 182 }
 183
 184 static inline void set_cqe_hw(struct mthca_cqe *cqe)
 185 {
 186         cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
 187 }
 188
 189 static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
 190 {
 191         __be32 *cqe = cqe_ptr;
 192
 193         (void) cqe;     /* avoid warning if mthca_dbg compiled away... */
 194         mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
 195                   be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]),
 196                   be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]),
 197                   be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7]));
 198 }
 199
 200 /*
 201  * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
 202  * should be correct before calling update_cons_index().
 203  */
 204 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
 205                                      int incr)
 206 {
 207         __be32 doorbell[2];
 208
 209         if (mthca_is_memfree(dev)) {
 210                 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
 211                 wmb();
 212         } else {
 213                 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
 214                 doorbell[1] = cpu_to_be32(incr - 1);
 215
 216                 mthca_write64(doorbell,
 217                               dev->kar + MTHCA_CQ_DOORBELL,
 218                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
 219                 /*
 220                  * Make sure doorbells don't leak out of CQ spinlock
 221                  * and reach the HCA out of order:
 222                  */
 223                 mmiowb();
 224         }
 225 }
 226
 227 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn)
 228 {
 229         struct mthca_cq *cq;
 230
 231         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 232
 233         if (!cq) {
 234                 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
 235                 return;
 236         }
 237
 238         ++cq->arm_sn;
 239
 240         cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
 241 }
 242
 243 void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
 244                     enum ib_event_type event_type)
 245 {
 246         struct mthca_cq *cq;
 247         struct ib_event event;
 248
 249         spin_lock(&dev->cq_table.lock);
 250
 251         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 252         if (cq)
 253                 ++cq->refcount;
 254
 255         spin_unlock(&dev->cq_table.lock);
 256
 257         if (!cq) {
 258                 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn);
 259                 return;
 260         }
 261
 262         event.device      = &dev->ib_dev;
 263         event.event       = event_type;
 264         event.element.cq  = &cq->ibcq;
 265         if (cq->ibcq.event_handler)
 266                 cq->ibcq.event_handler(&event, cq->ibcq.cq_context);
 267
 268         spin_lock(&dev->cq_table.lock);
 269         if (!--cq->refcount)
 270                 wake_up(&cq->wait);
 271         spin_unlock(&dev->cq_table.lock);
 272 }
 273
 274 static inline int is_recv_cqe(struct mthca_cqe *cqe)
 275 {
 276         if ((cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
 277             MTHCA_ERROR_CQE_OPCODE_MASK)
 278                 return !(cqe->opcode & 0x01);
 279         else
 280                 return !(cqe->is_send & 0x80);
 281 }
 282
 283 void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn,
 284                     struct mthca_srq *srq)
 285 {
 286         struct mthca_cqe *cqe;
 287         u32 prod_index;
 288         int i, nfreed = 0;
 289
 290         spin_lock_irq(&cq->lock);
 291
 292         /*
 293          * First we need to find the current producer index, so we
 294          * know where to start cleaning from.  It doesn't matter if HW
 295          * adds new entries after this loop -- the QP we're worried
 296          * about is already in RESET, so the new entries won't come
 297          * from our QP and therefore don't need to be checked.
 298          */
 299         for (prod_index = cq->cons_index;
 300              cqe_sw(get_cqe(cq, prod_index & cq->ibcq.cqe));
 301              ++prod_index)
 302                 if (prod_index == cq->cons_index + cq->ibcq.cqe)
 303                         break;
 304
 305         if (0)
 306                 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
 307                           qpn, cq->cqn, cq->cons_index, prod_index);
 308
 309         /*
 310          * Now sweep backwards through the CQ, removing CQ entries
 311          * that match our QP by copying older entries on top of them.
 312          */
 313         while ((int) --prod_index - (int) cq->cons_index >= 0) {
 314                 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
 315                 if (cqe->my_qpn == cpu_to_be32(qpn)) {
 316                         if (srq && is_recv_cqe(cqe))
 317                                 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe));
 318                         ++nfreed;
 319                 } else if (nfreed)
 320                         memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe),
 321                                cqe, MTHCA_CQ_ENTRY_SIZE);
 322         }
 323
 324         if (nfreed) {
 325                 for (i = 0; i < nfreed; ++i)
 326                         set_cqe_hw(get_cqe(cq, (cq->cons_index + i) & cq->ibcq.cqe));
 327                 wmb();
 328                 cq->cons_index += nfreed;
 329                 update_cons_index(dev, cq, nfreed);
 330         }
 331
 332         spin_unlock_irq(&cq->lock);
 333 }
 334
 335 void mthca_cq_resize_copy_cqes(struct mthca_cq *cq)
 336 {
 337         int i;
 338
 339         /*
 340          * In Tavor mode, the hardware keeps the consumer and producer
 341          * indices mod the CQ size.  Since we might be making the CQ
 342          * bigger, we need to deal with the case where the producer
 343          * index wrapped around before the CQ was resized.
 344          */
 345         if (!mthca_is_memfree(to_mdev(cq->ibcq.device)) &&
 346             cq->ibcq.cqe < cq->resize_buf->cqe) {
 347                 cq->cons_index &= cq->ibcq.cqe;
 348                 if (cqe_sw(get_cqe(cq, cq->ibcq.cqe)))
 349                         cq->cons_index -= cq->ibcq.cqe + 1;
 350         }
 351
 352         for (i = cq->cons_index; cqe_sw(get_cqe(cq, i & cq->ibcq.cqe)); ++i)
 353                 memcpy(get_cqe_from_buf(&cq->resize_buf->buf,
 354                                         i & cq->resize_buf->cqe),
 355                        get_cqe(cq, i & cq->ibcq.cqe), MTHCA_CQ_ENTRY_SIZE);
 356 }
 357
 358 int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent)
 359 {
 360         int ret;
 361         int i;
 362
 363         ret = mthca_buf_alloc(dev, nent * MTHCA_CQ_ENTRY_SIZE,
 364                               MTHCA_MAX_DIRECT_CQ_SIZE,
 365                               &buf->queue, &buf->is_direct,
 366                               &dev->driver_pd, 1, &buf->mr);
 367         if (ret)
 368                 return ret;
 369
 370         for (i = 0; i < nent; ++i)
 371                 set_cqe_hw(get_cqe_from_buf(buf, i));
 372
 373         return 0;
 374 }
 375
 376 void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe)
 377 {
 378         mthca_buf_free(dev, (cqe + 1) * MTHCA_CQ_ENTRY_SIZE, &buf->queue,
 379                        buf->is_direct, &buf->mr);
 380 }
 381
 382 static void handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
 383                              struct mthca_qp *qp, int wqe_index, int is_send,
 384                              struct mthca_err_cqe *cqe,
 385                              struct ib_wc *entry, int *free_cqe)
 386 {
 387         int dbd;
 388         __be32 new_wqe;
 389
 390         if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
 391                 mthca_dbg(dev, "local QP operation err "
 392                           "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
 393                           be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe),
 394                           cq->cqn, cq->cons_index);
 395                 dump_cqe(dev, cqe);
 396         }
 397
 398         /*
 399          * For completions in error, only work request ID, status, vendor error
 400          * (and freed resource count for RD) have to be set.
 401          */
 402         switch (cqe->syndrome) {
 403         case SYNDROME_LOCAL_LENGTH_ERR:
 404                 entry->status = IB_WC_LOC_LEN_ERR;
 405                 break;
 406         case SYNDROME_LOCAL_QP_OP_ERR:
 407                 entry->status = IB_WC_LOC_QP_OP_ERR;
 408                 break;
 409         case SYNDROME_LOCAL_EEC_OP_ERR:
 410                 entry->status = IB_WC_LOC_EEC_OP_ERR;
 411                 break;
 412         case SYNDROME_LOCAL_PROT_ERR:
 413                 entry->status = IB_WC_LOC_PROT_ERR;
 414                 break;
 415         case SYNDROME_WR_FLUSH_ERR:
 416                 entry->status = IB_WC_WR_FLUSH_ERR;
 417                 break;
 418         case SYNDROME_MW_BIND_ERR:
 419                 entry->status = IB_WC_MW_BIND_ERR;
 420                 break;
 421         case SYNDROME_BAD_RESP_ERR:
 422                 entry->status = IB_WC_BAD_RESP_ERR;
 423                 break;
 424         case SYNDROME_LOCAL_ACCESS_ERR:
 425                 entry->status = IB_WC_LOC_ACCESS_ERR;
 426                 break;
 427         case SYNDROME_REMOTE_INVAL_REQ_ERR:
 428                 entry->status = IB_WC_REM_INV_REQ_ERR;
 429                 break;
 430         case SYNDROME_REMOTE_ACCESS_ERR:
 431                 entry->status = IB_WC_REM_ACCESS_ERR;
 432                 break;
 433         case SYNDROME_REMOTE_OP_ERR:
 434                 entry->status = IB_WC_REM_OP_ERR;
 435                 break;
 436         case SYNDROME_RETRY_EXC_ERR:
 437                 entry->status = IB_WC_RETRY_EXC_ERR;
 438                 break;
 439         case SYNDROME_RNR_RETRY_EXC_ERR:
 440                 entry->status = IB_WC_RNR_RETRY_EXC_ERR;
 441                 break;
 442         case SYNDROME_LOCAL_RDD_VIOL_ERR:
 443                 entry->status = IB_WC_LOC_RDD_VIOL_ERR;
 444                 break;
 445         case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
 446                 entry->status = IB_WC_REM_INV_RD_REQ_ERR;
 447                 break;
 448         case SYNDROME_REMOTE_ABORTED_ERR:
 449                 entry->status = IB_WC_REM_ABORT_ERR;
 450                 break;
 451         case SYNDROME_INVAL_EECN_ERR:
 452                 entry->status = IB_WC_INV_EECN_ERR;
 453                 break;
 454         case SYNDROME_INVAL_EEC_STATE_ERR:
 455                 entry->status = IB_WC_INV_EEC_STATE_ERR;
 456                 break;
 457         default:
 458                 entry->status = IB_WC_GENERAL_ERR;
 459                 break;
 460         }
 461
 462         entry->vendor_err = cqe->vendor_err;
 463
 464         /*
 465          * Mem-free HCAs always generate one CQE per WQE, even in the
 466          * error case, so we don't have to check the doorbell count, etc.
 467          */
 468         if (mthca_is_memfree(dev))
 469                 return;
 470
 471         mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
 472
 473         /*
 474          * If we're at the end of the WQE chain, or we've used up our
 475          * doorbell count, free the CQE.  Otherwise just update it for
 476          * the next poll operation.
 477          */
 478         if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
 479                 return;
 480
 481         cqe->db_cnt   = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
 482         cqe->wqe      = new_wqe;
 483         cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
 484
 485         *free_cqe = 0;
 486 }
 487
 488 static inline int mthca_poll_one(struct mthca_dev *dev,
 489                                  struct mthca_cq *cq,
 490                                  struct mthca_qp **cur_qp,
 491                                  int *freed,
 492                                  struct ib_wc *entry)
 493 {
 494         struct mthca_wq *wq;
 495         struct mthca_cqe *cqe;
 496         int wqe_index;
 497         int is_error;
 498         int is_send;
 499         int free_cqe = 1;
 500         int err = 0;
 501
 502         cqe = next_cqe_sw(cq);
 503         if (!cqe)
 504                 return -EAGAIN;
 505
 506         /*
 507          * Make sure we read CQ entry contents after we've checked the
 508          * ownership bit.
 509          */
 510         rmb();
 511
 512         if (0) {
 513                 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
 514                           cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
 515                           be32_to_cpu(cqe->wqe));
 516                 dump_cqe(dev, cqe);
 517         }
 518
 519         is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
 520                 MTHCA_ERROR_CQE_OPCODE_MASK;
 521         is_send  = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
 522
 523         if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) {
 524                 /*
 525                  * We do not have to take the QP table lock here,
 526                  * because CQs will be locked while QPs are removed
 527                  * from the table.
 528                  */
 529                 *cur_qp = mthca_array_get(&dev->qp_table.qp,
 530                                           be32_to_cpu(cqe->my_qpn) &
 531                                           (dev->limits.num_qps - 1));
 532                 if (!*cur_qp) {
 533                         mthca_warn(dev, "CQ entry for unknown QP %06x\n",
 534                                    be32_to_cpu(cqe->my_qpn) & 0xffffff);
 535                         err = -EINVAL;
 536                         goto out;
 537                 }
 538         }
 539
 540         entry->qp = &(*cur_qp)->ibqp;
 541
 542         if (is_send) {
 543                 wq = &(*cur_qp)->sq;
 544                 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset)
 545                              >> wq->wqe_shift);
 546                 entry->wr_id = (*cur_qp)->wrid[wqe_index +
 547                                                (*cur_qp)->rq.max];
 548         } else if ((*cur_qp)->ibqp.srq) {
 549                 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq);
 550                 u32 wqe = be32_to_cpu(cqe->wqe);
 551                 wq = NULL;
 552                 wqe_index = wqe >> srq->wqe_shift;
 553                 entry->wr_id = srq->wrid[wqe_index];
 554                 mthca_free_srq_wqe(srq, wqe);
 555         } else {
 556                 s32 wqe;
 557                 wq = &(*cur_qp)->rq;
 558                 wqe = be32_to_cpu(cqe->wqe);
 559                 wqe_index = wqe >> wq->wqe_shift;
 560                 /*
 561                  * WQE addr == base - 1 might be reported in receive completion
 562                  * with error instead of (rq size - 1) by Sinai FW 1.0.800 and
 563                  * Arbel FW 5.1.400.  This bug should be fixed in later FW revs.
 564                  */
 565                 if (unlikely(wqe_index < 0))
 566                         wqe_index = wq->max - 1;
 567                 entry->wr_id = (*cur_qp)->wrid[wqe_index];
 568         }
 569
 570         if (wq) {
 571                 if (wq->last_comp < wqe_index)
 572                         wq->tail += wqe_index - wq->last_comp;
 573                 else
 574                         wq->tail += wqe_index + wq->max - wq->last_comp;
 575
 576                 wq->last_comp = wqe_index;
 577         }
 578
 579         if (is_error) {
 580                 handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
 581                                  (struct mthca_err_cqe *) cqe,
 582                                  entry, &free_cqe);
 583                 goto out;
 584         }
 585
 586         if (is_send) {
 587                 entry->wc_flags = 0;
 588                 switch (cqe->opcode) {
 589                 case MTHCA_OPCODE_RDMA_WRITE:
 590                         entry->opcode    = IB_WC_RDMA_WRITE;
 591                         break;
 592                 case MTHCA_OPCODE_RDMA_WRITE_IMM:
 593                         entry->opcode    = IB_WC_RDMA_WRITE;
 594                         entry->wc_flags |= IB_WC_WITH_IMM;
 595                         break;
 596                 case MTHCA_OPCODE_SEND:
 597                         entry->opcode    = IB_WC_SEND;
 598                         break;
 599                 case MTHCA_OPCODE_SEND_IMM:
 600                         entry->opcode    = IB_WC_SEND;
 601                         entry->wc_flags |= IB_WC_WITH_IMM;
 602                         break;
 603                 case MTHCA_OPCODE_RDMA_READ:
 604                         entry->opcode    = IB_WC_RDMA_READ;
 605                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
 606                         break;
 607                 case MTHCA_OPCODE_ATOMIC_CS:
 608                         entry->opcode    = IB_WC_COMP_SWAP;
 609                         entry->byte_len  = MTHCA_ATOMIC_BYTE_LEN;
 610                         break;
 611                 case MTHCA_OPCODE_ATOMIC_FA:
 612                         entry->opcode    = IB_WC_FETCH_ADD;
 613                         entry->byte_len  = MTHCA_ATOMIC_BYTE_LEN;
 614                         break;
 615                 case MTHCA_OPCODE_BIND_MW:
 616                         entry->opcode    = IB_WC_BIND_MW;
 617                         break;
 618                 default:
 619                         entry->opcode    = MTHCA_OPCODE_INVALID;
 620                         break;
 621                 }
 622         } else {
 623                 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
 624                 switch (cqe->opcode & 0x1f) {
 625                 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
 626                 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
 627                         entry->wc_flags = IB_WC_WITH_IMM;
 628                         entry->imm_data = cqe->imm_etype_pkey_eec;
 629                         entry->opcode = IB_WC_RECV;
 630                         break;
 631                 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
 632                 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
 633                         entry->wc_flags = IB_WC_WITH_IMM;
 634                         entry->imm_data = cqe->imm_etype_pkey_eec;
 635                         entry->opcode = IB_WC_RECV_RDMA_WITH_IMM;
 636                         break;
 637                 default:
 638                         entry->wc_flags = 0;
 639                         entry->opcode = IB_WC_RECV;
 640                         break;
 641                 }
 642                 entry->slid        = be16_to_cpu(cqe->rlid);
 643                 entry->sl          = be16_to_cpu(cqe->sl_g_mlpath) >> 12;
 644                 entry->src_qp      = be32_to_cpu(cqe->rqpn) & 0xffffff;
 645                 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f;
 646                 entry->pkey_index  = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
 647                 entry->wc_flags   |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ?
 648                                         IB_WC_GRH : 0;
 649         }
 650
 651         entry->status = IB_WC_SUCCESS;
 652
 653  out:
 654         if (likely(free_cqe)) {
 655                 set_cqe_hw(cqe);
 656                 ++(*freed);
 657                 ++cq->cons_index;
 658         }
 659
 660         return err;
 661 }
 662
 663 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
 664                   struct ib_wc *entry)
 665 {
 666         struct mthca_dev *dev = to_mdev(ibcq->device);
 667         struct mthca_cq *cq = to_mcq(ibcq);
 668         struct mthca_qp *qp = NULL;
 669         unsigned long flags;
 670         int err = 0;
 671         int freed = 0;
 672         int npolled;
 673
 674         spin_lock_irqsave(&cq->lock, flags);
 675
 676         npolled = 0;
 677 repoll:
 678         while (npolled < num_entries) {
 679                 err = mthca_poll_one(dev, cq, &qp,
 680                                      &freed, entry + npolled);
 681                 if (err)
 682                         break;
 683                 ++npolled;
 684         }
 685
 686         if (freed) {
 687                 wmb();
 688                 update_cons_index(dev, cq, freed);
 689         }
 690
 691         /*
 692          * If a CQ resize is in progress and we discovered that the
 693          * old buffer is empty, then peek in the new buffer, and if
 694          * it's not empty, switch to the new buffer and continue
 695          * polling there.
 696          */
 697         if (unlikely(err == -EAGAIN && cq->resize_buf &&
 698                      cq->resize_buf->state == CQ_RESIZE_READY)) {
 699                 /*
 700                  * In Tavor mode, the hardware keeps the producer
 701                  * index modulo the CQ size.  Since we might be making
 702                  * the CQ bigger, we need to mask our consumer index
 703                  * using the size of the old CQ buffer before looking
 704                  * in the new CQ buffer.
 705                  */
 706                 if (!mthca_is_memfree(dev))
 707                         cq->cons_index &= cq->ibcq.cqe;
 708
 709                 if (cqe_sw(get_cqe_from_buf(&cq->resize_buf->buf,
 710                                             cq->cons_index & cq->resize_buf->cqe))) {
 711                         struct mthca_cq_buf tbuf;
 712                         int tcqe;
 713
 714                         tbuf         = cq->buf;
 715                         tcqe         = cq->ibcq.cqe;
 716                         cq->buf      = cq->resize_buf->buf;
 717                         cq->ibcq.cqe = cq->resize_buf->cqe;
 718
 719                         cq->resize_buf->buf   = tbuf;
 720                         cq->resize_buf->cqe   = tcqe;
 721                         cq->resize_buf->state = CQ_RESIZE_SWAPPED;
 722
 723                         goto repoll;
 724                 }
 725         }
 726
 727         spin_unlock_irqrestore(&cq->lock, flags);
 728
 729         return err == 0 || err == -EAGAIN ? npolled : err;
 730 }
 731
 732 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags)
 733 {
 734         __be32 doorbell[2];
 735
 736         doorbell[0] = cpu_to_be32(((flags & IB_CQ_SOLICITED_MASK) ==
 737                                    IB_CQ_SOLICITED ?
 738                                    MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
 739                                    MTHCA_TAVOR_CQ_DB_REQ_NOT)      |
 740                                   to_mcq(cq)->cqn);
 741         doorbell[1] = (__force __be32) 0xffffffff;
 742
 743         mthca_write64(doorbell,
 744                       to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
 745                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
 746
 747         return 0;
 748 }
 749
 750 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
 751 {
 752         struct mthca_cq *cq = to_mcq(ibcq);
 753         __be32 doorbell[2];
 754         u32 sn;
 755         __be32 ci;
 756
 757         sn = cq->arm_sn & 3;
 758         ci = cpu_to_be32(cq->cons_index);
 759
 760         doorbell[0] = ci;
 761         doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
 762                                   ((flags & IB_CQ_SOLICITED_MASK) ==
 763                                    IB_CQ_SOLICITED ? 1 : 2));
 764
 765         mthca_write_db_rec(doorbell, cq->arm_db);
 766
 767         /*
 768          * Make sure that the doorbell record in host memory is
 769          * written before ringing the doorbell via PCI MMIO.
 770          */
 771         wmb();
 772
 773         doorbell[0] = cpu_to_be32((sn << 28)                       |
 774                                   ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
 775                                    MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
 776                                    MTHCA_ARBEL_CQ_DB_REQ_NOT)      |
 777                                   cq->cqn);
 778         doorbell[1] = ci;
 779
 780         mthca_write64(doorbell,
 781                       to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
 782                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
 783
 784         return 0;
 785 }
 786
 787 int mthca_init_cq(struct mthca_dev *dev, int nent,
 788                   struct mthca_ucontext *ctx, u32 pdn,
 789                   struct mthca_cq *cq)
 790 {
 791         struct mthca_mailbox *mailbox;
 792         struct mthca_cq_context *cq_context;
 793         int err = -ENOMEM;
 794         u8 status;
 795
 796         cq->ibcq.cqe  = nent - 1;
 797         cq->is_kernel = !ctx;
 798
 799         cq->cqn = mthca_alloc(&dev->cq_table.alloc);
 800         if (cq->cqn == -1)
 801                 return -ENOMEM;
 802
 803         if (mthca_is_memfree(dev)) {
 804                 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
 805                 if (err)
 806                         goto err_out;
 807
 808                 if (cq->is_kernel) {
 809                         cq->arm_sn = 1;
 810
 811                         err = -ENOMEM;
 812
 813                         cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
 814                                                              cq->cqn, &cq->set_ci_db);
 815                         if (cq->set_ci_db_index < 0)
 816                                 goto err_out_icm;
 817
 818                         cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
 819                                                           cq->cqn, &cq->arm_db);
 820                         if (cq->arm_db_index < 0)
 821                                 goto err_out_ci;
 822                 }
 823         }
 824
 825         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 826         if (IS_ERR(mailbox))
 827                 goto err_out_arm;
 828
 829         cq_context = mailbox->buf;
 830
 831         if (cq->is_kernel) {
 832                 err = mthca_alloc_cq_buf(dev, &cq->buf, nent);
 833                 if (err)
 834                         goto err_out_mailbox;
 835         }
 836
 837         spin_lock_init(&cq->lock);
 838         cq->refcount = 1;
 839         init_waitqueue_head(&cq->wait);
 840         mutex_init(&cq->mutex);
 841
 842         memset(cq_context, 0, sizeof *cq_context);
 843         cq_context->flags           = cpu_to_be32(MTHCA_CQ_STATUS_OK      |
 844                                                   MTHCA_CQ_STATE_DISARMED |
 845                                                   MTHCA_CQ_FLAG_TR);
 846         cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
 847         if (ctx)
 848                 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index);
 849         else
 850                 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
 851         cq_context->error_eqn       = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
 852         cq_context->comp_eqn        = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
 853         cq_context->pd              = cpu_to_be32(pdn);
 854         cq_context->lkey            = cpu_to_be32(cq->buf.mr.ibmr.lkey);
 855         cq_context->cqn             = cpu_to_be32(cq->cqn);
 856
 857         if (mthca_is_memfree(dev)) {
 858                 cq_context->ci_db    = cpu_to_be32(cq->set_ci_db_index);
 859                 cq_context->state_db = cpu_to_be32(cq->arm_db_index);
 860         }
 861
 862         err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
 863         if (err) {
 864                 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err);
 865                 goto err_out_free_mr;
 866         }
 867
 868         if (status) {
 869                 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n",
 870                            status);
 871                 err = -EINVAL;
 872                 goto err_out_free_mr;
 873         }
 874
 875         spin_lock_irq(&dev->cq_table.lock);
 876         if (mthca_array_set(&dev->cq_table.cq,
 877                             cq->cqn & (dev->limits.num_cqs - 1),
 878                             cq)) {
 879                 spin_unlock_irq(&dev->cq_table.lock);
 880                 goto err_out_free_mr;
 881         }
 882         spin_unlock_irq(&dev->cq_table.lock);
 883
 884         cq->cons_index = 0;
 885
 886         mthca_free_mailbox(dev, mailbox);
 887
 888         return 0;
 889
 890 err_out_free_mr:
 891         if (cq->is_kernel)
 892                 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
 893
 894 err_out_mailbox:
 895         mthca_free_mailbox(dev, mailbox);
 896
 897 err_out_arm:
 898         if (cq->is_kernel && mthca_is_memfree(dev))
 899                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
 900
 901 err_out_ci:
 902         if (cq->is_kernel && mthca_is_memfree(dev))
 903                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
 904
 905 err_out_icm:
 906         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
 907
 908 err_out:
 909         mthca_free(&dev->cq_table.alloc, cq->cqn);
 910
 911         return err;
 912 }
 913
 914 static inline int get_cq_refcount(struct mthca_dev *dev, struct mthca_cq *cq)
 915 {
 916         int c;
 917
 918         spin_lock_irq(&dev->cq_table.lock);
 919         c = cq->refcount;
 920         spin_unlock_irq(&dev->cq_table.lock);
 921
 922         return c;
 923 }
 924
 925 void mthca_free_cq(struct mthca_dev *dev,
 926                    struct mthca_cq *cq)
 927 {
 928         struct mthca_mailbox *mailbox;
 929         int err;
 930         u8 status;
 931
 932         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 933         if (IS_ERR(mailbox)) {
 934                 mthca_warn(dev, "No memory for mailbox to free CQ.\n");
 935                 return;
 936         }
 937
 938         err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
 939         if (err)
 940                 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err);
 941         else if (status)
 942                 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
 943
 944         if (0) {
 945                 __be32 *ctx = mailbox->buf;
 946                 int j;
 947
 948                 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
 949                        cq->cqn, cq->cons_index,
 950                        cq->is_kernel ? !!next_cqe_sw(cq) : 0);
 951                 for (j = 0; j < 16; ++j)
 952                         printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j]));
 953         }
 954
 955         spin_lock_irq(&dev->cq_table.lock);
 956         mthca_array_clear(&dev->cq_table.cq,
 957                           cq->cqn & (dev->limits.num_cqs - 1));
 958         --cq->refcount;
 959         spin_unlock_irq(&dev->cq_table.lock);
 960
 961         if (dev->mthca_flags & MTHCA_FLAG_MSI_X)
 962                 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector);
 963         else
 964                 synchronize_irq(dev->pdev->irq);
 965
 966         wait_event(cq->wait, !get_cq_refcount(dev, cq));
 967
 968         if (cq->is_kernel) {
 969                 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
 970                 if (mthca_is_memfree(dev)) {
 971                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM,    cq->arm_db_index);
 972                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
 973                 }
 974         }
 975
 976         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
 977         mthca_free(&dev->cq_table.alloc, cq->cqn);
 978         mthca_free_mailbox(dev, mailbox);
 979 }
 980
 981 int mthca_init_cq_table(struct mthca_dev *dev)
 982 {
 983         int err;
 984
 985         spin_lock_init(&dev->cq_table.lock);
 986
 987         err = mthca_alloc_init(&dev->cq_table.alloc,
 988                                dev->limits.num_cqs,
 989                                (1 << 24) - 1,
 990                                dev->limits.reserved_cqs);
 991         if (err)
 992                 return err;
 993
 994         err = mthca_array_init(&dev->cq_table.cq,
 995                                dev->limits.num_cqs);
 996         if (err)
 997                 mthca_alloc_cleanup(&dev->cq_table.alloc);
 998
 999         return err;
1000 }
1001
1002 void mthca_cleanup_cq_table(struct mthca_dev *dev)
1003 {
1004         mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
1005         mthca_alloc_cleanup(&dev->cq_table.alloc);
1006 }