2 * Suspend support specific for i386.
4 * Distribute under GPLv2
6 * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
7 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
10 #include <linux/config.h>
11 #include <linux/smp.h>
12 #include <linux/suspend.h>
13 #include <asm/proto.h>
15 #include <asm/pgtable.h>
17 struct saved_context saved_context;
19 unsigned long saved_context_eax, saved_context_ebx, saved_context_ecx, saved_context_edx;
20 unsigned long saved_context_esp, saved_context_ebp, saved_context_esi, saved_context_edi;
21 unsigned long saved_context_r08, saved_context_r09, saved_context_r10, saved_context_r11;
22 unsigned long saved_context_r12, saved_context_r13, saved_context_r14, saved_context_r15;
23 unsigned long saved_context_eflags;
25 void __save_processor_state(struct saved_context *ctxt)
32 asm volatile ("sgdt %0" : "=m" (ctxt->gdt_limit));
33 asm volatile ("sidt %0" : "=m" (ctxt->idt_limit));
34 asm volatile ("str %0" : "=m" (ctxt->tr));
36 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
37 /* EFER should be constant for kernel version, no need to handle it. */
41 asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
42 asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
43 asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
44 asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
45 asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
47 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
48 rdmsrl(MSR_GS_BASE, ctxt->gs_base);
49 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
54 asm volatile ("movq %%cr0, %0" : "=r" (ctxt->cr0));
55 asm volatile ("movq %%cr2, %0" : "=r" (ctxt->cr2));
56 asm volatile ("movq %%cr3, %0" : "=r" (ctxt->cr3));
57 asm volatile ("movq %%cr4, %0" : "=r" (ctxt->cr4));
58 asm volatile ("movq %%cr8, %0" : "=r" (ctxt->cr8));
61 void save_processor_state(void)
63 __save_processor_state(&saved_context);
66 static void do_fpu_end(void)
69 * Restore FPU regs if necessary
74 void __restore_processor_state(struct saved_context *ctxt)
79 asm volatile ("movq %0, %%cr8" :: "r" (ctxt->cr8));
80 asm volatile ("movq %0, %%cr4" :: "r" (ctxt->cr4));
81 asm volatile ("movq %0, %%cr3" :: "r" (ctxt->cr3));
82 asm volatile ("movq %0, %%cr2" :: "r" (ctxt->cr2));
83 asm volatile ("movq %0, %%cr0" :: "r" (ctxt->cr0));
86 * now restore the descriptor tables to their proper values
87 * ltr is done i fix_processor_context().
89 asm volatile ("lgdt %0" :: "m" (ctxt->gdt_limit));
90 asm volatile ("lidt %0" :: "m" (ctxt->idt_limit));
95 asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
96 asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
97 asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
98 load_gs_index(ctxt->gs);
99 asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
101 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
102 wrmsrl(MSR_GS_BASE, ctxt->gs_base);
103 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
105 fix_processor_context();
111 void restore_processor_state(void)
113 __restore_processor_state(&saved_context);
116 void fix_processor_context(void)
118 int cpu = smp_processor_id();
119 struct tss_struct *t = &per_cpu(init_tss, cpu);
121 set_tss_desc(cpu,t); /* This just modifies memory; should not be neccessary. But... This is neccessary, because 386 hardware has concept of busy TSS or some similar stupidity. */
123 cpu_gdt_table[cpu][GDT_ENTRY_TSS].type = 9;
125 syscall_init(); /* This sets MSR_*STAR and related */
126 load_TR_desc(); /* This does ltr */
127 load_LDT(¤t->active_mm->context); /* This does lldt */
130 * Now maybe reload the debug registers
132 if (current->thread.debugreg7){
133 loaddebug(¤t->thread, 0);
134 loaddebug(¤t->thread, 1);
135 loaddebug(¤t->thread, 2);
136 loaddebug(¤t->thread, 3);
138 loaddebug(¤t->thread, 6);
139 loaddebug(¤t->thread, 7);
144 #ifdef CONFIG_SOFTWARE_SUSPEND
145 /* Defined in arch/x86_64/kernel/suspend_asm.S */
146 extern int restore_image(void);
148 pgd_t *temp_level4_pgt;
150 static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
154 i = pud_index(address);
156 for (; i < PTRS_PER_PUD; pud++, i++) {
160 paddr = address + i*PUD_SIZE;
164 pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
167 set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
168 for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
173 pe = _PAGE_NX | _PAGE_PSE | _KERNPG_TABLE | paddr;
174 pe &= __supported_pte_mask;
175 set_pmd(pmd, __pmd(pe));
181 static int set_up_temporary_mappings(void)
183 unsigned long start, end, next;
186 temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC);
187 if (!temp_level4_pgt)
190 /* It is safe to reuse the original kernel mapping */
191 set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
192 init_level4_pgt[pgd_index(__START_KERNEL_map)]);
194 /* Set up the direct mapping from scratch */
195 start = (unsigned long)pfn_to_kaddr(0);
196 end = (unsigned long)pfn_to_kaddr(end_pfn);
198 for (; start < end; start = next) {
199 pud_t *pud = (pud_t *)get_safe_page(GFP_ATOMIC);
202 next = start + PGDIR_SIZE;
205 if ((error = res_phys_pud_init(pud, __pa(start), __pa(next))))
207 set_pgd(temp_level4_pgt + pgd_index(start),
208 mk_kernel_pgd(__pa(pud)));
213 int swsusp_arch_resume(void)
217 /* We have got enough memory and from now on we cannot recover */
218 if ((error = set_up_temporary_mappings()))
223 #endif /* CONFIG_SOFTWARE_SUSPEND */