Merge with /home/shaggy/git/linus-clean/
[linux-2.6] / arch / ia64 / sn / kernel / sn2 / ptc_deadlock.S
1 /* 
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
7  */
8
9 #include <asm/types.h>
10 #include <asm/sn/shub_mmr.h>
11
12 #define DEADLOCKBIT     SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT
13 #define WRITECOUNTMASK  SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK
14 #define ALIAS_OFFSET    (SH1_PIO_WRITE_STATUS_0_ALIAS-SH1_PIO_WRITE_STATUS_0)
15
16
17         .global sn2_ptc_deadlock_recovery_core
18         .proc   sn2_ptc_deadlock_recovery_core
19
20 sn2_ptc_deadlock_recovery_core:
21         .regstk 6,0,0,0
22
23         ptc0     = in0
24         data0    = in1
25         ptc1     = in2
26         data1    = in3
27         piowc    = in4
28         zeroval  = in5
29         piowcphy = r30
30         psrsave  = r2
31         scr1     = r16
32         scr2     = r17
33         mask     = r18
34
35
36         extr.u  piowcphy=piowc,0,61;;   // Convert piowc to uncached physical address
37         dep     piowcphy=-1,piowcphy,63,1
38         movl    mask=WRITECOUNTMASK
39
40 1:
41         add     scr2=ALIAS_OFFSET,piowc // Address of WRITE_STATUS alias register 
42         mov     scr1=7;;                // Clear DEADLOCK, WRITE_ERROR, MULTI_WRITE_ERROR
43         st8.rel [scr2]=scr1;;
44
45 5:      ld8.acq scr1=[piowc];;          // Wait for PIOs to complete.
46         and     scr2=scr1,mask;;        // mask of writecount bits
47         cmp.ne  p6,p0=zeroval,scr2
48 (p6)    br.cond.sptk 5b
49         
50
51
52         ////////////// BEGIN PHYSICAL MODE ////////////////////
53         mov psrsave=psr                 // Disable IC (no PMIs)
54         rsm psr.i | psr.dt | psr.ic;;
55         srlz.i;;
56
57         st8.rel [ptc0]=data0            // Write PTC0 & wait for completion.
58
59 5:      ld8.acq scr1=[piowcphy];;       // Wait for PIOs to complete.
60         and     scr2=scr1,mask;;        // mask of writecount bits
61         cmp.ne  p6,p0=zeroval,scr2
62 (p6)    br.cond.sptk 5b;;
63
64         tbit.nz p8,p7=scr1,DEADLOCKBIT;;// Test for DEADLOCK
65 (p7)    cmp.ne p7,p0=r0,ptc1;;          // Test for non-null ptc1
66         
67 (p7)    st8.rel [ptc1]=data1;;          // Now write PTC1.
68
69 5:      ld8.acq scr1=[piowcphy];;       // Wait for PIOs to complete.
70         and     scr2=scr1,mask;;        // mask of writecount bits
71         cmp.ne  p6,p0=zeroval,scr2
72 (p6)    br.cond.sptk 5b
73         
74         tbit.nz p8,p0=scr1,DEADLOCKBIT;;// Test for DEADLOCK
75
76         mov psr.l=psrsave;;             // Reenable IC
77         srlz.i;;
78         ////////////// END   PHYSICAL MODE ////////////////////
79
80 (p8)    br.cond.spnt 1b;;               // Repeat if DEADLOCK occurred.
81
82         br.ret.sptk     rp
83         .endp sn2_ptc_deadlock_recovery_core