git.oblomov.eu Git - linux-2.6/blob - arch/mips/mips-boards/malta/malta_int.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
   4  * Copyright (C) 2001 Ralf Baechle
   5  *
   6  *  This program is free software; you can distribute it and/or modify it
   7  *  under the terms of the GNU General Public License (Version 2) as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  *  for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License along
  16  *  with this program; if not, write to the Free Software Foundation, Inc.,
  17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  *
  19  * Routines for generic manipulation of the interrupts found on the MIPS
  20  * Malta board.
  21  * The interrupt controller is located in the South Bridge a PIIX4 device
  22  * with two internal 82C95 interrupt controllers.
  23  */
  24 #include <linux/init.h>
  25 #include <linux/irq.h>
  26 #include <linux/sched.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/kernel_stat.h>
  30 #include <linux/kernel.h>
  31 #include <linux/random.h>
  32
  33 #include <asm/i8259.h>
  34 #include <asm/irq_cpu.h>
  35 #include <asm/io.h>
  36 #include <asm/irq_regs.h>
  37 #include <asm/mips-boards/malta.h>
  38 #include <asm/mips-boards/maltaint.h>
  39 #include <asm/mips-boards/piix4.h>
  40 #include <asm/gt64120.h>
  41 #include <asm/mips-boards/generic.h>
  42 #include <asm/mips-boards/msc01_pci.h>
  43 #include <asm/msc01_ic.h>
  44
  45 static DEFINE_SPINLOCK(mips_irq_lock);
  46
  47 static inline int mips_pcibios_iack(void)
  48 {
  49         int irq;
  50         u32 dummy;
  51
  52         /*
  53          * Determine highest priority pending interrupt by performing
  54          * a PCI Interrupt Acknowledge cycle.
  55          */
  56         switch (mips_revision_sconid) {
  57         case MIPS_REVISION_SCON_SOCIT:
  58         case MIPS_REVISION_SCON_ROCIT:
  59         case MIPS_REVISION_SCON_SOCITSC:
  60         case MIPS_REVISION_SCON_SOCITSCP:
  61                 MSC_READ(MSC01_PCI_IACK, irq);
  62                 irq &= 0xff;
  63                 break;
  64         case MIPS_REVISION_SCON_GT64120:
  65                 irq = GT_READ(GT_PCI0_IACK_OFS);
  66                 irq &= 0xff;
  67                 break;
  68         case MIPS_REVISION_SCON_BONITO:
  69                 /* The following will generate a PCI IACK cycle on the
  70                  * Bonito controller. It's a little bit kludgy, but it
  71                  * was the easiest way to implement it in hardware at
  72                  * the given time.
  73                  */
  74                 BONITO_PCIMAP_CFG = 0x20000;
  75
  76                 /* Flush Bonito register block */
  77                 dummy = BONITO_PCIMAP_CFG;
  78                 iob();    /* sync */
  79
  80                 irq = readl((u32 *)_pcictrl_bonito_pcicfg);
  81                 iob();    /* sync */
  82                 irq &= 0xff;
  83                 BONITO_PCIMAP_CFG = 0;
  84                 break;
  85         default:
  86                 printk(KERN_WARNING "Unknown system controller.\n");
  87                 return -1;
  88         }
  89         return irq;
  90 }
  91
  92 static inline int get_int(void)
  93 {
  94         unsigned long flags;
  95         int irq;
  96         spin_lock_irqsave(&mips_irq_lock, flags);
  97
  98         irq = mips_pcibios_iack();
  99
 100         /*
 101          * The only way we can decide if an interrupt is spurious
 102          * is by checking the 8259 registers.  This needs a spinlock
 103          * on an SMP system,  so leave it up to the generic code...
 104          */
 105
 106         spin_unlock_irqrestore(&mips_irq_lock, flags);
 107
 108         return irq;
 109 }
 110
 111 static void malta_hw0_irqdispatch(void)
 112 {
 113         int irq;
 114
 115         irq = get_int();
 116         if (irq < 0) {
 117                 return;  /* interrupt has already been cleared */
 118         }
 119
 120         do_IRQ(MALTA_INT_BASE + irq);
 121 }
 122
 123 static void corehi_irqdispatch(void)
 124 {
 125         unsigned int intedge, intsteer, pcicmd, pcibadaddr;
 126         unsigned int pcimstat, intisr, inten, intpol;
 127         unsigned int intrcause, datalo, datahi;
 128         struct pt_regs *regs = get_irq_regs();
 129
 130         printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
 131         printk(KERN_EMERG "epc   : %08lx\nStatus: %08lx\n"
 132                         "Cause : %08lx\nbadVaddr : %08lx\n",
 133                         regs->cp0_epc, regs->cp0_status,
 134                         regs->cp0_cause, regs->cp0_badvaddr);
 135
 136         /* Read all the registers and then print them as there is a
 137            problem with interspersed printk's upsetting the Bonito controller.
 138            Do it for the others too.
 139         */
 140
 141         switch (mips_revision_sconid) {
 142         case MIPS_REVISION_SCON_SOCIT:
 143         case MIPS_REVISION_SCON_ROCIT:
 144         case MIPS_REVISION_SCON_SOCITSC:
 145         case MIPS_REVISION_SCON_SOCITSCP:
 146                 ll_msc_irq();
 147                 break;
 148         case MIPS_REVISION_SCON_GT64120:
 149                 intrcause = GT_READ(GT_INTRCAUSE_OFS);
 150                 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
 151                 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
 152                 printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
 153                 printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
 154                                 datahi, datalo);
 155                 break;
 156         case MIPS_REVISION_SCON_BONITO:
 157                 pcibadaddr = BONITO_PCIBADADDR;
 158                 pcimstat = BONITO_PCIMSTAT;
 159                 intisr = BONITO_INTISR;
 160                 inten = BONITO_INTEN;
 161                 intpol = BONITO_INTPOL;
 162                 intedge = BONITO_INTEDGE;
 163                 intsteer = BONITO_INTSTEER;
 164                 pcicmd = BONITO_PCICMD;
 165                 printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
 166                 printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
 167                 printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
 168                 printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
 169                 printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
 170                 printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
 171                 printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
 172                 printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
 173                 break;
 174         }
 175
 176         /* We die here*/
 177         die("CoreHi interrupt", regs);
 178 }
 179
 180 static inline int clz(unsigned long x)
 181 {
 182         __asm__(
 183         "       .set    push                                    \n"
 184         "       .set    mips32                                  \n"
 185         "       clz     %0, %1                                  \n"
 186         "       .set    pop                                     \n"
 187         : "=r" (x)
 188         : "r" (x));
 189
 190         return x;
 191 }
 192
 193 /*
 194  * Version of ffs that only looks at bits 12..15.
 195  */
 196 static inline unsigned int irq_ffs(unsigned int pending)
 197 {
 198 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
 199         return -clz(pending) + 31 - CAUSEB_IP;
 200 #else
 201         unsigned int a0 = 7;
 202         unsigned int t0;
 203
 204         t0 = pending & 0xf000;
 205         t0 = t0 < 1;
 206         t0 = t0 << 2;
 207         a0 = a0 - t0;
 208         pending = pending << t0;
 209
 210         t0 = pending & 0xc000;
 211         t0 = t0 < 1;
 212         t0 = t0 << 1;
 213         a0 = a0 - t0;
 214         pending = pending << t0;
 215
 216         t0 = pending & 0x8000;
 217         t0 = t0 < 1;
 218         //t0 = t0 << 2;
 219         a0 = a0 - t0;
 220         //pending = pending << t0;
 221
 222         return a0;
 223 #endif
 224 }
 225
 226 /*
 227  * IRQs on the Malta board look basically (barring software IRQs which we
 228  * don't use at all and all external interrupt sources are combined together
 229  * on hardware interrupt 0 (MIPS IRQ 2)) like:
 230  *
 231  *      MIPS IRQ        Source
 232  *      --------        ------
 233  *             0        Software (ignored)
 234  *             1        Software (ignored)
 235  *             2        Combined hardware interrupt (hw0)
 236  *             3        Hardware (ignored)
 237  *             4        Hardware (ignored)
 238  *             5        Hardware (ignored)
 239  *             6        Hardware (ignored)
 240  *             7        R4k timer (what we use)
 241  *
 242  * We handle the IRQ according to _our_ priority which is:
 243  *
 244  * Highest ----     R4k Timer
 245  * Lowest  ----     Combined hardware interrupt
 246  *
 247  * then we just return, if multiple IRQs are pending then we will just take
 248  * another exception, big deal.
 249  */
 250
 251 asmlinkage void plat_irq_dispatch(void)
 252 {
 253         unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
 254         int irq;
 255
 256         irq = irq_ffs(pending);
 257
 258         if (irq == MIPSCPU_INT_I8259A)
 259                 malta_hw0_irqdispatch();
 260         else if (irq >= 0)
 261                 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
 262         else
 263                 spurious_interrupt();
 264 }
 265
 266 static struct irqaction i8259irq = {
 267         .handler = no_action,
 268         .name = "XT-PIC cascade"
 269 };
 270
 271 static struct irqaction corehi_irqaction = {
 272         .handler = no_action,
 273         .name = "CoreHi"
 274 };
 275
 276 msc_irqmap_t __initdata msc_irqmap[] = {
 277         {MSC01C_INT_TMR,                MSC01_IRQ_EDGE, 0},
 278         {MSC01C_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 279 };
 280 int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
 281
 282 msc_irqmap_t __initdata msc_eicirqmap[] = {
 283         {MSC01E_INT_SW0,                MSC01_IRQ_LEVEL, 0},
 284         {MSC01E_INT_SW1,                MSC01_IRQ_LEVEL, 0},
 285         {MSC01E_INT_I8259A,             MSC01_IRQ_LEVEL, 0},
 286         {MSC01E_INT_SMI,                MSC01_IRQ_LEVEL, 0},
 287         {MSC01E_INT_COREHI,             MSC01_IRQ_LEVEL, 0},
 288         {MSC01E_INT_CORELO,             MSC01_IRQ_LEVEL, 0},
 289         {MSC01E_INT_TMR,                MSC01_IRQ_EDGE, 0},
 290         {MSC01E_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 291         {MSC01E_INT_PERFCTR,            MSC01_IRQ_LEVEL, 0},
 292         {MSC01E_INT_CPUCTR,             MSC01_IRQ_LEVEL, 0}
 293 };
 294 int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
 295
 296 void __init arch_init_irq(void)
 297 {
 298         init_i8259_irqs();
 299
 300         if (!cpu_has_veic)
 301                 mips_cpu_irq_init();
 302
 303         switch (mips_revision_sconid) {
 304         case MIPS_REVISION_SCON_SOCIT:
 305         case MIPS_REVISION_SCON_ROCIT:
 306                 if (cpu_has_veic)
 307                         init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
 308                                         MSC01E_INT_BASE, msc_eicirqmap,
 309                                         msc_nr_eicirqs);
 310                 else
 311                         init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
 312                                         MSC01C_INT_BASE, msc_irqmap,
 313                                         msc_nr_irqs);
 314                 break;
 315
 316         case MIPS_REVISION_SCON_SOCITSC:
 317         case MIPS_REVISION_SCON_SOCITSCP:
 318                 if (cpu_has_veic)
 319                         init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
 320                                         MSC01E_INT_BASE, msc_eicirqmap,
 321                                         msc_nr_eicirqs);
 322                 else
 323                         init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
 324                                         MSC01C_INT_BASE, msc_irqmap,
 325                                         msc_nr_irqs);
 326         }
 327
 328         if (cpu_has_veic) {
 329                 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
 330                 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
 331                 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
 332                 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
 333         }
 334         else if (cpu_has_vint) {
 335                 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
 336                 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
 337 #ifdef CONFIG_MIPS_MT_SMTC
 338                 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
 339                         (0x100 << MIPSCPU_INT_I8259A));
 340                 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
 341                         &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
 342                 /*
 343                  * Temporary hack to ensure that the subsidiary device
 344                  * interrupts coing in via the i8259A, but associated
 345                  * with low IRQ numbers, will restore the Status.IM
 346                  * value associated with the i8259A.
 347                  */
 348                 {
 349                         int i;
 350
 351                         for (i = 0; i < 16; i++)
 352                                 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
 353                 }
 354 #else /* Not SMTC */
 355                 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
 356                 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
 357                                                 &corehi_irqaction);
 358 #endif /* CONFIG_MIPS_MT_SMTC */
 359         }
 360         else {
 361                 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
 362                 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
 363                                                 &corehi_irqaction);
 364         }
 365 }