git.oblomov.eu Git - linux-2.6/blob - include/asm-blackfin/mach-bf548/bfin_serial_5xx.h

   1 #include <linux/serial.h>
   2 #include <asm/dma.h>
   3 #include <asm/portmux.h>
   4
   5 #define NR_PORTS                4
   6
   7 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
   8 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
   9 #define OFFSET_GCTL             0x08    /* Global Control Register              */
  10 #define OFFSET_LCR              0x0C    /* Line Control Register                */
  11 #define OFFSET_MCR              0x10    /* Modem Control Register               */
  12 #define OFFSET_LSR              0x14    /* Line Status Register                 */
  13 #define OFFSET_MSR              0x18    /* Modem Status Register                */
  14 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
  15 #define OFFSET_IER_SET          0x20    /* Set Interrupt Enable Register        */
  16 #define OFFSET_IER_CLEAR        0x24    /* Clear Interrupt Enable Register      */
  17 #define OFFSET_THR              0x28    /* Transmit Holding register            */
  18 #define OFFSET_RBR              0x2C    /* Receive Buffer register              */
  19
  20 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  21 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  22 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  23 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
  24 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  25 #define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
  26 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  27 #define UART_GET_MSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MSR))
  28 #define UART_GET_MCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MCR))
  29
  30 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
  31 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
  32 #define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
  33 #define UART_CLEAR_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
  34 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
  35 #define UART_PUT_LSR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
  36 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
  37 #define UART_CLEAR_LSR(uart)    bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
  38 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
  39 #define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
  40
  41 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
  42 # define CONFIG_SERIAL_BFIN_CTSRTS
  43
  44 # ifndef CONFIG_UART0_CTS_PIN
  45 #  define CONFIG_UART0_CTS_PIN -1
  46 # endif
  47
  48 # ifndef CONFIG_UART0_RTS_PIN
  49 #  define CONFIG_UART0_RTS_PIN -1
  50 # endif
  51
  52 # ifndef CONFIG_UART1_CTS_PIN
  53 #  define CONFIG_UART1_CTS_PIN -1
  54 # endif
  55
  56 # ifndef CONFIG_UART1_RTS_PIN
  57 #  define CONFIG_UART1_RTS_PIN -1
  58 # endif
  59 #endif
  60 /*
  61  * The pin configuration is different from schematic
  62  */
  63 struct bfin_serial_port {
  64         struct uart_port        port;
  65         unsigned int            old_status;
  66 #ifdef CONFIG_SERIAL_BFIN_DMA
  67         int                     tx_done;
  68         int                     tx_count;
  69         struct circ_buf         rx_dma_buf;
  70         struct timer_list       rx_dma_timer;
  71         int                     rx_dma_nrows;
  72         unsigned int            tx_dma_channel;
  73         unsigned int            rx_dma_channel;
  74         struct work_struct      tx_dma_workqueue;
  75 #endif
  76 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  77         struct work_struct      cts_workqueue;
  78         int             cts_pin;
  79         int             rts_pin;
  80 #endif
  81 };
  82
  83 struct bfin_serial_port bfin_serial_ports[NR_PORTS];
  84 struct bfin_serial_res {
  85         unsigned long   uart_base_addr;
  86         int             uart_irq;
  87 #ifdef CONFIG_SERIAL_BFIN_DMA
  88         unsigned int    uart_tx_dma_channel;
  89         unsigned int    uart_rx_dma_channel;
  90 #endif
  91 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  92         int     uart_cts_pin;
  93         int     uart_rts_pin;
  94 #endif
  95 };
  96
  97 struct bfin_serial_res bfin_serial_resource[] = {
  98 #ifdef CONFIG_SERIAL_BFIN_UART0
  99         {
 100         0xFFC00400,
 101         IRQ_UART0_RX,
 102 #ifdef CONFIG_SERIAL_BFIN_DMA
 103         CH_UART0_TX,
 104         CH_UART0_RX,
 105 #endif
 106 #ifdef CONFIG_BFIN_UART0_CTSRTS
 107         CONFIG_UART0_CTS_PIN,
 108         CONFIG_UART0_RTS_PIN,
 109 #endif
 110         },
 111 #endif
 112 #ifdef CONFIG_SERIAL_BFIN_UART1
 113         {
 114         0xFFC02000,
 115         IRQ_UART1_RX,
 116 #ifdef CONFIG_SERIAL_BFIN_DMA
 117         CH_UART1_TX,
 118         CH_UART1_RX,
 119 #endif
 120         },
 121 #endif
 122 #ifdef CONFIG_SERIAL_BFIN_UART2
 123         {
 124         0xFFC02100,
 125         IRQ_UART2_RX,
 126 #ifdef CONFIG_SERIAL_BFIN_DMA
 127         CH_UART2_TX,
 128         CH_UART2_RX,
 129 #endif
 130 #ifdef CONFIG_BFIN_UART2_CTSRTS
 131         CONFIG_UART2_CTS_PIN,
 132         CONFIG_UART2_RTS_PIN,
 133 #endif
 134         },
 135 #endif
 136 #ifdef CONFIG_SERIAL_BFIN_UART3
 137         {
 138         0xFFC03100,
 139         IRQ_UART3_RX,
 140 #ifdef CONFIG_SERIAL_BFIN_DMA
 141         CH_UART3_TX,
 142         CH_UART3_RX,
 143 #endif
 144         },
 145 #endif
 146 };
 147
 148 int nr_ports = ARRAY_SIZE(bfin_serial_resource);
 149
 150 #define DRIVER_NAME "bfin-uart"
 151
 152 static void bfin_serial_hw_init(struct bfin_serial_port *uart)
 153 {
 154 #ifdef CONFIG_SERIAL_BFIN_UART0
 155         peripheral_request(P_UART0_TX, DRIVER_NAME);
 156         peripheral_request(P_UART0_RX, DRIVER_NAME);
 157 #endif
 158
 159 #ifdef CONFIG_SERIAL_BFIN_UART1
 160         peripheral_request(P_UART1_TX, DRIVER_NAME);
 161         peripheral_request(P_UART1_RX, DRIVER_NAME);
 162
 163 #ifdef CONFIG_BFIN_UART1_CTSRTS
 164         peripheral_request(P_UART1_RTS, DRIVER_NAME);
 165         peripheral_request(P_UART1_CTS DRIVER_NAME);
 166 #endif
 167 #endif
 168
 169 #ifdef CONFIG_SERIAL_BFIN_UART2
 170         peripheral_request(P_UART2_TX, DRIVER_NAME);
 171         peripheral_request(P_UART2_RX, DRIVER_NAME);
 172 #endif
 173
 174 #ifdef CONFIG_SERIAL_BFIN_UART3
 175         peripheral_request(P_UART3_TX, DRIVER_NAME);
 176         peripheral_request(P_UART3_RX, DRIVER_NAME);
 177
 178 #ifdef CONFIG_BFIN_UART3_CTSRTS
 179         peripheral_request(P_UART3_RTS, DRIVER_NAME);
 180         peripheral_request(P_UART3_CTS DRIVER_NAME);
 181 #endif
 182 #endif
 183         SSYNC();
 184 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 185         if (uart->cts_pin >= 0) {
 186                 gpio_request(uart->cts_pin, DRIVER_NAME);
 187                 gpio_direction_input(uart->cts_pin);
 188         }
 189
 190         if (uart->rts_pin >= 0) {
 191                 gpio_request(uart->rts_pin, DRIVER_NAME);
 192                 gpio_direction_output(uart->rts_pin, 0);
 193         }
 194 #endif
 195 }