2 ** System Bus Adapter (SBA) I/O MMU manager
4 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6 ** (c) Copyright 2000-2004 Hewlett-Packard Company
8 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
10 ** This program is free software; you can redistribute it and/or modify
11 ** it under the terms of the GNU General Public License as published by
12 ** the Free Software Foundation; either version 2 of the License, or
13 ** (at your option) any later version.
16 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/
17 ** J5000/J7000/N-class/L-class machines and their successors.
19 ** FIXME: add DMA hint support programming in both sba and lba modules.
22 #include <linux/types.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
29 #include <linux/string.h>
30 #include <linux/pci.h>
31 #include <linux/scatterlist.h>
32 #include <linux/iommu-helper.h>
34 #include <asm/byteorder.h>
36 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */
38 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
40 #include <linux/proc_fs.h>
41 #include <linux/seq_file.h>
43 #include <asm/ropes.h>
44 #include <asm/mckinley.h> /* for proc_mckinley_root */
45 #include <asm/runway.h> /* for proc_runway_root */
46 #include <asm/pdc.h> /* for PDC_MODEL_* */
47 #include <asm/pdcpat.h> /* for is_pdc_pat() */
48 #include <asm/parisc-device.h>
50 #define MODULE_NAME "SBA"
53 ** The number of debug flags is a clue - this code is fragile.
54 ** Don't even think about messing with it unless you have
55 ** plenty of 710's to sacrifice to the computer gods. :^)
59 #undef DEBUG_SBA_RUN_SG
60 #undef DEBUG_SBA_RESOURCE
61 #undef ASSERT_PDIR_SANITY
62 #undef DEBUG_LARGE_SG_ENTRIES
66 #define DBG_INIT(x...) printk(x)
68 #define DBG_INIT(x...)
72 #define DBG_RUN(x...) printk(x)
77 #ifdef DEBUG_SBA_RUN_SG
78 #define DBG_RUN_SG(x...) printk(x)
80 #define DBG_RUN_SG(x...)
84 #ifdef DEBUG_SBA_RESOURCE
85 #define DBG_RES(x...) printk(x)
90 #define SBA_INLINE __inline__
92 #define DEFAULT_DMA_HINT_REG 0
94 struct sba_device *sba_list;
95 EXPORT_SYMBOL_GPL(sba_list);
97 static unsigned long ioc_needs_fdc = 0;
99 /* global count of IOMMUs in the system */
100 static unsigned int global_ioc_cnt = 0;
102 /* PA8700 (Piranha 2.2) bug workaround */
103 static unsigned long piranha_bad_128k = 0;
105 /* Looks nice and keeps the compiler happy */
106 #define SBA_DEV(d) ((struct sba_device *) (d))
108 #ifdef CONFIG_AGP_PARISC
109 #define SBA_AGP_SUPPORT
110 #endif /*CONFIG_AGP_PARISC*/
112 #ifdef SBA_AGP_SUPPORT
113 static int sba_reserve_agpgart = 1;
114 module_param(sba_reserve_agpgart, int, 0444);
115 MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART");
119 /************************************
120 ** SBA register read and write support
122 ** BE WARNED: register writes are posted.
123 ** (ie follow writes which must reach HW with a read)
125 ** Superdome (in particular, REO) allows only 64-bit CSR accesses.
127 #define READ_REG32(addr) readl(addr)
128 #define READ_REG64(addr) readq(addr)
129 #define WRITE_REG32(val, addr) writel((val), (addr))
130 #define WRITE_REG64(val, addr) writeq((val), (addr))
133 #define READ_REG(addr) READ_REG64(addr)
134 #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
136 #define READ_REG(addr) READ_REG32(addr)
137 #define WRITE_REG(value, addr) WRITE_REG32(value, addr)
140 #ifdef DEBUG_SBA_INIT
142 /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
145 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
146 * @hpa: base address of the sba
148 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
149 * IO Adapter (aka Bus Converter).
152 sba_dump_ranges(void __iomem *hpa)
154 DBG_INIT("SBA at 0x%p\n", hpa);
155 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
156 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
157 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
159 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
160 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
161 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
165 * sba_dump_tlb - debugging only - print IOMMU operating parameters
166 * @hpa: base address of the IOMMU
168 * Print the size/location of the IO MMU PDIR.
170 static void sba_dump_tlb(void __iomem *hpa)
172 DBG_INIT("IO TLB at 0x%p\n", hpa);
173 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
174 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
175 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
176 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
180 #define sba_dump_ranges(x)
181 #define sba_dump_tlb(x)
182 #endif /* DEBUG_SBA_INIT */
185 #ifdef ASSERT_PDIR_SANITY
188 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
189 * @ioc: IO MMU structure which owns the pdir we are interested in.
190 * @msg: text to print ont the output line.
193 * Print one entry of the IO MMU PDIR in human readable form.
196 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
198 /* start printing from lowest pde in rval */
199 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
200 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
203 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
205 rptr, pide & (BITS_PER_LONG - 1), *rptr);
208 while (rcnt < BITS_PER_LONG) {
209 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
210 (rcnt == (pide & (BITS_PER_LONG - 1)))
216 printk(KERN_DEBUG "%s", msg);
221 * sba_check_pdir - debugging only - consistency checker
222 * @ioc: IO MMU structure which owns the pdir we are interested in.
223 * @msg: text to print ont the output line.
225 * Verify the resource map and pdir state is consistent
228 sba_check_pdir(struct ioc *ioc, char *msg)
230 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
231 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
232 u64 *pptr = ioc->pdir_base; /* pdir ptr */
235 while (rptr < rptr_end) {
237 int rcnt = 32; /* number of bits we might check */
240 /* Get last byte and highest bit from that */
241 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
242 if ((rval ^ pde) & 0x80000000)
245 ** BUMMER! -- res_map != pdir --
246 ** Dump rval and matching pdir entries
248 sba_dump_pdir_entry(ioc, msg, pide);
252 rval <<= 1; /* try the next bit */
256 rptr++; /* look at next word of res_map */
258 /* It'd be nice if we always got here :^) */
264 * sba_dump_sg - debugging only - print Scatter-Gather list
265 * @ioc: IO MMU structure which owns the pdir we are interested in.
266 * @startsg: head of the SG list
267 * @nents: number of entries in SG list
269 * print the SG list so we can verify it's correct by hand.
272 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
274 while (nents-- > 0) {
275 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
277 (unsigned long) sg_dma_address(startsg),
279 sg_virt_addr(startsg), startsg->length);
284 #endif /* ASSERT_PDIR_SANITY */
289 /**************************************************************
291 * I/O Pdir Resource Management
293 * Bits set in the resource map are in use.
294 * Each bit can represent a number of pages.
295 * LSbs represent lower addresses (IOVA's).
297 ***************************************************************/
298 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
300 /* Convert from IOVP to IOVA and vice versa. */
303 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
304 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
305 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
307 /* only support Astro and ancestors. Saves a few cycles in key places */
308 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
309 #define SBA_IOVP(ioc,iova) (iova)
312 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
314 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
315 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
317 static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr,
318 unsigned int bitshiftcnt)
320 return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3)
325 * sba_search_bitmap - find free space in IO PDIR resource bitmap
326 * @ioc: IO MMU structure which owns the pdir we are interested in.
327 * @bits_wanted: number of entries we need.
329 * Find consecutive free bits in resource bitmap.
330 * Each bit represents one entry in the IO Pdir.
331 * Cool perf optimization: search for log2(size) bits at a time.
333 static SBA_INLINE unsigned long
334 sba_search_bitmap(struct ioc *ioc, struct device *dev,
335 unsigned long bits_wanted)
337 unsigned long *res_ptr = ioc->res_hint;
338 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
339 unsigned long pide = ~0UL, tpide;
340 unsigned long boundary_size;
344 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
345 1ULL << IOVP_SHIFT) >> IOVP_SHIFT;
347 #if defined(ZX1_SUPPORT)
348 BUG_ON(ioc->ibase & ~IOVP_MASK);
349 shift = ioc->ibase >> IOVP_SHIFT;
354 if (bits_wanted > (BITS_PER_LONG/2)) {
355 /* Search word at a time - no mask needed */
356 for(; res_ptr < res_end; ++res_ptr) {
357 tpide = ptr_to_pide(ioc, res_ptr, 0);
358 ret = iommu_is_span_boundary(tpide, bits_wanted,
361 if ((*res_ptr == 0) && !ret) {
362 *res_ptr = RESMAP_MASK(bits_wanted);
367 /* point to the next word on next pass */
369 ioc->res_bitshift = 0;
372 ** Search the resource bit map on well-aligned values.
373 ** "o" is the alignment.
374 ** We need the alignment to invalidate I/O TLB using
375 ** SBA HW features in the unmap path.
377 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
378 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o);
381 if (bitshiftcnt >= BITS_PER_LONG) {
385 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
387 DBG_RES("%s() o %ld %p", __func__, o, res_ptr);
388 while(res_ptr < res_end)
390 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
392 tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt);
393 ret = iommu_is_span_boundary(tpide, bits_wanted,
396 if ((((*res_ptr) & mask) == 0) && !ret) {
397 *res_ptr |= mask; /* mark resources busy! */
404 mask = RESMAP_MASK(bits_wanted);
409 /* look in the same word on the next pass */
410 ioc->res_bitshift = bitshiftcnt + bits_wanted;
414 if (res_end <= res_ptr) {
415 ioc->res_hint = (unsigned long *) ioc->res_map;
416 ioc->res_bitshift = 0;
418 ioc->res_hint = res_ptr;
425 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
426 * @ioc: IO MMU structure which owns the pdir we are interested in.
427 * @size: number of bytes to create a mapping for
429 * Given a size, find consecutive unmarked and then mark those bits in the
433 sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
435 unsigned int pages_needed = size >> IOVP_SHIFT;
436 #ifdef SBA_COLLECT_STATS
437 unsigned long cr_start = mfctl(16);
441 pide = sba_search_bitmap(ioc, dev, pages_needed);
442 if (pide >= (ioc->res_size << 3)) {
443 pide = sba_search_bitmap(ioc, dev, pages_needed);
444 if (pide >= (ioc->res_size << 3))
445 panic("%s: I/O MMU @ %p is out of mapping resources\n",
446 __FILE__, ioc->ioc_hpa);
449 #ifdef ASSERT_PDIR_SANITY
450 /* verify the first enable bit is clear */
451 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
452 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
456 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
457 __func__, size, pages_needed, pide,
458 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
461 #ifdef SBA_COLLECT_STATS
463 unsigned long cr_end = mfctl(16);
464 unsigned long tmp = cr_end - cr_start;
465 /* check for roll over */
466 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
468 ioc->avg_search[ioc->avg_idx++] = cr_start;
469 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
471 ioc->used_pages += pages_needed;
479 * sba_free_range - unmark bits in IO PDIR resource bitmap
480 * @ioc: IO MMU structure which owns the pdir we are interested in.
481 * @iova: IO virtual address which was previously allocated.
482 * @size: number of bytes to create a mapping for
484 * clear bits in the ioc's resource map
486 static SBA_INLINE void
487 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
489 unsigned long iovp = SBA_IOVP(ioc, iova);
490 unsigned int pide = PDIR_INDEX(iovp);
491 unsigned int ridx = pide >> 3; /* convert bit to byte address */
492 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
494 int bits_not_wanted = size >> IOVP_SHIFT;
496 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
497 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
499 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
500 __func__, (uint) iova, size,
501 bits_not_wanted, m, pide, res_ptr, *res_ptr);
503 #ifdef SBA_COLLECT_STATS
504 ioc->used_pages -= bits_not_wanted;
511 /**************************************************************
513 * "Dynamic DMA Mapping" support (aka "Coherent I/O")
515 ***************************************************************/
517 #ifdef SBA_HINT_SUPPORT
518 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
521 typedef unsigned long space_t;
522 #define KERNEL_SPACE 0
525 * sba_io_pdir_entry - fill in one IO PDIR entry
526 * @pdir_ptr: pointer to IO PDIR entry
527 * @sid: process Space ID - currently only support KERNEL_SPACE
528 * @vba: Virtual CPU address of buffer to map
529 * @hint: DMA hint set to use for this mapping
531 * SBA Mapping Routine
533 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
534 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
536 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
537 * for Astro/Ike looks like:
541 * +-+---------------------+----------------------------------+----+--------+
542 * |V| U | PPN[43:12] | U | VI |
543 * +-+---------------------+----------------------------------+----+--------+
545 * Pluto is basically identical, supports fewer physical address bits:
548 * +-+------------------------+-------------------------------+----+--------+
549 * |V| U | PPN[39:12] | U | VI |
550 * +-+------------------------+-------------------------------+----+--------+
552 * V == Valid Bit (Most Significant Bit is bit 0)
554 * PPN == Physical Page Number
555 * VI == Virtual Index (aka Coherent Index)
557 * LPA instruction output is put into PPN field.
558 * LCI (Load Coherence Index) instruction provides the "VI" bits.
560 * We pre-swap the bytes since PCX-W is Big Endian and the
561 * IOMMU uses little endian for the pdir.
564 static void SBA_INLINE
565 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
568 u64 pa; /* physical address */
569 register unsigned ci; /* coherent index */
571 pa = virt_to_phys(vba);
575 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
576 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */
578 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
579 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
582 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
583 * (bit #61, big endian), we have to flush and sync every time
584 * IO-PDIR is changed in Ike/Astro.
587 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
592 * sba_mark_invalid - invalidate one or more IO PDIR entries
593 * @ioc: IO MMU structure which owns the pdir we are interested in.
594 * @iova: IO Virtual Address mapped earlier
595 * @byte_cnt: number of bytes this mapping covers.
597 * Marking the IO PDIR entry(ies) as Invalid and invalidate
598 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
599 * is to purge stale entries in the IO TLB when unmapping entries.
601 * The PCOM register supports purging of multiple pages, with a minium
602 * of 1 page and a maximum of 2GB. Hardware requires the address be
603 * aligned to the size of the range being purged. The size of the range
604 * must be a power of 2. The "Cool perf optimization" in the
605 * allocation routine helps keep that true.
607 static SBA_INLINE void
608 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
610 u32 iovp = (u32) SBA_IOVP(ioc,iova);
611 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
613 #ifdef ASSERT_PDIR_SANITY
614 /* Assert first pdir entry is set.
616 ** Even though this is a big-endian machine, the entries
617 ** in the iopdir are little endian. That's why we look at
618 ** the byte at +7 instead of at +0.
620 if (0x80 != (((u8 *) pdir_ptr)[7])) {
621 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
625 if (byte_cnt > IOVP_SIZE)
628 unsigned long entries_per_cacheline = ioc_needs_fdc ?
629 L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
630 - (unsigned long) pdir_ptr;
634 /* set "size" field for PCOM */
635 iovp |= get_order(byte_cnt) + PAGE_SHIFT;
638 /* clear I/O Pdir entry "valid" bit first */
639 ((u8 *) pdir_ptr)[7] = 0;
641 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
643 entries_per_cacheline = L1_CACHE_SHIFT - 3;
647 byte_cnt -= IOVP_SIZE;
648 } while (byte_cnt > IOVP_SIZE);
650 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
653 ** clear I/O PDIR entry "valid" bit.
654 ** We have to R/M/W the cacheline regardless how much of the
655 ** pdir entry that we clobber.
656 ** The rest of the entry would be useful for debugging if we
657 ** could dump core on HPMC.
659 ((u8 *) pdir_ptr)[7] = 0;
661 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
663 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
667 * sba_dma_supported - PCI driver can query DMA support
668 * @dev: instance of PCI owned by the driver that's asking
669 * @mask: number of address bits this PCI device can handle
671 * See Documentation/PCI/PCI-DMA-mapping.txt
673 static int sba_dma_supported( struct device *dev, u64 mask)
678 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
683 /* Documentation/PCI/PCI-DMA-mapping.txt tells drivers to try 64-bit
684 * first, then fall back to 32-bit if that fails.
685 * We are just "encouraging" 32-bit DMA masks here since we can
686 * never allow IOMMU bypass unless we add special support for ZX1.
694 * check if mask is >= than the current max IO Virt Address
695 * The max IO Virt address will *always* < 30 bits.
697 return((int)(mask >= (ioc->ibase - 1 +
698 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
703 * sba_map_single - map one buffer and return IOVA for DMA
704 * @dev: instance of PCI owned by the driver that's asking.
705 * @addr: driver buffer to map.
706 * @size: number of bytes to map in driver buffer.
707 * @direction: R/W or both.
709 * See Documentation/PCI/PCI-DMA-mapping.txt
712 sba_map_single(struct device *dev, void *addr, size_t size,
713 enum dma_data_direction direction)
724 /* save offset bits */
725 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
727 /* round up to nearest IOVP_SIZE */
728 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
730 spin_lock_irqsave(&ioc->res_lock, flags);
731 #ifdef ASSERT_PDIR_SANITY
732 sba_check_pdir(ioc,"Check before sba_map_single()");
735 #ifdef SBA_COLLECT_STATS
736 ioc->msingle_calls++;
737 ioc->msingle_pages += size >> IOVP_SHIFT;
739 pide = sba_alloc_range(ioc, dev, size);
740 iovp = (dma_addr_t) pide << IOVP_SHIFT;
742 DBG_RUN("%s() 0x%p -> 0x%lx\n",
743 __func__, addr, (long) iovp | offset);
745 pdir_start = &(ioc->pdir_base[pide]);
748 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
750 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
752 (u8) (((u8 *) pdir_start)[7]),
753 (u8) (((u8 *) pdir_start)[6]),
754 (u8) (((u8 *) pdir_start)[5]),
755 (u8) (((u8 *) pdir_start)[4]),
756 (u8) (((u8 *) pdir_start)[3]),
757 (u8) (((u8 *) pdir_start)[2]),
758 (u8) (((u8 *) pdir_start)[1]),
759 (u8) (((u8 *) pdir_start)[0])
767 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
769 asm volatile("sync" : : );
771 #ifdef ASSERT_PDIR_SANITY
772 sba_check_pdir(ioc,"Check after sba_map_single()");
774 spin_unlock_irqrestore(&ioc->res_lock, flags);
776 /* form complete address */
777 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
782 * sba_unmap_single - unmap one IOVA and free resources
783 * @dev: instance of PCI owned by the driver that's asking.
784 * @iova: IOVA of driver buffer previously mapped.
785 * @size: number of bytes mapped in driver buffer.
786 * @direction: R/W or both.
788 * See Documentation/PCI/PCI-DMA-mapping.txt
791 sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
792 enum dma_data_direction direction)
795 #if DELAYED_RESOURCE_CNT > 0
796 struct sba_dma_pair *d;
801 DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size);
804 offset = iova & ~IOVP_MASK;
805 iova ^= offset; /* clear offset bits */
807 size = ALIGN(size, IOVP_SIZE);
809 spin_lock_irqsave(&ioc->res_lock, flags);
811 #ifdef SBA_COLLECT_STATS
812 ioc->usingle_calls++;
813 ioc->usingle_pages += size >> IOVP_SHIFT;
816 sba_mark_invalid(ioc, iova, size);
818 #if DELAYED_RESOURCE_CNT > 0
819 /* Delaying when we re-use a IO Pdir entry reduces the number
820 * of MMIO reads needed to flush writes to the PCOM register.
822 d = &(ioc->saved[ioc->saved_cnt]);
825 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
826 int cnt = ioc->saved_cnt;
828 sba_free_range(ioc, d->iova, d->size);
833 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
835 #else /* DELAYED_RESOURCE_CNT == 0 */
836 sba_free_range(ioc, iova, size);
838 /* If fdc's were issued, force fdc's to be visible now */
840 asm volatile("sync" : : );
842 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
843 #endif /* DELAYED_RESOURCE_CNT == 0 */
845 spin_unlock_irqrestore(&ioc->res_lock, flags);
847 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
848 ** For Astro based systems this isn't a big deal WRT performance.
849 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
850 ** we don't need the syncdma. The issue here is I/O MMU cachelines
851 ** are *not* coherent in all cases. May be hwrev dependent.
852 ** Need to investigate more.
853 asm volatile("syncdma");
859 * sba_alloc_consistent - allocate/map shared mem for DMA
860 * @hwdev: instance of PCI owned by the driver that's asking.
861 * @size: number of bytes mapped in driver buffer.
862 * @dma_handle: IOVA of new buffer.
864 * See Documentation/PCI/PCI-DMA-mapping.txt
866 static void *sba_alloc_consistent(struct device *hwdev, size_t size,
867 dma_addr_t *dma_handle, gfp_t gfp)
872 /* only support PCI */
877 ret = (void *) __get_free_pages(gfp, get_order(size));
880 memset(ret, 0, size);
881 *dma_handle = sba_map_single(hwdev, ret, size, 0);
889 * sba_free_consistent - free/unmap shared mem for DMA
890 * @hwdev: instance of PCI owned by the driver that's asking.
891 * @size: number of bytes mapped in driver buffer.
892 * @vaddr: virtual address IOVA of "consistent" buffer.
893 * @dma_handler: IO virtual address of "consistent" buffer.
895 * See Documentation/PCI/PCI-DMA-mapping.txt
898 sba_free_consistent(struct device *hwdev, size_t size, void *vaddr,
899 dma_addr_t dma_handle)
901 sba_unmap_single(hwdev, dma_handle, size, 0);
902 free_pages((unsigned long) vaddr, get_order(size));
907 ** Since 0 is a valid pdir_base index value, can't use that
908 ** to determine if a value is valid or not. Use a flag to indicate
909 ** the SG list entry contains a valid pdir index.
911 #define PIDE_FLAG 0x80000000UL
913 #ifdef SBA_COLLECT_STATS
914 #define IOMMU_MAP_STATS
916 #include "iommu-helpers.h"
918 #ifdef DEBUG_LARGE_SG_ENTRIES
924 * sba_map_sg - map Scatter/Gather list
925 * @dev: instance of PCI owned by the driver that's asking.
926 * @sglist: array of buffer/length pairs
927 * @nents: number of entries in list
928 * @direction: R/W or both.
930 * See Documentation/PCI/PCI-DMA-mapping.txt
933 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
934 enum dma_data_direction direction)
937 int coalesced, filled = 0;
940 DBG_RUN_SG("%s() START %d entries\n", __func__, nents);
944 /* Fast path single entry scatterlists. */
946 sg_dma_address(sglist) = sba_map_single(dev,
947 (void *)sg_virt_addr(sglist),
948 sglist->length, direction);
949 sg_dma_len(sglist) = sglist->length;
953 spin_lock_irqsave(&ioc->res_lock, flags);
955 #ifdef ASSERT_PDIR_SANITY
956 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
958 sba_dump_sg(ioc, sglist, nents);
959 panic("Check before sba_map_sg()");
963 #ifdef SBA_COLLECT_STATS
968 ** First coalesce the chunks and allocate I/O pdir space
970 ** If this is one DMA stream, we can properly map using the
971 ** correct virtual address associated with each DMA page.
972 ** w/o this association, we wouldn't have coherent DMA!
973 ** Access to the virtual address is what forces a two pass algorithm.
975 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range);
978 ** Program the I/O Pdir
980 ** map the virtual addresses to the I/O Pdir
981 ** o dma_address will contain the pdir index
982 ** o dma_len will contain the number of bytes to map
983 ** o address contains the virtual address.
985 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
987 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
989 asm volatile("sync" : : );
991 #ifdef ASSERT_PDIR_SANITY
992 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
994 sba_dump_sg(ioc, sglist, nents);
995 panic("Check after sba_map_sg()\n");
999 spin_unlock_irqrestore(&ioc->res_lock, flags);
1001 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled);
1008 * sba_unmap_sg - unmap Scatter/Gather list
1009 * @dev: instance of PCI owned by the driver that's asking.
1010 * @sglist: array of buffer/length pairs
1011 * @nents: number of entries in list
1012 * @direction: R/W or both.
1014 * See Documentation/PCI/PCI-DMA-mapping.txt
1017 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
1018 enum dma_data_direction direction)
1021 #ifdef ASSERT_PDIR_SANITY
1022 unsigned long flags;
1025 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1026 __func__, nents, sg_virt_addr(sglist), sglist->length);
1030 #ifdef SBA_COLLECT_STATS
1034 #ifdef ASSERT_PDIR_SANITY
1035 spin_lock_irqsave(&ioc->res_lock, flags);
1036 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1037 spin_unlock_irqrestore(&ioc->res_lock, flags);
1040 while (sg_dma_len(sglist) && nents--) {
1042 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction);
1043 #ifdef SBA_COLLECT_STATS
1044 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1045 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1050 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents);
1052 #ifdef ASSERT_PDIR_SANITY
1053 spin_lock_irqsave(&ioc->res_lock, flags);
1054 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1055 spin_unlock_irqrestore(&ioc->res_lock, flags);
1060 static struct hppa_dma_ops sba_ops = {
1061 .dma_supported = sba_dma_supported,
1062 .alloc_consistent = sba_alloc_consistent,
1063 .alloc_noncoherent = sba_alloc_consistent,
1064 .free_consistent = sba_free_consistent,
1065 .map_single = sba_map_single,
1066 .unmap_single = sba_unmap_single,
1067 .map_sg = sba_map_sg,
1068 .unmap_sg = sba_unmap_sg,
1069 .dma_sync_single_for_cpu = NULL,
1070 .dma_sync_single_for_device = NULL,
1071 .dma_sync_sg_for_cpu = NULL,
1072 .dma_sync_sg_for_device = NULL,
1076 /**************************************************************************
1078 ** SBA PAT PDC support
1080 ** o call pdc_pat_cell_module()
1081 ** o store ranges in PCI "resource" structures
1083 **************************************************************************/
1086 sba_get_pat_resources(struct sba_device *sba_dev)
1090 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1091 ** PAT PDC to program the SBA/LBA directed range registers...this
1092 ** burden may fall on the LBA code since it directly supports the
1093 ** PCI subsystem. It's not clear yet. - ggg
1095 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1097 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1098 Tells where the dvi bits are located in the address.
1099 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1105 /**************************************************************
1107 * Initialization and claim
1109 ***************************************************************/
1110 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1111 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1113 sba_alloc_pdir(unsigned int pdir_size)
1115 unsigned long pdir_base;
1116 unsigned long pdir_order = get_order(pdir_size);
1118 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
1119 if (NULL == (void *) pdir_base) {
1120 panic("%s() could not allocate I/O Page Table\n",
1124 /* If this is not PA8700 (PCX-W2)
1125 ** OR newer than ver 2.2
1126 ** OR in a system that doesn't need VINDEX bits from SBA,
1128 ** then we aren't exposed to the HW bug.
1130 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1131 || (boot_cpu_data.pdc.versions > 0x202)
1132 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1133 return (void *) pdir_base;
1136 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1138 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1139 * Ike/Astro can cause silent data corruption. This is only
1140 * a problem if the I/O PDIR is located in memory such that
1141 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1143 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1144 * right physical address, we can either avoid (IOPDIR <= 1MB)
1145 * or minimize (2MB IO Pdir) the problem if we restrict the
1146 * IO Pdir to a maximum size of 2MB-128K (1902K).
1148 * Because we always allocate 2^N sized IO pdirs, either of the
1149 * "bad" regions will be the last 128K if at all. That's easy
1153 if (pdir_order <= (19-12)) {
1154 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1155 /* allocate a new one on 512k alignment */
1156 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1157 /* release original */
1158 free_pages(pdir_base, pdir_order);
1160 pdir_base = new_pdir;
1162 /* release excess */
1163 while (pdir_order < (19-12)) {
1164 new_pdir += pdir_size;
1165 free_pages(new_pdir, pdir_order);
1173 ** Needs to be aligned on an "odd" 1MB boundary.
1175 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1177 /* release original */
1178 free_pages( pdir_base, pdir_order);
1180 /* release first 1MB */
1181 free_pages(new_pdir, 20-12);
1183 pdir_base = new_pdir + 1024*1024;
1185 if (pdir_order > (20-12)) {
1189 ** Flag tells init_bitmap() to mark bad 128k as used
1190 ** and to reduce the size by 128k.
1192 piranha_bad_128k = 1;
1194 new_pdir += 3*1024*1024;
1195 /* release last 1MB */
1196 free_pages(new_pdir, 20-12);
1198 /* release unusable 128KB */
1199 free_pages(new_pdir - 128*1024 , 17-12);
1201 pdir_size -= 128*1024;
1205 memset((void *) pdir_base, 0, pdir_size);
1206 return (void *) pdir_base;
1209 struct ibase_data_struct {
1214 static int setup_ibase_imask_callback(struct device *dev, void *data)
1216 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
1217 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1218 struct parisc_device *lba = to_parisc_device(dev);
1219 struct ibase_data_struct *ibd = data;
1220 int rope_num = (lba->hpa.start >> 13) & 0xf;
1221 if (rope_num >> 3 == ibd->ioc_num)
1222 lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask);
1226 /* setup Mercury or Elroy IBASE/IMASK registers. */
1228 setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1230 struct ibase_data_struct ibase_data = {
1235 device_for_each_child(&sba->dev, &ibase_data,
1236 setup_ibase_imask_callback);
1239 #ifdef SBA_AGP_SUPPORT
1241 sba_ioc_find_quicksilver(struct device *dev, void *data)
1243 int *agp_found = data;
1244 struct parisc_device *lba = to_parisc_device(dev);
1246 if (IS_QUICKSILVER(lba))
1253 sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1255 u32 iova_space_mask;
1256 u32 iova_space_size;
1257 int iov_order, tcnfg;
1258 #ifdef SBA_AGP_SUPPORT
1262 ** Firmware programs the base and size of a "safe IOVA space"
1263 ** (one that doesn't overlap memory or LMMIO space) in the
1264 ** IBASE and IMASK registers.
1266 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
1267 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
1269 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
1270 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1271 iova_space_size /= 2;
1275 ** iov_order is always based on a 1GB IOVA space since we want to
1276 ** turn on the other half for AGP GART.
1278 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
1279 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1281 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
1282 __func__, ioc->ioc_hpa, iova_space_size >> 20,
1283 iov_order + PAGE_SHIFT);
1285 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1286 get_order(ioc->pdir_size));
1287 if (!ioc->pdir_base)
1288 panic("Couldn't allocate I/O Page Table\n");
1290 memset(ioc->pdir_base, 0, ioc->pdir_size);
1292 DBG_INIT("%s() pdir %p size %x\n",
1293 __func__, ioc->pdir_base, ioc->pdir_size);
1295 #ifdef SBA_HINT_SUPPORT
1296 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1297 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1299 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1300 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1303 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
1304 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1306 /* build IMASK for IOC and Elroy */
1307 iova_space_mask = 0xffffffff;
1308 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1309 ioc->imask = iova_space_mask;
1311 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1313 sba_dump_tlb(ioc->ioc_hpa);
1315 setup_ibase_imask(sba, ioc, ioc_num);
1317 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
1321 ** Setting the upper bits makes checking for bypass addresses
1322 ** a little faster later on.
1324 ioc->imask |= 0xFFFFFFFF00000000UL;
1327 /* Set I/O PDIR Page size to system page size */
1328 switch (PAGE_SHIFT) {
1329 case 12: tcnfg = 0; break; /* 4K */
1330 case 13: tcnfg = 1; break; /* 8K */
1331 case 14: tcnfg = 2; break; /* 16K */
1332 case 16: tcnfg = 3; break; /* 64K */
1334 panic(__FILE__ "Unsupported system page size %d",
1338 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1341 ** Program the IOC's ibase and enable IOVA translation
1342 ** Bit zero == enable bit.
1344 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1347 ** Clear I/O TLB of any possible entries.
1348 ** (Yes. This is a bit paranoid...but so what)
1350 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
1352 #ifdef SBA_AGP_SUPPORT
1355 ** If an AGP device is present, only use half of the IOV space
1356 ** for PCI DMA. Unfortunately we can't know ahead of time
1357 ** whether GART support will actually be used, for now we
1358 ** can just key on any AGP device found in the system.
1359 ** We program the next pdir index after we stop w/ a key for
1360 ** the GART code to handshake on.
1362 device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver);
1364 if (agp_found && sba_reserve_agpgart) {
1365 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
1366 __func__, (iova_space_size/2) >> 20);
1367 ioc->pdir_size /= 2;
1368 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
1370 #endif /*SBA_AGP_SUPPORT*/
1374 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1376 u32 iova_space_size, iova_space_mask;
1377 unsigned int pdir_size, iov_order;
1380 ** Determine IOVA Space size from memory size.
1382 ** Ideally, PCI drivers would register the maximum number
1383 ** of DMA they can have outstanding for each device they
1384 ** own. Next best thing would be to guess how much DMA
1385 ** can be outstanding based on PCI Class/sub-class. Both
1386 ** methods still require some "extra" to support PCI
1387 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1389 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1390 ** for DMA hints - ergo only 30 bits max.
1393 iova_space_size = (u32) (num_physpages/global_ioc_cnt);
1395 /* limit IOVA space size to 1MB-1GB */
1396 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1397 iova_space_size = 1 << (20 - PAGE_SHIFT);
1399 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1400 iova_space_size = 1 << (30 - PAGE_SHIFT);
1404 ** iova space must be log2() in size.
1405 ** thus, pdir/res_map will also be log2().
1406 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1408 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1410 /* iova_space_size is now bytes, not pages */
1411 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1413 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1415 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
1418 (unsigned long) num_physpages >> (20 - PAGE_SHIFT),
1419 iova_space_size>>20,
1420 iov_order + PAGE_SHIFT);
1422 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1424 DBG_INIT("%s() pdir %p size %x\n",
1425 __func__, ioc->pdir_base, pdir_size);
1427 #ifdef SBA_HINT_SUPPORT
1428 /* FIXME : DMA HINTs not used */
1429 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1430 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1432 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1433 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1436 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1438 /* build IMASK for IOC and Elroy */
1439 iova_space_mask = 0xffffffff;
1440 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1443 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1444 ** ibase=0, imask=0xFE000000, size=0x2000000.
1447 ioc->imask = iova_space_mask; /* save it */
1449 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1452 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1453 __func__, ioc->ibase, ioc->imask);
1456 ** FIXME: Hint registers are programmed with default hint
1457 ** values during boot, so hints should be sane even if we
1458 ** can't reprogram them the way drivers want.
1461 setup_ibase_imask(sba, ioc, ioc_num);
1464 ** Program the IOC's ibase and enable IOVA translation
1466 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1467 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1469 /* Set I/O PDIR Page size to 4K */
1470 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG);
1473 ** Clear I/O TLB of any possible entries.
1474 ** (Yes. This is a bit paranoid...but so what)
1476 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1478 ioc->ibase = 0; /* used by SBA_IOVA and related macros */
1480 DBG_INIT("%s() DONE\n", __func__);
1485 /**************************************************************************
1487 ** SBA initialization code (HW and SW)
1489 ** o identify SBA chip itself
1490 ** o initialize SBA chip modes (HardFail)
1491 ** o initialize SBA chip modes (HardFail)
1492 ** o FIXME: initialize DMA hints for reasonable defaults
1494 **************************************************************************/
1496 static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
1498 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
1501 static void sba_hw_init(struct sba_device *sba_dev)
1507 if (!is_pdc_pat()) {
1508 /* Shutdown the USB controller on Astro-based workstations.
1509 ** Once we reprogram the IOMMU, the next DMA performed by
1510 ** USB will HPMC the box. USB is only enabled if a
1511 ** keyboard is present and found.
1513 ** With serial console, j6k v5.0 firmware says:
1514 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
1516 ** FIXME: Using GFX+USB console at power up but direct
1517 ** linux to serial console is still broken.
1518 ** USB could generate DMA so we must reset USB.
1519 ** The proper sequence would be:
1520 ** o block console output
1521 ** o reset USB device
1522 ** o reprogram serial port
1523 ** o unblock console output
1525 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
1526 pdc_io_reset_devices();
1533 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
1534 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
1537 ** Need to deal with DMA from LAN.
1538 ** Maybe use page zero boot device as a handle to talk
1539 ** to PDC about which device to shutdown.
1541 ** Netbooting, j6k v5.0 firmware says:
1542 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
1543 ** ARGH! invalid class.
1545 if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
1546 && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
1551 if (!IS_PLUTO(sba_dev->dev)) {
1552 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1553 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1554 __func__, sba_dev->sba_hpa, ioc_ctl);
1555 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1556 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
1557 /* j6700 v1.6 firmware sets 0x294f */
1558 /* A500 firmware sets 0x4d */
1560 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1562 #ifdef DEBUG_SBA_INIT
1563 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1564 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1568 if (IS_ASTRO(sba_dev->dev)) {
1570 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
1573 sba_dev->chip_resv.name = "Astro Intr Ack";
1574 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
1575 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
1576 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1579 } else if (IS_PLUTO(sba_dev->dev)) {
1582 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
1585 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
1586 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
1587 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
1588 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1591 sba_dev->iommu_resv.name = "IOVA Space";
1592 sba_dev->iommu_resv.start = 0x40000000UL;
1593 sba_dev->iommu_resv.end = 0x50000000UL - 1;
1594 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
1598 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
1599 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
1602 /* TODO - LOOKUP Ike/Stretch chipset mem map */
1604 /* XXX: What about Reo Grande? */
1606 sba_dev->num_ioc = num_ioc;
1607 for (i = 0; i < num_ioc; i++) {
1608 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
1611 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
1614 * Clear ROPE(N)_CONFIG AO bit.
1615 * Disables "NT Ordering" (~= !"Relaxed Ordering")
1616 * Overrides bit 1 in DMA Hint Sets.
1617 * Improves netperf UDP_STREAM by ~10% for bcm5701.
1619 if (IS_PLUTO(sba_dev->dev)) {
1620 void __iomem *rope_cfg;
1621 unsigned long cfg_val;
1623 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
1624 cfg_val = READ_REG(rope_cfg);
1625 cfg_val &= ~IOC_ROPE_AO;
1626 WRITE_REG(cfg_val, rope_cfg);
1630 ** Make sure the box crashes on rope errors.
1632 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
1635 /* flush out the last writes */
1636 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1638 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1640 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
1641 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
1643 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1644 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
1645 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
1648 if (IS_PLUTO(sba_dev->dev)) {
1649 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
1651 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1657 sba_common_init(struct sba_device *sba_dev)
1661 /* add this one to the head of the list (order doesn't matter)
1662 ** This will be useful for debugging - especially if we get coredumps
1664 sba_dev->next = sba_list;
1667 for(i=0; i< sba_dev->num_ioc; i++) {
1669 #ifdef DEBUG_DMB_TRAP
1670 extern void iterate_pages(unsigned long , unsigned long ,
1671 void (*)(pte_t * , unsigned long),
1673 void set_data_memory_break(pte_t * , unsigned long);
1675 /* resource map size dictated by pdir_size */
1676 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1678 /* Second part of PIRANHA BUG */
1679 if (piranha_bad_128k) {
1680 res_size -= (128*1024)/sizeof(u64);
1683 res_size >>= 3; /* convert bit count to byte count */
1684 DBG_INIT("%s() res_size 0x%x\n",
1685 __func__, res_size);
1687 sba_dev->ioc[i].res_size = res_size;
1688 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1690 #ifdef DEBUG_DMB_TRAP
1691 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1692 set_data_memory_break, 0);
1695 if (NULL == sba_dev->ioc[i].res_map)
1697 panic("%s:%s() could not allocate resource map\n",
1698 __FILE__, __func__ );
1701 memset(sba_dev->ioc[i].res_map, 0, res_size);
1702 /* next available IOVP - circular search */
1703 sba_dev->ioc[i].res_hint = (unsigned long *)
1704 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1706 #ifdef ASSERT_PDIR_SANITY
1707 /* Mark first bit busy - ie no IOVA 0 */
1708 sba_dev->ioc[i].res_map[0] = 0x80;
1709 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1712 /* Third (and last) part of PIRANHA BUG */
1713 if (piranha_bad_128k) {
1714 /* region from +1408K to +1536 is un-usable. */
1716 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1717 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1718 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1719 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1721 /* mark that part of the io pdir busy */
1722 while (p_start < p_end)
1727 #ifdef DEBUG_DMB_TRAP
1728 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1729 set_data_memory_break, 0);
1730 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1731 set_data_memory_break, 0);
1734 DBG_INIT("%s() %d res_map %x %p\n",
1735 __func__, i, res_size, sba_dev->ioc[i].res_map);
1738 spin_lock_init(&sba_dev->sba_lock);
1739 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1741 #ifdef DEBUG_SBA_INIT
1743 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1744 * (bit #61, big endian), we have to flush and sync every time
1745 * IO-PDIR is changed in Ike/Astro.
1747 if (ioc_needs_fdc) {
1748 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1750 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1755 #ifdef CONFIG_PROC_FS
1756 static int sba_proc_info(struct seq_file *m, void *p)
1758 struct sba_device *sba_dev = sba_list;
1759 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1760 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
1761 #ifdef SBA_COLLECT_STATS
1762 unsigned long avg = 0, min, max;
1766 len += seq_printf(m, "%s rev %d.%d\n",
1768 (sba_dev->hw_rev & 0x7) + 1,
1769 (sba_dev->hw_rev & 0x18) >> 3
1771 len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
1772 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1775 len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
1776 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
1778 len += seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
1779 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
1780 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
1781 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)
1785 len += seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", i,
1786 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
1787 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
1788 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)
1791 #ifdef SBA_COLLECT_STATS
1792 len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
1793 total_pages - ioc->used_pages, ioc->used_pages,
1794 (int) (ioc->used_pages * 100 / total_pages));
1796 min = max = ioc->avg_search[0];
1797 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1798 avg += ioc->avg_search[i];
1799 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1800 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1802 avg /= SBA_SEARCH_SAMPLE;
1803 len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1806 len += seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1807 ioc->msingle_calls, ioc->msingle_pages,
1808 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1810 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1811 min = ioc->usingle_calls;
1812 max = ioc->usingle_pages - ioc->usg_pages;
1813 len += seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1814 min, max, (int) ((max * 1000)/min));
1816 len += seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1817 ioc->msg_calls, ioc->msg_pages,
1818 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls));
1820 len += seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1821 ioc->usg_calls, ioc->usg_pages,
1822 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls));
1829 sba_proc_open(struct inode *i, struct file *f)
1831 return single_open(f, &sba_proc_info, NULL);
1834 static const struct file_operations sba_proc_fops = {
1835 .owner = THIS_MODULE,
1836 .open = sba_proc_open,
1838 .llseek = seq_lseek,
1839 .release = single_release,
1843 sba_proc_bitmap_info(struct seq_file *m, void *p)
1845 struct sba_device *sba_dev = sba_list;
1846 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1847 unsigned int *res_ptr = (unsigned int *)ioc->res_map;
1850 for (i = 0; i < (ioc->res_size/sizeof(unsigned int)); ++i, ++res_ptr) {
1852 len += seq_printf(m, "\n ");
1853 len += seq_printf(m, " %08x", *res_ptr);
1855 len += seq_printf(m, "\n");
1861 sba_proc_bitmap_open(struct inode *i, struct file *f)
1863 return single_open(f, &sba_proc_bitmap_info, NULL);
1866 static const struct file_operations sba_proc_bitmap_fops = {
1867 .owner = THIS_MODULE,
1868 .open = sba_proc_bitmap_open,
1870 .llseek = seq_lseek,
1871 .release = single_release,
1873 #endif /* CONFIG_PROC_FS */
1875 static struct parisc_device_id sba_tbl[] = {
1876 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
1877 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
1878 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
1879 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
1880 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
1884 static int sba_driver_callback(struct parisc_device *);
1886 static struct parisc_driver sba_driver = {
1887 .name = MODULE_NAME,
1888 .id_table = sba_tbl,
1889 .probe = sba_driver_callback,
1893 ** Determine if sba should claim this chip (return 0) or not (return 1).
1894 ** If so, initialize the chip and tell other partners in crime they
1897 static int sba_driver_callback(struct parisc_device *dev)
1899 struct sba_device *sba_dev;
1903 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE);
1904 #ifdef CONFIG_PROC_FS
1905 struct proc_dir_entry *root;
1908 sba_dump_ranges(sba_addr);
1910 /* Read HW Rev First */
1911 func_class = READ_REG(sba_addr + SBA_FCLASS);
1913 if (IS_ASTRO(dev)) {
1914 unsigned long fclass;
1915 static char astro_rev[]="Astro ?.?";
1917 /* Astro is broken...Read HW Rev First */
1918 fclass = READ_REG(sba_addr);
1920 astro_rev[6] = '1' + (char) (fclass & 0x7);
1921 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
1922 version = astro_rev;
1924 } else if (IS_IKE(dev)) {
1925 static char ike_rev[] = "Ike rev ?";
1926 ike_rev[8] = '0' + (char) (func_class & 0xff);
1928 } else if (IS_PLUTO(dev)) {
1929 static char pluto_rev[]="Pluto ?.?";
1930 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
1931 pluto_rev[8] = '0' + (char) (func_class & 0x0f);
1932 version = pluto_rev;
1934 static char reo_rev[] = "REO rev ?";
1935 reo_rev[8] = '0' + (char) (func_class & 0xff);
1939 if (!global_ioc_cnt) {
1940 global_ioc_cnt = count_parisc_driver(&sba_driver);
1942 /* Astro and Pluto have one IOC per SBA */
1943 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev)))
1944 global_ioc_cnt *= 2;
1947 printk(KERN_INFO "%s found %s at 0x%llx\n",
1948 MODULE_NAME, version, (unsigned long long)dev->hpa.start);
1950 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
1952 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
1956 parisc_set_drvdata(dev, sba_dev);
1958 for(i=0; i<MAX_IOC; i++)
1959 spin_lock_init(&(sba_dev->ioc[i].res_lock));
1962 sba_dev->hw_rev = func_class;
1963 sba_dev->name = dev->name;
1964 sba_dev->sba_hpa = sba_addr;
1966 sba_get_pat_resources(sba_dev);
1967 sba_hw_init(sba_dev);
1968 sba_common_init(sba_dev);
1970 hppa_dma_ops = &sba_ops;
1972 #ifdef CONFIG_PROC_FS
1973 switch (dev->id.hversion) {
1974 case PLUTO_MCKINLEY_PORT:
1975 root = proc_mckinley_root;
1977 case ASTRO_RUNWAY_PORT:
1978 case IKE_MERCED_PORT:
1980 root = proc_runway_root;
1984 proc_create("sba_iommu", 0, root, &sba_proc_fops);
1985 proc_create("sba_iommu-bitmap", 0, root, &sba_proc_bitmap_fops);
1993 ** One time initialization to let the world know the SBA was found.
1994 ** This is the only routine which is NOT static.
1995 ** Must be called exactly once before pci_init().
1997 void __init sba_init(void)
1999 register_parisc_driver(&sba_driver);
2004 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
2005 * @dev: The parisc device.
2007 * Returns the appropriate IOMMU data for the given parisc PCI controller.
2008 * This is cached and used later for PCI DMA Mapping.
2010 void * sba_get_iommu(struct parisc_device *pci_hba)
2012 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2013 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2014 char t = sba_dev->id.hw_type;
2015 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
2017 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
2019 return &(sba->ioc[iocnum]);
2024 * sba_directed_lmmio - return first directed LMMIO range routed to rope
2025 * @pa_dev: The parisc device.
2026 * @r: resource PCI host controller wants start/end fields assigned.
2028 * For the given parisc PCI controller, determine if any direct ranges
2029 * are routed down the corresponding rope.
2031 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
2033 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2034 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2035 char t = sba_dev->id.hw_type;
2037 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2039 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2041 r->start = r->end = 0;
2043 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
2044 for (i=0; i<4; i++) {
2046 void __iomem *reg = sba->sba_hpa + i*0x18;
2048 base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
2049 if ((base & 1) == 0)
2050 continue; /* not enabled */
2052 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
2054 if ((size & (ROPES_PER_IOC-1)) != rope)
2055 continue; /* directed down different rope */
2057 r->start = (base & ~1UL) | PCI_F_EXTEND;
2058 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
2059 r->end = r->start + size;
2065 * sba_distributed_lmmio - return portion of distributed LMMIO range
2066 * @pa_dev: The parisc device.
2067 * @r: resource PCI host controller wants start/end fields assigned.
2069 * For the given parisc PCI controller, return portion of distributed LMMIO
2070 * range. The distributed LMMIO is always present and it's just a question
2071 * of the base address and size of the range.
2073 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
2075 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2076 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2077 char t = sba_dev->id.hw_type;
2079 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2081 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2083 r->start = r->end = 0;
2085 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
2086 if ((base & 1) == 0) {
2087 BUG(); /* Gah! Distr Range wasn't enabled! */
2091 r->start = (base & ~1UL) | PCI_F_EXTEND;
2093 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
2094 r->start += rope * (size + 1); /* adjust base for this rope */
2095 r->end = r->start + size;