Merge gregkh@master.kernel.org:/home/rmk/linux-2.6-arm
[linux-2.6] / drivers / scsi / sata_vsc.c
1 /*
2  *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
3  *
4  *  Maintained by:  Jeremy Higdon @ SGI
5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
6  *                  on emails.
7  *
8  *  Copyright 2004 SGI
9  *
10  *  Bits from Jeff Garzik, Copyright RedHat, Inc.
11  *
12  *
13  *  This program is free software; you can redistribute it and/or modify
14  *  it under the terms of the GNU General Public License as published by
15  *  the Free Software Foundation; either version 2, or (at your option)
16  *  any later version.
17  *
18  *  This program is distributed in the hope that it will be useful,
19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21  *  GNU General Public License for more details.
22  *
23  *  You should have received a copy of the GNU General Public License
24  *  along with this program; see the file COPYING.  If not, write to
25  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26  *
27  *
28  *  libata documentation is available via 'make {ps|pdf}docs',
29  *  as Documentation/DocBook/libata.*
30  *
31  *  Vitesse hardware documentation presumably available under NDA.
32  *  Intel 31244 (same hardware interface) documentation presumably
33  *  available from http://developer.intel.com/
34  *
35  */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/device.h>
46 #include <scsi/scsi_host.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME        "sata_vsc"
50 #define DRV_VERSION     "2.0"
51
52 enum {
53         /* Interrupt register offsets (from chip base address) */
54         VSC_SATA_INT_STAT_OFFSET        = 0x00,
55         VSC_SATA_INT_MASK_OFFSET        = 0x04,
56
57         /* Taskfile registers offsets */
58         VSC_SATA_TF_CMD_OFFSET          = 0x00,
59         VSC_SATA_TF_DATA_OFFSET         = 0x00,
60         VSC_SATA_TF_ERROR_OFFSET        = 0x04,
61         VSC_SATA_TF_FEATURE_OFFSET      = 0x06,
62         VSC_SATA_TF_NSECT_OFFSET        = 0x08,
63         VSC_SATA_TF_LBAL_OFFSET         = 0x0c,
64         VSC_SATA_TF_LBAM_OFFSET         = 0x10,
65         VSC_SATA_TF_LBAH_OFFSET         = 0x14,
66         VSC_SATA_TF_DEVICE_OFFSET       = 0x18,
67         VSC_SATA_TF_STATUS_OFFSET       = 0x1c,
68         VSC_SATA_TF_COMMAND_OFFSET      = 0x1d,
69         VSC_SATA_TF_ALTSTATUS_OFFSET    = 0x28,
70         VSC_SATA_TF_CTL_OFFSET          = 0x29,
71
72         /* DMA base */
73         VSC_SATA_UP_DESCRIPTOR_OFFSET   = 0x64,
74         VSC_SATA_UP_DATA_BUFFER_OFFSET  = 0x6C,
75         VSC_SATA_DMA_CMD_OFFSET         = 0x70,
76
77         /* SCRs base */
78         VSC_SATA_SCR_STATUS_OFFSET      = 0x100,
79         VSC_SATA_SCR_ERROR_OFFSET       = 0x104,
80         VSC_SATA_SCR_CONTROL_OFFSET     = 0x108,
81
82         /* Port stride */
83         VSC_SATA_PORT_OFFSET            = 0x200,
84
85         /* Error interrupt status bit offsets */
86         VSC_SATA_INT_ERROR_CRC          = 0x40,
87         VSC_SATA_INT_ERROR_T            = 0x20,
88         VSC_SATA_INT_ERROR_P            = 0x10,
89         VSC_SATA_INT_ERROR_R            = 0x8,
90         VSC_SATA_INT_ERROR_E            = 0x4,
91         VSC_SATA_INT_ERROR_M            = 0x2,
92         VSC_SATA_INT_PHY_CHANGE         = 0x1,
93         VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC  | VSC_SATA_INT_ERROR_T | \
94                               VSC_SATA_INT_ERROR_P    | VSC_SATA_INT_ERROR_R | \
95                               VSC_SATA_INT_ERROR_E    | VSC_SATA_INT_ERROR_M | \
96                               VSC_SATA_INT_PHY_CHANGE),
97 };
98
99
100 #define is_vsc_sata_int_err(port_idx, int_status) \
101          (int_status & (VSC_SATA_INT_ERROR << (8 * port_idx)))
102
103
104 static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
105 {
106         if (sc_reg > SCR_CONTROL)
107                 return 0xffffffffU;
108         return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
109 }
110
111
112 static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
113                                u32 val)
114 {
115         if (sc_reg > SCR_CONTROL)
116                 return;
117         writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
118 }
119
120
121 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
122 {
123         void __iomem *mask_addr;
124         u8 mask;
125
126         mask_addr = ap->host_set->mmio_base +
127                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
128         mask = readb(mask_addr);
129         if (ctl & ATA_NIEN)
130                 mask |= 0x80;
131         else
132                 mask &= 0x7F;
133         writeb(mask, mask_addr);
134 }
135
136
137 static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
138 {
139         struct ata_ioports *ioaddr = &ap->ioaddr;
140         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
141
142         /*
143          * The only thing the ctl register is used for is SRST.
144          * That is not enabled or disabled via tf_load.
145          * However, if ATA_NIEN is changed, then we need to change the interrupt register.
146          */
147         if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
148                 ap->last_ctl = tf->ctl;
149                 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
150         }
151         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
152                 writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
153                 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
154                 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
155                 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
156                 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
157         } else if (is_addr) {
158                 writew(tf->feature, ioaddr->feature_addr);
159                 writew(tf->nsect, ioaddr->nsect_addr);
160                 writew(tf->lbal, ioaddr->lbal_addr);
161                 writew(tf->lbam, ioaddr->lbam_addr);
162                 writew(tf->lbah, ioaddr->lbah_addr);
163         }
164
165         if (tf->flags & ATA_TFLAG_DEVICE)
166                 writeb(tf->device, ioaddr->device_addr);
167
168         ata_wait_idle(ap);
169 }
170
171
172 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
173 {
174         struct ata_ioports *ioaddr = &ap->ioaddr;
175         u16 nsect, lbal, lbam, lbah, feature;
176
177         tf->command = ata_check_status(ap);
178         tf->device = readw(ioaddr->device_addr);
179         feature = readw(ioaddr->error_addr);
180         nsect = readw(ioaddr->nsect_addr);
181         lbal = readw(ioaddr->lbal_addr);
182         lbam = readw(ioaddr->lbam_addr);
183         lbah = readw(ioaddr->lbah_addr);
184
185         tf->feature = feature;
186         tf->nsect = nsect;
187         tf->lbal = lbal;
188         tf->lbam = lbam;
189         tf->lbah = lbah;
190
191         if (tf->flags & ATA_TFLAG_LBA48) {
192                 tf->hob_feature = feature >> 8;
193                 tf->hob_nsect = nsect >> 8;
194                 tf->hob_lbal = lbal >> 8;
195                 tf->hob_lbam = lbam >> 8;
196                 tf->hob_lbah = lbah >> 8;
197         }
198 }
199
200
201 /*
202  * vsc_sata_interrupt
203  *
204  * Read the interrupt register and process for the devices that have them pending.
205  */
206 static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance,
207                                        struct pt_regs *regs)
208 {
209         struct ata_host_set *host_set = dev_instance;
210         unsigned int i;
211         unsigned int handled = 0;
212         u32 int_status;
213
214         spin_lock(&host_set->lock);
215
216         int_status = readl(host_set->mmio_base + VSC_SATA_INT_STAT_OFFSET);
217
218         for (i = 0; i < host_set->n_ports; i++) {
219                 if (int_status & ((u32) 0xFF << (8 * i))) {
220                         struct ata_port *ap;
221
222                         ap = host_set->ports[i];
223
224                         if (is_vsc_sata_int_err(i, int_status)) {
225                                 u32 err_status;
226                                 printk(KERN_DEBUG "%s: ignoring interrupt(s)\n", __FUNCTION__);
227                                 err_status = ap ? vsc_sata_scr_read(ap, SCR_ERROR) : 0;
228                                 vsc_sata_scr_write(ap, SCR_ERROR, err_status);
229                                 handled++;
230                         }
231
232                         if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
233                                 struct ata_queued_cmd *qc;
234
235                                 qc = ata_qc_from_tag(ap, ap->active_tag);
236                                 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
237                                         handled += ata_host_intr(ap, qc);
238                                 else if (is_vsc_sata_int_err(i, int_status)) {
239                                         /*
240                                          * On some chips (i.e. Intel 31244), an error
241                                          * interrupt will sneak in at initialization
242                                          * time (phy state changes).  Clearing the SCR
243                                          * error register is not required, but it prevents
244                                          * the phy state change interrupts from recurring
245                                          * later.
246                                          */
247                                         u32 err_status;
248                                         err_status = vsc_sata_scr_read(ap, SCR_ERROR);
249                                         printk(KERN_DEBUG "%s: clearing interrupt, "
250                                                "status %x; sata err status %x\n",
251                                                __FUNCTION__,
252                                                int_status, err_status);
253                                         vsc_sata_scr_write(ap, SCR_ERROR, err_status);
254                                         /* Clear interrupt status */
255                                         ata_chk_status(ap);
256                                         handled++;
257                                 }
258                         }
259                 }
260         }
261
262         spin_unlock(&host_set->lock);
263
264         return IRQ_RETVAL(handled);
265 }
266
267
268 static struct scsi_host_template vsc_sata_sht = {
269         .module                 = THIS_MODULE,
270         .name                   = DRV_NAME,
271         .ioctl                  = ata_scsi_ioctl,
272         .queuecommand           = ata_scsi_queuecmd,
273         .can_queue              = ATA_DEF_QUEUE,
274         .this_id                = ATA_SHT_THIS_ID,
275         .sg_tablesize           = LIBATA_MAX_PRD,
276         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
277         .emulated               = ATA_SHT_EMULATED,
278         .use_clustering         = ATA_SHT_USE_CLUSTERING,
279         .proc_name              = DRV_NAME,
280         .dma_boundary           = ATA_DMA_BOUNDARY,
281         .slave_configure        = ata_scsi_slave_config,
282         .slave_destroy          = ata_scsi_slave_destroy,
283         .bios_param             = ata_std_bios_param,
284 };
285
286
287 static const struct ata_port_operations vsc_sata_ops = {
288         .port_disable           = ata_port_disable,
289         .tf_load                = vsc_sata_tf_load,
290         .tf_read                = vsc_sata_tf_read,
291         .exec_command           = ata_exec_command,
292         .check_status           = ata_check_status,
293         .dev_select             = ata_std_dev_select,
294         .bmdma_setup            = ata_bmdma_setup,
295         .bmdma_start            = ata_bmdma_start,
296         .bmdma_stop             = ata_bmdma_stop,
297         .bmdma_status           = ata_bmdma_status,
298         .qc_prep                = ata_qc_prep,
299         .qc_issue               = ata_qc_issue_prot,
300         .data_xfer              = ata_mmio_data_xfer,
301         .freeze                 = ata_bmdma_freeze,
302         .thaw                   = ata_bmdma_thaw,
303         .error_handler          = ata_bmdma_error_handler,
304         .post_internal_cmd      = ata_bmdma_post_internal_cmd,
305         .irq_handler            = vsc_sata_interrupt,
306         .irq_clear              = ata_bmdma_irq_clear,
307         .scr_read               = vsc_sata_scr_read,
308         .scr_write              = vsc_sata_scr_write,
309         .port_start             = ata_port_start,
310         .port_stop              = ata_port_stop,
311         .host_stop              = ata_pci_host_stop,
312 };
313
314 static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
315 {
316         port->cmd_addr          = base + VSC_SATA_TF_CMD_OFFSET;
317         port->data_addr         = base + VSC_SATA_TF_DATA_OFFSET;
318         port->error_addr        = base + VSC_SATA_TF_ERROR_OFFSET;
319         port->feature_addr      = base + VSC_SATA_TF_FEATURE_OFFSET;
320         port->nsect_addr        = base + VSC_SATA_TF_NSECT_OFFSET;
321         port->lbal_addr         = base + VSC_SATA_TF_LBAL_OFFSET;
322         port->lbam_addr         = base + VSC_SATA_TF_LBAM_OFFSET;
323         port->lbah_addr         = base + VSC_SATA_TF_LBAH_OFFSET;
324         port->device_addr       = base + VSC_SATA_TF_DEVICE_OFFSET;
325         port->status_addr       = base + VSC_SATA_TF_STATUS_OFFSET;
326         port->command_addr      = base + VSC_SATA_TF_COMMAND_OFFSET;
327         port->altstatus_addr    = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
328         port->ctl_addr          = base + VSC_SATA_TF_CTL_OFFSET;
329         port->bmdma_addr        = base + VSC_SATA_DMA_CMD_OFFSET;
330         port->scr_addr          = base + VSC_SATA_SCR_STATUS_OFFSET;
331         writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
332         writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
333 }
334
335
336 static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
337 {
338         static int printed_version;
339         struct ata_probe_ent *probe_ent = NULL;
340         unsigned long base;
341         int pci_dev_busy = 0;
342         void __iomem *mmio_base;
343         int rc;
344
345         if (!printed_version++)
346                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
347
348         rc = pci_enable_device(pdev);
349         if (rc)
350                 return rc;
351
352         /*
353          * Check if we have needed resource mapped.
354          */
355         if (pci_resource_len(pdev, 0) == 0) {
356                 rc = -ENODEV;
357                 goto err_out;
358         }
359
360         rc = pci_request_regions(pdev, DRV_NAME);
361         if (rc) {
362                 pci_dev_busy = 1;
363                 goto err_out;
364         }
365
366         /*
367          * Use 32 bit DMA mask, because 64 bit address support is poor.
368          */
369         rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
370         if (rc)
371                 goto err_out_regions;
372         rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
373         if (rc)
374                 goto err_out_regions;
375
376         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
377         if (probe_ent == NULL) {
378                 rc = -ENOMEM;
379                 goto err_out_regions;
380         }
381         memset(probe_ent, 0, sizeof(*probe_ent));
382         probe_ent->dev = pci_dev_to_dev(pdev);
383         INIT_LIST_HEAD(&probe_ent->node);
384
385         mmio_base = pci_iomap(pdev, 0, 0);
386         if (mmio_base == NULL) {
387                 rc = -ENOMEM;
388                 goto err_out_free_ent;
389         }
390         base = (unsigned long) mmio_base;
391
392         /*
393          * Due to a bug in the chip, the default cache line size can't be used
394          */
395         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
396
397         probe_ent->sht = &vsc_sata_sht;
398         probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
399                                 ATA_FLAG_MMIO;
400         probe_ent->port_ops = &vsc_sata_ops;
401         probe_ent->n_ports = 4;
402         probe_ent->irq = pdev->irq;
403         probe_ent->irq_flags = IRQF_SHARED;
404         probe_ent->mmio_base = mmio_base;
405
406         /* We don't care much about the PIO/UDMA masks, but the core won't like us
407          * if we don't fill these
408          */
409         probe_ent->pio_mask = 0x1f;
410         probe_ent->mwdma_mask = 0x07;
411         probe_ent->udma_mask = 0x7f;
412
413         /* We have 4 ports per PCI function */
414         vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
415         vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
416         vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
417         vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
418
419         pci_set_master(pdev);
420
421         /*
422          * Config offset 0x98 is "Extended Control and Status Register 0"
423          * Default value is (1 << 28).  All bits except bit 28 are reserved in
424          * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
425          * If bit 28 is clear, each port has its own LED.
426          */
427         pci_write_config_dword(pdev, 0x98, 0);
428
429         /* FIXME: check ata_device_add return value */
430         ata_device_add(probe_ent);
431         kfree(probe_ent);
432
433         return 0;
434
435 err_out_free_ent:
436         kfree(probe_ent);
437 err_out_regions:
438         pci_release_regions(pdev);
439 err_out:
440         if (!pci_dev_busy)
441                 pci_disable_device(pdev);
442         return rc;
443 }
444
445
446 static const struct pci_device_id vsc_sata_pci_tbl[] = {
447         { PCI_VENDOR_ID_VITESSE, 0x7174,
448           PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
449         { PCI_VENDOR_ID_INTEL, 0x3200,
450           PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
451         { }     /* terminate list */
452 };
453
454
455 static struct pci_driver vsc_sata_pci_driver = {
456         .name                   = DRV_NAME,
457         .id_table               = vsc_sata_pci_tbl,
458         .probe                  = vsc_sata_init_one,
459         .remove                 = ata_pci_remove_one,
460 };
461
462
463 static int __init vsc_sata_init(void)
464 {
465         return pci_module_init(&vsc_sata_pci_driver);
466 }
467
468
469 static void __exit vsc_sata_exit(void)
470 {
471         pci_unregister_driver(&vsc_sata_pci_driver);
472 }
473
474
475 MODULE_AUTHOR("Jeremy Higdon");
476 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
477 MODULE_LICENSE("GPL");
478 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
479 MODULE_VERSION(DRV_VERSION);
480
481 module_init(vsc_sata_init);
482 module_exit(vsc_sata_exit);