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   1 /* linux/arch/arm/mach-s3c2410/mach-jive.c
   2  *
   3  * Copyright 2007 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://armlinux.simtec.co.uk/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/list.h>
  17 #include <linux/timer.h>
  18 #include <linux/init.h>
  19 #include <linux/sysdev.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/i2c.h>
  23
  24 #include <video/ili9320.h>
  25
  26 #include <linux/spi/spi.h>
  27
  28 #include <asm/mach/arch.h>
  29 #include <asm/mach/map.h>
  30 #include <asm/mach/irq.h>
  31
  32 #include <plat/regs-serial.h>
  33 #include <plat/nand.h>
  34 #include <plat/iic.h>
  35
  36 #include <mach/regs-power.h>
  37 #include <mach/regs-gpio.h>
  38 #include <mach/regs-mem.h>
  39 #include <mach/regs-lcd.h>
  40 #include <mach/spi-gpio.h>
  41 #include <mach/fb.h>
  42
  43 #include <asm/mach-types.h>
  44
  45 #include <linux/mtd/mtd.h>
  46 #include <linux/mtd/nand.h>
  47 #include <linux/mtd/nand_ecc.h>
  48 #include <linux/mtd/partitions.h>
  49
  50 #include <plat/clock.h>
  51 #include <plat/devs.h>
  52 #include <plat/cpu.h>
  53 #include <plat/pm.h>
  54 #include <plat/udc.h>
  55
  56 static struct map_desc jive_iodesc[] __initdata = {
  57 };
  58
  59 #define UCON S3C2410_UCON_DEFAULT
  60 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
  61 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  62
  63 static struct s3c2410_uartcfg jive_uartcfgs[] = {
  64         [0] = {
  65                 .hwport      = 0,
  66                 .flags       = 0,
  67                 .ucon        = UCON,
  68                 .ulcon       = ULCON,
  69                 .ufcon       = UFCON,
  70         },
  71         [1] = {
  72                 .hwport      = 1,
  73                 .flags       = 0,
  74                 .ucon        = UCON,
  75                 .ulcon       = ULCON,
  76                 .ufcon       = UFCON,
  77         },
  78         [2] = {
  79                 .hwport      = 2,
  80                 .flags       = 0,
  81                 .ucon        = UCON,
  82                 .ulcon       = ULCON,
  83                 .ufcon       = UFCON,
  84         }
  85 };
  86
  87 /* Jive flash assignment
  88  *
  89  * 0x00000000-0x00028000 : uboot
  90  * 0x00028000-0x0002c000 : uboot env
  91  * 0x0002c000-0x00030000 : spare
  92  * 0x00030000-0x00200000 : zimage A
  93  * 0x00200000-0x01600000 : cramfs A
  94  * 0x01600000-0x017d0000 : zimage B
  95  * 0x017d0000-0x02bd0000 : cramfs B
  96  * 0x02bd0000-0x03fd0000 : yaffs
  97  */
  98 static struct mtd_partition jive_imageA_nand_part[] = {
  99
 100 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
 101         /* Don't allow access to the bootloader from linux */
 102         {
 103                 .name           = "uboot",
 104                 .offset         = 0,
 105                 .size           = (160 * SZ_1K),
 106                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 107         },
 108
 109         /* spare */
 110         {
 111                 .name           = "spare",
 112                 .offset         = (176 * SZ_1K),
 113                 .size           = (16 * SZ_1K),
 114         },
 115 #endif
 116
 117         /* booted images */
 118         {
 119                 .name           = "kernel (ro)",
 120                 .offset         = (192 * SZ_1K),
 121                 .size           = (SZ_2M) - (192 * SZ_1K),
 122                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 123         }, {
 124                 .name           = "root (ro)",
 125                 .offset         = (SZ_2M),
 126                 .size           = (20 * SZ_1M),
 127                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 128         },
 129
 130         /* yaffs */
 131         {
 132                 .name           = "yaffs",
 133                 .offset         = (44 * SZ_1M),
 134                 .size           = (20 * SZ_1M),
 135         },
 136
 137         /* bootloader environment */
 138         {
 139                 .name           = "env",
 140                 .offset         = (160 * SZ_1K),
 141                 .size           = (16 * SZ_1K),
 142         },
 143
 144         /* upgrade images */
 145         {
 146                 .name           = "zimage",
 147                 .offset         = (22 * SZ_1M),
 148                 .size           = (2 * SZ_1M) - (192 * SZ_1K),
 149         }, {
 150                 .name           = "cramfs",
 151                 .offset         = (24 * SZ_1M) - (192*SZ_1K),
 152                 .size           = (20 * SZ_1M),
 153         },
 154 };
 155
 156 static struct mtd_partition jive_imageB_nand_part[] = {
 157
 158 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
 159         /* Don't allow access to the bootloader from linux */
 160         {
 161                 .name           = "uboot",
 162                 .offset         = 0,
 163                 .size           = (160 * SZ_1K),
 164                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 165         },
 166
 167         /* spare */
 168         {
 169                 .name           = "spare",
 170                 .offset         = (176 * SZ_1K),
 171                 .size           = (16 * SZ_1K),
 172         },
 173 #endif
 174
 175         /* booted images */
 176         {
 177                 .name           = "kernel (ro)",
 178                 .offset         = (22 * SZ_1M),
 179                 .size           = (2 * SZ_1M) - (192 * SZ_1K),
 180                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 181         },
 182         {
 183                 .name           = "root (ro)",
 184                 .offset         = (24 * SZ_1M) - (192 * SZ_1K),
 185                 .size           = (20 * SZ_1M),
 186                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 187         },
 188
 189         /* yaffs */
 190         {
 191                 .name           = "yaffs",
 192                 .offset         = (44 * SZ_1M),
 193                 .size           = (20 * SZ_1M),
 194         },
 195
 196         /* bootloader environment */
 197         {
 198                 .name           = "env",
 199                 .offset         = (160 * SZ_1K),
 200                 .size           = (16 * SZ_1K),
 201         },
 202
 203         /* upgrade images */
 204         {
 205                 .name           = "zimage",
 206                 .offset         = (192 * SZ_1K),
 207                 .size           = (2 * SZ_1M) - (192 * SZ_1K),
 208         }, {
 209                 .name           = "cramfs",
 210                 .offset         = (2 * SZ_1M),
 211                 .size           = (20 * SZ_1M),
 212         },
 213 };
 214
 215 static struct s3c2410_nand_set jive_nand_sets[] = {
 216         [0] = {
 217                 .name           = "flash",
 218                 .nr_chips       = 1,
 219                 .nr_partitions  = ARRAY_SIZE(jive_imageA_nand_part),
 220                 .partitions     = jive_imageA_nand_part,
 221         },
 222 };
 223
 224 static struct s3c2410_platform_nand jive_nand_info = {
 225         /* set taken from osiris nand timings, possibly still conservative */
 226         .tacls          = 30,
 227         .twrph0         = 55,
 228         .twrph1         = 40,
 229         .sets           = jive_nand_sets,
 230         .nr_sets        = ARRAY_SIZE(jive_nand_sets),
 231 };
 232
 233 static int __init jive_mtdset(char *options)
 234 {
 235         struct s3c2410_nand_set *nand = &jive_nand_sets[0];
 236         unsigned long set;
 237
 238         if (options == NULL || options[0] == '\0')
 239                 return 0;
 240
 241         if (strict_strtoul(options, 10, &set)) {
 242                 printk(KERN_ERR "failed to parse mtdset=%s\n", options);
 243                 return 0;
 244         }
 245
 246         switch (set) {
 247         case 1:
 248                 nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
 249                 nand->partitions = jive_imageB_nand_part;
 250         case 0:
 251                 /* this is already setup in the nand info */
 252                 break;
 253         default:
 254                 printk(KERN_ERR "Unknown mtd set %ld specified,"
 255                        "using default.", set);
 256         }
 257
 258         return 0;
 259 }
 260
 261 /* parse the mtdset= option given to the kernel command line */
 262 __setup("mtdset=", jive_mtdset);
 263
 264 /* LCD timing and setup */
 265
 266 #define LCD_XRES         (240)
 267 #define LCD_YRES         (320)
 268 #define LCD_LEFT_MARGIN  (12)
 269 #define LCD_RIGHT_MARGIN (12)
 270 #define LCD_LOWER_MARGIN (12)
 271 #define LCD_UPPER_MARGIN (12)
 272 #define LCD_VSYNC        (2)
 273 #define LCD_HSYNC        (2)
 274
 275 #define LCD_REFRESH      (60)
 276
 277 #define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
 278 #define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
 279
 280 static struct s3c2410fb_display jive_vgg2432a4_display[] = {
 281         [0] = {
 282                 .width          = LCD_XRES,
 283                 .height         = LCD_YRES,
 284                 .xres           = LCD_XRES,
 285                 .yres           = LCD_YRES,
 286                 .left_margin    = LCD_LEFT_MARGIN,
 287                 .right_margin   = LCD_RIGHT_MARGIN,
 288                 .upper_margin   = LCD_UPPER_MARGIN,
 289                 .lower_margin   = LCD_LOWER_MARGIN,
 290                 .hsync_len      = LCD_HSYNC,
 291                 .vsync_len      = LCD_VSYNC,
 292
 293                 .pixclock       = (1000000000000LL /
 294                                    (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
 295
 296                 .bpp            = 16,
 297                 .type           = (S3C2410_LCDCON1_TFT16BPP |
 298                                    S3C2410_LCDCON1_TFT),
 299
 300                 .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
 301                                    S3C2410_LCDCON5_INVVLINE |
 302                                    S3C2410_LCDCON5_INVVFRAME |
 303                                    S3C2410_LCDCON5_INVVDEN |
 304                                    S3C2410_LCDCON5_PWREN),
 305         },
 306 };
 307
 308 /* todo - put into gpio header */
 309
 310 #define S3C2410_GPCCON_MASK(x)  (3 << ((x) * 2))
 311 #define S3C2410_GPDCON_MASK(x)  (3 << ((x) * 2))
 312
 313 static struct s3c2410fb_mach_info jive_lcd_config = {
 314         .displays        = jive_vgg2432a4_display,
 315         .num_displays    = ARRAY_SIZE(jive_vgg2432a4_display),
 316         .default_display = 0,
 317
 318         /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
 319          * and disable the pull down resistors on pins we are using for LCD
 320          * data. */
 321
 322         .gpcup          = (0xf << 1) | (0x3f << 10),
 323
 324         .gpccon         = (S3C2410_GPC1_VCLK   | S3C2410_GPC2_VLINE |
 325                            S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
 326                            S3C2410_GPC10_VD2   | S3C2410_GPC11_VD3 |
 327                            S3C2410_GPC12_VD4   | S3C2410_GPC13_VD5 |
 328                            S3C2410_GPC14_VD6   | S3C2410_GPC15_VD7),
 329
 330         .gpccon_mask    = (S3C2410_GPCCON_MASK(1)  | S3C2410_GPCCON_MASK(2)  |
 331                            S3C2410_GPCCON_MASK(3)  | S3C2410_GPCCON_MASK(4)  |
 332                            S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
 333                            S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
 334                            S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
 335
 336         .gpdup          = (0x3f << 2) | (0x3f << 10),
 337
 338         .gpdcon         = (S3C2410_GPD2_VD10  | S3C2410_GPD3_VD11 |
 339                            S3C2410_GPD4_VD12  | S3C2410_GPD5_VD13 |
 340                            S3C2410_GPD6_VD14  | S3C2410_GPD7_VD15 |
 341                            S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
 342                            S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
 343                            S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
 344
 345         .gpdcon_mask    = (S3C2410_GPDCON_MASK(2)  | S3C2410_GPDCON_MASK(3) |
 346                            S3C2410_GPDCON_MASK(4)  | S3C2410_GPDCON_MASK(5) |
 347                            S3C2410_GPDCON_MASK(6)  | S3C2410_GPDCON_MASK(7) |
 348                            S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
 349                            S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
 350                            S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
 351 };
 352
 353 /* ILI9320 support. */
 354
 355 static void jive_lcm_reset(unsigned int set)
 356 {
 357         printk(KERN_DEBUG "%s(%d)\n", __func__, set);
 358
 359         s3c2410_gpio_setpin(S3C2410_GPG13, set);
 360         s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
 361 }
 362
 363 #undef LCD_UPPER_MARGIN
 364 #define LCD_UPPER_MARGIN 2
 365
 366 static struct ili9320_platdata jive_lcm_config = {
 367         .hsize          = LCD_XRES,
 368         .vsize          = LCD_YRES,
 369
 370         .reset          = jive_lcm_reset,
 371         .suspend        = ILI9320_SUSPEND_DEEP,
 372
 373         .entry_mode     = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
 374         .display2       = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
 375                            ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
 376         .display3       = 0x0,
 377         .display4       = 0x0,
 378         .rgb_if1        = (ILI9320_RGBIF1_RIM_RGB18 |
 379                            ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
 380         .rgb_if2        = ILI9320_RGBIF2_DPL,
 381         .interface2     = 0x0,
 382         .interface3     = 0x3,
 383         .interface4     = (ILI9320_INTERFACE4_RTNE(16) |
 384                            ILI9320_INTERFACE4_DIVE(1)),
 385         .interface5     = 0x0,
 386         .interface6     = 0x0,
 387 };
 388
 389 /* LCD SPI support */
 390
 391 static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
 392 {
 393         s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1);
 394 }
 395
 396 static struct s3c2410_spigpio_info jive_lcd_spi = {
 397         .bus_num        = 1,
 398         .pin_clk        = S3C2410_GPG8,
 399         .pin_mosi       = S3C2410_GPB8,
 400         .num_chipselect = 1,
 401         .chip_select    = jive_lcd_spi_chipselect,
 402 };
 403
 404 static struct platform_device jive_device_lcdspi = {
 405         .name           = "spi_s3c24xx_gpio",
 406         .id             = 1,
 407         .num_resources  = 0,
 408         .dev.platform_data = &jive_lcd_spi,
 409 };
 410
 411 /* WM8750 audio code SPI definition */
 412
 413 static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
 414 {
 415         s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1);
 416 }
 417
 418 static struct s3c2410_spigpio_info jive_wm8750_spi = {
 419         .bus_num        = 2,
 420         .pin_clk        = S3C2410_GPB4,
 421         .pin_mosi       = S3C2410_GPB9,
 422         .num_chipselect = 1,
 423         .chip_select    = jive_wm8750_chipselect,
 424 };
 425
 426 static struct platform_device jive_device_wm8750 = {
 427         .name           = "spi_s3c24xx_gpio",
 428         .id             = 2,
 429         .num_resources  = 0,
 430         .dev.platform_data = &jive_wm8750_spi,
 431 };
 432
 433 /* JIVE SPI devices. */
 434
 435 static struct spi_board_info __initdata jive_spi_devs[] = {
 436         [0] = {
 437                 .modalias       = "VGG2432A4",
 438                 .bus_num        = 1,
 439                 .chip_select    = 0,
 440                 .mode           = SPI_MODE_3,   /* CPOL=1, CPHA=1 */
 441                 .max_speed_hz   = 100000,
 442                 .platform_data  = &jive_lcm_config,
 443         }, {
 444                 .modalias       = "WM8750",
 445                 .bus_num        = 2,
 446                 .chip_select    = 0,
 447                 .mode           = SPI_MODE_0,   /* CPOL=0, CPHA=0 */
 448                 .max_speed_hz   = 100000,
 449         },
 450 };
 451
 452 /* I2C bus and device configuration. */
 453
 454 static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
 455         .frequency      = 80 * 1000,
 456         .flags          = S3C_IICFLG_FILTER,
 457         .sda_delay      = 2,
 458 };
 459
 460 static struct i2c_board_info jive_i2c_devs[] __initdata = {
 461         [0] = {
 462                 I2C_BOARD_INFO("lis302dl", 0x1c),
 463                 .irq    = IRQ_EINT14,
 464         },
 465 };
 466
 467 /* The platform devices being used. */
 468
 469 static struct platform_device *jive_devices[] __initdata = {
 470         &s3c_device_usb,
 471         &s3c_device_rtc,
 472         &s3c_device_wdt,
 473         &s3c_device_i2c0,
 474         &s3c_device_lcd,
 475         &jive_device_lcdspi,
 476         &jive_device_wm8750,
 477         &s3c_device_nand,
 478         &s3c_device_usbgadget,
 479 };
 480
 481 static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
 482         .vbus_pin       = S3C2410_GPG1,         /* detect is on GPG1 */
 483 };
 484
 485 /* Jive power management device */
 486
 487 #ifdef CONFIG_PM
 488 static int jive_pm_suspend(struct sys_device *sd, pm_message_t state)
 489 {
 490         /* Write the magic value u-boot uses to check for resume into
 491          * the INFORM0 register, and ensure INFORM1 is set to the
 492          * correct address to resume from. */
 493
 494         __raw_writel(0x2BED, S3C2412_INFORM0);
 495         __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
 496
 497         return 0;
 498 }
 499
 500 static int jive_pm_resume(struct sys_device *sd)
 501 {
 502         __raw_writel(0x0, S3C2412_INFORM0);
 503         return 0;
 504 }
 505
 506 #else
 507 #define jive_pm_suspend NULL
 508 #define jive_pm_resume NULL
 509 #endif
 510
 511 static struct sysdev_class jive_pm_sysclass = {
 512         .name           = "jive-pm",
 513         .suspend        = jive_pm_suspend,
 514         .resume         = jive_pm_resume,
 515 };
 516
 517 static struct sys_device jive_pm_sysdev = {
 518         .cls            = &jive_pm_sysclass,
 519 };
 520
 521 static void __init jive_map_io(void)
 522 {
 523         s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
 524         s3c24xx_init_clocks(12000000);
 525         s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
 526 }
 527
 528 static void jive_power_off(void)
 529 {
 530         printk(KERN_INFO "powering system down...\n");
 531
 532         s3c2410_gpio_setpin(S3C2410_GPC5, 1);
 533         s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT);
 534 }
 535
 536 static void __init jive_machine_init(void)
 537 {
 538         /* register system devices for managing low level suspend */
 539
 540         sysdev_class_register(&jive_pm_sysclass);
 541         sysdev_register(&jive_pm_sysdev);
 542
 543         /* write our sleep configurations for the IO. Pull down all unused
 544          * IO, ensure that we have turned off all peripherals we do not
 545          * need, and configure the ones we do need. */
 546
 547         /* Port B sleep */
 548
 549         __raw_writel(S3C2412_SLPCON_IN(0)   |
 550                      S3C2412_SLPCON_PULL(1) |
 551                      S3C2412_SLPCON_HIGH(2) |
 552                      S3C2412_SLPCON_PULL(3) |
 553                      S3C2412_SLPCON_PULL(4) |
 554                      S3C2412_SLPCON_PULL(5) |
 555                      S3C2412_SLPCON_PULL(6) |
 556                      S3C2412_SLPCON_HIGH(7) |
 557                      S3C2412_SLPCON_PULL(8) |
 558                      S3C2412_SLPCON_PULL(9) |
 559                      S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
 560
 561         /* Port C sleep */
 562
 563         __raw_writel(S3C2412_SLPCON_PULL(0) |
 564                      S3C2412_SLPCON_PULL(1) |
 565                      S3C2412_SLPCON_PULL(2) |
 566                      S3C2412_SLPCON_PULL(3) |
 567                      S3C2412_SLPCON_PULL(4) |
 568                      S3C2412_SLPCON_PULL(5) |
 569                      S3C2412_SLPCON_LOW(6)  |
 570                      S3C2412_SLPCON_PULL(6) |
 571                      S3C2412_SLPCON_PULL(7) |
 572                      S3C2412_SLPCON_PULL(8) |
 573                      S3C2412_SLPCON_PULL(9) |
 574                      S3C2412_SLPCON_PULL(10) |
 575                      S3C2412_SLPCON_PULL(11) |
 576                      S3C2412_SLPCON_PULL(12) |
 577                      S3C2412_SLPCON_PULL(13) |
 578                      S3C2412_SLPCON_PULL(14) |
 579                      S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
 580
 581         /* Port D sleep */
 582
 583         __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
 584
 585         /* Port F sleep */
 586
 587         __raw_writel(S3C2412_SLPCON_LOW(0)  |
 588                      S3C2412_SLPCON_LOW(1)  |
 589                      S3C2412_SLPCON_LOW(2)  |
 590                      S3C2412_SLPCON_EINT(3) |
 591                      S3C2412_SLPCON_EINT(4) |
 592                      S3C2412_SLPCON_EINT(5) |
 593                      S3C2412_SLPCON_EINT(6) |
 594                      S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
 595
 596         /* Port G sleep */
 597
 598         __raw_writel(S3C2412_SLPCON_IN(0)    |
 599                      S3C2412_SLPCON_IN(1)    |
 600                      S3C2412_SLPCON_IN(2)    |
 601                      S3C2412_SLPCON_IN(3)    |
 602                      S3C2412_SLPCON_IN(4)    |
 603                      S3C2412_SLPCON_IN(5)    |
 604                      S3C2412_SLPCON_IN(6)    |
 605                      S3C2412_SLPCON_IN(7)    |
 606                      S3C2412_SLPCON_PULL(8)  |
 607                      S3C2412_SLPCON_PULL(9)  |
 608                      S3C2412_SLPCON_IN(10)   |
 609                      S3C2412_SLPCON_PULL(11) |
 610                      S3C2412_SLPCON_PULL(12) |
 611                      S3C2412_SLPCON_PULL(13) |
 612                      S3C2412_SLPCON_IN(14)   |
 613                      S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
 614
 615         /* Port H sleep */
 616
 617         __raw_writel(S3C2412_SLPCON_PULL(0) |
 618                      S3C2412_SLPCON_PULL(1) |
 619                      S3C2412_SLPCON_PULL(2) |
 620                      S3C2412_SLPCON_PULL(3) |
 621                      S3C2412_SLPCON_PULL(4) |
 622                      S3C2412_SLPCON_PULL(5) |
 623                      S3C2412_SLPCON_PULL(6) |
 624                      S3C2412_SLPCON_IN(7)   |
 625                      S3C2412_SLPCON_IN(8)   |
 626                      S3C2412_SLPCON_PULL(9) |
 627                      S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
 628
 629         /* initialise the power management now we've setup everything. */
 630
 631         s3c_pm_init();
 632
 633         s3c_device_nand.dev.platform_data = &jive_nand_info;
 634
 635         /* initialise the spi */
 636
 637         s3c2410_gpio_setpin(S3C2410_GPG13, 0);
 638         s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
 639
 640         s3c2410_gpio_setpin(S3C2410_GPB7, 1);
 641         s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);
 642
 643         s3c2410_gpio_setpin(S3C2410_GPB6, 0);
 644         s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);
 645
 646         s3c2410_gpio_setpin(S3C2410_GPG8, 1);
 647         s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);
 648
 649         /* initialise the WM8750 spi */
 650
 651         s3c2410_gpio_setpin(S3C2410_GPH10, 1);
 652         s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT);
 653
 654         /* Turn off suspend on both USB ports, and switch the
 655          * selectable USB port to USB device mode. */
 656
 657         s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
 658                               S3C2410_MISCCR_USBSUSPND0 |
 659                               S3C2410_MISCCR_USBSUSPND1, 0x0);
 660
 661         s3c24xx_udc_set_platdata(&jive_udc_cfg);
 662         s3c24xx_fb_set_platdata(&jive_lcd_config);
 663
 664         spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
 665
 666         s3c_i2c0_set_platdata(&jive_i2c_cfg);
 667         i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
 668
 669         pm_power_off = jive_power_off;
 670
 671         platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
 672 }
 673
 674 MACHINE_START(JIVE, "JIVE")
 675         /* Maintainer: Ben Dooks <ben@fluff.org> */
 676         .phys_io        = S3C2410_PA_UART,
 677         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 678         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 679
 680         .init_irq       = s3c24xx_init_irq,
 681         .map_io         = jive_map_io,
 682         .init_machine   = jive_machine_init,
 683         .timer          = &s3c24xx_timer,
 684 MACHINE_END