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   1 /*
   2  *************************************************************************
   3  * Ralink Tech Inc.
   4  * 5F., No.36, Taiyuan St., Jhubei City,
   5  * Hsinchu County 302,
   6  * Taiwan, R.O.C.
   7  *
   8  * (c) Copyright 2002-2007, Ralink Technology, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify  *
  11  * it under the terms of the GNU General Public License as published by  *
  12  * the Free Software Foundation; either version 2 of the License, or     *
  13  * (at your option) any later version.                                   *
  14  *                                                                       *
  15  * This program is distributed in the hope that it will be useful,       *
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  * GNU General Public License for more details.                          *
  19  *                                                                       *
  20  * You should have received a copy of the GNU General Public License     *
  21  * along with this program; if not, write to the                         *
  22  * Free Software Foundation, Inc.,                                       *
  23  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  *                                                                       *
  25  *************************************************************************
  26
  27         Module Name:
  28         rt28xx.h
  29
  30         Abstract:
  31         RT28xx ASIC related definition & structures
  32
  33         Revision History:
  34         Who                     When              What
  35         --------        ----------        ----------------------------------------------
  36        Jan Lee           Jan-3-2006     created for RT2860c
  37 */
  38
  39 #ifndef __RT28XX_H__
  40 #define __RT28XX_H__
  41
  42
  43 //
  44 // PCI registers - base address 0x0000
  45 //
  46 #define PCI_CFG                 0x0000
  47 #define PCI_EECTRL                      0x0004
  48 #define PCI_MCUCTRL                     0x0008
  49
  50 //
  51 // SCH/DMA registers - base address 0x0200
  52 //
  53 // INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit
  54 //
  55 #define DMA_CSR0      0x200
  56 #define INT_SOURCE_CSR      0x200
  57 #ifdef RT_BIG_ENDIAN
  58 typedef union   _INT_SOURCE_CSR_STRUC   {
  59         struct  {
  60                 UINT32          :14;
  61                 UINT32          TxCoherent:1;
  62                 UINT32          RxCoherent:1;
  63                 UINT32          GPTimer:1;
  64                 UINT32          AutoWakeup:1;//bit14
  65                 UINT32          TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c
  66                 UINT32          PreTBTT:1;
  67                 UINT32          TBTTInt:1;
  68                 UINT32          RxTxCoherent:1;
  69                 UINT32          MCUCommandINT:1;
  70                 UINT32          MgmtDmaDone:1;
  71                 UINT32          HccaDmaDone:1;
  72                 UINT32          Ac3DmaDone:1;
  73                 UINT32          Ac2DmaDone:1;
  74                 UINT32          Ac1DmaDone:1;
  75                 UINT32          Ac0DmaDone:1;
  76                 UINT32          RxDone:1;
  77                 UINT32          TxDelayINT:1;   //delayed interrupt, not interrupt until several int or time limit hit
  78                 UINT32          RxDelayINT:1; //dealyed interrupt
  79         }       field;
  80         UINT32                  word;
  81 }       INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
  82 #else
  83 typedef union   _INT_SOURCE_CSR_STRUC   {
  84         struct  {
  85                 UINT32          RxDelayINT:1;
  86                 UINT32          TxDelayINT:1;
  87                 UINT32          RxDone:1;
  88                 UINT32          Ac0DmaDone:1;//4
  89                 UINT32          Ac1DmaDone:1;
  90                 UINT32          Ac2DmaDone:1;
  91                 UINT32          Ac3DmaDone:1;
  92                 UINT32          HccaDmaDone:1; // bit7
  93                 UINT32          MgmtDmaDone:1;
  94                 UINT32          MCUCommandINT:1;//bit 9
  95                 UINT32          RxTxCoherent:1;
  96                 UINT32          TBTTInt:1;
  97                 UINT32          PreTBTT:1;
  98                 UINT32          TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c
  99                 UINT32          AutoWakeup:1;//bit14
 100                 UINT32          GPTimer:1;
 101                 UINT32          RxCoherent:1;//bit16
 102                 UINT32          TxCoherent:1;
 103                 UINT32          :14;
 104         }       field;
 105         UINT32                  word;
 106 } INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
 107 #endif
 108
 109 //
 110 // INT_MASK_CSR:   Interrupt MASK register.   1: the interrupt is mask OFF
 111 //
 112 #define INT_MASK_CSR        0x204
 113 #ifdef RT_BIG_ENDIAN
 114 typedef union   _INT_MASK_CSR_STRUC     {
 115         struct  {
 116                 UINT32          TxCoherent:1;
 117                 UINT32          RxCoherent:1;
 118                 UINT32          :20;
 119                 UINT32          MCUCommandINT:1;
 120                 UINT32          MgmtDmaDone:1;
 121                 UINT32          HccaDmaDone:1;
 122                 UINT32          Ac3DmaDone:1;
 123                 UINT32          Ac2DmaDone:1;
 124                 UINT32          Ac1DmaDone:1;
 125                 UINT32          Ac0DmaDone:1;
 126                 UINT32          RxDone:1;
 127                 UINT32          TxDelay:1;
 128                 UINT32          RXDelay_INT_MSK:1;
 129         }       field;
 130         UINT32                  word;
 131 }INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
 132 #else
 133 typedef union   _INT_MASK_CSR_STRUC     {
 134         struct  {
 135                 UINT32          RXDelay_INT_MSK:1;
 136                 UINT32          TxDelay:1;
 137                 UINT32          RxDone:1;
 138                 UINT32          Ac0DmaDone:1;
 139                 UINT32          Ac1DmaDone:1;
 140                 UINT32          Ac2DmaDone:1;
 141                 UINT32          Ac3DmaDone:1;
 142                 UINT32          HccaDmaDone:1;
 143                 UINT32          MgmtDmaDone:1;
 144                 UINT32          MCUCommandINT:1;
 145                 UINT32          :20;
 146                 UINT32          RxCoherent:1;
 147                 UINT32          TxCoherent:1;
 148         }       field;
 149         UINT32                  word;
 150 } INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
 151 #endif
 152 #define WPDMA_GLO_CFG   0x208
 153 #ifdef RT_BIG_ENDIAN
 154 typedef union   _WPDMA_GLO_CFG_STRUC    {
 155         struct  {
 156                 UINT32          HDR_SEG_LEN:16;
 157                 UINT32          RXHdrScater:8;
 158                 UINT32          BigEndian:1;
 159                 UINT32          EnTXWriteBackDDONE:1;
 160                 UINT32          WPDMABurstSIZE:2;
 161                 UINT32          RxDMABusy:1;
 162                 UINT32          EnableRxDMA:1;
 163                 UINT32          TxDMABusy:1;
 164                 UINT32          EnableTxDMA:1;
 165         }       field;
 166         UINT32                  word;
 167 }WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
 168 #else
 169 typedef union   _WPDMA_GLO_CFG_STRUC    {
 170         struct  {
 171                 UINT32          EnableTxDMA:1;
 172                 UINT32          TxDMABusy:1;
 173                 UINT32          EnableRxDMA:1;
 174                 UINT32          RxDMABusy:1;
 175                 UINT32          WPDMABurstSIZE:2;
 176                 UINT32          EnTXWriteBackDDONE:1;
 177                 UINT32          BigEndian:1;
 178                 UINT32          RXHdrScater:8;
 179                 UINT32          HDR_SEG_LEN:16;
 180         }       field;
 181         UINT32                  word;
 182 } WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
 183 #endif
 184 #define WPDMA_RST_IDX   0x20c
 185 #ifdef RT_BIG_ENDIAN
 186 typedef union   _WPDMA_RST_IDX_STRUC    {
 187         struct  {
 188                 UINT32          :15;
 189                 UINT32          RST_DRX_IDX0:1;
 190                 UINT32          rsv:10;
 191                 UINT32          RST_DTX_IDX5:1;
 192                 UINT32          RST_DTX_IDX4:1;
 193                 UINT32          RST_DTX_IDX3:1;
 194                 UINT32          RST_DTX_IDX2:1;
 195                 UINT32          RST_DTX_IDX1:1;
 196                 UINT32          RST_DTX_IDX0:1;
 197         }       field;
 198         UINT32                  word;
 199 }WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
 200 #else
 201 typedef union   _WPDMA_RST_IDX_STRUC    {
 202         struct  {
 203                 UINT32          RST_DTX_IDX0:1;
 204                 UINT32          RST_DTX_IDX1:1;
 205                 UINT32          RST_DTX_IDX2:1;
 206                 UINT32          RST_DTX_IDX3:1;
 207                 UINT32          RST_DTX_IDX4:1;
 208                 UINT32          RST_DTX_IDX5:1;
 209                 UINT32          rsv:10;
 210                 UINT32          RST_DRX_IDX0:1;
 211                 UINT32          :15;
 212         }       field;
 213         UINT32                  word;
 214 } WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
 215 #endif
 216 #define DELAY_INT_CFG  0x0210
 217 #ifdef RT_BIG_ENDIAN
 218 typedef union   _DELAY_INT_CFG_STRUC    {
 219         struct  {
 220                 UINT32          TXDLY_INT_EN:1;
 221                 UINT32          TXMAX_PINT:7;
 222                 UINT32          TXMAX_PTIME:8;
 223                 UINT32          RXDLY_INT_EN:1;
 224                 UINT32          RXMAX_PINT:7;
 225                 UINT32          RXMAX_PTIME:8;
 226         }       field;
 227         UINT32                  word;
 228 }DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
 229 #else
 230 typedef union   _DELAY_INT_CFG_STRUC    {
 231         struct  {
 232                 UINT32          RXMAX_PTIME:8;
 233                 UINT32          RXMAX_PINT:7;
 234                 UINT32          RXDLY_INT_EN:1;
 235                 UINT32          TXMAX_PTIME:8;
 236                 UINT32          TXMAX_PINT:7;
 237                 UINT32          TXDLY_INT_EN:1;
 238         }       field;
 239         UINT32                  word;
 240 } DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
 241 #endif
 242 #define WMM_AIFSN_CFG   0x0214
 243 #ifdef RT_BIG_ENDIAN
 244 typedef union   _AIFSN_CSR_STRUC        {
 245         struct  {
 246             UINT32   Rsv:16;
 247             UINT32   Aifsn3:4;       // for AC_VO
 248             UINT32   Aifsn2:4;       // for AC_VI
 249             UINT32   Aifsn1:4;       // for AC_BK
 250             UINT32   Aifsn0:4;       // for AC_BE
 251         }       field;
 252         UINT32                  word;
 253 }       AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
 254 #else
 255 typedef union   _AIFSN_CSR_STRUC        {
 256         struct  {
 257             UINT32   Aifsn0:4;       // for AC_BE
 258             UINT32   Aifsn1:4;       // for AC_BK
 259             UINT32   Aifsn2:4;       // for AC_VI
 260             UINT32   Aifsn3:4;       // for AC_VO
 261             UINT32   Rsv:16;
 262         }       field;
 263         UINT32                  word;
 264 }       AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
 265 #endif
 266 //
 267 // CWMIN_CSR: CWmin for each EDCA AC
 268 //
 269 #define WMM_CWMIN_CFG   0x0218
 270 #ifdef RT_BIG_ENDIAN
 271 typedef union   _CWMIN_CSR_STRUC        {
 272         struct  {
 273             UINT32   Rsv:16;
 274             UINT32   Cwmin3:4;       // for AC_VO
 275             UINT32   Cwmin2:4;       // for AC_VI
 276             UINT32   Cwmin1:4;       // for AC_BK
 277             UINT32   Cwmin0:4;       // for AC_BE
 278         }       field;
 279         UINT32                  word;
 280 }       CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
 281 #else
 282 typedef union   _CWMIN_CSR_STRUC        {
 283         struct  {
 284             UINT32   Cwmin0:4;       // for AC_BE
 285             UINT32   Cwmin1:4;       // for AC_BK
 286             UINT32   Cwmin2:4;       // for AC_VI
 287             UINT32   Cwmin3:4;       // for AC_VO
 288             UINT32   Rsv:16;
 289         }       field;
 290         UINT32                  word;
 291 }       CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
 292 #endif
 293
 294 //
 295 // CWMAX_CSR: CWmin for each EDCA AC
 296 //
 297 #define WMM_CWMAX_CFG   0x021c
 298 #ifdef RT_BIG_ENDIAN
 299 typedef union   _CWMAX_CSR_STRUC        {
 300         struct  {
 301             UINT32   Rsv:16;
 302             UINT32   Cwmax3:4;       // for AC_VO
 303             UINT32   Cwmax2:4;       // for AC_VI
 304             UINT32   Cwmax1:4;       // for AC_BK
 305             UINT32   Cwmax0:4;       // for AC_BE
 306         }       field;
 307         UINT32                  word;
 308 }       CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
 309 #else
 310 typedef union   _CWMAX_CSR_STRUC        {
 311         struct  {
 312             UINT32   Cwmax0:4;       // for AC_BE
 313             UINT32   Cwmax1:4;       // for AC_BK
 314             UINT32   Cwmax2:4;       // for AC_VI
 315             UINT32   Cwmax3:4;       // for AC_VO
 316             UINT32   Rsv:16;
 317         }       field;
 318         UINT32                  word;
 319 }       CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
 320 #endif
 321
 322
 323 //
 324 // AC_TXOP_CSR0: AC_BK/AC_BE TXOP register
 325 //
 326 #define WMM_TXOP0_CFG    0x0220
 327 #ifdef RT_BIG_ENDIAN
 328 typedef union   _AC_TXOP_CSR0_STRUC     {
 329         struct  {
 330             USHORT  Ac1Txop;        // for AC_BE, in unit of 32us
 331             USHORT  Ac0Txop;        // for AC_BK, in unit of 32us
 332         }       field;
 333         UINT32                  word;
 334 }       AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
 335 #else
 336 typedef union   _AC_TXOP_CSR0_STRUC     {
 337         struct  {
 338             USHORT  Ac0Txop;        // for AC_BK, in unit of 32us
 339             USHORT  Ac1Txop;        // for AC_BE, in unit of 32us
 340         }       field;
 341         UINT32                  word;
 342 }       AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
 343 #endif
 344
 345 //
 346 // AC_TXOP_CSR1: AC_VO/AC_VI TXOP register
 347 //
 348 #define WMM_TXOP1_CFG    0x0224
 349 #ifdef RT_BIG_ENDIAN
 350 typedef union   _AC_TXOP_CSR1_STRUC     {
 351         struct  {
 352             USHORT  Ac3Txop;        // for AC_VO, in unit of 32us
 353             USHORT  Ac2Txop;        // for AC_VI, in unit of 32us
 354         }       field;
 355         UINT32                  word;
 356 }       AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
 357 #else
 358 typedef union   _AC_TXOP_CSR1_STRUC     {
 359         struct  {
 360             USHORT  Ac2Txop;        // for AC_VI, in unit of 32us
 361             USHORT  Ac3Txop;        // for AC_VO, in unit of 32us
 362         }       field;
 363         UINT32                  word;
 364 }       AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
 365 #endif
 366 #define RINGREG_DIFF                    0x10
 367 #define GPIO_CTRL_CFG    0x0228 //MAC_CSR13
 368 #define MCU_CMD_CFG    0x022c
 369 #define TX_BASE_PTR0     0x0230 //AC_BK base address
 370 #define TX_MAX_CNT0      0x0234
 371 #define TX_CTX_IDX0       0x0238
 372 #define TX_DTX_IDX0      0x023c
 373 #define TX_BASE_PTR1     0x0240         //AC_BE base address
 374 #define TX_MAX_CNT1      0x0244
 375 #define TX_CTX_IDX1       0x0248
 376 #define TX_DTX_IDX1      0x024c
 377 #define TX_BASE_PTR2     0x0250         //AC_VI base address
 378 #define TX_MAX_CNT2      0x0254
 379 #define TX_CTX_IDX2       0x0258
 380 #define TX_DTX_IDX2      0x025c
 381 #define TX_BASE_PTR3     0x0260         //AC_VO base address
 382 #define TX_MAX_CNT3      0x0264
 383 #define TX_CTX_IDX3       0x0268
 384 #define TX_DTX_IDX3      0x026c
 385 #define TX_BASE_PTR4     0x0270         //HCCA base address
 386 #define TX_MAX_CNT4      0x0274
 387 #define TX_CTX_IDX4       0x0278
 388 #define TX_DTX_IDX4      0x027c
 389 #define TX_BASE_PTR5     0x0280         //MGMT base address
 390 #define  TX_MAX_CNT5     0x0284
 391 #define TX_CTX_IDX5       0x0288
 392 #define TX_DTX_IDX5      0x028c
 393 #define TX_MGMTMAX_CNT      TX_MAX_CNT5
 394 #define TX_MGMTCTX_IDX       TX_CTX_IDX5
 395 #define TX_MGMTDTX_IDX      TX_DTX_IDX5
 396 #define RX_BASE_PTR     0x0290  //RX base address
 397 #define RX_MAX_CNT      0x0294
 398 #define RX_CRX_IDX       0x0298
 399 #define RX_DRX_IDX      0x029c
 400 #define USB_DMA_CFG      0x02a0
 401 #ifdef RT_BIG_ENDIAN
 402 typedef union   _USB_DMA_CFG_STRUC      {
 403         struct  {
 404             UINT32  TxBusy:1;           //USB DMA TX FSM busy . debug only
 405             UINT32  RxBusy:1;        //USB DMA RX FSM busy . debug only
 406             UINT32  EpoutValid:6;        //OUT endpoint data valid. debug only
 407             UINT32  TxBulkEn:1;        //Enable USB DMA Tx
 408             UINT32  RxBulkEn:1;        //Enable USB DMA Rx
 409             UINT32  RxBulkAggEn:1;        //Enable Rx Bulk Aggregation
 410             UINT32  TxopHalt:1;        //Halt TXOP count down when TX buffer is full.
 411             UINT32  TxClear:1;        //Clear USB DMA TX path
 412             UINT32  rsv:2;
 413             UINT32  phyclear:1;                 //phy watch dog enable. write 1
 414             UINT32  RxBulkAggLmt:8;        //Rx Bulk Aggregation Limit  in unit of 1024 bytes
 415             UINT32  RxBulkAggTOut:8;        //Rx Bulk Aggregation TimeOut  in unit of 33ns
 416         }       field;
 417         UINT32                  word;
 418 }       USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
 419 #else
 420 typedef union   _USB_DMA_CFG_STRUC      {
 421         struct  {
 422             UINT32  RxBulkAggTOut:8;        //Rx Bulk Aggregation TimeOut  in unit of 33ns
 423             UINT32  RxBulkAggLmt:8;        //Rx Bulk Aggregation Limit  in unit of 256 bytes
 424             UINT32  phyclear:1;                 //phy watch dog enable. write 1
 425             UINT32  rsv:2;
 426             UINT32  TxClear:1;        //Clear USB DMA TX path
 427             UINT32  TxopHalt:1;        //Halt TXOP count down when TX buffer is full.
 428             UINT32  RxBulkAggEn:1;        //Enable Rx Bulk Aggregation
 429             UINT32  RxBulkEn:1;        //Enable USB DMA Rx
 430             UINT32  TxBulkEn:1;        //Enable USB DMA Tx
 431             UINT32  EpoutValid:6;        //OUT endpoint data valid
 432             UINT32  RxBusy:1;        //USB DMA RX FSM busy
 433             UINT32  TxBusy:1;           //USB DMA TX FSM busy
 434         }       field;
 435         UINT32                  word;
 436 }       USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
 437 #endif
 438
 439 //
 440 //  3  PBF  registers
 441 //
 442 //
 443 // Most are for debug. Driver doesn't touch PBF register.
 444 #define         PBF_SYS_CTRL     0x0400
 445 #define     PBF_CFG                 0x0408
 446 #define         PBF_MAX_PCNT     0x040C
 447 #define         PBF_CTRL                0x0410
 448 #define         PBF_INT_STA      0x0414
 449 #define         PBF_INT_ENA      0x0418
 450 #define         TXRXQ_PCNT       0x0438
 451 #define         PBF_DBG                  0x043c
 452 #define     PBF_CAP_CTRL     0x0440
 453
 454 //
 455 //  4  MAC  registers
 456 //
 457 //
 458 //  4.1 MAC SYSTEM  configuration registers (offset:0x1000)
 459 //
 460 #define MAC_CSR0            0x1000
 461 #ifdef RT_BIG_ENDIAN
 462 typedef union   _ASIC_VER_ID_STRUC      {
 463         struct  {
 464             USHORT  ASICVer;        // version : 2860
 465             USHORT  ASICRev;        // reversion  : 0
 466         }       field;
 467         UINT32                  word;
 468 }       ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
 469 #else
 470 typedef union   _ASIC_VER_ID_STRUC      {
 471         struct  {
 472             USHORT  ASICRev;        // reversion  : 0
 473             USHORT  ASICVer;        // version : 2860
 474         }       field;
 475         UINT32                  word;
 476 }       ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
 477 #endif
 478 #define MAC_SYS_CTRL            0x1004          //MAC_CSR1
 479 #define MAC_ADDR_DW0                            0x1008          // MAC ADDR DW0
 480 #define MAC_ADDR_DW1                     0x100c         // MAC ADDR DW1
 481 //
 482 // MAC_CSR2: STA MAC register 0
 483 //
 484 #ifdef RT_BIG_ENDIAN
 485 typedef union   _MAC_DW0_STRUC  {
 486         struct  {
 487                 UCHAR           Byte3;          // MAC address byte 3
 488                 UCHAR           Byte2;          // MAC address byte 2
 489                 UCHAR           Byte1;          // MAC address byte 1
 490                 UCHAR           Byte0;          // MAC address byte 0
 491         }       field;
 492         UINT32                  word;
 493 }       MAC_DW0_STRUC, *PMAC_DW0_STRUC;
 494 #else
 495 typedef union   _MAC_DW0_STRUC  {
 496         struct  {
 497                 UCHAR           Byte0;          // MAC address byte 0
 498                 UCHAR           Byte1;          // MAC address byte 1
 499                 UCHAR           Byte2;          // MAC address byte 2
 500                 UCHAR           Byte3;          // MAC address byte 3
 501         }       field;
 502         UINT32                  word;
 503 }       MAC_DW0_STRUC, *PMAC_DW0_STRUC;
 504 #endif
 505
 506 //
 507 // MAC_CSR3: STA MAC register 1
 508 //
 509 #ifdef RT_BIG_ENDIAN
 510 typedef union   _MAC_DW1_STRUC  {
 511         struct  {
 512                 UCHAR           Rsvd1;
 513                 UCHAR           U2MeMask;
 514                 UCHAR           Byte5;          // MAC address byte 5
 515                 UCHAR           Byte4;          // MAC address byte 4
 516         }       field;
 517         UINT32                  word;
 518 }       MAC_DW1_STRUC, *PMAC_DW1_STRUC;
 519 #else
 520 typedef union   _MAC_DW1_STRUC  {
 521         struct  {
 522                 UCHAR           Byte4;          // MAC address byte 4
 523                 UCHAR           Byte5;          // MAC address byte 5
 524                 UCHAR           U2MeMask;
 525                 UCHAR           Rsvd1;
 526         }       field;
 527         UINT32                  word;
 528 }       MAC_DW1_STRUC, *PMAC_DW1_STRUC;
 529 #endif
 530
 531 #define MAC_BSSID_DW0                           0x1010          // MAC BSSID DW0
 532 #define MAC_BSSID_DW1                           0x1014          // MAC BSSID DW1
 533
 534 //
 535 // MAC_CSR5: BSSID register 1
 536 //
 537 #ifdef RT_BIG_ENDIAN
 538 typedef union   _MAC_CSR5_STRUC {
 539         struct  {
 540                 USHORT          Rsvd:11;
 541                 USHORT          MBssBcnNum:3;
 542                 USHORT          BssIdMode:2; // 0: one BSSID, 10: 4 BSSID,  01: 2 BSSID , 11: 8BSSID
 543                 UCHAR           Byte5;           // BSSID byte 5
 544                 UCHAR           Byte4;           // BSSID byte 4
 545         }       field;
 546         UINT32                  word;
 547 }       MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
 548 #else
 549 typedef union   _MAC_CSR5_STRUC {
 550         struct  {
 551                 UCHAR           Byte4;           // BSSID byte 4
 552                 UCHAR           Byte5;           // BSSID byte 5
 553                 USHORT          BssIdMask:2; // 0: one BSSID, 10: 4 BSSID,  01: 2 BSSID , 11: 8BSSID
 554                 USHORT          MBssBcnNum:3;
 555                 USHORT          Rsvd:11;
 556         }       field;
 557         UINT32                  word;
 558 }       MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
 559 #endif
 560
 561 #define MAX_LEN_CFG              0x1018         // rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
 562 #define BBP_CSR_CFG                     0x101c          //
 563 //
 564 // BBP_CSR_CFG: BBP serial control register
 565 //
 566 #ifdef RT_BIG_ENDIAN
 567 typedef union   _BBP_CSR_CFG_STRUC      {
 568         struct  {
 569                 UINT32          :12;
 570                 UINT32          BBP_RW_MODE:1;          // 0: use serial mode  1:parallel
 571                 UINT32          BBP_PAR_DUR:1;              // 0: 4 MAC clock cycles  1: 8 MAC clock cycles
 572                 UINT32          Busy:1;                         // 1: ASIC is busy execute BBP programming.
 573                 UINT32          fRead:1;                    // 0: Write BBP, 1: Read BBP
 574                 UINT32          RegNum:8;                       // Selected     BBP     register
 575                 UINT32          Value:8;                        // Register     value to program into BBP
 576         }       field;
 577         UINT32                  word;
 578 }       BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
 579 #else
 580 typedef union   _BBP_CSR_CFG_STRUC      {
 581         struct  {
 582                 UINT32          Value:8;                        // Register     value to program into BBP
 583                 UINT32          RegNum:8;                       // Selected     BBP     register
 584                 UINT32          fRead:1;                    // 0: Write BBP, 1: Read BBP
 585                 UINT32          Busy:1;                         // 1: ASIC is busy execute BBP programming.
 586                 UINT32          BBP_PAR_DUR:1;               // 0: 4 MAC clock cycles  1: 8 MAC clock cycles
 587                 UINT32          BBP_RW_MODE:1;          // 0: use serial mode  1:parallel
 588                 UINT32          :12;
 589         }       field;
 590         UINT32                  word;
 591 }       BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
 592 #endif
 593 #define RF_CSR_CFG0                     0x1020
 594 //
 595 // RF_CSR_CFG: RF control register
 596 //
 597 #ifdef RT_BIG_ENDIAN
 598 typedef union   _RF_CSR_CFG0_STRUC      {
 599         struct  {
 600                 UINT32          Busy:1;             // 0: idle 1: 8busy
 601                 UINT32          Sel:1;                          // 0:RF_LE0 activate  1:RF_LE1 activate
 602                 UINT32          StandbyMode:1;              // 0: high when stand by 1: low when standby
 603                 UINT32          bitwidth:5;                     // Selected     BBP     register
 604                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 605         }       field;
 606         UINT32                  word;
 607 }       RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
 608 #else
 609 typedef union   _RF_CSR_CFG0_STRUC      {
 610         struct  {
 611                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 612                 UINT32          bitwidth:5;                     // Selected     BBP     register
 613                 UINT32          StandbyMode:1;              // 0: high when stand by 1: low when standby
 614                 UINT32          Sel:1;                          // 0:RF_LE0 activate  1:RF_LE1 activate
 615                 UINT32          Busy:1;             // 0: idle 1: 8busy
 616         }       field;
 617         UINT32                  word;
 618 }       RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
 619 #endif
 620 #define RF_CSR_CFG1                     0x1024
 621 #ifdef RT_BIG_ENDIAN
 622 typedef union   _RF_CSR_CFG1_STRUC      {
 623         struct  {
 624                 UINT32          rsv:7;              // 0: idle 1: 8busy
 625                 UINT32          RFGap:5;                        // Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
 626                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 627         }       field;
 628         UINT32                  word;
 629 }       RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
 630 #else
 631 typedef union   _RF_CSR_CFG1_STRUC      {
 632         struct  {
 633                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 634                 UINT32          RFGap:5;                        // Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
 635                 UINT32          rsv:7;              // 0: idle 1: 8busy
 636         }       field;
 637         UINT32                  word;
 638 }       RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
 639 #endif
 640 #define RF_CSR_CFG2                     0x1028          //
 641 #ifdef RT_BIG_ENDIAN
 642 typedef union   _RF_CSR_CFG2_STRUC      {
 643         struct  {
 644                 UINT32          rsv:8;              // 0: idle 1: 8busy
 645                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 646         }       field;
 647         UINT32                  word;
 648 }       RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
 649 #else
 650 typedef union   _RF_CSR_CFG2_STRUC      {
 651         struct  {
 652                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 653                 UINT32          rsv:8;              // 0: idle 1: 8busy
 654         }       field;
 655         UINT32                  word;
 656 }       RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
 657 #endif
 658 #define LED_CFG                         0x102c          //  MAC_CSR14
 659 #ifdef RT_BIG_ENDIAN
 660 typedef union   _LED_CFG_STRUC  {
 661         struct  {
 662                 UINT32          :1;
 663                 UINT32          LedPolar:1;                     // Led Polarity.  0: active low1: active high
 664                 UINT32          YLedMode:2;                     // yellow Led Mode
 665                 UINT32          GLedMode:2;                     // green Led Mode
 666                 UINT32          RLedMode:2;                     // red Led Mode    0: off1: blinking upon TX2: periodic slow blinking3: always on
 667                 UINT32          rsv:2;
 668                 UINT32          SlowBlinkPeriod:6;                      // slow blinking period. unit:1ms
 669                 UINT32          OffPeriod:8;                    // blinking off period unit 1ms
 670                 UINT32          OnPeriod:8;                     // blinking on period unit 1ms
 671         }       field;
 672         UINT32                  word;
 673 }       LED_CFG_STRUC, *PLED_CFG_STRUC;
 674 #else
 675 typedef union   _LED_CFG_STRUC  {
 676         struct  {
 677                 UINT32          OnPeriod:8;                     // blinking on period unit 1ms
 678                 UINT32          OffPeriod:8;                    // blinking off period unit 1ms
 679                 UINT32          SlowBlinkPeriod:6;                      // slow blinking period. unit:1ms
 680                 UINT32          rsv:2;
 681                 UINT32          RLedMode:2;                     // red Led Mode    0: off1: blinking upon TX2: periodic slow blinking3: always on
 682                 UINT32          GLedMode:2;                     // green Led Mode
 683                 UINT32          YLedMode:2;                     // yellow Led Mode
 684                 UINT32          LedPolar:1;                     // Led Polarity.  0: active low1: active high
 685                 UINT32          :1;
 686         }       field;
 687         UINT32                  word;
 688 }       LED_CFG_STRUC, *PLED_CFG_STRUC;
 689 #endif
 690 //
 691 //  4.2 MAC TIMING  configuration registers (offset:0x1100)
 692 //
 693 #define XIFS_TIME_CFG             0x1100                 // MAC_CSR8  MAC_CSR9
 694 #ifdef RT_BIG_ENDIAN
 695 typedef union   _IFS_SLOT_CFG_STRUC     {
 696         struct  {
 697             UINT32  rsv:2;
 698             UINT32  BBRxendEnable:1;        //  reference RXEND signal to begin XIFS defer
 699             UINT32  EIFS:9;        //  unit 1us
 700             UINT32  OfdmXifsTime:4;        //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
 701             UINT32  OfdmSifsTime:8;        //  unit 1us. Applied after OFDM RX/TX
 702             UINT32  CckmSifsTime:8;        //  unit 1us. Applied after CCK RX/TX
 703         }       field;
 704         UINT32                  word;
 705 }       IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
 706 #else
 707 typedef union   _IFS_SLOT_CFG_STRUC     {
 708         struct  {
 709             UINT32  CckmSifsTime:8;        //  unit 1us. Applied after CCK RX/TX
 710             UINT32  OfdmSifsTime:8;        //  unit 1us. Applied after OFDM RX/TX
 711             UINT32  OfdmXifsTime:4;        //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
 712             UINT32  EIFS:9;        //  unit 1us
 713             UINT32  BBRxendEnable:1;        //  reference RXEND signal to begin XIFS defer
 714             UINT32  rsv:2;
 715         }       field;
 716         UINT32                  word;
 717 }       IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
 718 #endif
 719
 720 #define BKOFF_SLOT_CFG             0x1104                //  mac_csr9 last 8 bits
 721 #define NAV_TIME_CFG             0x1108          // NAV  (MAC_CSR15)
 722 #define CH_TIME_CFG             0x110C                  // Count as channel busy
 723 #define PBF_LIFE_TIMER             0x1110                //TX/RX MPDU timestamp timer (free run)Unit: 1us
 724 #define BCN_TIME_CFG             0x1114          // TXRX_CSR9
 725
 726 #define BCN_OFFSET0                             0x042C
 727 #define BCN_OFFSET1                             0x0430
 728
 729 //
 730 // BCN_TIME_CFG : Synchronization control register
 731 //
 732 #ifdef RT_BIG_ENDIAN
 733 typedef union   _BCN_TIME_CFG_STRUC     {
 734         struct  {
 735                 UINT32          TxTimestampCompensate:8;
 736         UINT32       :3;
 737                 UINT32          bBeaconGen:1;           // Enable beacon generator
 738         UINT32       bTBTTEnable:1;
 739                 UINT32          TsfSyncMode:2;          // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
 740                 UINT32          bTsfTicking:1;          // Enable TSF auto counting
 741                 UINT32       BeaconInterval:16;  // in unit of 1/16 TU
 742         }       field;
 743         UINT32                  word;
 744 }       BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
 745 #else
 746 typedef union   _BCN_TIME_CFG_STRUC     {
 747         struct  {
 748                 UINT32       BeaconInterval:16;  // in unit of 1/16 TU
 749                 UINT32          bTsfTicking:1;          // Enable TSF auto counting
 750                 UINT32          TsfSyncMode:2;          // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
 751         UINT32       bTBTTEnable:1;
 752                 UINT32          bBeaconGen:1;           // Enable beacon generator
 753         UINT32       :3;
 754                 UINT32          TxTimestampCompensate:8;
 755         }       field;
 756         UINT32                  word;
 757 }       BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
 758 #endif
 759 #define TBTT_SYNC_CFG            0x1118                 // txrx_csr10
 760 #define TSF_TIMER_DW0             0x111C                // Local TSF timer lsb 32 bits. Read-only
 761 #define TSF_TIMER_DW1             0x1120                // msb 32 bits. Read-only.
 762 #define TBTT_TIMER              0x1124                  // TImer remains till next TBTT. Read-only.  TXRX_CSR14
 763 #define INT_TIMER_CFG                   0x1128                  //
 764 #define INT_TIMER_EN                    0x112c                  //  GP-timer and pre-tbtt Int enable
 765 #define CH_IDLE_STA                     0x1130                  //  channel idle time
 766 #define CH_BUSY_STA                     0x1134                  //  channle busy time
 767 //
 768 //  4.2 MAC POWER  configuration registers (offset:0x1200)
 769 //
 770 #define MAC_STATUS_CFG             0x1200                // old MAC_CSR12
 771 #define PWR_PIN_CFG             0x1204           // old MAC_CSR12
 772 #define AUTO_WAKEUP_CFG             0x1208               // old MAC_CSR10
 773 //
 774 // AUTO_WAKEUP_CFG: Manual power control / status register
 775 //
 776 #ifdef RT_BIG_ENDIAN
 777 typedef union   _AUTO_WAKEUP_STRUC      {
 778         struct  {
 779                 UINT32          :16;
 780                 UINT32          EnableAutoWakeup:1;     // 0:sleep, 1:awake
 781                 UINT32       NumofSleepingTbtt:7;          // ForceWake has high privilege than PutToSleep when both set
 782                 UINT32       AutoLeadTime:8;
 783         }       field;
 784         UINT32                  word;
 785 }       AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
 786 #else
 787 typedef union   _AUTO_WAKEUP_STRUC      {
 788         struct  {
 789                 UINT32       AutoLeadTime:8;
 790                 UINT32       NumofSleepingTbtt:7;          // ForceWake has high privilege than PutToSleep when both set
 791                 UINT32          EnableAutoWakeup:1;     // 0:sleep, 1:awake
 792                 UINT32          :16;
 793         }       field;
 794         UINT32                  word;
 795 }       AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
 796 #endif
 797 //
 798 //  4.3 MAC TX  configuration registers (offset:0x1300)
 799 //
 800
 801 #define EDCA_AC0_CFG    0x1300          //AC_TXOP_CSR0 0x3474
 802 #define EDCA_AC1_CFG    0x1304
 803 #define EDCA_AC2_CFG    0x1308
 804 #define EDCA_AC3_CFG    0x130c
 805 #ifdef RT_BIG_ENDIAN
 806 typedef union   _EDCA_AC_CFG_STRUC      {
 807         struct  {
 808             UINT32  :12;        //
 809             UINT32  Cwmax:4;        //unit power of 2
 810             UINT32  Cwmin:4;        //
 811             UINT32  Aifsn:4;        // # of slot time
 812             UINT32  AcTxop:8;        //  in unit of 32us
 813         }       field;
 814         UINT32                  word;
 815 }       EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
 816 #else
 817 typedef union   _EDCA_AC_CFG_STRUC      {
 818         struct  {
 819             UINT32  AcTxop:8;        //  in unit of 32us
 820             UINT32  Aifsn:4;        // # of slot time
 821             UINT32  Cwmin:4;        //
 822             UINT32  Cwmax:4;        //unit power of 2
 823             UINT32  :12;       //
 824         }       field;
 825         UINT32                  word;
 826 }       EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
 827 #endif
 828
 829 #define EDCA_TID_AC_MAP 0x1310
 830 #define TX_PWR_CFG_0    0x1314
 831 #define TX_PWR_CFG_1    0x1318
 832 #define TX_PWR_CFG_2    0x131C
 833 #define TX_PWR_CFG_3    0x1320
 834 #define TX_PWR_CFG_4    0x1324
 835 #define TX_PIN_CFG              0x1328
 836 #define TX_BAND_CFG     0x132c          // 0x1 use upper 20MHz. 0 juse lower 20MHz
 837 #define TX_SW_CFG0              0x1330
 838 #define TX_SW_CFG1              0x1334
 839 #define TX_SW_CFG2              0x1338
 840 #define TXOP_THRES_CFG          0x133c
 841 #define TXOP_CTRL_CFG           0x1340
 842 #define TX_RTS_CFG              0x1344
 843
 844 #ifdef RT_BIG_ENDIAN
 845 typedef union   _TX_RTS_CFG_STRUC       {
 846         struct  {
 847             UINT32       rsv:7;
 848             UINT32       RtsFbkEn:1;    // enable rts rate fallback
 849             UINT32       RtsThres:16;    // unit:byte
 850             UINT32       AutoRtsRetryLimit:8;
 851         }       field;
 852         UINT32                  word;
 853 }       TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
 854 #else
 855 typedef union   _TX_RTS_CFG_STRUC       {
 856         struct  {
 857             UINT32       AutoRtsRetryLimit:8;
 858             UINT32       RtsThres:16;    // unit:byte
 859             UINT32       RtsFbkEn:1;    // enable rts rate fallback
 860             UINT32       rsv:7;     // 1: HT non-STBC control frame enable
 861         }       field;
 862         UINT32                  word;
 863 }       TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
 864 #endif
 865 #define TX_TIMEOUT_CFG  0x1348
 866 #ifdef RT_BIG_ENDIAN
 867 typedef union   _TX_TIMEOUT_CFG_STRUC   {
 868         struct  {
 869             UINT32       rsv2:8;
 870             UINT32       TxopTimeout:8; //TXOP timeout value for TXOP truncation.  It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
 871             UINT32       RxAckTimeout:8;        // unit:slot. Used for TX precedure
 872             UINT32       MpduLifeTime:4;    //  expiration time = 2^(9+MPDU LIFE TIME)  us
 873             UINT32       rsv:4;
 874         }       field;
 875         UINT32                  word;
 876 }       TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
 877 #else
 878 typedef union   _TX_TIMEOUT_CFG_STRUC   {
 879         struct  {
 880             UINT32       rsv:4;
 881             UINT32       MpduLifeTime:4;    //  expiration time = 2^(9+MPDU LIFE TIME)  us
 882             UINT32       RxAckTimeout:8;        // unit:slot. Used for TX precedure
 883             UINT32       TxopTimeout:8; //TXOP timeout value for TXOP truncation.  It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
 884             UINT32       rsv2:8;     // 1: HT non-STBC control frame enable
 885         }       field;
 886         UINT32                  word;
 887 }       TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
 888 #endif
 889 #define TX_RTY_CFG      0x134c
 890 #ifdef RT_BIG_ENDIAN
 891 typedef union PACKED _TX_RTY_CFG_STRUC  {
 892         struct  {
 893             UINT32       rsv:1;
 894             UINT32       TxautoFBEnable:1;    // Tx retry PHY rate auto fallback enable
 895             UINT32       AggRtyMode:1;  // Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
 896             UINT32       NonAggRtyMode:1;       // Non-Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
 897             UINT32       LongRtyThre:12;        // Long retry threshoold
 898             UINT32       LongRtyLimit:8;        //long retry limit
 899             UINT32       ShortRtyLimit:8;       //  short retry limit
 900
 901         }       field;
 902         UINT32                  word;
 903 }       TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
 904 #else
 905 typedef union PACKED _TX_RTY_CFG_STRUC  {
 906         struct  {
 907             UINT32       ShortRtyLimit:8;       //  short retry limit
 908             UINT32       LongRtyLimit:8;        //long retry limit
 909             UINT32       LongRtyThre:12;        // Long retry threshoold
 910             UINT32       NonAggRtyMode:1;       // Non-Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
 911             UINT32       AggRtyMode:1;  // Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
 912             UINT32       TxautoFBEnable:1;    // Tx retry PHY rate auto fallback enable
 913             UINT32       rsv:1;     // 1: HT non-STBC control frame enable
 914         }       field;
 915         UINT32                  word;
 916 }       TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
 917 #endif
 918 #define TX_LINK_CFG     0x1350
 919 #ifdef RT_BIG_ENDIAN
 920 typedef union   PACKED _TX_LINK_CFG_STRUC       {
 921         struct PACKED {
 922             UINT32       RemotMFS:8;    //remote MCS feedback sequence number
 923             UINT32       RemotMFB:8;    //  remote MCS feedback
 924             UINT32       rsv:3; //
 925             UINT32       TxCFAckEn:1;   //   Piggyback CF-ACK enable
 926             UINT32       TxRDGEn:1;     // RDG TX enable
 927             UINT32       TxMRQEn:1;     //  MCS request TX enable
 928             UINT32       RemoteUMFSEnable:1;    //  remote unsolicit  MFB enable.  0: not apply remote remote unsolicit (MFS=7)
 929             UINT32       MFBEnable:1;   //  TX apply remote MFB 1:enable
 930             UINT32       RemoteMFBLifeTime:8;   //remote MFB life time. unit : 32us
 931         }       field;
 932         UINT32                  word;
 933 }       TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
 934 #else
 935 typedef union   PACKED _TX_LINK_CFG_STRUC       {
 936         struct PACKED {
 937             UINT32       RemoteMFBLifeTime:8;   //remote MFB life time. unit : 32us
 938             UINT32       MFBEnable:1;   //  TX apply remote MFB 1:enable
 939             UINT32       RemoteUMFSEnable:1;    //  remote unsolicit  MFB enable.  0: not apply remote remote unsolicit (MFS=7)
 940             UINT32       TxMRQEn:1;     //  MCS request TX enable
 941             UINT32       TxRDGEn:1;     // RDG TX enable
 942             UINT32       TxCFAckEn:1;   //   Piggyback CF-ACK enable
 943             UINT32       rsv:3; //
 944             UINT32       RemotMFB:8;    //  remote MCS feedback
 945             UINT32       RemotMFS:8;    //remote MCS feedback sequence number
 946         }       field;
 947         UINT32                  word;
 948 }       TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
 949 #endif
 950 #define HT_FBK_CFG0     0x1354
 951 #ifdef RT_BIG_ENDIAN
 952 typedef union PACKED _HT_FBK_CFG0_STRUC {
 953         struct  {
 954             UINT32       HTMCS7FBK:4;
 955             UINT32       HTMCS6FBK:4;
 956             UINT32       HTMCS5FBK:4;
 957             UINT32       HTMCS4FBK:4;
 958             UINT32       HTMCS3FBK:4;
 959             UINT32       HTMCS2FBK:4;
 960             UINT32       HTMCS1FBK:4;
 961             UINT32       HTMCS0FBK:4;
 962         }       field;
 963         UINT32                  word;
 964 }       HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
 965 #else
 966 typedef union PACKED _HT_FBK_CFG0_STRUC {
 967         struct  {
 968             UINT32       HTMCS0FBK:4;
 969             UINT32       HTMCS1FBK:4;
 970             UINT32       HTMCS2FBK:4;
 971             UINT32       HTMCS3FBK:4;
 972             UINT32       HTMCS4FBK:4;
 973             UINT32       HTMCS5FBK:4;
 974             UINT32       HTMCS6FBK:4;
 975             UINT32       HTMCS7FBK:4;
 976         }       field;
 977         UINT32                  word;
 978 }       HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
 979 #endif
 980 #define HT_FBK_CFG1     0x1358
 981 #ifdef RT_BIG_ENDIAN
 982 typedef union   _HT_FBK_CFG1_STRUC      {
 983         struct  {
 984             UINT32       HTMCS15FBK:4;
 985             UINT32       HTMCS14FBK:4;
 986             UINT32       HTMCS13FBK:4;
 987             UINT32       HTMCS12FBK:4;
 988             UINT32       HTMCS11FBK:4;
 989             UINT32       HTMCS10FBK:4;
 990             UINT32       HTMCS9FBK:4;
 991             UINT32       HTMCS8FBK:4;
 992         }       field;
 993         UINT32                  word;
 994 }       HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
 995 #else
 996 typedef union   _HT_FBK_CFG1_STRUC      {
 997         struct  {
 998             UINT32       HTMCS8FBK:4;
 999             UINT32       HTMCS9FBK:4;
1000             UINT32       HTMCS10FBK:4;
1001             UINT32       HTMCS11FBK:4;
1002             UINT32       HTMCS12FBK:4;
1003             UINT32       HTMCS13FBK:4;
1004             UINT32       HTMCS14FBK:4;
1005             UINT32       HTMCS15FBK:4;
1006         }       field;
1007         UINT32                  word;
1008 }       HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
1009 #endif
1010 #define LG_FBK_CFG0     0x135c
1011 #ifdef RT_BIG_ENDIAN
1012 typedef union   _LG_FBK_CFG0_STRUC      {
1013         struct  {
1014             UINT32       OFDMMCS7FBK:4; //initial value is 6
1015             UINT32       OFDMMCS6FBK:4; //initial value is 5
1016             UINT32       OFDMMCS5FBK:4; //initial value is 4
1017             UINT32       OFDMMCS4FBK:4; //initial value is 3
1018             UINT32       OFDMMCS3FBK:4; //initial value is 2
1019             UINT32       OFDMMCS2FBK:4; //initial value is 1
1020             UINT32       OFDMMCS1FBK:4; //initial value is 0
1021             UINT32       OFDMMCS0FBK:4; //initial value is 0
1022         }       field;
1023         UINT32                  word;
1024 }       LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
1025 #else
1026 typedef union   _LG_FBK_CFG0_STRUC      {
1027         struct  {
1028             UINT32       OFDMMCS0FBK:4; //initial value is 0
1029             UINT32       OFDMMCS1FBK:4; //initial value is 0
1030             UINT32       OFDMMCS2FBK:4; //initial value is 1
1031             UINT32       OFDMMCS3FBK:4; //initial value is 2
1032             UINT32       OFDMMCS4FBK:4; //initial value is 3
1033             UINT32       OFDMMCS5FBK:4; //initial value is 4
1034             UINT32       OFDMMCS6FBK:4; //initial value is 5
1035             UINT32       OFDMMCS7FBK:4; //initial value is 6
1036         }       field;
1037         UINT32                  word;
1038 }       LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
1039 #endif
1040 #define LG_FBK_CFG1             0x1360
1041 #ifdef RT_BIG_ENDIAN
1042 typedef union   _LG_FBK_CFG1_STRUC      {
1043         struct  {
1044             UINT32       rsv:16;
1045             UINT32       CCKMCS3FBK:4;  //initial value is 2
1046             UINT32       CCKMCS2FBK:4;  //initial value is 1
1047             UINT32       CCKMCS1FBK:4;  //initial value is 0
1048             UINT32       CCKMCS0FBK:4;  //initial value is 0
1049         }       field;
1050         UINT32                  word;
1051 }       LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
1052 #else
1053 typedef union   _LG_FBK_CFG1_STRUC      {
1054         struct  {
1055             UINT32       CCKMCS0FBK:4;  //initial value is 0
1056             UINT32       CCKMCS1FBK:4;  //initial value is 0
1057             UINT32       CCKMCS2FBK:4;  //initial value is 1
1058             UINT32       CCKMCS3FBK:4;  //initial value is 2
1059             UINT32       rsv:16;
1060         }       field;
1061         UINT32                  word;
1062 }       LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
1063 #endif
1064
1065 //=======================================================
1066 //================ Protection Paramater================================
1067 //=======================================================
1068 #define CCK_PROT_CFG    0x1364          //CCK Protection
1069 #define ASIC_SHORTNAV           1
1070 #define ASIC_LONGNAV            2
1071 #define ASIC_RTS                1
1072 #define ASIC_CTS                2
1073 #ifdef RT_BIG_ENDIAN
1074 typedef union   _PROT_CFG_STRUC {
1075         struct  {
1076             UINT32       rsv:5;
1077             UINT32       RTSThEn:1;     //RTS threshold enable on CCK TX
1078             UINT32       TxopAllowGF40:1;       //CCK TXOP allowance.0:disallow.
1079             UINT32       TxopAllowGF20:1;       //CCK TXOP allowance.0:disallow.
1080             UINT32       TxopAllowMM40:1;       //CCK TXOP allowance.0:disallow.
1081             UINT32       TxopAllowMM20:1;       //CCK TXOP allowance. 0:disallow.
1082             UINT32       TxopAllowOfdm:1;       //CCK TXOP allowance.0:disallow.
1083             UINT32       TxopAllowCck:1;        //CCK TXOP allowance.0:disallow.
1084             UINT32       ProtectNav:2;  //TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect,  2:LongNAVProtect, 3:rsv
1085             UINT32       ProtectCtrl:2; //Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
1086             UINT32       ProtectRate:16;        //Protection control frame rate for CCK TX(RTS/CTS/CFEnd).
1087         }       field;
1088         UINT32                  word;
1089 }       PROT_CFG_STRUC, *PPROT_CFG_STRUC;
1090 #else
1091 typedef union   _PROT_CFG_STRUC {
1092         struct  {
1093             UINT32       ProtectRate:16;        //Protection control frame rate for CCK TX(RTS/CTS/CFEnd).
1094             UINT32       ProtectCtrl:2; //Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
1095             UINT32       ProtectNav:2;  //TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect,  2:LongNAVProtect, 3:rsv
1096             UINT32       TxopAllowCck:1;        //CCK TXOP allowance.0:disallow.
1097             UINT32       TxopAllowOfdm:1;       //CCK TXOP allowance.0:disallow.
1098             UINT32       TxopAllowMM20:1;       //CCK TXOP allowance. 0:disallow.
1099             UINT32       TxopAllowMM40:1;       //CCK TXOP allowance.0:disallow.
1100             UINT32       TxopAllowGF20:1;       //CCK TXOP allowance.0:disallow.
1101             UINT32       TxopAllowGF40:1;       //CCK TXOP allowance.0:disallow.
1102             UINT32       RTSThEn:1;     //RTS threshold enable on CCK TX
1103             UINT32       rsv:5;
1104         }       field;
1105         UINT32                  word;
1106 }       PROT_CFG_STRUC, *PPROT_CFG_STRUC;
1107 #endif
1108
1109 #define OFDM_PROT_CFG   0x1368          //OFDM Protection
1110 #define MM20_PROT_CFG   0x136C          //MM20 Protection
1111 #define MM40_PROT_CFG   0x1370          //MM40 Protection
1112 #define GF20_PROT_CFG   0x1374          //GF20 Protection
1113 #define GF40_PROT_CFG   0x1378          //GR40 Protection
1114 #define EXP_CTS_TIME    0x137C          //
1115 #define EXP_ACK_TIME    0x1380          //
1116
1117 //
1118 //  4.4 MAC RX configuration registers (offset:0x1400)
1119 //
1120 #define RX_FILTR_CFG    0x1400                  //TXRX_CSR0
1121 #define AUTO_RSP_CFG    0x1404                  //TXRX_CSR4
1122 //
1123 // TXRX_CSR4: Auto-Responder/
1124 //
1125 #ifdef RT_BIG_ENDIAN
1126 typedef union _AUTO_RSP_CFG_STRUC {
1127  struct {
1128      UINT32        :24;
1129      UINT32       AckCtsPsmBit:1;   // Power bit value in conrtrol frame
1130      UINT32       DualCTSEn:1;   // Power bit value in conrtrol frame
1131      UINT32       rsv:1;   // Power bit value in conrtrol frame
1132      UINT32       AutoResponderPreamble:1;    // 0:long, 1:short preamble
1133      UINT32       CTS40MRef:1;  // Response CTS 40MHz duplicate mode
1134      UINT32       CTS40MMode:1;  // Response CTS 40MHz duplicate mode
1135      UINT32       BACAckPolicyEnable:1;    // 0:long, 1:short preamble
1136      UINT32       AutoResponderEnable:1;
1137  } field;
1138  UINT32   word;
1139 } AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
1140 #else
1141 typedef union _AUTO_RSP_CFG_STRUC {
1142  struct {
1143      UINT32       AutoResponderEnable:1;
1144      UINT32       BACAckPolicyEnable:1;    // 0:long, 1:short preamble
1145      UINT32       CTS40MMode:1;  // Response CTS 40MHz duplicate mode
1146      UINT32       CTS40MRef:1;  // Response CTS 40MHz duplicate mode
1147      UINT32       AutoResponderPreamble:1;    // 0:long, 1:short preamble
1148      UINT32       rsv:1;   // Power bit value in conrtrol frame
1149      UINT32       DualCTSEn:1;   // Power bit value in conrtrol frame
1150      UINT32       AckCtsPsmBit:1;   // Power bit value in conrtrol frame
1151      UINT32        :24;
1152  } field;
1153  UINT32   word;
1154 } AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
1155 #endif
1156
1157 #define LEGACY_BASIC_RATE       0x1408  //  TXRX_CSR5           0x3054
1158 #define HT_BASIC_RATE           0x140c
1159 #define HT_CTRL_CFG             0x1410
1160 #define SIFS_COST_CFG           0x1414
1161 #define RX_PARSER_CFG           0x1418  //Set NAV for all received frames
1162
1163 //
1164 //  4.5 MAC Security configuration (offset:0x1500)
1165 //
1166 #define TX_SEC_CNT0             0x1500          //
1167 #define RX_SEC_CNT0             0x1504          //
1168 #define CCMP_FC_MUTE            0x1508          //
1169 //
1170 //  4.6 HCCA/PSMP (offset:0x1600)
1171 //
1172 #define TXOP_HLDR_ADDR0         0x1600
1173 #define TXOP_HLDR_ADDR1         0x1604
1174 #define TXOP_HLDR_ET            0x1608
1175 #define QOS_CFPOLL_RA_DW0               0x160c
1176 #define QOS_CFPOLL_A1_DW1               0x1610
1177 #define QOS_CFPOLL_QC           0x1614
1178 //
1179 //  4.7 MAC Statistis registers (offset:0x1700)
1180 //
1181 #define RX_STA_CNT0             0x1700          //
1182 #define RX_STA_CNT1             0x1704          //
1183 #define RX_STA_CNT2             0x1708          //
1184
1185 //
1186 // RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count
1187 //
1188 #ifdef RT_BIG_ENDIAN
1189 typedef union   _RX_STA_CNT0_STRUC      {
1190         struct  {
1191             USHORT  PhyErr;
1192             USHORT  CrcErr;
1193         }       field;
1194         UINT32                  word;
1195 }       RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
1196 #else
1197 typedef union   _RX_STA_CNT0_STRUC      {
1198         struct  {
1199             USHORT  CrcErr;
1200             USHORT  PhyErr;
1201         }       field;
1202         UINT32                  word;
1203 }       RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
1204 #endif
1205
1206 //
1207 // RX_STA_CNT1_STRUC: RX False CCA count & RX LONG frame count
1208 //
1209 #ifdef RT_BIG_ENDIAN
1210 typedef union   _RX_STA_CNT1_STRUC      {
1211         struct  {
1212             USHORT  PlcpErr;
1213             USHORT  FalseCca;
1214         }       field;
1215         UINT32                  word;
1216 }       RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
1217 #else
1218 typedef union   _RX_STA_CNT1_STRUC      {
1219         struct  {
1220             USHORT  FalseCca;
1221             USHORT  PlcpErr;
1222         }       field;
1223         UINT32                  word;
1224 }       RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
1225 #endif
1226
1227 //
1228 // RX_STA_CNT2_STRUC:
1229 //
1230 #ifdef RT_BIG_ENDIAN
1231 typedef union   _RX_STA_CNT2_STRUC      {
1232         struct  {
1233             USHORT  RxFifoOverflowCount;
1234             USHORT  RxDupliCount;
1235         }       field;
1236         UINT32                  word;
1237 }       RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
1238 #else
1239 typedef union   _RX_STA_CNT2_STRUC      {
1240         struct  {
1241             USHORT  RxDupliCount;
1242             USHORT  RxFifoOverflowCount;
1243         }       field;
1244         UINT32                  word;
1245 }       RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
1246 #endif
1247 #define TX_STA_CNT0             0x170C          //
1248 //
1249 // STA_CSR3: TX Beacon count
1250 //
1251 #ifdef RT_BIG_ENDIAN
1252 typedef union   _TX_STA_CNT0_STRUC      {
1253         struct  {
1254             USHORT  TxBeaconCount;
1255             USHORT  TxFailCount;
1256         }       field;
1257         UINT32                  word;
1258 }       TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
1259 #else
1260 typedef union   _TX_STA_CNT0_STRUC      {
1261         struct  {
1262             USHORT  TxFailCount;
1263             USHORT  TxBeaconCount;
1264         }       field;
1265         UINT32                  word;
1266 }       TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
1267 #endif
1268 #define TX_STA_CNT1             0x1710          //
1269 //
1270 // TX_STA_CNT1: TX tx count
1271 //
1272 #ifdef RT_BIG_ENDIAN
1273 typedef union   _TX_STA_CNT1_STRUC      {
1274         struct  {
1275             USHORT  TxRetransmit;
1276             USHORT  TxSuccess;
1277         }       field;
1278         UINT32                  word;
1279 }       TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
1280 #else
1281 typedef union   _TX_STA_CNT1_STRUC      {
1282         struct  {
1283             USHORT  TxSuccess;
1284             USHORT  TxRetransmit;
1285         }       field;
1286         UINT32                  word;
1287 }       TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
1288 #endif
1289 #define TX_STA_CNT2             0x1714          //
1290 //
1291 // TX_STA_CNT2: TX tx count
1292 //
1293 #ifdef RT_BIG_ENDIAN
1294 typedef union   _TX_STA_CNT2_STRUC      {
1295         struct  {
1296             USHORT  TxUnderFlowCount;
1297             USHORT  TxZeroLenCount;
1298         }       field;
1299         UINT32                  word;
1300 }       TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
1301 #else
1302 typedef union   _TX_STA_CNT2_STRUC      {
1303         struct  {
1304             USHORT  TxZeroLenCount;
1305             USHORT  TxUnderFlowCount;
1306         }       field;
1307         UINT32                  word;
1308 }       TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
1309 #endif
1310 #define TX_STA_FIFO             0x1718          //
1311 //
1312 // TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register
1313 //
1314 #ifdef RT_BIG_ENDIAN
1315 typedef union PACKED _TX_STA_FIFO_STRUC {
1316         struct  {
1317                 UINT32          Reserve:2;
1318                 UINT32          TxBF:1; // 3*3
1319                 UINT32          SuccessRate:13; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
1320 //              UINT32          SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
1321                 UINT32          wcid:8;         //wireless client index
1322                 UINT32          TxAckRequired:1;    // ack required
1323                 UINT32          TxAggre:1;    // Tx is aggregated
1324                 UINT32          TxSuccess:1;   // Tx success. whether success or not
1325                 UINT32          PidType:4;
1326                 UINT32          bValid:1;   // 1:This register contains a valid TX result
1327         }       field;
1328         UINT32                  word;
1329 }       TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
1330 #else
1331 typedef union PACKED _TX_STA_FIFO_STRUC {
1332         struct  {
1333                 UINT32          bValid:1;   // 1:This register contains a valid TX result
1334                 UINT32          PidType:4;
1335                 UINT32          TxSuccess:1;   // Tx No retry success
1336                 UINT32          TxAggre:1;    // Tx Retry Success
1337                 UINT32          TxAckRequired:1;    // Tx fail
1338                 UINT32          wcid:8;         //wireless client index
1339 //              UINT32          SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
1340                 UINT32          SuccessRate:13; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
1341                 UINT32          TxBF:1;
1342                 UINT32          Reserve:2;
1343         }       field;
1344         UINT32                  word;
1345 }       TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
1346 #endif
1347 // Debug counter
1348 #define TX_AGG_CNT      0x171c
1349 #ifdef RT_BIG_ENDIAN
1350 typedef union   _TX_AGG_CNT_STRUC       {
1351         struct  {
1352             USHORT  AggTxCount;
1353             USHORT  NonAggTxCount;
1354         }       field;
1355         UINT32                  word;
1356 }       TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
1357 #else
1358 typedef union   _TX_AGG_CNT_STRUC       {
1359         struct  {
1360             USHORT  NonAggTxCount;
1361             USHORT  AggTxCount;
1362         }       field;
1363         UINT32                  word;
1364 }       TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
1365 #endif
1366 // Debug counter
1367 #define TX_AGG_CNT0     0x1720
1368 #ifdef RT_BIG_ENDIAN
1369 typedef union   _TX_AGG_CNT0_STRUC      {
1370         struct  {
1371             USHORT  AggSize2Count;
1372             USHORT  AggSize1Count;
1373         }       field;
1374         UINT32                  word;
1375 }       TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
1376 #else
1377 typedef union   _TX_AGG_CNT0_STRUC      {
1378         struct  {
1379             USHORT  AggSize1Count;
1380             USHORT  AggSize2Count;
1381         }       field;
1382         UINT32                  word;
1383 }       TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
1384 #endif
1385 // Debug counter
1386 #define TX_AGG_CNT1     0x1724
1387 #ifdef RT_BIG_ENDIAN
1388 typedef union   _TX_AGG_CNT1_STRUC      {
1389         struct  {
1390             USHORT  AggSize4Count;
1391             USHORT  AggSize3Count;
1392         }       field;
1393         UINT32                  word;
1394 }       TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
1395 #else
1396 typedef union   _TX_AGG_CNT1_STRUC      {
1397         struct  {
1398             USHORT  AggSize3Count;
1399             USHORT  AggSize4Count;
1400         }       field;
1401         UINT32                  word;
1402 }       TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
1403 #endif
1404 #define TX_AGG_CNT2     0x1728
1405 #ifdef RT_BIG_ENDIAN
1406 typedef union   _TX_AGG_CNT2_STRUC      {
1407         struct  {
1408             USHORT  AggSize6Count;
1409             USHORT  AggSize5Count;
1410         }       field;
1411         UINT32                  word;
1412 }       TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
1413 #else
1414 typedef union   _TX_AGG_CNT2_STRUC      {
1415         struct  {
1416             USHORT  AggSize5Count;
1417             USHORT  AggSize6Count;
1418         }       field;
1419         UINT32                  word;
1420 }       TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
1421 #endif
1422 // Debug counter
1423 #define TX_AGG_CNT3     0x172c
1424 #ifdef RT_BIG_ENDIAN
1425 typedef union   _TX_AGG_CNT3_STRUC      {
1426         struct  {
1427             USHORT  AggSize8Count;
1428             USHORT  AggSize7Count;
1429         }       field;
1430         UINT32                  word;
1431 }       TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
1432 #else
1433 typedef union   _TX_AGG_CNT3_STRUC      {
1434         struct  {
1435             USHORT  AggSize7Count;
1436             USHORT  AggSize8Count;
1437         }       field;
1438         UINT32                  word;
1439 }       TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
1440 #endif
1441 // Debug counter
1442 #define TX_AGG_CNT4     0x1730
1443 #ifdef RT_BIG_ENDIAN
1444 typedef union   _TX_AGG_CNT4_STRUC      {
1445         struct  {
1446             USHORT  AggSize10Count;
1447             USHORT  AggSize9Count;
1448         }       field;
1449         UINT32                  word;
1450 }       TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
1451 #else
1452 typedef union   _TX_AGG_CNT4_STRUC      {
1453         struct  {
1454             USHORT  AggSize9Count;
1455             USHORT  AggSize10Count;
1456         }       field;
1457         UINT32                  word;
1458 }       TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
1459 #endif
1460 #define TX_AGG_CNT5     0x1734
1461 #ifdef RT_BIG_ENDIAN
1462 typedef union   _TX_AGG_CNT5_STRUC      {
1463         struct  {
1464             USHORT  AggSize12Count;
1465             USHORT  AggSize11Count;
1466         }       field;
1467         UINT32                  word;
1468 }       TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
1469 #else
1470 typedef union   _TX_AGG_CNT5_STRUC      {
1471         struct  {
1472             USHORT  AggSize11Count;
1473             USHORT  AggSize12Count;
1474         }       field;
1475         UINT32                  word;
1476 }       TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
1477 #endif
1478 #define TX_AGG_CNT6             0x1738
1479 #ifdef RT_BIG_ENDIAN
1480 typedef union   _TX_AGG_CNT6_STRUC      {
1481         struct  {
1482             USHORT  AggSize14Count;
1483             USHORT  AggSize13Count;
1484         }       field;
1485         UINT32                  word;
1486 }       TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
1487 #else
1488 typedef union   _TX_AGG_CNT6_STRUC      {
1489         struct  {
1490             USHORT  AggSize13Count;
1491             USHORT  AggSize14Count;
1492         }       field;
1493         UINT32                  word;
1494 }       TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
1495 #endif
1496 #define TX_AGG_CNT7             0x173c
1497 #ifdef RT_BIG_ENDIAN
1498 typedef union   _TX_AGG_CNT7_STRUC      {
1499         struct  {
1500             USHORT  AggSize16Count;
1501             USHORT  AggSize15Count;
1502         }       field;
1503         UINT32                  word;
1504 }       TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
1505 #else
1506 typedef union   _TX_AGG_CNT7_STRUC      {
1507         struct  {
1508             USHORT  AggSize15Count;
1509             USHORT  AggSize16Count;
1510         }       field;
1511         UINT32                  word;
1512 }       TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
1513 #endif
1514 #define MPDU_DENSITY_CNT                0x1740
1515 #ifdef RT_BIG_ENDIAN
1516 typedef union   _MPDU_DEN_CNT_STRUC     {
1517         struct  {
1518             USHORT  RXZeroDelCount;     //RX zero length delimiter count
1519             USHORT  TXZeroDelCount;     //TX zero length delimiter count
1520         }       field;
1521         UINT32                  word;
1522 }       MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
1523 #else
1524 typedef union   _MPDU_DEN_CNT_STRUC     {
1525         struct  {
1526             USHORT  TXZeroDelCount;     //TX zero length delimiter count
1527             USHORT  RXZeroDelCount;     //RX zero length delimiter count
1528         }       field;
1529         UINT32                  word;
1530 }       MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
1531 #endif
1532 //
1533 // TXRX control registers - base address 0x3000
1534 //
1535 // rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1536 #define TXRX_CSR1           0x77d0
1537
1538 //
1539 // Security key table memory, base address = 0x1000
1540 //
1541 #define MAC_WCID_BASE           0x1800 //8-bytes(use only 6-bytes) * 256 entry =
1542 #define HW_WCID_ENTRY_SIZE   8
1543 #define PAIRWISE_KEY_TABLE_BASE     0x4000      // 32-byte * 256-entry =  -byte
1544 #define HW_KEY_ENTRY_SIZE           0x20
1545 #define PAIRWISE_IVEIV_TABLE_BASE     0x6000      // 8-byte * 256-entry =  -byte
1546 #define MAC_IVEIV_TABLE_BASE     0x6000      // 8-byte * 256-entry =  -byte
1547 #define HW_IVEIV_ENTRY_SIZE   8
1548 #define MAC_WCID_ATTRIBUTE_BASE     0x6800      // 4-byte * 256-entry =  -byte
1549 #define HW_WCID_ATTRI_SIZE   4
1550 #define WCID_RESERVED                   0x6bfc
1551 #define SHARED_KEY_TABLE_BASE       0x6c00      // 32-byte * 16-entry = 512-byte
1552 #define SHARED_KEY_MODE_BASE       0x7000      // 32-byte * 16-entry = 512-byte
1553 #define HW_SHARED_KEY_MODE_SIZE   4
1554 #define SHAREDKEYTABLE                  0
1555 #define PAIRWISEKEYTABLE                        1
1556
1557
1558 #ifdef RT_BIG_ENDIAN
1559 typedef union   _SHAREDKEY_MODE_STRUC   {
1560         struct  {
1561                 UINT32       :1;
1562                 UINT32       Bss1Key3CipherAlg:3;
1563                 UINT32       :1;
1564                 UINT32       Bss1Key2CipherAlg:3;
1565                 UINT32       :1;
1566                 UINT32       Bss1Key1CipherAlg:3;
1567                 UINT32       :1;
1568                 UINT32       Bss1Key0CipherAlg:3;
1569                 UINT32       :1;
1570                 UINT32       Bss0Key3CipherAlg:3;
1571                 UINT32       :1;
1572                 UINT32       Bss0Key2CipherAlg:3;
1573                 UINT32       :1;
1574                 UINT32       Bss0Key1CipherAlg:3;
1575                 UINT32       :1;
1576                 UINT32       Bss0Key0CipherAlg:3;
1577         }       field;
1578         UINT32                  word;
1579 }       SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
1580 #else
1581 typedef union   _SHAREDKEY_MODE_STRUC   {
1582         struct  {
1583                 UINT32       Bss0Key0CipherAlg:3;
1584                 UINT32       :1;
1585                 UINT32       Bss0Key1CipherAlg:3;
1586                 UINT32       :1;
1587                 UINT32       Bss0Key2CipherAlg:3;
1588                 UINT32       :1;
1589                 UINT32       Bss0Key3CipherAlg:3;
1590                 UINT32       :1;
1591                 UINT32       Bss1Key0CipherAlg:3;
1592                 UINT32       :1;
1593                 UINT32       Bss1Key1CipherAlg:3;
1594                 UINT32       :1;
1595                 UINT32       Bss1Key2CipherAlg:3;
1596                 UINT32       :1;
1597                 UINT32       Bss1Key3CipherAlg:3;
1598                 UINT32       :1;
1599         }       field;
1600         UINT32                  word;
1601 }       SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
1602 #endif
1603 // 64-entry for pairwise key table
1604 typedef struct _HW_WCID_ENTRY {  // 8-byte per entry
1605     UCHAR   Address[6];
1606     UCHAR   Rsv[2];
1607 } HW_WCID_ENTRY, PHW_WCID_ENTRY;
1608
1609
1610
1611 //
1612 // Other on-chip shared memory space, base = 0x2000
1613 //
1614
1615 // CIS space - base address = 0x2000
1616 #define HW_CIS_BASE             0x2000
1617
1618 // Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function.
1619 #define HW_CS_CTS_BASE                  0x7700
1620 // DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1621 #define HW_DFS_CTS_BASE                 0x7780
1622 #define HW_CTS_FRAME_SIZE               0x80
1623
1624 // 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes
1625 // to save debugging settings
1626 #define HW_DEBUG_SETTING_BASE   0x77f0  // 0x77f0~0x77ff total 16 bytes
1627 #define HW_DEBUG_SETTING_BASE2   0x7770  // 0x77f0~0x77ff total 16 bytes
1628
1629 #if 0
1630 // on-chip BEACON frame space - base address = 0x7800
1631 #define HW_BEACON_MAX_SIZE      0x0800 /* unit: byte */
1632 #define HW_BEACON_BASE0         0x7800
1633 #define HW_BEACON_BASE1         0x7900
1634 #define HW_BEACON_BASE2         0x7a00
1635 #define HW_BEACON_BASE3         0x7b00
1636 #define HW_BEACON_BASE4         0x7c00
1637 #define HW_BEACON_BASE5         0x7d00
1638 #define HW_BEACON_BASE6         0x7e00
1639 #define HW_BEACON_BASE7         0x7f00
1640 /* 1. HW_BEACON_OFFSET/64B must be 0;
1641    2. BCN_OFFSET0 must also be changed in NICInitializeAsic();
1642    3. max 0x0800 for 8 beacon frames; */
1643 #else
1644 // In order to support maximum 8 MBSS and its maximum length is 512 for each beacon
1645 // Three section discontinue memory segments will be used.
1646 // 1. The original region for BCN 0~3
1647 // 2. Extract memory from FCE table for BCN 4~5
1648 // 3. Extract memory from Pair-wise key table for BCN 6~7
1649 //        It occupied those memory of wcid 238~253 for BCN 6
1650 //                                                    and wcid 222~237 for BCN 7
1651 #define HW_BEACON_MAX_SIZE      0x1000 /* unit: byte */
1652 #define HW_BEACON_BASE0         0x7800
1653 #define HW_BEACON_BASE1         0x7A00
1654 #define HW_BEACON_BASE2         0x7C00
1655 #define HW_BEACON_BASE3         0x7E00
1656 #define HW_BEACON_BASE4         0x7200
1657 #define HW_BEACON_BASE5         0x7400
1658 #define HW_BEACON_BASE6         0x5DC0
1659 #define HW_BEACON_BASE7         0x5BC0
1660 #endif
1661
1662 #define HW_BEACON_MAX_COUNT     8
1663 #define HW_BEACON_OFFSET                0x0200
1664 #define HW_BEACON_CONTENT_LEN   (HW_BEACON_OFFSET - TXWI_SIZE)
1665
1666 // HOST-MCU shared memory - base address = 0x2100
1667 #define HOST_CMD_CSR            0x404
1668 #define H2M_MAILBOX_CSR         0x7010
1669 #define H2M_MAILBOX_CID         0x7014
1670 #define H2M_MAILBOX_STATUS      0x701c
1671 #define H2M_INT_SRC             0x7024
1672 #define H2M_BBP_AGENT           0x7028
1673 #define M2H_CMD_DONE_CSR        0x000c
1674 #define MCU_TXOP_ARRAY_BASE     0x000c   // TODO: to be provided by Albert
1675 #define MCU_TXOP_ENTRY_SIZE     32       // TODO: to be provided by Albert
1676 #define MAX_NUM_OF_TXOP_ENTRY   16       // TODO: must be same with 8051 firmware
1677 #define MCU_MBOX_VERSION        0x01     // TODO: to be confirmed by Albert
1678 #define MCU_MBOX_VERSION_OFFSET 5        // TODO: to be provided by Albert
1679
1680 //
1681 // Host DMA registers - base address 0x200 .  TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT,
1682 //
1683 //
1684 //  DMA RING DESCRIPTOR
1685 //
1686 #define E2PROM_CSR          0x0004
1687 #define IO_CNTL_CSR         0x77d0
1688
1689 #ifdef RT2870
1690 // 8051 firmware image for usb - use last-half base address = 0x3000
1691 #define FIRMWARE_IMAGE_BASE     0x3000
1692 #define MAX_FIRMWARE_IMAGE_SIZE 0x1000    // 4kbyte
1693 #endif // RT2870 //
1694
1695 // TODO: ????? old RT2560 registers. to keep them or remove them?
1696 //#define MCAST0                  0x0178  // multicast filter register 0
1697 //#define MCAST1                  0x017c  // multicast filter register 1
1698
1699
1700 // ================================================================
1701 // Tx / Rx / Mgmt ring descriptor definition
1702 // ================================================================
1703
1704 // the following PID values are used to mark outgoing frame type in TXD->PID so that
1705 // proper TX statistics can be collected based on these categories
1706 // b3-2 of PID field -
1707 #define PID_MGMT                        0x05
1708 #define PID_BEACON                      0x0c
1709 #define PID_DATA_NORMALUCAST            0x02
1710 #define PID_DATA_AMPDU          0x04
1711 #define PID_DATA_NO_ACK         0x08
1712 #define PID_DATA_NOT_NORM_ACK           0x03
1713 #if 0
1714 #define PTYPE_DATA_REQUIRE_ACK  0x00 // b7-6:00, b5-0: 0~59 is MAC table index (AID?), 60~63 is WDS index
1715 #define PTYPE_NULL_AT_HIGH_RATE 0x04 // b7-6:01, b5-0: 0~59 is MAC table index (AID?), 60~63 is WDS index
1716 #define PTYPE_RESERVED          0x08 // b7-6:10
1717 #define PTYPE_SPECIAL           0x0c // b7-6:11
1718
1719 // when b3-2=11 (PTYPE_SPECIAL), b1-0 coube be ...
1720 #define PSUBTYPE_DATA_NO_ACK    0x00
1721 #define PSUBTYPE_MGMT           0x01
1722 #define PSUBTYPE_OTHER_CNTL     0x02
1723 #define PSUBTYPE_RTS            0x03
1724 #endif
1725 // value domain of pTxD->HostQId (4-bit: 0~15)
1726 #define QID_AC_BK               1   // meet ACI definition in 802.11e
1727 #define QID_AC_BE               0   // meet ACI definition in 802.11e
1728 #define QID_AC_VI               2
1729 #define QID_AC_VO               3
1730 #define QID_HCCA                4
1731 #define NUM_OF_TX_RING          5
1732 #define QID_MGMT                13
1733 #define QID_RX                  14
1734 #define QID_OTHER               15
1735
1736
1737 // ------------------------------------------------------
1738 // BBP & RF     definition
1739 // ------------------------------------------------------
1740 #define BUSY                            1
1741 #define IDLE                            0
1742
1743 #define RF_R00                                      0
1744 #define RF_R01                                      1
1745 #define RF_R02                                      2
1746 #define RF_R03                                      3
1747 #define RF_R04                                      4
1748 #define RF_R05                                      5
1749 #define RF_R06                                      6
1750 #define RF_R07                                      7
1751 #define RF_R08                                      8
1752 #define RF_R09                                      9
1753 #define RF_R10                                      10
1754 #define RF_R11                                      11
1755 #define RF_R12                                      12
1756 #define RF_R13                                      13
1757 #define RF_R14                                      14
1758 #define RF_R15                                      15
1759 #define RF_R16                                      16
1760 #define RF_R17                                      17
1761 #define RF_R18                                      18
1762 #define RF_R19                                      19
1763 #define RF_R20                                      20
1764 #define RF_R21                                      21
1765 #define RF_R22                                      22
1766 #define RF_R23                                      23
1767 #define RF_R24                                      24
1768 #define RF_R25                                      25
1769 #define RF_R26                                      26
1770 #define RF_R27                                      27
1771 #define RF_R28                                      28
1772 #define RF_R29                                      29
1773 #define RF_R30                                      30
1774 #define RF_R31                                      31
1775
1776 #define BBP_R0                                      0  // version
1777 #define BBP_R1                                  1  // TSSI
1778 #define BBP_R2                                  2  // TX configure
1779 #define BBP_R3                      3
1780 #define BBP_R4                      4
1781 #define BBP_R5                      5
1782 #define BBP_R6                      6
1783 #define BBP_R14                             14 // RX configure
1784 #define BBP_R16                     16
1785 #define BBP_R17                     17 // RX sensibility
1786 #define BBP_R18                     18
1787 #define BBP_R21                     21
1788 #define BBP_R22                     22
1789 #define BBP_R24                     24
1790 #define BBP_R25                     25
1791 #define BBP_R49                     49 //TSSI
1792 #define BBP_R50                     50
1793 #define BBP_R51                     51
1794 #define BBP_R52                     52
1795 #define BBP_R55                     55
1796 #define BBP_R62                     62 // Rx SQ0 Threshold HIGH
1797 #define BBP_R63                     63
1798 #define BBP_R64                     64
1799 #define BBP_R65                     65
1800 #define BBP_R66                     66
1801 #define BBP_R67                     67
1802 #define BBP_R68                     68
1803 #define BBP_R69                     69
1804 #define BBP_R70                     70 // Rx AGC SQ CCK Xcorr threshold
1805 #define BBP_R73                     73
1806 #define BBP_R75                                         75
1807 #define BBP_R77                     77
1808 #define BBP_R81                     81
1809 #define BBP_R82                     82
1810 #define BBP_R83                     83
1811 #define BBP_R84                     84
1812 #define BBP_R86                                         86
1813 #define BBP_R91                                         91
1814 #define BBP_R92                                         92
1815 #define BBP_R94                     94 // Tx Gain Control
1816 #define BBP_R103                    103
1817 #define BBP_R105                    105
1818 #define BBP_R113                    113
1819 #define BBP_R114                    114
1820 #define BBP_R115                    115
1821 #define BBP_R116                    116
1822 #define BBP_R117                    117
1823 #define BBP_R118                    118
1824 #define BBP_R119                    119
1825 #define BBP_R120                    120
1826 #define BBP_R121                    121
1827 #define BBP_R122                    122
1828 #define BBP_R123                    123
1829
1830
1831 #define BBPR94_DEFAULT              0x06 // Add 1 value will gain 1db
1832
1833 //#define PHY_TR_SWITCH_TIME          5  // usec
1834
1835 //#define BBP_R17_LOW_SENSIBILITY     0x50
1836 //#define BBP_R17_MID_SENSIBILITY     0x41
1837 //#define BBP_R17_DYNAMIC_UP_BOUND    0x40
1838 #define RSSI_FOR_VERY_LOW_SENSIBILITY -35
1839 #define RSSI_FOR_LOW_SENSIBILITY      -58
1840 #define RSSI_FOR_MID_LOW_SENSIBILITY  -80
1841 #define RSSI_FOR_MID_SENSIBILITY      -90
1842
1843 //-------------------------------------------------------------------------
1844 // EEPROM definition
1845 //-------------------------------------------------------------------------
1846 #define EEDO                        0x08
1847 #define EEDI                        0x04
1848 #define EECS                        0x02
1849 #define EESK                        0x01
1850 #define EERL                        0x80
1851
1852 #define EEPROM_WRITE_OPCODE         0x05
1853 #define EEPROM_READ_OPCODE          0x06
1854 #define EEPROM_EWDS_OPCODE          0x10
1855 #define EEPROM_EWEN_OPCODE          0x13
1856
1857 #define NUM_EEPROM_BBP_PARMS            19                      // Include NIC Config 0, 1, CR, TX ALC step, BBPs
1858 #define NUM_EEPROM_TX_G_PARMS           7
1859 #define EEPROM_NIC1_OFFSET          0x34                // The address is from NIC config 0, not BBP register ID
1860 #define EEPROM_NIC2_OFFSET          0x36                // The address is from NIC config 0, not BBP register ID
1861 #define EEPROM_BBP_BASE_OFFSET          0xf0            // The address is from NIC config 0, not BBP register ID
1862 #define EEPROM_G_TX_PWR_OFFSET          0x52
1863 #define EEPROM_G_TX2_PWR_OFFSET         0x60
1864 #define EEPROM_LED1_OFFSET                      0x3c
1865 #define EEPROM_LED2_OFFSET                      0x3e
1866 #define EEPROM_LED3_OFFSET                      0x40
1867 #define EEPROM_LNA_OFFSET                       0x44
1868 #define EEPROM_RSSI_BG_OFFSET           0x46
1869 #define EEPROM_RSSI_A_OFFSET            0x4a
1870 #define EEPROM_DEFINE_MAX_TXPWR         0x4e
1871 #define EEPROM_TXPOWER_BYRATE_20MHZ_2_4G        0xde    // 20MHZ 2.4G tx power.
1872 #define EEPROM_TXPOWER_BYRATE_40MHZ_2_4G        0xee    // 40MHZ 2.4G tx power.
1873 #define EEPROM_TXPOWER_BYRATE_20MHZ_5G          0xfa    // 20MHZ 5G tx power.
1874 #define EEPROM_TXPOWER_BYRATE_40MHZ_5G          0x10a   // 40MHZ 5G tx power.
1875 #define EEPROM_A_TX_PWR_OFFSET      0x78
1876 #define EEPROM_A_TX2_PWR_OFFSET      0xa6
1877 //#define EEPROM_Japan_TX_PWR_OFFSET      0x90 // 802.11j
1878 //#define EEPROM_Japan_TX2_PWR_OFFSET      0xbe
1879 //#define EEPROM_TSSI_REF_OFFSET        0x54
1880 //#define EEPROM_TSSI_DELTA_OFFSET      0x24
1881 //#define EEPROM_CCK_TX_PWR_OFFSET  0x62
1882 //#define EEPROM_CALIBRATE_OFFSET       0x7c
1883 #define EEPROM_VERSION_OFFSET       0x02
1884 #define EEPROM_FREQ_OFFSET                      0x3a
1885 #define EEPROM_TXPOWER_BYRATE   0xde    // 20MHZ power.
1886 #define EEPROM_TXPOWER_DELTA            0x50    // 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ.
1887 #define VALID_EEPROM_VERSION        1
1888
1889 // PairKeyMode definition
1890 #define PKMODE_NONE                 0
1891 #define PKMODE_WEP64                1
1892 #define PKMODE_WEP128               2
1893 #define PKMODE_TKIP                 3
1894 #define PKMODE_AES                  4
1895 #define PKMODE_CKIP64               5
1896 #define PKMODE_CKIP128              6
1897 #define PKMODE_TKIP_NO_MIC          7       // MIC appended by driver: not a valid value in hardware key table
1898
1899 // =================================================================================
1900 // WCID  format
1901 // =================================================================================
1902 //7.1   WCID  ENTRY  format  : 8bytes
1903 typedef struct  _WCID_ENTRY_STRUC {
1904         UCHAR           RXBABitmap7;    // bit0 for TID8, bit7 for TID 15
1905         UCHAR           RXBABitmap0;    // bit0 for TID0, bit7 for TID 7
1906         UCHAR           MAC[6]; // 0 for shared key table.  1 for pairwise key table
1907 }       WCID_ENTRY_STRUC, *PWCID_ENTRY_STRUC;
1908
1909 //8.1.1 SECURITY  KEY  format  : 8DW
1910 // 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table
1911 typedef struct _HW_KEY_ENTRY {          // 32-byte per entry
1912     UCHAR   Key[16];
1913     UCHAR   TxMic[8];
1914     UCHAR   RxMic[8];
1915 } HW_KEY_ENTRY, *PHW_KEY_ENTRY;
1916
1917 //8.1.2 IV/EIV  format  : 2DW
1918
1919 //8.1.3 RX attribute entry format  : 1DW
1920 #ifdef RT_BIG_ENDIAN
1921 typedef struct  _MAC_ATTRIBUTE_STRUC {
1922         UINT32          rsv:22;
1923         UINT32          RXWIUDF:3;
1924         UINT32          BSSIDIdx:3; //multipleBSS index for the WCID
1925         UINT32          PairKeyMode:3;
1926         UINT32          KeyTab:1;       // 0 for shared key table.  1 for pairwise key table
1927 }       MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
1928 #else
1929 typedef struct  _MAC_ATTRIBUTE_STRUC {
1930         UINT32          KeyTab:1;       // 0 for shared key table.  1 for pairwise key table
1931         UINT32          PairKeyMode:3;
1932         UINT32          BSSIDIdx:3; //multipleBSS index for the WCID
1933         UINT32          RXWIUDF:3;
1934         UINT32          rsv:22;
1935 }       MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
1936 #endif
1937
1938
1939 // =================================================================================
1940 // TX / RX ring descriptor format
1941 // =================================================================================
1942
1943 // the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO.
1944 // MAC block use this TXINFO to control the transmission behavior of this frame.
1945 #define FIFO_MGMT                 0
1946 #define FIFO_HCCA                 1
1947 #define FIFO_EDCA                 2
1948
1949 //
1950 // TX descriptor format, Tx     ring, Mgmt Ring
1951 //
1952 #ifdef RT_BIG_ENDIAN
1953 typedef struct  PACKED _TXD_STRUC {
1954         // Word 0
1955         UINT32          SDPtr0;
1956         // Word 1
1957         UINT32          DMADONE:1;
1958         UINT32          LastSec0:1;
1959         UINT32          SDLen0:14;
1960         UINT32          Burst:1;
1961         UINT32          LastSec1:1;
1962         UINT32          SDLen1:14;
1963         // Word 2
1964         UINT32          SDPtr1;
1965         // Word 3
1966         UINT32          ICO:1;
1967         UINT32          UCO:1;
1968         UINT32          TCO:1;
1969         UINT32          rsv:2;
1970         UINT32          QSEL:2; // select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
1971         UINT32          WIV:1;  // Wireless Info Valid. 1 if Driver already fill WI,  o if DMA needs to copy WI to correctposition
1972         UINT32          rsv2:24;
1973 }       TXD_STRUC, *PTXD_STRUC;
1974 #else
1975 typedef struct  PACKED _TXD_STRUC {
1976         // Word 0
1977         UINT32          SDPtr0;
1978         // Word 1
1979         UINT32          SDLen1:14;
1980         UINT32          LastSec1:1;
1981         UINT32          Burst:1;
1982         UINT32          SDLen0:14;
1983         UINT32          LastSec0:1;
1984         UINT32          DMADONE:1;
1985         //Word2
1986         UINT32          SDPtr1;
1987         //Word3
1988         UINT32          rsv2:24;
1989         UINT32          WIV:1;  // Wireless Info Valid. 1 if Driver already fill WI,  o if DMA needs to copy WI to correctposition
1990         UINT32          QSEL:2; // select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
1991         UINT32          rsv:2;
1992         UINT32          TCO:1;  //
1993         UINT32          UCO:1;  //
1994         UINT32          ICO:1;  //
1995 }       TXD_STRUC, *PTXD_STRUC;
1996 #endif
1997
1998
1999 //
2000 // TXD Wireless Information format for Tx ring and Mgmt Ring
2001 //
2002 //txop : for txop mode
2003 // 0:txop for the MPDU frame will be handles by ASIC by register
2004 // 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS
2005 #ifdef RT_BIG_ENDIAN
2006 typedef struct  PACKED _TXWI_STRUC {
2007         // Word 0
2008         UINT32          PHYMODE:2;
2009         UINT32          TxBF:1; // 3*3
2010         UINT32          rsv2:1;
2011 //      UINT32          rsv2:2;
2012         UINT32          Ifs:1;  //
2013         UINT32          STBC:2; //channel bandwidth 20MHz or 40 MHz
2014         UINT32          ShortGI:1;
2015         UINT32          BW:1;   //channel bandwidth 20MHz or 40 MHz
2016         UINT32          MCS:7;
2017
2018         UINT32          rsv:6;
2019         UINT32          txop:2; //tx back off mode 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
2020         UINT32          MpduDensity:3;
2021         UINT32          AMPDU:1;
2022
2023         UINT32          TS:1;
2024         UINT32          CFACK:1;
2025         UINT32          MIMOps:1;       // the remote peer is in dynamic MIMO-PS mode
2026         UINT32          FRAG:1;         // 1 to inform TKIP engine this is a fragment.
2027         // Word 1
2028         UINT32          PacketId:4;
2029         UINT32          MPDUtotalByteCount:12;
2030         UINT32          WirelessCliID:8;
2031         UINT32          BAWinSize:6;
2032         UINT32          NSEQ:1;
2033         UINT32          ACK:1;
2034         // Word 2
2035         UINT32          IV;
2036         // Word 3
2037         UINT32          EIV;
2038 }       TXWI_STRUC, *PTXWI_STRUC;
2039 #else
2040 typedef struct  PACKED _TXWI_STRUC {
2041         // Word 0
2042         UINT32          FRAG:1;         // 1 to inform TKIP engine this is a fragment.
2043         UINT32          MIMOps:1;       // the remote peer is in dynamic MIMO-PS mode
2044         UINT32          CFACK:1;
2045         UINT32          TS:1;
2046
2047         UINT32          AMPDU:1;
2048         UINT32          MpduDensity:3;
2049         UINT32          txop:2; //FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
2050         UINT32          rsv:6;
2051
2052         UINT32          MCS:7;
2053         UINT32          BW:1;   //channel bandwidth 20MHz or 40 MHz
2054         UINT32          ShortGI:1;
2055         UINT32          STBC:2; // 1: STBC support MCS =0-7,   2,3 : RESERVE
2056         UINT32          Ifs:1;  //
2057 //      UINT32          rsv2:2; //channel bandwidth 20MHz or 40 MHz
2058         UINT32          rsv2:1;
2059         UINT32          TxBF:1; // 3*3
2060         UINT32          PHYMODE:2;
2061         // Word 1
2062         UINT32          ACK:1;
2063         UINT32          NSEQ:1;
2064         UINT32          BAWinSize:6;
2065         UINT32          WirelessCliID:8;
2066         UINT32          MPDUtotalByteCount:12;
2067         UINT32          PacketId:4;
2068         //Word2
2069         UINT32          IV;
2070         //Word3
2071         UINT32          EIV;
2072 }       TXWI_STRUC, *PTXWI_STRUC;
2073 #endif
2074 //
2075 // Rx descriptor format, Rx     Ring
2076 //
2077 //
2078 // RXWI wireless information format, in PBF. invisible in driver.
2079 //
2080 #ifdef RT_BIG_ENDIAN
2081 typedef struct  PACKED _RXWI_STRUC {
2082         // Word 0
2083         UINT32          TID:4;
2084         UINT32          MPDUtotalByteCount:12;
2085         UINT32          UDF:3;
2086         UINT32          BSSID:3;
2087         UINT32          KeyIndex:2;
2088         UINT32          WirelessCliID:8;
2089         // Word 1
2090         UINT32          PHYMODE:2;              // 1: this RX frame is unicast to me
2091         UINT32          rsv:3;
2092         UINT32          STBC:2;
2093         UINT32          ShortGI:1;
2094         UINT32          BW:1;
2095         UINT32          MCS:7;
2096         UINT32          SEQUENCE:12;
2097         UINT32          FRAG:4;
2098         // Word 2
2099         UINT32          rsv1:8;
2100         UINT32          RSSI2:8;
2101         UINT32          RSSI1:8;
2102         UINT32          RSSI0:8;
2103         // Word 3
2104         UINT32          rsv2:16;
2105         UINT32          SNR1:8;
2106         UINT32          SNR0:8;
2107 }       RXWI_STRUC, *PRXWI_STRUC;
2108 #else
2109 typedef struct  PACKED _RXWI_STRUC {
2110         // Word 0
2111         UINT32          WirelessCliID:8;
2112         UINT32          KeyIndex:2;
2113         UINT32          BSSID:3;
2114         UINT32          UDF:3;
2115         UINT32          MPDUtotalByteCount:12;
2116         UINT32          TID:4;
2117         // Word 1
2118         UINT32          FRAG:4;
2119         UINT32          SEQUENCE:12;
2120         UINT32          MCS:7;
2121         UINT32          BW:1;
2122         UINT32          ShortGI:1;
2123         UINT32          STBC:2;
2124         UINT32          rsv:3;
2125         UINT32          PHYMODE:2;              // 1: this RX frame is unicast to me
2126         //Word2
2127         UINT32          RSSI0:8;
2128         UINT32          RSSI1:8;
2129         UINT32          RSSI2:8;
2130         UINT32          rsv1:8;
2131         //Word3
2132         UINT32          SNR0:8;
2133         UINT32          SNR1:8;
2134         UINT32          rsv2:16;
2135 }       RXWI_STRUC, *PRXWI_STRUC;
2136 #endif
2137
2138
2139 // =================================================================================
2140 // HOST-MCU communication data structure
2141 // =================================================================================
2142
2143 //
2144 // H2M_MAILBOX_CSR: Host-to-MCU Mailbox
2145 //
2146 #ifdef RT_BIG_ENDIAN
2147 typedef union  _H2M_MAILBOX_STRUC {
2148     struct {
2149         UINT32       Owner:8;
2150         UINT32       CmdToken:8;    // 0xff tells MCU not to report CmdDoneInt after excuting the command
2151         UINT32       HighByte:8;
2152         UINT32       LowByte:8;
2153     }   field;
2154     UINT32           word;
2155 } H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
2156 #else
2157 typedef union  _H2M_MAILBOX_STRUC {
2158     struct {
2159         UINT32       LowByte:8;
2160         UINT32       HighByte:8;
2161         UINT32       CmdToken:8;
2162         UINT32       Owner:8;
2163     }   field;
2164     UINT32           word;
2165 } H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
2166 #endif
2167
2168 //
2169 // M2H_CMD_DONE_CSR: MCU-to-Host command complete indication
2170 //
2171 #ifdef RT_BIG_ENDIAN
2172 typedef union _M2H_CMD_DONE_STRUC {
2173     struct  {
2174         UINT32       CmdToken3;
2175         UINT32       CmdToken2;
2176         UINT32       CmdToken1;
2177         UINT32       CmdToken0;
2178     } field;
2179     UINT32           word;
2180 } M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
2181 #else
2182 typedef union _M2H_CMD_DONE_STRUC {
2183     struct  {
2184         UINT32       CmdToken0;
2185         UINT32       CmdToken1;
2186         UINT32       CmdToken2;
2187         UINT32       CmdToken3;
2188     } field;
2189     UINT32           word;
2190 } M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
2191 #endif
2192
2193
2194
2195 //
2196 // MCU_LEDCS: MCU LED Control Setting.
2197 //
2198 #ifdef RT_BIG_ENDIAN
2199 typedef union  _MCU_LEDCS_STRUC {
2200         struct  {
2201                 UCHAR           Polarity:1;
2202                 UCHAR           LedMode:7;
2203         } field;
2204         UCHAR                           word;
2205 } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
2206 #else
2207 typedef union  _MCU_LEDCS_STRUC {
2208         struct  {
2209                 UCHAR           LedMode:7;
2210                 UCHAR           Polarity:1;
2211         } field;
2212         UCHAR                   word;
2213 } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
2214 #endif
2215 // =================================================================================
2216 // Register format
2217 // =================================================================================
2218
2219
2220
2221 //NAV_TIME_CFG :NAV
2222 #ifdef RT_BIG_ENDIAN
2223 typedef union   _NAV_TIME_CFG_STRUC     {
2224         struct  {
2225                 USHORT          rsv:6;
2226                 USHORT          ZeroSifs:1;               // Applied zero SIFS timer after OFDM RX 0: disable
2227                 USHORT          Eifs:9;               // in unit of 1-us
2228                 UCHAR       SlotTime;    // in unit of 1-us
2229                 UCHAR           Sifs;               // in unit of 1-us
2230         }       field;
2231         UINT32                  word;
2232 }       NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
2233 #else
2234 typedef union   _NAV_TIME_CFG_STRUC     {
2235         struct  {
2236                 UCHAR           Sifs;               // in unit of 1-us
2237                 UCHAR       SlotTime;    // in unit of 1-us
2238                 USHORT          Eifs:9;               // in unit of 1-us
2239                 USHORT          ZeroSifs:1;               // Applied zero SIFS timer after OFDM RX 0: disable
2240                 USHORT          rsv:6;
2241         }       field;
2242         UINT32                  word;
2243 }       NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
2244 #endif
2245
2246
2247
2248
2249
2250 //
2251 // RX_FILTR_CFG:  /RX configuration register
2252 //
2253 #ifdef RT_BIG_ENDIAN
2254 typedef union   RX_FILTR_CFG_STRUC      {
2255         struct  {
2256                 UINT32          :15;
2257                 UINT32       DropRsvCntlType:1;
2258
2259                 UINT32          DropBAR:1;       //
2260                 UINT32          DropBA:1;               //
2261                 UINT32          DropPsPoll:1;           // Drop Ps-Poll
2262                 UINT32          DropRts:1;              // Drop Ps-Poll
2263
2264                 UINT32          DropCts:1;              // Drop Ps-Poll
2265                 UINT32          DropAck:1;              // Drop Ps-Poll
2266                 UINT32          DropCFEnd:1;            // Drop Ps-Poll
2267                 UINT32          DropCFEndAck:1;         // Drop Ps-Poll
2268
2269                 UINT32          DropDuplicate:1;                // Drop duplicate frame
2270                 UINT32          DropBcast:1;            // Drop broadcast frames
2271                 UINT32          DropMcast:1;            // Drop multicast frames
2272                 UINT32          DropVerErr:1;       // Drop version error frame
2273
2274                 UINT32          DropNotMyBSSID:1;                       // Drop fram ToDs bit is true
2275                 UINT32          DropNotToMe:1;          // Drop not to me unicast frame
2276                 UINT32          DropPhyErr:1;           // Drop physical error
2277                 UINT32          DropCRCErr:1;           // Drop CRC error
2278         }       field;
2279         UINT32                  word;
2280 }       RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
2281 #else
2282 typedef union   _RX_FILTR_CFG_STRUC     {
2283         struct  {
2284                 UINT32          DropCRCErr:1;           // Drop CRC error
2285                 UINT32          DropPhyErr:1;           // Drop physical error
2286                 UINT32          DropNotToMe:1;          // Drop not to me unicast frame
2287                 UINT32          DropNotMyBSSID:1;                       // Drop fram ToDs bit is true
2288
2289                 UINT32          DropVerErr:1;       // Drop version error frame
2290                 UINT32          DropMcast:1;            // Drop multicast frames
2291                 UINT32          DropBcast:1;            // Drop broadcast frames
2292                 UINT32          DropDuplicate:1;                // Drop duplicate frame
2293
2294                 UINT32          DropCFEndAck:1;         // Drop Ps-Poll
2295                 UINT32          DropCFEnd:1;            // Drop Ps-Poll
2296                 UINT32          DropAck:1;              // Drop Ps-Poll
2297                 UINT32          DropCts:1;              // Drop Ps-Poll
2298
2299                 UINT32          DropRts:1;              // Drop Ps-Poll
2300                 UINT32          DropPsPoll:1;           // Drop Ps-Poll
2301                 UINT32          DropBA:1;               //
2302                 UINT32          DropBAR:1;       //
2303
2304                 UINT32          DropRsvCntlType:1;
2305                 UINT32          :15;
2306         }       field;
2307         UINT32                  word;
2308 }       RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
2309 #endif
2310
2311
2312
2313
2314 //
2315 // PHY_CSR4: RF serial control register
2316 //
2317 #ifdef RT_BIG_ENDIAN
2318 typedef union   _PHY_CSR4_STRUC {
2319         struct  {
2320                 UINT32          Busy:1;                         // 1: ASIC is busy execute RF programming.
2321                 UINT32          PLL_LD:1;                       // RF PLL_LD status
2322                 UINT32          IFSelect:1;                     // 1: select IF to program,     0: select RF to program
2323                 UINT32          NumberOfBits:5;         // Number of bits used in RFRegValue (I:20,     RFMD:22)
2324                 UINT32          RFRegValue:24;          // Register     value (include register id)     serial out to RF/IF     chip.
2325         }       field;
2326         UINT32                  word;
2327 }       PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
2328 #else
2329 typedef union   _PHY_CSR4_STRUC {
2330         struct  {
2331                 UINT32          RFRegValue:24;          // Register     value (include register id)     serial out to RF/IF     chip.
2332                 UINT32          NumberOfBits:5;         // Number of bits used in RFRegValue (I:20,     RFMD:22)
2333                 UINT32          IFSelect:1;                     // 1: select IF to program,     0: select RF to program
2334                 UINT32          PLL_LD:1;                       // RF PLL_LD status
2335                 UINT32          Busy:1;                         // 1: ASIC is busy execute RF programming.
2336         }       field;
2337         UINT32                  word;
2338 }       PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
2339 #endif
2340
2341
2342 //
2343 // SEC_CSR5: shared key table security mode register
2344 //
2345 #ifdef RT_BIG_ENDIAN
2346 typedef union   _SEC_CSR5_STRUC {
2347         struct  {
2348         UINT32       :1;
2349         UINT32       Bss3Key3CipherAlg:3;
2350         UINT32       :1;
2351         UINT32       Bss3Key2CipherAlg:3;
2352         UINT32       :1;
2353         UINT32       Bss3Key1CipherAlg:3;
2354         UINT32       :1;
2355         UINT32       Bss3Key0CipherAlg:3;
2356         UINT32       :1;
2357         UINT32       Bss2Key3CipherAlg:3;
2358         UINT32       :1;
2359         UINT32       Bss2Key2CipherAlg:3;
2360         UINT32       :1;
2361         UINT32       Bss2Key1CipherAlg:3;
2362         UINT32       :1;
2363         UINT32       Bss2Key0CipherAlg:3;
2364         }       field;
2365         UINT32                  word;
2366 }       SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
2367 #else
2368 typedef union   _SEC_CSR5_STRUC {
2369         struct  {
2370         UINT32       Bss2Key0CipherAlg:3;
2371         UINT32       :1;
2372         UINT32       Bss2Key1CipherAlg:3;
2373         UINT32       :1;
2374         UINT32       Bss2Key2CipherAlg:3;
2375         UINT32       :1;
2376         UINT32       Bss2Key3CipherAlg:3;
2377         UINT32       :1;
2378         UINT32       Bss3Key0CipherAlg:3;
2379         UINT32       :1;
2380         UINT32       Bss3Key1CipherAlg:3;
2381         UINT32       :1;
2382         UINT32       Bss3Key2CipherAlg:3;
2383         UINT32       :1;
2384         UINT32       Bss3Key3CipherAlg:3;
2385         UINT32       :1;
2386         }       field;
2387         UINT32                  word;
2388 }       SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
2389 #endif
2390
2391
2392 //
2393 // HOST_CMD_CSR: For HOST to interrupt embedded processor
2394 //
2395 #ifdef RT_BIG_ENDIAN
2396 typedef union   _HOST_CMD_CSR_STRUC     {
2397         struct  {
2398             UINT32   Rsv:24;
2399             UINT32   HostCommand:8;
2400         }       field;
2401         UINT32                  word;
2402 }       HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
2403 #else
2404 typedef union   _HOST_CMD_CSR_STRUC     {
2405         struct  {
2406             UINT32   HostCommand:8;
2407             UINT32   Rsv:24;
2408         }       field;
2409         UINT32                  word;
2410 }       HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
2411 #endif
2412
2413
2414 //
2415 // AIFSN_CSR: AIFSN for each EDCA AC
2416 //
2417
2418
2419
2420 //
2421 // E2PROM_CSR: EEPROM control register
2422 //
2423 #ifdef RT_BIG_ENDIAN
2424 typedef union   _E2PROM_CSR_STRUC       {
2425         struct  {
2426                 UINT32          Rsvd:25;
2427                 UINT32       LoadStatus:1;   // 1:loading, 0:done
2428                 UINT32          Type:1;                 // 1: 93C46, 0:93C66
2429                 UINT32          EepromDO:1;
2430                 UINT32          EepromDI:1;
2431                 UINT32          EepromCS:1;
2432                 UINT32          EepromSK:1;
2433                 UINT32          Reload:1;               // Reload EEPROM content, write one to reload, self-cleared.
2434         }       field;
2435         UINT32                  word;
2436 }       E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
2437 #else
2438 typedef union   _E2PROM_CSR_STRUC       {
2439         struct  {
2440                 UINT32          Reload:1;               // Reload EEPROM content, write one to reload, self-cleared.
2441                 UINT32          EepromSK:1;
2442                 UINT32          EepromCS:1;
2443                 UINT32          EepromDI:1;
2444                 UINT32          EepromDO:1;
2445                 UINT32          Type:1;                 // 1: 93C46, 0:93C66
2446                 UINT32       LoadStatus:1;   // 1:loading, 0:done
2447                 UINT32          Rsvd:25;
2448         }       field;
2449         UINT32                  word;
2450 }       E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
2451 #endif
2452
2453
2454 // -------------------------------------------------------------------
2455 //  E2PROM data layout
2456 // -------------------------------------------------------------------
2457
2458 //
2459 // EEPROM antenna select format
2460 //
2461 #ifdef RT_BIG_ENDIAN
2462 typedef union   _EEPROM_ANTENNA_STRUC   {
2463         struct  {
2464                 USHORT      Rsv:4;
2465                 USHORT      RfIcType:4;             // see E2PROM document
2466                 USHORT          TxPath:4;       // 1: 1T, 2: 2T
2467                 USHORT          RxPath:4;       // 1: 1R, 2: 2R, 3: 3R
2468         }       field;
2469         USHORT                  word;
2470 }       EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
2471 #else
2472 typedef union   _EEPROM_ANTENNA_STRUC   {
2473         struct  {
2474                 USHORT          RxPath:4;       // 1: 1R, 2: 2R, 3: 3R
2475                 USHORT          TxPath:4;       // 1: 1T, 2: 2T
2476                 USHORT      RfIcType:4;             // see E2PROM document
2477                 USHORT      Rsv:4;
2478         }       field;
2479         USHORT                  word;
2480 }       EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
2481 #endif
2482
2483 #ifdef RT_BIG_ENDIAN
2484 typedef union _EEPROM_NIC_CINFIG2_STRUC {
2485         struct  {
2486         USHORT          Rsv2:6;                                 // must be 0
2487                 USHORT          BW40MAvailForA:1;                       // 0:enable, 1:disable
2488                 USHORT          BW40MAvailForG:1;                       // 0:enable, 1:disable
2489                 USHORT          EnableWPSPBC:1;                 // WPS PBC Control bit
2490                 USHORT          BW40MSidebandForA:1;
2491                 USHORT          BW40MSidebandForG:1;
2492                 USHORT          CardbusAcceleration:1;  // !!! NOTE: 0 - enable, 1 - disable
2493                 USHORT          ExternalLNAForA:1;                      // external LNA enable for 5G
2494                 USHORT          ExternalLNAForG:1;                      // external LNA enable for 2.4G
2495                 USHORT          DynamicTxAgcControl:1;                  //
2496                 USHORT          HardwareRadioControl:1; // Whether RF is controlled by driver or HW. 1:enable hw control, 0:disable
2497         }       field;
2498         USHORT                  word;
2499 }       EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
2500 #else
2501 typedef union _EEPROM_NIC_CINFIG2_STRUC {
2502         struct {
2503                 USHORT          HardwareRadioControl:1; // 1:enable, 0:disable
2504                 USHORT          DynamicTxAgcControl:1;                  //
2505                 USHORT          ExternalLNAForG:1;                              //
2506                 USHORT          ExternalLNAForA:1;                      // external LNA enable for 2.4G
2507                 USHORT          CardbusAcceleration:1;  // !!! NOTE: 0 - enable, 1 - disable
2508                 USHORT          BW40MSidebandForG:1;
2509                 USHORT          BW40MSidebandForA:1;
2510                 USHORT          EnableWPSPBC:1;                 // WPS PBC Control bit
2511                 USHORT          BW40MAvailForG:1;                       // 0:enable, 1:disable
2512                 USHORT          BW40MAvailForA:1;                       // 0:enable, 1:disable
2513                 USHORT          Rsv2:6;                 // must be 0
2514         }       field;
2515         USHORT                  word;
2516 }       EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
2517 #endif
2518
2519 //
2520 // TX_PWR Value valid range 0xFA(-6) ~ 0x24(36)
2521 //
2522 #ifdef RT_BIG_ENDIAN
2523 typedef union   _EEPROM_TX_PWR_STRUC    {
2524         struct  {
2525                 CHAR    Byte1;                          // High Byte
2526                 CHAR    Byte0;                          // Low Byte
2527         }       field;
2528         USHORT  word;
2529 }       EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
2530 #else
2531 typedef union   _EEPROM_TX_PWR_STRUC    {
2532         struct  {
2533                 CHAR    Byte0;                          // Low Byte
2534                 CHAR    Byte1;                          // High Byte
2535         }       field;
2536         USHORT  word;
2537 }       EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
2538 #endif
2539
2540 #ifdef RT_BIG_ENDIAN
2541 typedef union   _EEPROM_VERSION_STRUC   {
2542         struct  {
2543                 UCHAR   Version;                        // High Byte
2544                 UCHAR   FaeReleaseNumber;       // Low Byte
2545         }       field;
2546         USHORT  word;
2547 }       EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
2548 #else
2549 typedef union   _EEPROM_VERSION_STRUC   {
2550         struct  {
2551                 UCHAR   FaeReleaseNumber;       // Low Byte
2552                 UCHAR   Version;                        // High Byte
2553         }       field;
2554         USHORT  word;
2555 }       EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
2556 #endif
2557
2558 #ifdef RT_BIG_ENDIAN
2559 typedef union   _EEPROM_LED_STRUC       {
2560         struct  {
2561                 USHORT  Rsvd:3;                         // Reserved
2562                 USHORT  LedMode:5;                      // Led mode.
2563                 USHORT  PolarityGPIO_4:1;       // Polarity GPIO#4 setting.
2564                 USHORT  PolarityGPIO_3:1;       // Polarity GPIO#3 setting.
2565                 USHORT  PolarityGPIO_2:1;       // Polarity GPIO#2 setting.
2566                 USHORT  PolarityGPIO_1:1;       // Polarity GPIO#1 setting.
2567                 USHORT  PolarityGPIO_0:1;       // Polarity GPIO#0 setting.
2568                 USHORT  PolarityACT:1;          // Polarity ACT setting.
2569                 USHORT  PolarityRDY_A:1;                // Polarity RDY_A setting.
2570                 USHORT  PolarityRDY_G:1;                // Polarity RDY_G setting.
2571         }       field;
2572         USHORT  word;
2573 }       EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
2574 #else
2575 typedef union   _EEPROM_LED_STRUC       {
2576         struct  {
2577                 USHORT  PolarityRDY_G:1;                // Polarity RDY_G setting.
2578                 USHORT  PolarityRDY_A:1;                // Polarity RDY_A setting.
2579                 USHORT  PolarityACT:1;          // Polarity ACT setting.
2580                 USHORT  PolarityGPIO_0:1;       // Polarity GPIO#0 setting.
2581                 USHORT  PolarityGPIO_1:1;       // Polarity GPIO#1 setting.
2582                 USHORT  PolarityGPIO_2:1;       // Polarity GPIO#2 setting.
2583                 USHORT  PolarityGPIO_3:1;       // Polarity GPIO#3 setting.
2584                 USHORT  PolarityGPIO_4:1;       // Polarity GPIO#4 setting.
2585                 USHORT  LedMode:5;                      // Led mode.
2586                 USHORT  Rsvd:3;                         // Reserved
2587         }       field;
2588         USHORT  word;
2589 }       EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
2590 #endif
2591
2592 #ifdef RT_BIG_ENDIAN
2593 typedef union   _EEPROM_TXPOWER_DELTA_STRUC     {
2594         struct  {
2595                 UCHAR   TxPowerEnable:1;// Enable
2596                 UCHAR   Type:1;                 // 1: plus the delta value, 0: minus the delta value
2597                 UCHAR   DeltaValue:6;   // Tx Power dalta value (MAX=4)
2598         }       field;
2599         UCHAR   value;
2600 }       EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
2601 #else
2602 typedef union   _EEPROM_TXPOWER_DELTA_STRUC     {
2603         struct  {
2604                 UCHAR   DeltaValue:6;   // Tx Power dalta value (MAX=4)
2605                 UCHAR   Type:1;                 // 1: plus the delta value, 0: minus the delta value
2606                 UCHAR   TxPowerEnable:1;// Enable
2607         }       field;
2608         UCHAR   value;
2609 }       EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
2610 #endif
2611
2612 //
2613 // QOS_CSR0: TXOP holder address0 register
2614 //
2615 #ifdef RT_BIG_ENDIAN
2616 typedef union   _QOS_CSR0_STRUC {
2617         struct  {
2618                 UCHAR           Byte3;          // MAC address byte 3
2619                 UCHAR           Byte2;          // MAC address byte 2
2620                 UCHAR           Byte1;          // MAC address byte 1
2621                 UCHAR           Byte0;          // MAC address byte 0
2622         }       field;
2623         UINT32                  word;
2624 }       QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
2625 #else
2626 typedef union   _QOS_CSR0_STRUC {
2627         struct  {
2628                 UCHAR           Byte0;          // MAC address byte 0
2629                 UCHAR           Byte1;          // MAC address byte 1
2630                 UCHAR           Byte2;          // MAC address byte 2
2631                 UCHAR           Byte3;          // MAC address byte 3
2632         }       field;
2633         UINT32                  word;
2634 }       QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
2635 #endif
2636
2637 //
2638 // QOS_CSR1: TXOP holder address1 register
2639 //
2640 #ifdef RT_BIG_ENDIAN
2641 typedef union   _QOS_CSR1_STRUC {
2642         struct  {
2643                 UCHAR           Rsvd1;
2644                 UCHAR           Rsvd0;
2645                 UCHAR           Byte5;          // MAC address byte 5
2646                 UCHAR           Byte4;          // MAC address byte 4
2647         }       field;
2648         UINT32                  word;
2649 }       QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
2650 #else
2651 typedef union   _QOS_CSR1_STRUC {
2652         struct  {
2653                 UCHAR           Byte4;          // MAC address byte 4
2654                 UCHAR           Byte5;          // MAC address byte 5
2655                 UCHAR           Rsvd0;
2656                 UCHAR           Rsvd1;
2657         }       field;
2658         UINT32                  word;
2659 }       QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
2660 #endif
2661
2662 #define RF_CSR_CFG      0x500
2663 #ifdef RT_BIG_ENDIAN
2664 typedef union   _RF_CSR_CFG_STRUC       {
2665         struct  {
2666                 UINT    Rsvd1:14;                               // Reserved
2667                 UINT    RF_CSR_KICK:1;                  // kick RF register read/write
2668                 UINT    RF_CSR_WR:1;                    // 0: read  1: write
2669                 UINT    Rsvd2:3;                                // Reserved
2670                 UINT    TESTCSR_RFACC_REGNUM:5; // RF register ID
2671                 UINT    RF_CSR_DATA:8;                  // DATA
2672         }       field;
2673         UINT    word;
2674 }       RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
2675 #else
2676 typedef union   _RF_CSR_CFG_STRUC       {
2677         struct  {
2678                 UINT    RF_CSR_DATA:8;                  // DATA
2679                 UINT    TESTCSR_RFACC_REGNUM:5; // RF register ID
2680                 UINT    Rsvd2:3;                                // Reserved
2681                 UINT    RF_CSR_WR:1;                    // 0: read  1: write
2682                 UINT    RF_CSR_KICK:1;                  // kick RF register read/write
2683                 UINT    Rsvd1:14;                               // Reserved
2684         }       field;
2685         UINT    word;
2686 }       RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
2687 #endif
2688
2689 #endif  // __RT28XX_H__