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   1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
   2  *
   3  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
   4  * Copyright (C) 2002, 2006  David S. Miller (davem@davemloft.net)
   5  *
   6  * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
   7  *   Maxim Krasnyanskiy <maxk@qualcomm.com>
   8  *
   9  * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
  10  * rates to be programmed into the UART.  Also eliminated a lot of
  11  * duplicated code in the console setup.
  12  *   Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
  13  *
  14  * Ported to new 2.5.x UART layer.
  15  *   David S. Miller <davem@davemloft.net>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/major.h>
  24 #include <linux/string.h>
  25 #include <linux/ptrace.h>
  26 #include <linux/ioport.h>
  27 #include <linux/circ_buf.h>
  28 #include <linux/serial.h>
  29 #include <linux/sysrq.h>
  30 #include <linux/console.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/slab.h>
  33 #include <linux/delay.h>
  34 #include <linux/init.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/irq.h>
  38 #include <asm/prom.h>
  39 #include <asm/of_device.h>
  40
  41 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  42 #define SUPPORT_SYSRQ
  43 #endif
  44
  45 #include <linux/serial_core.h>
  46
  47 #include "suncore.h"
  48 #include "sunsab.h"
  49
  50 struct uart_sunsab_port {
  51         struct uart_port                port;           /* Generic UART port    */
  52         union sab82532_async_regs       __iomem *regs;  /* Chip registers       */
  53         unsigned long                   irqflags;       /* IRQ state flags      */
  54         int                             dsr;            /* Current DSR state    */
  55         unsigned int                    cec_timeout;    /* Chip poll timeout... */
  56         unsigned int                    tec_timeout;    /* likewise             */
  57         unsigned char                   interrupt_mask0;/* ISR0 masking         */
  58         unsigned char                   interrupt_mask1;/* ISR1 masking         */
  59         unsigned char                   pvr_dtr_bit;    /* Which PVR bit is DTR */
  60         unsigned char                   pvr_dsr_bit;    /* Which PVR bit is DSR */
  61         int                             type;           /* SAB82532 version     */
  62
  63         /* Setting configuration bits while the transmitter is active
  64          * can cause garbage characters to get emitted by the chip.
  65          * Therefore, we cache such writes here and do the real register
  66          * write the next time the transmitter becomes idle.
  67          */
  68         unsigned int                    cached_ebrg;
  69         unsigned char                   cached_mode;
  70         unsigned char                   cached_pvr;
  71         unsigned char                   cached_dafo;
  72 };
  73
  74 /*
  75  * This assumes you have a 29.4912 MHz clock for your UART.
  76  */
  77 #define SAB_BASE_BAUD ( 29491200 / 16 )
  78
  79 static char *sab82532_version[16] = {
  80         "V1.0", "V2.0", "V3.2", "V(0x03)",
  81         "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
  82         "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
  83         "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
  84 };
  85
  86 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
  87 #define SAB82532_MAX_CEC_TIMEOUT  50000 /* 2.5 TX CLKs (at 50 baud) */
  88
  89 #define SAB82532_RECV_FIFO_SIZE 32      /* Standard async fifo sizes */
  90 #define SAB82532_XMIT_FIFO_SIZE 32
  91
  92 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
  93 {
  94         int timeout = up->tec_timeout;
  95
  96         while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
  97                 udelay(1);
  98 }
  99
 100 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
 101 {
 102         int timeout = up->cec_timeout;
 103
 104         while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
 105                 udelay(1);
 106 }
 107
 108 static struct tty_struct *
 109 receive_chars(struct uart_sunsab_port *up,
 110               union sab82532_irq_status *stat)
 111 {
 112         struct tty_struct *tty = NULL;
 113         unsigned char buf[32];
 114         int saw_console_brk = 0;
 115         int free_fifo = 0;
 116         int count = 0;
 117         int i;
 118
 119         if (up->port.info != NULL)              /* Unopened serial console */
 120                 tty = up->port.info->tty;
 121
 122         /* Read number of BYTES (Character + Status) available. */
 123         if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
 124                 count = SAB82532_RECV_FIFO_SIZE;
 125                 free_fifo++;
 126         }
 127
 128         if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
 129                 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
 130                 free_fifo++;
 131         }
 132
 133         /* Issue a FIFO read command in case we where idle. */
 134         if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
 135                 sunsab_cec_wait(up);
 136                 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
 137                 return tty;
 138         }
 139
 140         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 141                 free_fifo++;
 142
 143         /* Read the FIFO. */
 144         for (i = 0; i < count; i++)
 145                 buf[i] = readb(&up->regs->r.rfifo[i]);
 146
 147         /* Issue Receive Message Complete command. */
 148         if (free_fifo) {
 149                 sunsab_cec_wait(up);
 150                 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
 151         }
 152
 153         /* Count may be zero for BRK, so we check for it here */
 154         if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
 155             (up->port.line == up->port.cons->index))
 156                 saw_console_brk = 1;
 157
 158         for (i = 0; i < count; i++) {
 159                 unsigned char ch = buf[i], flag;
 160
 161                 if (tty == NULL) {
 162                         uart_handle_sysrq_char(&up->port, ch);
 163                         continue;
 164                 }
 165
 166                 flag = TTY_NORMAL;
 167                 up->port.icount.rx++;
 168
 169                 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
 170                                                 SAB82532_ISR0_FERR |
 171                                                 SAB82532_ISR0_RFO)) ||
 172                     unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
 173                         /*
 174                          * For statistics only
 175                          */
 176                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 177                                 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
 178                                                      SAB82532_ISR0_FERR);
 179                                 up->port.icount.brk++;
 180                                 /*
 181                                  * We do the SysRQ and SAK checking
 182                                  * here because otherwise the break
 183                                  * may get masked by ignore_status_mask
 184                                  * or read_status_mask.
 185                                  */
 186                                 if (uart_handle_break(&up->port))
 187                                         continue;
 188                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 189                                 up->port.icount.parity++;
 190                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 191                                 up->port.icount.frame++;
 192                         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 193                                 up->port.icount.overrun++;
 194
 195                         /*
 196                          * Mask off conditions which should be ingored.
 197                          */
 198                         stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
 199                         stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
 200
 201                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 202                                 flag = TTY_BREAK;
 203                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 204                                 flag = TTY_PARITY;
 205                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 206                                 flag = TTY_FRAME;
 207                 }
 208
 209                 if (uart_handle_sysrq_char(&up->port, ch))
 210                         continue;
 211
 212                 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
 213                     (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
 214                         tty_insert_flip_char(tty, ch, flag);
 215                 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 216                         tty_insert_flip_char(tty, 0, TTY_OVERRUN);
 217         }
 218
 219         if (saw_console_brk)
 220                 sun_do_break();
 221
 222         return tty;
 223 }
 224
 225 static void sunsab_stop_tx(struct uart_port *);
 226 static void sunsab_tx_idle(struct uart_sunsab_port *);
 227
 228 static void transmit_chars(struct uart_sunsab_port *up,
 229                            union sab82532_irq_status *stat)
 230 {
 231         struct circ_buf *xmit = &up->port.info->xmit;
 232         int i;
 233
 234         if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
 235                 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
 236                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 237                 set_bit(SAB82532_ALLS, &up->irqflags);
 238         }
 239
 240 #if 0 /* bde@nwlink.com says this check causes problems */
 241         if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
 242                 return;
 243 #endif
 244
 245         if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
 246                 return;
 247
 248         set_bit(SAB82532_XPR, &up->irqflags);
 249         sunsab_tx_idle(up);
 250
 251         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 252                 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 253                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 254                 return;
 255         }
 256
 257         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 258         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 259         clear_bit(SAB82532_ALLS, &up->irqflags);
 260
 261         /* Stuff 32 bytes into Transmit FIFO. */
 262         clear_bit(SAB82532_XPR, &up->irqflags);
 263         for (i = 0; i < up->port.fifosize; i++) {
 264                 writeb(xmit->buf[xmit->tail],
 265                        &up->regs->w.xfifo[i]);
 266                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 267                 up->port.icount.tx++;
 268                 if (uart_circ_empty(xmit))
 269                         break;
 270         }
 271
 272         /* Issue a Transmit Frame command. */
 273         sunsab_cec_wait(up);
 274         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 275
 276         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 277                 uart_write_wakeup(&up->port);
 278
 279         if (uart_circ_empty(xmit))
 280                 sunsab_stop_tx(&up->port);
 281 }
 282
 283 static void check_status(struct uart_sunsab_port *up,
 284                          union sab82532_irq_status *stat)
 285 {
 286         if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
 287                 uart_handle_dcd_change(&up->port,
 288                                        !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
 289
 290         if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
 291                 uart_handle_cts_change(&up->port,
 292                                        (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
 293
 294         if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
 295                 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
 296                 up->port.icount.dsr++;
 297         }
 298
 299         wake_up_interruptible(&up->port.info->delta_msr_wait);
 300 }
 301
 302 static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
 303 {
 304         struct uart_sunsab_port *up = dev_id;
 305         struct tty_struct *tty;
 306         union sab82532_irq_status status;
 307         unsigned long flags;
 308
 309         spin_lock_irqsave(&up->port.lock, flags);
 310
 311         status.stat = 0;
 312         if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA0)
 313                 status.sreg.isr0 = readb(&up->regs->r.isr0);
 314         if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA1)
 315                 status.sreg.isr1 = readb(&up->regs->r.isr1);
 316
 317         tty = NULL;
 318         if (status.stat) {
 319                 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 320                                          SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
 321                     (status.sreg.isr1 & SAB82532_ISR1_BRK))
 322                         tty = receive_chars(up, &status);
 323                 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
 324                     (status.sreg.isr1 & SAB82532_ISR1_CSC))
 325                         check_status(up, &status);
 326                 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
 327                         transmit_chars(up, &status);
 328         }
 329
 330         spin_unlock(&up->port.lock);
 331
 332         if (tty)
 333                 tty_flip_buffer_push(tty);
 334
 335         up++;
 336
 337         spin_lock(&up->port.lock);
 338
 339         status.stat = 0;
 340         if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB0)
 341                 status.sreg.isr0 = readb(&up->regs->r.isr0);
 342         if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB1)
 343                 status.sreg.isr1 = readb(&up->regs->r.isr1);
 344
 345         tty = NULL;
 346         if (status.stat) {
 347                 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 348                                          SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
 349                     (status.sreg.isr1 & SAB82532_ISR1_BRK))
 350
 351                         tty = receive_chars(up, &status);
 352                 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
 353                     (status.sreg.isr1 & (SAB82532_ISR1_BRK | SAB82532_ISR1_CSC)))
 354                         check_status(up, &status);
 355                 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
 356                         transmit_chars(up, &status);
 357         }
 358
 359         spin_unlock_irqrestore(&up->port.lock, flags);
 360
 361         if (tty)
 362                 tty_flip_buffer_push(tty);
 363
 364         return IRQ_HANDLED;
 365 }
 366
 367 /* port->lock is not held.  */
 368 static unsigned int sunsab_tx_empty(struct uart_port *port)
 369 {
 370         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 371         int ret;
 372
 373         /* Do not need a lock for a state test like this.  */
 374         if (test_bit(SAB82532_ALLS, &up->irqflags))
 375                 ret = TIOCSER_TEMT;
 376         else
 377                 ret = 0;
 378
 379         return ret;
 380 }
 381
 382 /* port->lock held by caller.  */
 383 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
 384 {
 385         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 386
 387         if (mctrl & TIOCM_RTS) {
 388                 up->cached_mode &= ~SAB82532_MODE_FRTS;
 389                 up->cached_mode |= SAB82532_MODE_RTS;
 390         } else {
 391                 up->cached_mode |= (SAB82532_MODE_FRTS |
 392                                     SAB82532_MODE_RTS);
 393         }
 394         if (mctrl & TIOCM_DTR) {
 395                 up->cached_pvr &= ~(up->pvr_dtr_bit);
 396         } else {
 397                 up->cached_pvr |= up->pvr_dtr_bit;
 398         }
 399
 400         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 401         if (test_bit(SAB82532_XPR, &up->irqflags))
 402                 sunsab_tx_idle(up);
 403 }
 404
 405 /* port->lock is held by caller and interrupts are disabled.  */
 406 static unsigned int sunsab_get_mctrl(struct uart_port *port)
 407 {
 408         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 409         unsigned char val;
 410         unsigned int result;
 411
 412         result = 0;
 413
 414         val = readb(&up->regs->r.pvr);
 415         result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
 416
 417         val = readb(&up->regs->r.vstr);
 418         result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
 419
 420         val = readb(&up->regs->r.star);
 421         result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
 422
 423         return result;
 424 }
 425
 426 /* port->lock held by caller.  */
 427 static void sunsab_stop_tx(struct uart_port *port)
 428 {
 429         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 430
 431         up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 432         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 433 }
 434
 435 /* port->lock held by caller.  */
 436 static void sunsab_tx_idle(struct uart_sunsab_port *up)
 437 {
 438         if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
 439                 u8 tmp;
 440
 441                 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
 442                 writeb(up->cached_mode, &up->regs->rw.mode);
 443                 writeb(up->cached_pvr, &up->regs->rw.pvr);
 444                 writeb(up->cached_dafo, &up->regs->w.dafo);
 445
 446                 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
 447                 tmp = readb(&up->regs->rw.ccr2);
 448                 tmp &= ~0xc0;
 449                 tmp |= (up->cached_ebrg >> 2) & 0xc0;
 450                 writeb(tmp, &up->regs->rw.ccr2);
 451         }
 452 }
 453
 454 /* port->lock held by caller.  */
 455 static void sunsab_start_tx(struct uart_port *port)
 456 {
 457         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 458         struct circ_buf *xmit = &up->port.info->xmit;
 459         int i;
 460
 461         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 462         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 463
 464         if (!test_bit(SAB82532_XPR, &up->irqflags))
 465                 return;
 466
 467         clear_bit(SAB82532_ALLS, &up->irqflags);
 468         clear_bit(SAB82532_XPR, &up->irqflags);
 469
 470         for (i = 0; i < up->port.fifosize; i++) {
 471                 writeb(xmit->buf[xmit->tail],
 472                        &up->regs->w.xfifo[i]);
 473                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 474                 up->port.icount.tx++;
 475                 if (uart_circ_empty(xmit))
 476                         break;
 477         }
 478
 479         /* Issue a Transmit Frame command.  */
 480         sunsab_cec_wait(up);
 481         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 482 }
 483
 484 /* port->lock is not held.  */
 485 static void sunsab_send_xchar(struct uart_port *port, char ch)
 486 {
 487         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 488         unsigned long flags;
 489
 490         spin_lock_irqsave(&up->port.lock, flags);
 491
 492         sunsab_tec_wait(up);
 493         writeb(ch, &up->regs->w.tic);
 494
 495         spin_unlock_irqrestore(&up->port.lock, flags);
 496 }
 497
 498 /* port->lock held by caller.  */
 499 static void sunsab_stop_rx(struct uart_port *port)
 500 {
 501         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 502
 503         up->interrupt_mask0 |= SAB82532_ISR0_TCD;
 504         writeb(up->interrupt_mask1, &up->regs->w.imr0);
 505 }
 506
 507 /* port->lock held by caller.  */
 508 static void sunsab_enable_ms(struct uart_port *port)
 509 {
 510         /* For now we always receive these interrupts.  */
 511 }
 512
 513 /* port->lock is not held.  */
 514 static void sunsab_break_ctl(struct uart_port *port, int break_state)
 515 {
 516         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 517         unsigned long flags;
 518         unsigned char val;
 519
 520         spin_lock_irqsave(&up->port.lock, flags);
 521
 522         val = up->cached_dafo;
 523         if (break_state)
 524                 val |= SAB82532_DAFO_XBRK;
 525         else
 526                 val &= ~SAB82532_DAFO_XBRK;
 527         up->cached_dafo = val;
 528
 529         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 530         if (test_bit(SAB82532_XPR, &up->irqflags))
 531                 sunsab_tx_idle(up);
 532
 533         spin_unlock_irqrestore(&up->port.lock, flags);
 534 }
 535
 536 /* port->lock is not held.  */
 537 static int sunsab_startup(struct uart_port *port)
 538 {
 539         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 540         unsigned long flags;
 541         unsigned char tmp;
 542
 543         spin_lock_irqsave(&up->port.lock, flags);
 544
 545         /*
 546          * Wait for any commands or immediate characters
 547          */
 548         sunsab_cec_wait(up);
 549         sunsab_tec_wait(up);
 550
 551         /*
 552          * Clear the FIFO buffers.
 553          */
 554         writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
 555         sunsab_cec_wait(up);
 556         writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
 557
 558         /*
 559          * Clear the interrupt registers.
 560          */
 561         (void) readb(&up->regs->r.isr0);
 562         (void) readb(&up->regs->r.isr1);
 563
 564         /*
 565          * Now, initialize the UART
 566          */
 567         writeb(0, &up->regs->w.ccr0);                           /* power-down */
 568         writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
 569                SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
 570         writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
 571         writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
 572                SAB82532_CCR2_TOE, &up->regs->w.ccr2);
 573         writeb(0, &up->regs->w.ccr3);
 574         writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
 575         up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
 576                            SAB82532_MODE_RAC);
 577         writeb(up->cached_mode, &up->regs->w.mode);
 578         writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
 579
 580         tmp = readb(&up->regs->rw.ccr0);
 581         tmp |= SAB82532_CCR0_PU;        /* power-up */
 582         writeb(tmp, &up->regs->rw.ccr0);
 583
 584         /*
 585          * Finally, enable interrupts
 586          */
 587         up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 588                                SAB82532_IMR0_PLLA);
 589         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 590         up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 591                                SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 592                                SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 593                                SAB82532_IMR1_XPR);
 594         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 595         set_bit(SAB82532_ALLS, &up->irqflags);
 596         set_bit(SAB82532_XPR, &up->irqflags);
 597
 598         spin_unlock_irqrestore(&up->port.lock, flags);
 599
 600         return 0;
 601 }
 602
 603 /* port->lock is not held.  */
 604 static void sunsab_shutdown(struct uart_port *port)
 605 {
 606         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 607         unsigned long flags;
 608
 609         spin_lock_irqsave(&up->port.lock, flags);
 610
 611         /* Disable Interrupts */
 612         up->interrupt_mask0 = 0xff;
 613         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 614         up->interrupt_mask1 = 0xff;
 615         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 616
 617         /* Disable break condition */
 618         up->cached_dafo = readb(&up->regs->rw.dafo);
 619         up->cached_dafo &= ~SAB82532_DAFO_XBRK;
 620         writeb(up->cached_dafo, &up->regs->rw.dafo);
 621
 622         /* Disable Receiver */
 623         up->cached_mode &= ~SAB82532_MODE_RAC;
 624         writeb(up->cached_mode, &up->regs->rw.mode);
 625
 626         /*
 627          * XXX FIXME
 628          *
 629          * If the chip is powered down here the system hangs/crashes during
 630          * reboot or shutdown.  This needs to be investigated further,
 631          * similar behaviour occurs in 2.4 when the driver is configured
 632          * as a module only.  One hint may be that data is sometimes
 633          * transmitted at 9600 baud during shutdown (regardless of the
 634          * speed the chip was configured for when the port was open).
 635          */
 636 #if 0
 637         /* Power Down */
 638         tmp = readb(&up->regs->rw.ccr0);
 639         tmp &= ~SAB82532_CCR0_PU;
 640         writeb(tmp, &up->regs->rw.ccr0);
 641 #endif
 642
 643         spin_unlock_irqrestore(&up->port.lock, flags);
 644 }
 645
 646 /*
 647  * This is used to figure out the divisor speeds.
 648  *
 649  * The formula is:    Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
 650  *
 651  * with               0 <= N < 64 and 0 <= M < 16
 652  */
 653
 654 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
 655 {
 656         int     n, m;
 657
 658         if (baud == 0) {
 659                 *n_ret = 0;
 660                 *m_ret = 0;
 661                 return;
 662         }
 663
 664         /*
 665          * We scale numbers by 10 so that we get better accuracy
 666          * without having to use floating point.  Here we increment m
 667          * until n is within the valid range.
 668          */
 669         n = (SAB_BASE_BAUD * 10) / baud;
 670         m = 0;
 671         while (n >= 640) {
 672                 n = n / 2;
 673                 m++;
 674         }
 675         n = (n+5) / 10;
 676         /*
 677          * We try very hard to avoid speeds with M == 0 since they may
 678          * not work correctly for XTAL frequences above 10 MHz.
 679          */
 680         if ((m == 0) && ((n & 1) == 0)) {
 681                 n = n / 2;
 682                 m++;
 683         }
 684         *n_ret = n - 1;
 685         *m_ret = m;
 686 }
 687
 688 /* Internal routine, port->lock is held and local interrupts are disabled.  */
 689 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
 690                                   unsigned int iflag, unsigned int baud,
 691                                   unsigned int quot)
 692 {
 693         unsigned char dafo;
 694         int bits, n, m;
 695
 696         /* Byte size and parity */
 697         switch (cflag & CSIZE) {
 698               case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 699               case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
 700               case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
 701               case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
 702               /* Never happens, but GCC is too dumb to figure it out */
 703               default:  dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 704         }
 705
 706         if (cflag & CSTOPB) {
 707                 dafo |= SAB82532_DAFO_STOP;
 708                 bits++;
 709         }
 710
 711         if (cflag & PARENB) {
 712                 dafo |= SAB82532_DAFO_PARE;
 713                 bits++;
 714         }
 715
 716         if (cflag & PARODD) {
 717                 dafo |= SAB82532_DAFO_PAR_ODD;
 718         } else {
 719                 dafo |= SAB82532_DAFO_PAR_EVEN;
 720         }
 721         up->cached_dafo = dafo;
 722
 723         calc_ebrg(baud, &n, &m);
 724
 725         up->cached_ebrg = n | (m << 6);
 726
 727         up->tec_timeout = (10 * 1000000) / baud;
 728         up->cec_timeout = up->tec_timeout >> 2;
 729
 730         /* CTS flow control flags */
 731         /* We encode read_status_mask and ignore_status_mask like so:
 732          *
 733          * ---------------------
 734          * | ... | ISR1 | ISR0 |
 735          * ---------------------
 736          *  ..    15   8 7    0
 737          */
 738
 739         up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 740                                      SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
 741                                      SAB82532_ISR0_CDSC);
 742         up->port.read_status_mask |= (SAB82532_ISR1_CSC |
 743                                       SAB82532_ISR1_ALLS |
 744                                       SAB82532_ISR1_XPR) << 8;
 745         if (iflag & INPCK)
 746                 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
 747                                               SAB82532_ISR0_FERR);
 748         if (iflag & (BRKINT | PARMRK))
 749                 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
 750
 751         /*
 752          * Characteres to ignore
 753          */
 754         up->port.ignore_status_mask = 0;
 755         if (iflag & IGNPAR)
 756                 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
 757                                                 SAB82532_ISR0_FERR);
 758         if (iflag & IGNBRK) {
 759                 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
 760                 /*
 761                  * If we're ignoring parity and break indicators,
 762                  * ignore overruns too (for real raw support).
 763                  */
 764                 if (iflag & IGNPAR)
 765                         up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
 766         }
 767
 768         /*
 769          * ignore all characters if CREAD is not set
 770          */
 771         if ((cflag & CREAD) == 0)
 772                 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
 773                                                 SAB82532_ISR0_TCD);
 774
 775         uart_update_timeout(&up->port, cflag,
 776                             (up->port.uartclk / (16 * quot)));
 777
 778         /* Now schedule a register update when the chip's
 779          * transmitter is idle.
 780          */
 781         up->cached_mode |= SAB82532_MODE_RAC;
 782         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 783         if (test_bit(SAB82532_XPR, &up->irqflags))
 784                 sunsab_tx_idle(up);
 785 }
 786
 787 /* port->lock is not held.  */
 788 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
 789                                struct ktermios *old)
 790 {
 791         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 792         unsigned long flags;
 793         unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 794         unsigned int quot = uart_get_divisor(port, baud);
 795
 796         spin_lock_irqsave(&up->port.lock, flags);
 797         sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
 798         spin_unlock_irqrestore(&up->port.lock, flags);
 799 }
 800
 801 static const char *sunsab_type(struct uart_port *port)
 802 {
 803         struct uart_sunsab_port *up = (void *)port;
 804         static char buf[36];
 805
 806         sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
 807         return buf;
 808 }
 809
 810 static void sunsab_release_port(struct uart_port *port)
 811 {
 812 }
 813
 814 static int sunsab_request_port(struct uart_port *port)
 815 {
 816         return 0;
 817 }
 818
 819 static void sunsab_config_port(struct uart_port *port, int flags)
 820 {
 821 }
 822
 823 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
 824 {
 825         return -EINVAL;
 826 }
 827
 828 static struct uart_ops sunsab_pops = {
 829         .tx_empty       = sunsab_tx_empty,
 830         .set_mctrl      = sunsab_set_mctrl,
 831         .get_mctrl      = sunsab_get_mctrl,
 832         .stop_tx        = sunsab_stop_tx,
 833         .start_tx       = sunsab_start_tx,
 834         .send_xchar     = sunsab_send_xchar,
 835         .stop_rx        = sunsab_stop_rx,
 836         .enable_ms      = sunsab_enable_ms,
 837         .break_ctl      = sunsab_break_ctl,
 838         .startup        = sunsab_startup,
 839         .shutdown       = sunsab_shutdown,
 840         .set_termios    = sunsab_set_termios,
 841         .type           = sunsab_type,
 842         .release_port   = sunsab_release_port,
 843         .request_port   = sunsab_request_port,
 844         .config_port    = sunsab_config_port,
 845         .verify_port    = sunsab_verify_port,
 846 };
 847
 848 static struct uart_driver sunsab_reg = {
 849         .owner                  = THIS_MODULE,
 850         .driver_name            = "serial",
 851         .dev_name               = "ttyS",
 852         .major                  = TTY_MAJOR,
 853 };
 854
 855 static struct uart_sunsab_port *sunsab_ports;
 856 static int num_channels;
 857
 858 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
 859
 860 static void sunsab_console_putchar(struct uart_port *port, int c)
 861 {
 862         struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
 863         unsigned long flags;
 864
 865         spin_lock_irqsave(&up->port.lock, flags);
 866
 867         sunsab_tec_wait(up);
 868         writeb(c, &up->regs->w.tic);
 869
 870         spin_unlock_irqrestore(&up->port.lock, flags);
 871 }
 872
 873 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
 874 {
 875         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 876
 877         uart_console_write(&up->port, s, n, sunsab_console_putchar);
 878         sunsab_tec_wait(up);
 879 }
 880
 881 static int sunsab_console_setup(struct console *con, char *options)
 882 {
 883         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 884         unsigned long flags;
 885         unsigned int baud, quot;
 886
 887         /*
 888          * The console framework calls us for each and every port
 889          * registered. Defer the console setup until the requested
 890          * port has been properly discovered. A bit of a hack,
 891          * though...
 892          */
 893         if (up->port.type != PORT_SUNSAB)
 894                 return -1;
 895
 896         printk("Console: ttyS%d (SAB82532)\n",
 897                (sunsab_reg.minor - 64) + con->index);
 898
 899         sunserial_console_termios(con);
 900
 901         switch (con->cflag & CBAUD) {
 902         case B150: baud = 150; break;
 903         case B300: baud = 300; break;
 904         case B600: baud = 600; break;
 905         case B1200: baud = 1200; break;
 906         case B2400: baud = 2400; break;
 907         case B4800: baud = 4800; break;
 908         default: case B9600: baud = 9600; break;
 909         case B19200: baud = 19200; break;
 910         case B38400: baud = 38400; break;
 911         case B57600: baud = 57600; break;
 912         case B115200: baud = 115200; break;
 913         case B230400: baud = 230400; break;
 914         case B460800: baud = 460800; break;
 915         };
 916
 917         /*
 918          * Temporary fix.
 919          */
 920         spin_lock_init(&up->port.lock);
 921
 922         /*
 923          * Initialize the hardware
 924          */
 925         sunsab_startup(&up->port);
 926
 927         spin_lock_irqsave(&up->port.lock, flags);
 928
 929         /*
 930          * Finally, enable interrupts
 931          */
 932         up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 933                                 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
 934         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 935         up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 936                                 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 937                                 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 938                                 SAB82532_IMR1_XPR;
 939         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 940
 941         quot = uart_get_divisor(&up->port, baud);
 942         sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
 943         sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
 944
 945         spin_unlock_irqrestore(&up->port.lock, flags);
 946
 947         return 0;
 948 }
 949
 950 static struct console sunsab_console = {
 951         .name   =       "ttyS",
 952         .write  =       sunsab_console_write,
 953         .device =       uart_console_device,
 954         .setup  =       sunsab_console_setup,
 955         .flags  =       CON_PRINTBUFFER,
 956         .index  =       -1,
 957         .data   =       &sunsab_reg,
 958 };
 959
 960 static inline struct console *SUNSAB_CONSOLE(void)
 961 {
 962         int i;
 963
 964         if (con_is_present())
 965                 return NULL;
 966
 967         for (i = 0; i < num_channels; i++) {
 968                 int this_minor = sunsab_reg.minor + i;
 969
 970                 if ((this_minor - 64) == (serial_console - 1))
 971                         break;
 972         }
 973         if (i == num_channels)
 974                 return NULL;
 975
 976         sunsab_console.index = i;
 977
 978         return &sunsab_console;
 979 }
 980 #else
 981 #define SUNSAB_CONSOLE()        (NULL)
 982 #define sunsab_console_init()   do { } while (0)
 983 #endif
 984
 985 static int __devinit sunsab_init_one(struct uart_sunsab_port *up,
 986                                      struct of_device *op,
 987                                      unsigned long offset,
 988                                      int line)
 989 {
 990         up->port.line = line;
 991         up->port.dev = &op->dev;
 992
 993         up->port.mapbase = op->resource[0].start + offset;
 994         up->port.membase = of_ioremap(&op->resource[0], offset,
 995                                       sizeof(union sab82532_async_regs),
 996                                       "sab");
 997         if (!up->port.membase)
 998                 return -ENOMEM;
 999         up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
1000
1001         up->port.irq = op->irqs[0];
1002
1003         up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
1004         up->port.iotype = UPIO_MEM;
1005
1006         writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
1007
1008         up->port.ops = &sunsab_pops;
1009         up->port.type = PORT_SUNSAB;
1010         up->port.uartclk = SAB_BASE_BAUD;
1011
1012         up->type = readb(&up->regs->r.vstr) & 0x0f;
1013         writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
1014         writeb(0xff, &up->regs->w.pim);
1015         if ((up->port.line & 0x1) == 0) {
1016                 up->pvr_dsr_bit = (1 << 0);
1017                 up->pvr_dtr_bit = (1 << 1);
1018         } else {
1019                 up->pvr_dsr_bit = (1 << 3);
1020                 up->pvr_dtr_bit = (1 << 2);
1021         }
1022         up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
1023         writeb(up->cached_pvr, &up->regs->w.pvr);
1024         up->cached_mode = readb(&up->regs->rw.mode);
1025         up->cached_mode |= SAB82532_MODE_FRTS;
1026         writeb(up->cached_mode, &up->regs->rw.mode);
1027         up->cached_mode |= SAB82532_MODE_RTS;
1028         writeb(up->cached_mode, &up->regs->rw.mode);
1029
1030         up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1031         up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1032
1033         if (!(up->port.line & 0x01)) {
1034                 int err;
1035
1036                 err = request_irq(up->port.irq, sunsab_interrupt,
1037                                   IRQF_SHARED, "sab", up);
1038                 if (err) {
1039                         of_iounmap(&op->resource[0],
1040                                    up->port.membase,
1041                                    sizeof(union sab82532_async_regs));
1042                         return err;
1043                 }
1044         }
1045
1046         return 0;
1047 }
1048
1049 static int __devinit sab_probe(struct of_device *op, const struct of_device_id *match)
1050 {
1051         static int inst;
1052         struct uart_sunsab_port *up;
1053         int err;
1054
1055         up = &sunsab_ports[inst * 2];
1056
1057         err = sunsab_init_one(&up[0], op,
1058                               0,
1059                               (inst * 2) + 0);
1060         if (err)
1061                 return err;
1062
1063         err = sunsab_init_one(&up[1], op,
1064                               sizeof(union sab82532_async_regs),
1065                               (inst * 2) + 1);
1066         if (err) {
1067                 of_iounmap(&op->resource[0],
1068                            up[0].port.membase,
1069                            sizeof(union sab82532_async_regs));
1070                 free_irq(up[0].port.irq, &up[0]);
1071                 return err;
1072         }
1073
1074         uart_add_one_port(&sunsab_reg, &up[0].port);
1075         uart_add_one_port(&sunsab_reg, &up[1].port);
1076
1077         dev_set_drvdata(&op->dev, &up[0]);
1078
1079         inst++;
1080
1081         return 0;
1082 }
1083
1084 static void __devexit sab_remove_one(struct uart_sunsab_port *up)
1085 {
1086         struct of_device *op = to_of_device(up->port.dev);
1087
1088         uart_remove_one_port(&sunsab_reg, &up->port);
1089         if (!(up->port.line & 1))
1090                 free_irq(up->port.irq, up);
1091         of_iounmap(&op->resource[0],
1092                    up->port.membase,
1093                    sizeof(union sab82532_async_regs));
1094 }
1095
1096 static int __devexit sab_remove(struct of_device *op)
1097 {
1098         struct uart_sunsab_port *up = dev_get_drvdata(&op->dev);
1099
1100         sab_remove_one(&up[0]);
1101         sab_remove_one(&up[1]);
1102
1103         dev_set_drvdata(&op->dev, NULL);
1104
1105         return 0;
1106 }
1107
1108 static struct of_device_id sab_match[] = {
1109         {
1110                 .name = "se",
1111         },
1112         {
1113                 .name = "serial",
1114                 .compatible = "sab82532",
1115         },
1116         {},
1117 };
1118 MODULE_DEVICE_TABLE(of, sab_match);
1119
1120 static struct of_platform_driver sab_driver = {
1121         .name           = "sab",
1122         .match_table    = sab_match,
1123         .probe          = sab_probe,
1124         .remove         = __devexit_p(sab_remove),
1125 };
1126
1127 static int __init sunsab_init(void)
1128 {
1129         struct device_node *dp;
1130         int err;
1131
1132         num_channels = 0;
1133         for_each_node_by_name(dp, "se")
1134                 num_channels += 2;
1135         for_each_node_by_name(dp, "serial") {
1136                 if (of_device_is_compatible(dp, "sab82532"))
1137                         num_channels += 2;
1138         }
1139
1140         if (num_channels) {
1141                 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1142                                        num_channels, GFP_KERNEL);
1143                 if (!sunsab_ports)
1144                         return -ENOMEM;
1145
1146                 sunsab_reg.minor = sunserial_current_minor;
1147                 sunsab_reg.nr = num_channels;
1148
1149                 err = uart_register_driver(&sunsab_reg);
1150                 if (err) {
1151                         kfree(sunsab_ports);
1152                         sunsab_ports = NULL;
1153
1154                         return err;
1155                 }
1156
1157                 sunsab_reg.tty_driver->name_base = sunsab_reg.minor - 64;
1158                 sunsab_reg.cons = SUNSAB_CONSOLE();
1159                 sunserial_current_minor += num_channels;
1160         }
1161
1162         return of_register_driver(&sab_driver, &of_bus_type);
1163 }
1164
1165 static void __exit sunsab_exit(void)
1166 {
1167         of_unregister_driver(&sab_driver);
1168         if (num_channels) {
1169                 sunserial_current_minor -= num_channels;
1170                 uart_unregister_driver(&sunsab_reg);
1171         }
1172
1173         kfree(sunsab_ports);
1174         sunsab_ports = NULL;
1175 }
1176
1177 module_init(sunsab_init);
1178 module_exit(sunsab_exit);
1179
1180 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1181 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1182 MODULE_LICENSE("GPL");