2 * ATI Frame Buffer Device Driver Core
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * This driver supports the following ATI graphics chips:
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
16 * This driver is partly based on the PowerMac console driver:
18 * Copyright (C) 1996 Paul Mackerras
20 * and on the PowerMac ATI/mach64 display driver:
22 * Copyright (C) 1997 Michael AK Tesch
24 * with work by Jon Howell
26 * Anthony Tong <atong@uiuc.edu>
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
35 * Many thanks to Nitya from ATI devrel for support and patience !
38 /******************************************************************************
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
47 (Anyone with Mac to help with this?)
49 ******************************************************************************/
52 #include <linux/module.h>
53 #include <linux/moduleparam.h>
54 #include <linux/kernel.h>
55 #include <linux/errno.h>
56 #include <linux/string.h>
58 #include <linux/slab.h>
59 #include <linux/vmalloc.h>
60 #include <linux/delay.h>
61 #include <linux/console.h>
63 #include <linux/init.h>
64 #include <linux/pci.h>
65 #include <linux/interrupt.h>
66 #include <linux/spinlock.h>
67 #include <linux/wait.h>
68 #include <linux/backlight.h>
71 #include <asm/uaccess.h>
73 #include <video/mach64.h>
78 #include <asm/machdep.h>
80 #include "../macmodes.h"
88 #include <linux/adb.h>
89 #include <linux/pmu.h>
91 #ifdef CONFIG_BOOTX_TEXT
92 #include <asm/btext.h>
94 #ifdef CONFIG_PMAC_BACKLIGHT
95 #include <asm/backlight.h>
107 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
108 /* - must be large enough to catch all GUI-Regs */
109 /* - must be aligned to a PAGE boundary */
110 #define GUI_RESERVE (1 * PAGE_SIZE)
112 /* FIXME: remove the FAIL definition */
113 #define FAIL(msg) do { \
114 if (!(var->activate & FB_ACTIVATE_TEST)) \
115 printk(KERN_CRIT "atyfb: " msg "\n"); \
118 #define FAIL_MAX(msg, x, _max_) do { \
120 if (!(var->activate & FB_ACTIVATE_TEST)) \
121 printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
126 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
128 #define DPRINTK(fmt, args...)
131 #define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
132 #define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
134 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
135 static const u32 lt_lcd_regs[] = {
142 0, /* EXT_VERT_STRETCH */
147 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
149 if (M64_HAS(LT_LCD_REGS)) {
150 aty_st_le32(lt_lcd_regs[index], val, par);
154 /* write addr byte */
155 temp = aty_ld_le32(LCD_INDEX, par);
156 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
157 /* write the register value */
158 aty_st_le32(LCD_DATA, val, par);
162 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
164 if (M64_HAS(LT_LCD_REGS)) {
165 return aty_ld_le32(lt_lcd_regs[index], par);
169 /* write addr byte */
170 temp = aty_ld_le32(LCD_INDEX, par);
171 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
172 /* read the register value */
173 return aty_ld_le32(LCD_DATA, par);
176 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
178 #ifdef CONFIG_FB_ATY_GENERIC_LCD
182 * Reduce a fraction by factoring out the largest common divider of the
183 * fraction's numerator and denominator.
185 static void ATIReduceRatio(int *Numerator, int *Denominator)
187 int Multiplier, Divider, Remainder;
189 Multiplier = *Numerator;
190 Divider = *Denominator;
192 while ((Remainder = Multiplier % Divider))
194 Multiplier = Divider;
198 *Numerator /= Divider;
199 *Denominator /= Divider;
203 * The Hardware parameters for each card
206 struct aty_cmap_regs {
214 struct pci_mmap_map {
218 unsigned long prot_flag;
219 unsigned long prot_mask;
222 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
224 .type = FB_TYPE_PACKED_PIXELS,
225 .visual = FB_VISUAL_PSEUDOCOLOR,
231 * Frame buffer device API
234 static int atyfb_open(struct fb_info *info, int user);
235 static int atyfb_release(struct fb_info *info, int user);
236 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
237 static int atyfb_set_par(struct fb_info *info);
238 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
239 u_int transp, struct fb_info *info);
240 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
241 static int atyfb_blank(int blank, struct fb_info *info);
242 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
243 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
244 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
245 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
247 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
249 static int atyfb_sync(struct fb_info *info);
255 static int aty_init(struct fb_info *info, const char *name);
257 static int store_video_par(char *videopar, unsigned char m64_num);
260 static struct crtc saved_crtc;
261 static union aty_pll saved_pll;
262 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
264 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
265 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
266 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
267 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
269 static int read_aty_sense(const struct atyfb_par *par);
274 * Interface used by the world
277 static struct fb_var_screeninfo default_var = {
278 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
279 640, 480, 640, 480, 0, 0, 8, 0,
280 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
281 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
282 0, FB_VMODE_NONINTERLACED
285 static struct fb_videomode defmode = {
286 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
287 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
288 0, FB_VMODE_NONINTERLACED
291 static struct fb_ops atyfb_ops = {
292 .owner = THIS_MODULE,
293 .fb_open = atyfb_open,
294 .fb_release = atyfb_release,
295 .fb_check_var = atyfb_check_var,
296 .fb_set_par = atyfb_set_par,
297 .fb_setcolreg = atyfb_setcolreg,
298 .fb_pan_display = atyfb_pan_display,
299 .fb_blank = atyfb_blank,
300 .fb_ioctl = atyfb_ioctl,
301 .fb_fillrect = atyfb_fillrect,
302 .fb_copyarea = atyfb_copyarea,
303 .fb_imageblit = atyfb_imageblit,
305 .fb_mmap = atyfb_mmap,
307 .fb_sync = atyfb_sync,
318 static int comp_sync __devinitdata = -1;
322 static int default_vmode __devinitdata = VMODE_CHOOSE;
323 static int default_cmode __devinitdata = CMODE_CHOOSE;
325 module_param_named(vmode, default_vmode, int, 0);
326 MODULE_PARM_DESC(vmode, "int: video mode for mac");
327 module_param_named(cmode, default_cmode, int, 0);
328 MODULE_PARM_DESC(cmode, "int: color mode for mac");
332 static unsigned int mach64_count __devinitdata = 0;
333 static unsigned long phys_vmembase[FB_MAX] __devinitdata = { 0, };
334 static unsigned long phys_size[FB_MAX] __devinitdata = { 0, };
335 static unsigned long phys_guiregbase[FB_MAX] __devinitdata = { 0, };
338 /* top -> down is an evolution of mach64 chipset, any corrections? */
339 #define ATI_CHIP_88800GX (M64F_GX)
340 #define ATI_CHIP_88800CX (M64F_GX)
342 #define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
343 #define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
345 #define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
346 #define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
348 #define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
349 #define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
350 #define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
352 /* FIXME what is this chip? */
353 #define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
355 /* make sets shorter */
356 #define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
358 #define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
359 /*#define ATI_CHIP_264GTDVD ?*/
360 #define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
362 #define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
363 #define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
364 #define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
366 #define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
367 #define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
372 int pll, mclk, xclk, ecp_max;
374 } aty_chips[] __devinitdata = {
375 #ifdef CONFIG_FB_ATY_GX
377 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
378 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
379 #endif /* CONFIG_FB_ATY_GX */
381 #ifdef CONFIG_FB_ATY_CT
382 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
383 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
385 /* FIXME what is this chip? */
386 { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
388 { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
389 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
391 { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
392 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
394 { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
396 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
398 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
399 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
400 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
401 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
403 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
404 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
405 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
406 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
407 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
409 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
410 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
411 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
412 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
413 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
415 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
416 { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
417 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
418 { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
419 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
420 { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
422 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
423 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
424 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
425 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
426 #endif /* CONFIG_FB_ATY_CT */
430 static int __devinit correct_chipset(struct atyfb_par *par)
438 for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
439 if (par->pci_id == aty_chips[i].pci_id)
442 name = aty_chips[i].name;
443 par->pll_limits.pll_max = aty_chips[i].pll;
444 par->pll_limits.mclk = aty_chips[i].mclk;
445 par->pll_limits.xclk = aty_chips[i].xclk;
446 par->pll_limits.ecp_max = aty_chips[i].ecp_max;
447 par->features = aty_chips[i].features;
449 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
450 type = chip_id & CFG_CHIP_TYPE;
451 rev = (chip_id & CFG_CHIP_REV) >> 24;
453 switch(par->pci_id) {
454 #ifdef CONFIG_FB_ATY_GX
455 case PCI_CHIP_MACH64GX:
459 case PCI_CHIP_MACH64CX:
464 #ifdef CONFIG_FB_ATY_CT
465 case PCI_CHIP_MACH64VT:
466 switch (rev & 0x07) {
468 switch (rev & 0xc0) {
470 name = "ATI264VT (A3) (Mach64 VT)";
471 par->pll_limits.pll_max = 170;
472 par->pll_limits.mclk = 67;
473 par->pll_limits.xclk = 67;
474 par->pll_limits.ecp_max = 80;
475 par->features = ATI_CHIP_264VT;
478 name = "ATI264VT2 (A4) (Mach64 VT)";
479 par->pll_limits.pll_max = 200;
480 par->pll_limits.mclk = 67;
481 par->pll_limits.xclk = 67;
482 par->pll_limits.ecp_max = 80;
483 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
488 name = "ATI264VT3 (B1) (Mach64 VT)";
489 par->pll_limits.pll_max = 200;
490 par->pll_limits.mclk = 67;
491 par->pll_limits.xclk = 67;
492 par->pll_limits.ecp_max = 80;
493 par->features = ATI_CHIP_264VTB;
496 name = "ATI264VT3 (B2) (Mach64 VT)";
497 par->pll_limits.pll_max = 200;
498 par->pll_limits.mclk = 67;
499 par->pll_limits.xclk = 67;
500 par->pll_limits.ecp_max = 80;
501 par->features = ATI_CHIP_264VT3;
505 case PCI_CHIP_MACH64GT:
506 switch (rev & 0x07) {
508 name = "3D RAGE II (Mach64 GT)";
509 par->pll_limits.pll_max = 170;
510 par->pll_limits.mclk = 67;
511 par->pll_limits.xclk = 67;
512 par->pll_limits.ecp_max = 80;
513 par->features = ATI_CHIP_264GTB;
516 name = "3D RAGE II+ (Mach64 GT)";
517 par->pll_limits.pll_max = 200;
518 par->pll_limits.mclk = 67;
519 par->pll_limits.xclk = 67;
520 par->pll_limits.ecp_max = 100;
521 par->features = ATI_CHIP_264GTB;
528 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
532 static char ram_dram[] __devinitdata = "DRAM";
533 static char ram_resv[] __devinitdata = "RESV";
534 #ifdef CONFIG_FB_ATY_GX
535 static char ram_vram[] __devinitdata = "VRAM";
536 #endif /* CONFIG_FB_ATY_GX */
537 #ifdef CONFIG_FB_ATY_CT
538 static char ram_edo[] __devinitdata = "EDO";
539 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
540 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
541 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
542 static char ram_off[] __devinitdata = "OFF";
543 #endif /* CONFIG_FB_ATY_CT */
546 static u32 pseudo_palette[17];
548 #ifdef CONFIG_FB_ATY_GX
549 static char *aty_gx_ram[8] __devinitdata = {
550 ram_dram, ram_vram, ram_vram, ram_dram,
551 ram_dram, ram_vram, ram_vram, ram_resv
553 #endif /* CONFIG_FB_ATY_GX */
555 #ifdef CONFIG_FB_ATY_CT
556 static char *aty_ct_ram[8] __devinitdata = {
557 ram_off, ram_dram, ram_edo, ram_edo,
558 ram_sdram, ram_sgram, ram_sdram32, ram_resv
560 #endif /* CONFIG_FB_ATY_CT */
562 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
564 u32 pixclock = var->pixclock;
565 #ifdef CONFIG_FB_ATY_GENERIC_LCD
567 par->pll.ct.xres = 0;
568 if (par->lcd_table != 0) {
569 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
570 if(lcd_on_off & LCD_ON) {
571 par->pll.ct.xres = var->xres;
572 pixclock = par->lcd_pixclock;
579 #if defined(CONFIG_PPC)
582 * Apple monitor sense
585 static int __devinit read_aty_sense(const struct atyfb_par *par)
589 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
591 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
593 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
594 sense = ((i & 0x3000) >> 3) | (i & 0x100);
596 /* drive each sense line low in turn and collect the other 2 */
597 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
599 i = aty_ld_le32(GP_IO, par);
600 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
601 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
604 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
606 i = aty_ld_le32(GP_IO, par);
607 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
608 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
611 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
613 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
614 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
618 #endif /* defined(CONFIG_PPC) */
620 /* ------------------------------------------------------------------------- */
626 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
628 #ifdef CONFIG_FB_ATY_GENERIC_LCD
629 if (par->lcd_table != 0) {
630 if(!M64_HAS(LT_LCD_REGS)) {
631 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
632 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
634 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
635 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
638 /* switch to non shadow registers */
639 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
640 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
642 /* save stretching */
643 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
644 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
645 if (!M64_HAS(LT_LCD_REGS))
646 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
649 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
650 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
651 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
652 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
653 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
654 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
655 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
657 #ifdef CONFIG_FB_ATY_GENERIC_LCD
658 if (par->lcd_table != 0) {
659 /* switch to shadow registers */
660 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
661 SHADOW_EN | SHADOW_RW_EN, par);
663 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
664 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
665 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
666 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
668 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
670 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
673 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
675 #ifdef CONFIG_FB_ATY_GENERIC_LCD
676 if (par->lcd_table != 0) {
678 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
680 /* update non-shadow registers first */
681 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
682 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
683 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
685 /* temporarily disable stretching */
686 aty_st_lcd(HORZ_STRETCHING,
687 crtc->horz_stretching &
688 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
689 aty_st_lcd(VERT_STRETCHING,
690 crtc->vert_stretching &
691 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
692 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
696 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
698 DPRINTK("setting up CRTC\n");
699 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
700 ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
701 (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
702 (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
704 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
705 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
706 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
707 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
708 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
709 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
710 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
712 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
713 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
714 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
715 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
716 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
717 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
719 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
722 if (par->accel_flags & FB_ACCELF_TEXT)
723 aty_init_engine(par, info);
725 #ifdef CONFIG_FB_ATY_GENERIC_LCD
726 /* after setting the CRTC registers we should set the LCD registers. */
727 if (par->lcd_table != 0) {
728 /* switch to shadow registers */
729 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
730 (SHADOW_EN | SHADOW_RW_EN), par);
732 DPRINTK("set shadow CRT to %ix%i %c%c\n",
733 ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
734 (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
736 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
737 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
738 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
739 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
741 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
742 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
743 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
744 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
746 /* restore CRTC selection & shadow state and enable stretching */
747 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
748 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
749 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
750 if(!M64_HAS(LT_LCD_REGS))
751 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
753 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
754 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
755 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
756 if(!M64_HAS(LT_LCD_REGS)) {
757 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
758 aty_ld_le32(LCD_INDEX, par);
759 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
762 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
765 static int aty_var_to_crtc(const struct fb_info *info,
766 const struct fb_var_screeninfo *var, struct crtc *crtc)
768 struct atyfb_par *par = (struct atyfb_par *) info->par;
769 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
770 u32 sync, vmode, vdisplay;
771 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
772 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
773 u32 pix_width, dp_pix_width, dp_chain_mask;
778 vxres = var->xres_virtual;
779 vyres = var->yres_virtual;
780 xoffset = var->xoffset;
781 yoffset = var->yoffset;
782 bpp = var->bits_per_pixel;
784 bpp = (var->green.length == 5) ? 15 : 16;
788 /* convert (and round up) and validate */
789 if (vxres < xres + xoffset)
790 vxres = xres + xoffset;
793 if (vyres < yres + yoffset)
794 vyres = yres + yoffset;
799 pix_width = CRTC_PIX_WIDTH_8BPP;
801 HOST_8BPP | SRC_8BPP | DST_8BPP |
802 BYTE_ORDER_LSB_TO_MSB;
803 dp_chain_mask = DP_CHAIN_8BPP;
804 } else if (bpp <= 15) {
806 pix_width = CRTC_PIX_WIDTH_15BPP;
807 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
808 BYTE_ORDER_LSB_TO_MSB;
809 dp_chain_mask = DP_CHAIN_15BPP;
810 } else if (bpp <= 16) {
812 pix_width = CRTC_PIX_WIDTH_16BPP;
813 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
814 BYTE_ORDER_LSB_TO_MSB;
815 dp_chain_mask = DP_CHAIN_16BPP;
816 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
818 pix_width = CRTC_PIX_WIDTH_24BPP;
820 HOST_8BPP | SRC_8BPP | DST_8BPP |
821 BYTE_ORDER_LSB_TO_MSB;
822 dp_chain_mask = DP_CHAIN_24BPP;
823 } else if (bpp <= 32) {
825 pix_width = CRTC_PIX_WIDTH_32BPP;
826 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
827 BYTE_ORDER_LSB_TO_MSB;
828 dp_chain_mask = DP_CHAIN_32BPP;
832 if (vxres * vyres * bpp / 8 > info->fix.smem_len)
833 FAIL("not enough video RAM");
835 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
836 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
838 if((xres > 1600) || (yres > 1200)) {
839 FAIL("MACH64 chips are designed for max 1600x1200\n"
840 "select anoter resolution.");
842 h_sync_strt = h_disp + var->right_margin;
843 h_sync_end = h_sync_strt + var->hsync_len;
844 h_sync_dly = var->right_margin & 7;
845 h_total = h_sync_end + h_sync_dly + var->left_margin;
847 v_sync_strt = v_disp + var->lower_margin;
848 v_sync_end = v_sync_strt + var->vsync_len;
849 v_total = v_sync_end + var->upper_margin;
851 #ifdef CONFIG_FB_ATY_GENERIC_LCD
852 if (par->lcd_table != 0) {
853 if(!M64_HAS(LT_LCD_REGS)) {
854 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
855 crtc->lcd_index = lcd_index &
856 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
857 aty_st_le32(LCD_INDEX, lcd_index, par);
860 if (!M64_HAS(MOBIL_BUS))
861 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
863 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
864 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
866 crtc->lcd_gen_cntl &=
867 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
868 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
869 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
870 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
872 if((crtc->lcd_gen_cntl & LCD_ON) &&
873 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
874 /* We cannot display the mode on the LCD. If the CRT is enabled
875 we can turn off the LCD.
876 If the CRT is off, it isn't a good idea to switch it on; we don't
877 know if one is connected. So it's better to fail then.
879 if (crtc->lcd_gen_cntl & CRT_ON) {
880 if (!(var->activate & FB_ACTIVATE_TEST))
881 PRINTKI("Disable LCD panel, because video mode does not fit.\n");
882 crtc->lcd_gen_cntl &= ~LCD_ON;
883 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
885 if (!(var->activate & FB_ACTIVATE_TEST))
886 PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
892 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
894 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
895 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
896 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
898 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
900 /* This is horror! When we simulate, say 640x480 on an 800x600
901 LCD monitor, the CRTC should be programmed 800x600 values for
902 the non visible part, but 640x480 for the visible part.
903 This code has been tested on a laptop with it's 1400x1050 LCD
904 monitor and a conventional monitor both switched on.
905 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
906 works with little glitches also with DOUBLESCAN modes
908 if (yres < par->lcd_height) {
909 VScan = par->lcd_height / yres;
912 vmode |= FB_VMODE_DOUBLE;
916 h_sync_strt = h_disp + par->lcd_right_margin;
917 h_sync_end = h_sync_strt + par->lcd_hsync_len;
918 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
919 h_total = h_disp + par->lcd_hblank_len;
921 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
922 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
923 v_total = v_disp + par->lcd_vblank_len / VScan;
925 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
927 h_disp = (h_disp >> 3) - 1;
928 h_sync_strt = (h_sync_strt >> 3) - 1;
929 h_sync_end = (h_sync_end >> 3) - 1;
930 h_total = (h_total >> 3) - 1;
931 h_sync_wid = h_sync_end - h_sync_strt;
933 FAIL_MAX("h_disp too large", h_disp, 0xff);
934 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
935 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
936 if(h_sync_wid > 0x1f)
938 FAIL_MAX("h_total too large", h_total, 0x1ff);
940 if (vmode & FB_VMODE_DOUBLE) {
948 #ifdef CONFIG_FB_ATY_GENERIC_LCD
949 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
950 vdisplay = par->lcd_height;
957 v_sync_wid = v_sync_end - v_sync_strt;
959 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
960 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
961 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
962 if(v_sync_wid > 0x1f)
964 FAIL_MAX("v_total too large", v_total, 0x7ff);
966 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
971 crtc->xoffset = xoffset;
972 crtc->yoffset = yoffset;
974 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
975 crtc->vline_crnt_vline = 0;
977 crtc->h_tot_disp = h_total | (h_disp<<16);
978 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
979 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
980 crtc->v_tot_disp = v_total | (v_disp<<16);
981 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
983 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
984 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
985 crtc->gen_cntl |= CRTC_VGA_LINEAR;
987 /* Enable doublescan mode if requested */
988 if (vmode & FB_VMODE_DOUBLE)
989 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
990 /* Enable interlaced mode if requested */
991 if (vmode & FB_VMODE_INTERLACED)
992 crtc->gen_cntl |= CRTC_INTERLACE_EN;
993 #ifdef CONFIG_FB_ATY_GENERIC_LCD
994 if (par->lcd_table != 0) {
996 if(vmode & FB_VMODE_DOUBLE)
998 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
999 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
1000 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
1001 USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
1002 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
1004 /* MOBILITY M1 tested, FIXME: LT */
1005 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1006 if (!M64_HAS(LT_LCD_REGS))
1007 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1008 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1010 crtc->horz_stretching &=
1011 ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1012 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1013 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1016 * The horizontal blender misbehaves when HDisplay is less than a
1017 * a certain threshold (440 for a 1024-wide panel). It doesn't
1018 * stretch such modes enough. Use pixel replication instead of
1019 * blending to stretch modes that can be made to exactly fit the
1020 * panel width. The undocumented "NoLCDBlend" option allows the
1021 * pixel-replicated mode to be slightly wider or narrower than the
1022 * panel width. It also causes a mode that is exactly half as wide
1023 * as the panel to be pixel-replicated, rather than blended.
1025 int HDisplay = xres & ~7;
1026 int nStretch = par->lcd_width / HDisplay;
1027 int Remainder = par->lcd_width % HDisplay;
1029 if ((!Remainder && ((nStretch > 2))) ||
1030 (((HDisplay * 16) / par->lcd_width) < 7)) {
1031 static const char StretchLoops[] = {10, 12, 13, 15, 16};
1032 int horz_stretch_loop = -1, BestRemainder;
1033 int Numerator = HDisplay, Denominator = par->lcd_width;
1035 ATIReduceRatio(&Numerator, &Denominator);
1037 BestRemainder = (Numerator * 16) / Denominator;
1038 while (--Index >= 0) {
1039 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1041 if (Remainder < BestRemainder) {
1042 horz_stretch_loop = Index;
1043 if (!(BestRemainder = Remainder))
1048 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1049 int horz_stretch_ratio = 0, Accumulator = 0;
1050 int reuse_previous = 1;
1052 Index = StretchLoops[horz_stretch_loop];
1054 while (--Index >= 0) {
1055 if (Accumulator > 0)
1056 horz_stretch_ratio |= reuse_previous;
1058 Accumulator += Denominator;
1059 Accumulator -= Numerator;
1060 reuse_previous <<= 1;
1063 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1064 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1065 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1066 break; /* Out of the do { ... } while (0) */
1070 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1071 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1075 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1076 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1077 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1079 if (!M64_HAS(LT_LCD_REGS) &&
1080 xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1081 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1084 * Don't use vertical blending if the mode is too wide or not
1085 * vertically stretched.
1087 crtc->vert_stretching = 0;
1089 /* copy to shadow crtc */
1090 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1091 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1092 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1093 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1095 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1097 if (M64_HAS(MAGIC_FIFO)) {
1098 /* FIXME: display FIFO low watermark values */
1099 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1101 crtc->dp_pix_width = dp_pix_width;
1102 crtc->dp_chain_mask = dp_chain_mask;
1107 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1109 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1110 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1112 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1114 u32 double_scan, interlace;
1117 h_total = crtc->h_tot_disp & 0x1ff;
1118 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1119 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1120 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1121 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1122 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1123 v_total = crtc->v_tot_disp & 0x7ff;
1124 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1125 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1126 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1127 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1128 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1129 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1130 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1131 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1134 xres = (h_disp + 1) * 8;
1136 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1137 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1138 hslen = h_sync_wid * 8;
1139 upper = v_total - v_sync_strt - v_sync_wid;
1140 lower = v_sync_strt - v_disp;
1142 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1143 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1144 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1146 switch (pix_width) {
1148 case CRTC_PIX_WIDTH_4BPP:
1150 var->red.offset = 0;
1151 var->red.length = 8;
1152 var->green.offset = 0;
1153 var->green.length = 8;
1154 var->blue.offset = 0;
1155 var->blue.length = 8;
1156 var->transp.offset = 0;
1157 var->transp.length = 0;
1160 case CRTC_PIX_WIDTH_8BPP:
1162 var->red.offset = 0;
1163 var->red.length = 8;
1164 var->green.offset = 0;
1165 var->green.length = 8;
1166 var->blue.offset = 0;
1167 var->blue.length = 8;
1168 var->transp.offset = 0;
1169 var->transp.length = 0;
1171 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1173 var->red.offset = 10;
1174 var->red.length = 5;
1175 var->green.offset = 5;
1176 var->green.length = 5;
1177 var->blue.offset = 0;
1178 var->blue.length = 5;
1179 var->transp.offset = 0;
1180 var->transp.length = 0;
1182 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1184 var->red.offset = 11;
1185 var->red.length = 5;
1186 var->green.offset = 5;
1187 var->green.length = 6;
1188 var->blue.offset = 0;
1189 var->blue.length = 5;
1190 var->transp.offset = 0;
1191 var->transp.length = 0;
1193 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1195 var->red.offset = 16;
1196 var->red.length = 8;
1197 var->green.offset = 8;
1198 var->green.length = 8;
1199 var->blue.offset = 0;
1200 var->blue.length = 8;
1201 var->transp.offset = 0;
1202 var->transp.length = 0;
1204 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1206 var->red.offset = 16;
1207 var->red.length = 8;
1208 var->green.offset = 8;
1209 var->green.length = 8;
1210 var->blue.offset = 0;
1211 var->blue.length = 8;
1212 var->transp.offset = 24;
1213 var->transp.length = 8;
1216 PRINTKE("Invalid pixel width\n");
1223 var->xres_virtual = crtc->vxres;
1224 var->yres_virtual = crtc->vyres;
1225 var->bits_per_pixel = bpp;
1226 var->left_margin = left;
1227 var->right_margin = right;
1228 var->upper_margin = upper;
1229 var->lower_margin = lower;
1230 var->hsync_len = hslen;
1231 var->vsync_len = vslen;
1233 var->vmode = FB_VMODE_NONINTERLACED;
1234 /* In double scan mode, the vertical parameters are doubled, so we need to
1235 half them to get the right values.
1236 In interlaced mode the values are already correct, so no correction is
1240 var->vmode = FB_VMODE_INTERLACED;
1243 var->vmode = FB_VMODE_DOUBLE;
1245 var->upper_margin>>=1;
1246 var->lower_margin>>=1;
1253 /* ------------------------------------------------------------------------- */
1255 static int atyfb_set_par(struct fb_info *info)
1257 struct atyfb_par *par = (struct atyfb_par *) info->par;
1258 struct fb_var_screeninfo *var = &info->var;
1262 struct fb_var_screeninfo debug;
1268 if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1271 pixclock = atyfb_get_pixclock(var, par);
1273 if (pixclock == 0) {
1274 PRINTKE("Invalid pixclock\n");
1277 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1281 par->accel_flags = var->accel_flags; /* hack */
1283 if (var->accel_flags) {
1284 info->fbops->fb_sync = atyfb_sync;
1285 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1287 info->fbops->fb_sync = NULL;
1288 info->flags |= FBINFO_HWACCEL_DISABLED;
1291 if (par->blitter_may_be_busy)
1294 aty_set_crtc(par, &par->crtc);
1295 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1296 par->pll_ops->set_pll(info, &par->pll);
1299 if(par->pll_ops && par->pll_ops->pll_to_var)
1300 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1304 if(0 == pixclock_in_ps) {
1305 PRINTKE("ALERT ops->pll_to_var get 0\n");
1306 pixclock_in_ps = pixclock;
1309 memset(&debug, 0, sizeof(debug));
1310 if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1311 u32 hSync, vRefresh;
1312 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1313 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1315 h_disp = debug.xres;
1316 h_sync_strt = h_disp + debug.right_margin;
1317 h_sync_end = h_sync_strt + debug.hsync_len;
1318 h_total = h_sync_end + debug.left_margin;
1319 v_disp = debug.yres;
1320 v_sync_strt = v_disp + debug.lower_margin;
1321 v_sync_end = v_sync_strt + debug.vsync_len;
1322 v_total = v_sync_end + debug.upper_margin;
1324 hSync = 1000000000 / (pixclock_in_ps * h_total);
1325 vRefresh = (hSync * 1000) / v_total;
1326 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1328 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1331 DPRINTK("atyfb_set_par\n");
1332 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1333 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1334 var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1335 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps);
1336 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1337 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1338 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1339 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1340 h_disp, h_sync_strt, h_sync_end, h_total,
1341 v_disp, v_sync_strt, v_sync_end, v_total);
1342 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1344 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1345 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1349 if (!M64_HAS(INTEGRATED)) {
1350 /* Don't forget MEM_CNTL */
1351 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1352 switch (var->bits_per_pixel) {
1363 aty_st_le32(MEM_CNTL, tmp, par);
1365 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1366 if (!M64_HAS(MAGIC_POSTDIV))
1367 tmp |= par->mem_refresh_rate << 20;
1368 switch (var->bits_per_pixel) {
1380 if (M64_HAS(CT_BUS)) {
1381 aty_st_le32(DAC_CNTL, 0x87010184, par);
1382 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1383 } else if (M64_HAS(VT_BUS)) {
1384 aty_st_le32(DAC_CNTL, 0x87010184, par);
1385 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1386 } else if (M64_HAS(MOBIL_BUS)) {
1387 aty_st_le32(DAC_CNTL, 0x80010102, par);
1388 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1391 aty_st_le32(DAC_CNTL, 0x86010102, par);
1392 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1393 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1395 aty_st_le32(MEM_CNTL, tmp, par);
1397 aty_st_8(DAC_MASK, 0xff, par);
1399 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1400 info->fix.visual = var->bits_per_pixel <= 8 ?
1401 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1403 /* Initialize the graphics engine */
1404 if (par->accel_flags & FB_ACCELF_TEXT)
1405 aty_init_engine(par, info);
1407 #ifdef CONFIG_BOOTX_TEXT
1408 btext_update_display(info->fix.smem_start,
1409 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1410 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1411 var->bits_per_pixel,
1412 par->crtc.vxres * var->bits_per_pixel / 8);
1413 #endif /* CONFIG_BOOTX_TEXT */
1415 /* switch to accelerator mode */
1416 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1417 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1421 /* dump non shadow CRTC, pll, LCD registers */
1424 /* CRTC registers */
1426 printk("debug atyfb: Mach64 non-shadow register values:");
1427 for (i = 0; i < 256; i = i+4) {
1428 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1429 printk(" %08X", aty_ld_le32(i, par));
1433 #ifdef CONFIG_FB_ATY_CT
1436 printk("debug atyfb: Mach64 PLL register values:");
1437 for (i = 0; i < 64; i++) {
1438 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1439 if(i%4 == 0) printk(" ");
1440 printk("%02X", aty_ld_pll_ct(i, par));
1443 #endif /* CONFIG_FB_ATY_CT */
1445 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1446 if (par->lcd_table != 0) {
1449 printk("debug atyfb: LCD register values:");
1450 if(M64_HAS(LT_LCD_REGS)) {
1451 for(i = 0; i <= POWER_MANAGEMENT; i++) {
1452 if(i == EXT_VERT_STRETCH)
1454 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1455 printk(" %08X", aty_ld_lcd(i, par));
1459 for (i = 0; i < 64; i++) {
1460 if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1461 printk(" %08X", aty_ld_lcd(i, par));
1466 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1472 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1474 struct atyfb_par *par = (struct atyfb_par *) info->par;
1480 memcpy(&pll, &(par->pll), sizeof(pll));
1482 if((err = aty_var_to_crtc(info, var, &crtc)))
1485 pixclock = atyfb_get_pixclock(var, par);
1487 if (pixclock == 0) {
1488 if (!(var->activate & FB_ACTIVATE_TEST))
1489 PRINTKE("Invalid pixclock\n");
1492 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1496 if (var->accel_flags & FB_ACCELF_TEXT)
1497 info->var.accel_flags = FB_ACCELF_TEXT;
1499 info->var.accel_flags = 0;
1501 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1502 if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1505 aty_crtc_to_var(&crtc, var);
1506 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1510 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1512 u32 xoffset = info->var.xoffset;
1513 u32 yoffset = info->var.yoffset;
1514 u32 vxres = par->crtc.vxres;
1515 u32 bpp = info->var.bits_per_pixel;
1517 par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1522 * Open/Release the frame buffer device
1525 static int atyfb_open(struct fb_info *info, int user)
1527 struct atyfb_par *par = (struct atyfb_par *) info->par;
1538 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1540 struct atyfb_par *par = dev_id;
1544 spin_lock(&par->int_lock);
1546 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1548 if (int_cntl & CRTC_VBLANK_INT) {
1549 /* clear interrupt */
1550 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1551 par->vblank.count++;
1552 if (par->vblank.pan_display) {
1553 par->vblank.pan_display = 0;
1554 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1556 wake_up_interruptible(&par->vblank.wait);
1560 spin_unlock(&par->int_lock);
1562 return IRQ_RETVAL(handled);
1565 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1569 if (!test_and_set_bit(0, &par->irq_flags)) {
1570 if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
1571 clear_bit(0, &par->irq_flags);
1574 spin_lock_irq(&par->int_lock);
1575 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1576 /* clear interrupt */
1577 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1578 /* enable interrupt */
1579 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1580 spin_unlock_irq(&par->int_lock);
1581 } else if (reenable) {
1582 spin_lock_irq(&par->int_lock);
1583 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1584 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1585 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1586 /* re-enable interrupt */
1587 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1589 spin_unlock_irq(&par->int_lock);
1595 static int aty_disable_irq(struct atyfb_par *par)
1599 if (test_and_clear_bit(0, &par->irq_flags)) {
1600 if (par->vblank.pan_display) {
1601 par->vblank.pan_display = 0;
1602 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1604 spin_lock_irq(&par->int_lock);
1605 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1606 /* disable interrupt */
1607 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1608 spin_unlock_irq(&par->int_lock);
1609 free_irq(par->irq, par);
1615 static int atyfb_release(struct fb_info *info, int user)
1617 struct atyfb_par *par = (struct atyfb_par *) info->par;
1624 int was_mmaped = par->mmaped;
1629 struct fb_var_screeninfo var;
1631 /* Now reset the default display config, we have no
1632 * idea what the program(s) which mmap'd the chip did
1633 * to the configuration, nor whether it restored it
1638 var.accel_flags &= ~FB_ACCELF_TEXT;
1640 var.accel_flags |= FB_ACCELF_TEXT;
1641 if (var.yres == var.yres_virtual) {
1642 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1643 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1644 if (var.yres_virtual < var.yres)
1645 var.yres_virtual = var.yres;
1649 aty_disable_irq(par);
1656 * Pan or Wrap the Display
1658 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1661 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1663 struct atyfb_par *par = (struct atyfb_par *) info->par;
1664 u32 xres, yres, xoffset, yoffset;
1666 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1667 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1668 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1670 xoffset = (var->xoffset + 7) & ~7;
1671 yoffset = var->yoffset;
1672 if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1674 info->var.xoffset = xoffset;
1675 info->var.yoffset = yoffset;
1679 set_off_pitch(par, info);
1680 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1681 par->vblank.pan_display = 1;
1683 par->vblank.pan_display = 0;
1684 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1690 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1692 struct aty_interrupt *vbl;
1704 ret = aty_enable_irq(par, 0);
1709 ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1714 aty_enable_irq(par, 1);
1723 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1724 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1730 u8 mclk_post_div; /* 1,2,3,4,8 */
1731 u8 mclk_fb_mult; /* 2 or 4 */
1732 u8 xclk_post_div; /* 1,2,3,4,8 */
1734 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1735 u32 dsp_xclks_per_row; /* 0-16383 */
1736 u32 dsp_loop_latency; /* 0-15 */
1737 u32 dsp_precision; /* 0-7 */
1738 u32 dsp_on; /* 0-2047 */
1739 u32 dsp_off; /* 0-2047 */
1742 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1743 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1746 #ifndef FBIO_WAITFORVSYNC
1747 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1750 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1752 struct atyfb_par *par = (struct atyfb_par *) info->par;
1754 struct fbtype fbtyp;
1760 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1761 fbtyp.fb_width = par->crtc.vxres;
1762 fbtyp.fb_height = par->crtc.vyres;
1763 fbtyp.fb_depth = info->var.bits_per_pixel;
1764 fbtyp.fb_cmsize = info->cmap.len;
1765 fbtyp.fb_size = info->fix.smem_len;
1766 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1769 #endif /* __sparc__ */
1771 case FBIO_WAITFORVSYNC:
1775 if (get_user(crtc, (__u32 __user *) arg))
1778 return aty_waitforvblank(par, crtc);
1782 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1784 if (M64_HAS(INTEGRATED)) {
1786 union aty_pll *pll = &(par->pll);
1787 u32 dsp_config = pll->ct.dsp_config;
1788 u32 dsp_on_off = pll->ct.dsp_on_off;
1789 clk.ref_clk_per = par->ref_clk_per;
1790 clk.pll_ref_div = pll->ct.pll_ref_div;
1791 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1792 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1793 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1794 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1795 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1796 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1797 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1798 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1799 clk.dsp_precision = (dsp_config >> 20) & 7;
1800 clk.dsp_off = dsp_on_off & 0x7ff;
1801 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1802 if (copy_to_user((struct atyclk __user *) arg, &clk,
1809 if (M64_HAS(INTEGRATED)) {
1811 union aty_pll *pll = &(par->pll);
1812 if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1814 par->ref_clk_per = clk.ref_clk_per;
1815 pll->ct.pll_ref_div = clk.pll_ref_div;
1816 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1817 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1818 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1819 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1820 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1821 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1822 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1823 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1824 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1825 /*aty_calc_pll_ct(info, &pll->ct);*/
1826 aty_set_pll_ct(info, pll);
1831 if (get_user(par->features, (u32 __user *) arg))
1835 if (put_user(par->features, (u32 __user *) arg))
1838 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1845 static int atyfb_sync(struct fb_info *info)
1847 struct atyfb_par *par = (struct atyfb_par *) info->par;
1849 if (par->blitter_may_be_busy)
1855 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1857 struct atyfb_par *par = (struct atyfb_par *) info->par;
1858 unsigned int size, page, map_size = 0;
1859 unsigned long map_offset = 0;
1866 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1869 off = vma->vm_pgoff << PAGE_SHIFT;
1870 size = vma->vm_end - vma->vm_start;
1872 /* To stop the swapper from even considering these pages. */
1873 vma->vm_flags |= (VM_IO | VM_RESERVED);
1875 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1876 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1877 off += 0x8000000000000000UL;
1879 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1881 /* Each page, see which map applies */
1882 for (page = 0; page < size;) {
1884 for (i = 0; par->mmap_map[i].size; i++) {
1885 unsigned long start = par->mmap_map[i].voff;
1886 unsigned long end = start + par->mmap_map[i].size;
1887 unsigned long offset = off + page;
1894 map_size = par->mmap_map[i].size - (offset - start);
1896 par->mmap_map[i].poff + (offset - start);
1903 if (page + map_size > size)
1904 map_size = size - page;
1906 pgprot_val(vma->vm_page_prot) &=
1907 ~(par->mmap_map[i].prot_mask);
1908 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1910 if (remap_pfn_range(vma, vma->vm_start + page,
1911 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1932 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1936 for (i = 0; i < 256; i++) {
1937 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1938 if (M64_HAS(EXTRA_BRIGHT))
1940 aty_st_8(DAC_CNTL, tmp, par);
1941 aty_st_8(DAC_MASK, 0xff, par);
1943 writeb(i, &par->aty_cmap_regs->rindex);
1944 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1945 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1946 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1947 writeb(i, &par->aty_cmap_regs->windex);
1948 writeb(atyfb_save.r[1 - enter][i],
1949 &par->aty_cmap_regs->lut);
1950 writeb(atyfb_save.g[1 - enter][i],
1951 &par->aty_cmap_regs->lut);
1952 writeb(atyfb_save.b[1 - enter][i],
1953 &par->aty_cmap_regs->lut);
1957 static void atyfb_palette(int enter)
1959 struct atyfb_par *par;
1960 struct fb_info *info;
1963 for (i = 0; i < FB_MAX; i++) {
1964 info = registered_fb[i];
1965 if (info && info->fbops == &atyfb_ops) {
1966 par = (struct atyfb_par *) info->par;
1968 atyfb_save_palette(par, enter);
1970 atyfb_save.yoffset = info->var.yoffset;
1971 info->var.yoffset = 0;
1972 set_off_pitch(par, info);
1974 info->var.yoffset = atyfb_save.yoffset;
1975 set_off_pitch(par, info);
1977 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1982 #endif /* __sparc__ */
1986 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1988 /* Power management routines. Those are used for PowerBook sleep.
1990 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1995 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1996 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1997 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1998 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2004 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2005 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2007 pm &= ~(PWR_BLON | AUTO_PWR_UP);
2009 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2010 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2013 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2015 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2017 if ((--timeout) == 0)
2019 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2023 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2024 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2027 pm |= (PWR_BLON | AUTO_PWR_UP);
2028 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2029 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2032 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2034 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2036 if ((--timeout) == 0)
2038 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2042 return timeout ? 0 : -EIO;
2045 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2047 struct fb_info *info = pci_get_drvdata(pdev);
2048 struct atyfb_par *par = (struct atyfb_par *) info->par;
2050 #ifndef CONFIG_PPC_PMAC
2051 /* HACK ALERT ! Once I find a proper way to say to each driver
2052 * individually what will happen with it's PCI slot, I'll change
2053 * that. On laptops, the AGP slot is just unclocked, so D2 is
2054 * expected, while on desktops, the card is powered off
2057 #endif /* CONFIG_PPC_PMAC */
2059 if (state.event == pdev->dev.power.power_state.event)
2062 acquire_console_sem();
2064 fb_set_suspend(info, 1);
2066 /* Idle & reset engine */
2068 aty_reset_engine(par);
2070 /* Blank display and LCD */
2071 atyfb_blank(FB_BLANK_POWERDOWN, info);
2074 par->lock_blank = 1;
2076 /* Set chip to "suspend" mode */
2077 if (aty_power_mgmt(1, par)) {
2079 par->lock_blank = 0;
2080 atyfb_blank(FB_BLANK_UNBLANK, info);
2081 fb_set_suspend(info, 0);
2082 release_console_sem();
2086 release_console_sem();
2088 pdev->dev.power.power_state = state;
2093 static int atyfb_pci_resume(struct pci_dev *pdev)
2095 struct fb_info *info = pci_get_drvdata(pdev);
2096 struct atyfb_par *par = (struct atyfb_par *) info->par;
2098 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2101 acquire_console_sem();
2103 if (pdev->dev.power.power_state.event == 2)
2104 aty_power_mgmt(0, par);
2107 /* Restore display */
2108 atyfb_set_par(info);
2111 fb_set_suspend(info, 0);
2114 par->lock_blank = 0;
2115 atyfb_blank(FB_BLANK_UNBLANK, info);
2117 release_console_sem();
2119 pdev->dev.power.power_state = PMSG_ON;
2124 #endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2127 #ifdef CONFIG_FB_ATY_BACKLIGHT
2128 #define MAX_LEVEL 0xFF
2130 static struct backlight_properties aty_bl_data;
2132 /* Call with fb_info->bl_mutex held */
2133 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2135 struct fb_info *info = pci_get_drvdata(par->pdev);
2138 /* Get and convert the value */
2139 atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2143 else if (atylevel > MAX_LEVEL)
2144 atylevel = MAX_LEVEL;
2149 /* Call with fb_info->bl_mutex held */
2150 static int __aty_bl_update_status(struct backlight_device *bd)
2152 struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2153 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2156 if (bd->props->power != FB_BLANK_UNBLANK ||
2157 bd->props->fb_blank != FB_BLANK_UNBLANK)
2160 level = bd->props->brightness;
2162 reg |= (BLMOD_EN | BIASMOD_EN);
2164 reg &= ~BIAS_MOD_LEVEL_MASK;
2165 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2167 reg &= ~BIAS_MOD_LEVEL_MASK;
2168 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2170 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2175 static int aty_bl_update_status(struct backlight_device *bd)
2177 struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2178 struct fb_info *info = pci_get_drvdata(par->pdev);
2181 mutex_lock(&info->bl_mutex);
2182 ret = __aty_bl_update_status(bd);
2183 mutex_unlock(&info->bl_mutex);
2188 static int aty_bl_get_brightness(struct backlight_device *bd)
2190 return bd->props->brightness;
2193 static struct backlight_properties aty_bl_data = {
2194 .owner = THIS_MODULE,
2195 .get_brightness = aty_bl_get_brightness,
2196 .update_status = aty_bl_update_status,
2197 .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
2200 static void aty_bl_set_power(struct fb_info *info, int power)
2202 mutex_lock(&info->bl_mutex);
2205 down(&info->bl_dev->sem);
2206 info->bl_dev->props->power = power;
2207 __aty_bl_update_status(info->bl_dev);
2208 up(&info->bl_dev->sem);
2211 mutex_unlock(&info->bl_mutex);
2214 static void aty_bl_init(struct atyfb_par *par)
2216 struct fb_info *info = pci_get_drvdata(par->pdev);
2217 struct backlight_device *bd;
2220 #ifdef CONFIG_PMAC_BACKLIGHT
2221 if (!pmac_has_backlight_type("ati"))
2225 snprintf(name, sizeof(name), "atybl%d", info->node);
2227 bd = backlight_device_register(name, par, &aty_bl_data);
2229 info->bl_dev = NULL;
2230 printk(KERN_WARNING "aty: Backlight registration failed\n");
2234 mutex_lock(&info->bl_mutex);
2236 fb_bl_default_curve(info, 0,
2237 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2238 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2239 mutex_unlock(&info->bl_mutex);
2242 bd->props->brightness = aty_bl_data.max_brightness;
2243 bd->props->power = FB_BLANK_UNBLANK;
2244 bd->props->update_status(bd);
2247 #ifdef CONFIG_PMAC_BACKLIGHT
2248 mutex_lock(&pmac_backlight_mutex);
2249 if (!pmac_backlight)
2250 pmac_backlight = bd;
2251 mutex_unlock(&pmac_backlight_mutex);
2254 printk("aty: Backlight initialized (%s)\n", name);
2262 static void aty_bl_exit(struct atyfb_par *par)
2264 struct fb_info *info = pci_get_drvdata(par->pdev);
2266 #ifdef CONFIG_PMAC_BACKLIGHT
2267 mutex_lock(&pmac_backlight_mutex);
2270 mutex_lock(&info->bl_mutex);
2272 #ifdef CONFIG_PMAC_BACKLIGHT
2273 if (pmac_backlight == info->bl_dev)
2274 pmac_backlight = NULL;
2277 backlight_device_unregister(info->bl_dev);
2279 printk("aty: Backlight unloaded\n");
2281 mutex_unlock(&info->bl_mutex);
2283 #ifdef CONFIG_PMAC_BACKLIGHT
2284 mutex_unlock(&pmac_backlight_mutex);
2288 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2290 static void __devinit aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2292 const int ragepro_tbl[] = {
2293 44, 50, 55, 66, 75, 80, 100
2295 const int ragexl_tbl[] = {
2296 50, 66, 75, 83, 90, 95, 100, 105,
2297 110, 115, 120, 125, 133, 143, 166
2299 const int *refresh_tbl;
2302 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2303 refresh_tbl = ragexl_tbl;
2304 size = ARRAY_SIZE(ragexl_tbl);
2306 refresh_tbl = ragepro_tbl;
2307 size = ARRAY_SIZE(ragepro_tbl);
2310 for (i=0; i < size; i++) {
2311 if (xclk < refresh_tbl[i])
2314 par->mem_refresh_rate = i;
2321 static struct fb_info *fb_list = NULL;
2323 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2324 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2325 struct fb_var_screeninfo *var)
2329 if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2331 var->xres = var->xres_virtual = par->lcd_hdisp;
2332 var->right_margin = par->lcd_right_margin;
2333 var->left_margin = par->lcd_hblank_len -
2334 (par->lcd_right_margin + par->lcd_hsync_dly +
2335 par->lcd_hsync_len);
2336 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2337 var->yres = var->yres_virtual = par->lcd_vdisp;
2338 var->lower_margin = par->lcd_lower_margin;
2339 var->upper_margin = par->lcd_vblank_len -
2340 (par->lcd_lower_margin + par->lcd_vsync_len);
2341 var->vsync_len = par->lcd_vsync_len;
2342 var->pixclock = par->lcd_pixclock;
2348 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2350 static int __devinit aty_init(struct fb_info *info, const char *name)
2352 struct atyfb_par *par = (struct atyfb_par *) info->par;
2353 const char *ramname = NULL, *xtal;
2354 int gtb_memsize, has_var = 0;
2355 struct fb_var_screeninfo var;
2358 #if defined(CONFIG_PPC)
2362 init_waitqueue_head(&par->vblank.wait);
2363 spin_lock_init(&par->int_lock);
2365 par->aty_cmap_regs =
2366 (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2368 #ifdef CONFIG_PPC_PMAC
2369 /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2370 * and set the frequency manually. */
2371 if (machine_is_compatible("PowerBook2,1")) {
2372 par->pll_limits.mclk = 70;
2373 par->pll_limits.xclk = 53;
2377 par->pll_limits.pll_max = pll;
2379 par->pll_limits.mclk = mclk;
2381 par->pll_limits.xclk = xclk;
2383 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2384 par->pll_per = 1000000/par->pll_limits.pll_max;
2385 par->mclk_per = 1000000/par->pll_limits.mclk;
2386 par->xclk_per = 1000000/par->pll_limits.xclk;
2388 par->ref_clk_per = 1000000000000ULL / 14318180;
2391 #ifdef CONFIG_FB_ATY_GX
2392 if (!M64_HAS(INTEGRATED)) {
2394 u8 dac_type, dac_subtype, clk_type;
2395 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2396 par->bus_type = (stat0 >> 0) & 0x07;
2397 par->ram_type = (stat0 >> 3) & 0x07;
2398 ramname = aty_gx_ram[par->ram_type];
2399 /* FIXME: clockchip/RAMDAC probing? */
2400 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2402 clk_type = CLK_ATI18818_1;
2403 dac_type = (stat0 >> 9) & 0x07;
2404 if (dac_type == 0x07)
2405 dac_subtype = DAC_ATT20C408;
2407 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2409 dac_type = DAC_IBMRGB514;
2410 dac_subtype = DAC_IBMRGB514;
2411 clk_type = CLK_IBMRGB514;
2413 switch (dac_subtype) {
2415 par->dac_ops = &aty_dac_ibm514;
2417 case DAC_ATI68860_B:
2418 case DAC_ATI68860_C:
2419 par->dac_ops = &aty_dac_ati68860b;
2423 par->dac_ops = &aty_dac_att21c498;
2426 PRINTKI("aty_init: DAC type not implemented yet!\n");
2427 par->dac_ops = &aty_dac_unsupported;
2432 case CLK_ATI18818_1:
2433 par->pll_ops = &aty_pll_ati18818_1;
2437 par->pll_ops = &aty_pll_ibm514;
2440 #if 0 /* dead code */
2442 par->pll_ops = &aty_pll_stg1703;
2445 par->pll_ops = &aty_pll_ch8398;
2448 par->pll_ops = &aty_pll_att20c408;
2452 PRINTKI("aty_init: CLK type not implemented yet!");
2453 par->pll_ops = &aty_pll_unsupported;
2457 #endif /* CONFIG_FB_ATY_GX */
2458 #ifdef CONFIG_FB_ATY_CT
2459 if (M64_HAS(INTEGRATED)) {
2460 par->dac_ops = &aty_dac_ct;
2461 par->pll_ops = &aty_pll_ct;
2462 par->bus_type = PCI;
2463 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2464 ramname = aty_ct_ram[par->ram_type];
2465 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2466 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2467 par->pll_limits.mclk = 63;
2470 if (M64_HAS(GTB_DSP)
2471 && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2473 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2474 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2479 if (diff2 < diff1) {
2480 par->ref_clk_per = 1000000000000ULL / 29498928;
2484 #endif /* CONFIG_FB_ATY_CT */
2486 /* save previous video mode */
2487 aty_get_crtc(par, &saved_crtc);
2488 if(par->pll_ops->get_pll)
2489 par->pll_ops->get_pll(info, &saved_pll);
2491 i = aty_ld_le32(MEM_CNTL, par);
2492 gtb_memsize = M64_HAS(GTB_DSP);
2494 switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2496 info->fix.smem_len = 0x80000;
2499 info->fix.smem_len = 0x100000;
2501 case MEM_SIZE_2M_GTB:
2502 info->fix.smem_len = 0x200000;
2504 case MEM_SIZE_4M_GTB:
2505 info->fix.smem_len = 0x400000;
2507 case MEM_SIZE_6M_GTB:
2508 info->fix.smem_len = 0x600000;
2510 case MEM_SIZE_8M_GTB:
2511 info->fix.smem_len = 0x800000;
2514 info->fix.smem_len = 0x80000;
2516 switch (i & MEM_SIZE_ALIAS) {
2518 info->fix.smem_len = 0x80000;
2521 info->fix.smem_len = 0x100000;
2524 info->fix.smem_len = 0x200000;
2527 info->fix.smem_len = 0x400000;
2530 info->fix.smem_len = 0x600000;
2533 info->fix.smem_len = 0x800000;
2536 info->fix.smem_len = 0x80000;
2539 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2540 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2541 info->fix.smem_len += 0x400000;
2545 info->fix.smem_len = vram * 1024;
2546 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2547 if (info->fix.smem_len <= 0x80000)
2549 else if (info->fix.smem_len <= 0x100000)
2551 else if (info->fix.smem_len <= 0x200000)
2552 i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2553 else if (info->fix.smem_len <= 0x400000)
2554 i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2555 else if (info->fix.smem_len <= 0x600000)
2556 i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2558 i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2559 aty_st_le32(MEM_CNTL, i, par);
2563 * Reg Block 0 (CT-compatible block) is at mmio_start
2564 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2567 info->fix.mmio_len = 0x400;
2568 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2569 } else if (M64_HAS(CT)) {
2570 info->fix.mmio_len = 0x400;
2571 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2572 } else if (M64_HAS(VT)) {
2573 info->fix.mmio_start -= 0x400;
2574 info->fix.mmio_len = 0x800;
2575 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2577 info->fix.mmio_start -= 0x400;
2578 info->fix.mmio_len = 0x800;
2579 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2582 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2583 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2584 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2585 par->pll_limits.mclk, par->pll_limits.xclk);
2587 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2588 if (M64_HAS(INTEGRATED)) {
2590 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2591 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2592 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n"
2594 aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2595 aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2596 aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2597 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2598 for (i = 0; i < 40; i++)
2599 printk(" %02x", aty_ld_pll_ct(i, par));
2603 if(par->pll_ops->init_pll)
2604 par->pll_ops->init_pll(info, &par->pll);
2607 * Last page of 8 MB (4 MB on ISA) aperture is MMIO
2608 * FIXME: we should use the auxiliary aperture instead so we can access
2609 * the full 8 MB of video RAM on 8 MB boards
2612 if (!par->aux_start &&
2613 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2614 info->fix.smem_len -= GUI_RESERVE;
2617 * Disable register access through the linear aperture
2618 * if the auxiliary aperture is used so we can access
2619 * the full 8 MB of video RAM on 8 MB boards.
2622 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2625 par->mtrr_aper = -1;
2628 /* Cover the whole resource. */
2629 par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2630 if (par->mtrr_aper >= 0 && !par->aux_start) {
2631 /* Make a hole for mmio. */
2632 par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2633 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2634 if (par->mtrr_reg < 0) {
2635 mtrr_del(par->mtrr_aper, 0, 0);
2636 par->mtrr_aper = -1;
2642 info->fbops = &atyfb_ops;
2643 info->pseudo_palette = pseudo_palette;
2644 info->flags = FBINFO_DEFAULT |
2645 FBINFO_HWACCEL_IMAGEBLIT |
2646 FBINFO_HWACCEL_FILLRECT |
2647 FBINFO_HWACCEL_COPYAREA |
2648 FBINFO_HWACCEL_YPAN;
2650 #ifdef CONFIG_PMAC_BACKLIGHT
2651 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2652 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2653 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2654 | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2657 if (M64_HAS(MOBIL_BUS)) {
2658 #ifdef CONFIG_FB_ATY_BACKLIGHT
2663 memset(&var, 0, sizeof(var));
2665 if (machine_is(powermac)) {
2667 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2668 * applies to all Mac video cards
2671 if (mac_find_mode(&var, info, mode, 8))
2674 if (default_vmode == VMODE_CHOOSE) {
2675 if (M64_HAS(G3_PB_1024x768))
2676 /* G3 PowerBook with 1024x768 LCD */
2677 default_vmode = VMODE_1024_768_60;
2678 else if (machine_is_compatible("iMac"))
2679 default_vmode = VMODE_1024_768_75;
2680 else if (machine_is_compatible
2682 /* iBook with 800x600 LCD */
2683 default_vmode = VMODE_800_600_60;
2685 default_vmode = VMODE_640_480_67;
2686 sense = read_aty_sense(par);
2687 PRINTKI("monitor sense=%x, mode %d\n",
2688 sense, mac_map_monitor_sense(sense));
2690 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2691 default_vmode = VMODE_640_480_60;
2692 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2693 default_cmode = CMODE_8;
2694 if (!mac_vmode_to_var(default_vmode, default_cmode,
2700 #endif /* !CONFIG_PPC */
2702 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2703 if (!atyfb_get_timings_from_lcd(par, &var))
2707 if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2714 var.accel_flags &= ~FB_ACCELF_TEXT;
2716 var.accel_flags |= FB_ACCELF_TEXT;
2718 if (comp_sync != -1) {
2720 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2722 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2725 if (var.yres == var.yres_virtual) {
2726 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2727 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2728 if (var.yres_virtual < var.yres)
2729 var.yres_virtual = var.yres;
2732 if (atyfb_check_var(&var, info)) {
2733 PRINTKE("can't set default video mode\n");
2738 atyfb_save_palette(par, 0);
2741 #ifdef CONFIG_FB_ATY_CT
2742 if (!noaccel && M64_HAS(INTEGRATED))
2743 aty_init_cursor(info);
2744 #endif /* CONFIG_FB_ATY_CT */
2747 fb_alloc_cmap(&info->cmap, 256, 0);
2749 if (register_framebuffer(info) < 0)
2754 PRINTKI("fb%d: %s frame buffer device on %s\n",
2755 info->node, info->fix.id, name);
2759 /* restore video mode */
2760 aty_set_crtc(par, &saved_crtc);
2761 par->pll_ops->set_pll(info, &saved_pll);
2764 if (par->mtrr_reg >= 0) {
2765 mtrr_del(par->mtrr_reg, 0, 0);
2768 if (par->mtrr_aper >= 0) {
2769 mtrr_del(par->mtrr_aper, 0, 0);
2770 par->mtrr_aper = -1;
2777 static int __devinit store_video_par(char *video_str, unsigned char m64_num)
2780 unsigned long vmembase, size, guiregbase;
2782 PRINTKI("store_video_par() '%s' \n", video_str);
2784 if (!(p = strsep(&video_str, ";")) || !*p)
2785 goto mach64_invalid;
2786 vmembase = simple_strtoul(p, NULL, 0);
2787 if (!(p = strsep(&video_str, ";")) || !*p)
2788 goto mach64_invalid;
2789 size = simple_strtoul(p, NULL, 0);
2790 if (!(p = strsep(&video_str, ";")) || !*p)
2791 goto mach64_invalid;
2792 guiregbase = simple_strtoul(p, NULL, 0);
2794 phys_vmembase[m64_num] = vmembase;
2795 phys_size[m64_num] = size;
2796 phys_guiregbase[m64_num] = guiregbase;
2797 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2802 phys_vmembase[m64_num] = 0;
2805 #endif /* CONFIG_ATARI */
2808 * Blank the display.
2811 static int atyfb_blank(int blank, struct fb_info *info)
2813 struct atyfb_par *par = (struct atyfb_par *) info->par;
2816 if (par->lock_blank || par->asleep)
2819 #ifdef CONFIG_FB_ATY_BACKLIGHT
2820 if (machine_is(powermac) && blank > FB_BLANK_NORMAL)
2821 aty_bl_set_power(info, FB_BLANK_POWERDOWN);
2822 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2823 if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2824 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2825 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2827 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2831 gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2833 case FB_BLANK_UNBLANK:
2834 gen_cntl &= ~0x400004c;
2836 case FB_BLANK_NORMAL:
2837 gen_cntl |= 0x4000040;
2839 case FB_BLANK_VSYNC_SUSPEND:
2840 gen_cntl |= 0x4000048;
2842 case FB_BLANK_HSYNC_SUSPEND:
2843 gen_cntl |= 0x4000044;
2845 case FB_BLANK_POWERDOWN:
2846 gen_cntl |= 0x400004c;
2849 aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2851 #ifdef CONFIG_FB_ATY_BACKLIGHT
2852 if (machine_is(powermac) && blank <= FB_BLANK_NORMAL)
2853 aty_bl_set_power(info, FB_BLANK_UNBLANK);
2854 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2855 if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2856 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2857 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2859 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2866 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2867 const struct atyfb_par *par)
2870 out_8(&par->aty_cmap_regs->windex, regno);
2871 out_8(&par->aty_cmap_regs->lut, red);
2872 out_8(&par->aty_cmap_regs->lut, green);
2873 out_8(&par->aty_cmap_regs->lut, blue);
2875 writeb(regno, &par->aty_cmap_regs->windex);
2876 writeb(red, &par->aty_cmap_regs->lut);
2877 writeb(green, &par->aty_cmap_regs->lut);
2878 writeb(blue, &par->aty_cmap_regs->lut);
2883 * Set a single color register. The values supplied are already
2884 * rounded down to the hardware's capabilities (according to the
2885 * entries in the var structure). Return != 0 for invalid regno.
2886 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2889 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2890 u_int transp, struct fb_info *info)
2892 struct atyfb_par *par = (struct atyfb_par *) info->par;
2894 u32 *pal = info->pseudo_palette;
2896 depth = info->var.bits_per_pixel;
2898 depth = (info->var.green.length == 5) ? 15 : 16;
2904 (depth == 16 && regno > 63) ||
2905 (depth == 15 && regno > 31))
2912 par->palette[regno].red = red;
2913 par->palette[regno].green = green;
2914 par->palette[regno].blue = blue;
2919 pal[regno] = (regno << 10) | (regno << 5) | regno;
2922 pal[regno] = (regno << 11) | (regno << 5) | regno;
2925 pal[regno] = (regno << 16) | (regno << 8) | regno;
2928 i = (regno << 8) | regno;
2929 pal[regno] = (i << 16) | i;
2934 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2935 if (M64_HAS(EXTRA_BRIGHT))
2936 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2937 aty_st_8(DAC_CNTL, i, par);
2938 aty_st_8(DAC_MASK, 0xff, par);
2940 if (M64_HAS(INTEGRATED)) {
2943 aty_st_pal(regno << 3, red,
2944 par->palette[regno<<1].green,
2946 red = par->palette[regno>>1].red;
2947 blue = par->palette[regno>>1].blue;
2949 } else if (depth == 15) {
2951 for(i = 0; i < 8; i++) {
2952 aty_st_pal(regno + i, red, green, blue, par);
2956 aty_st_pal(regno, red, green, blue, par);
2965 extern void (*prom_palette) (int);
2967 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2968 struct fb_info *info, unsigned long addr)
2970 extern int con_is_present(void);
2972 struct atyfb_par *par = info->par;
2973 struct pcidev_cookie *pcp;
2975 int node, len, i, j, ret;
2978 /* Do not attach when we have a serial console. */
2979 if (!con_is_present())
2983 * Map memory-mapped registers.
2985 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2986 info->fix.mmio_start = addr + 0x7ffc00UL;
2989 * Map in big-endian aperture.
2991 info->screen_base = (char *) (addr + 0x800000UL);
2992 info->fix.smem_start = addr + 0x800000UL;
2995 * Figure mmap addresses from PCI config space.
2996 * Split Framebuffer in big- and little-endian halfs.
2998 for (i = 0; i < 6 && pdev->resource[i].start; i++)
3002 par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
3003 if (!par->mmap_map) {
3004 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
3007 memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
3009 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
3010 struct resource *rp = &pdev->resource[i];
3011 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
3017 io = (rp->flags & IORESOURCE_IO);
3019 size = rp->end - base + 1;
3021 pci_read_config_dword(pdev, breg, &pbase);
3027 * Map the framebuffer a second time, this time without
3028 * the braindead _PAGE_IE setting. This is used by the
3029 * fixed Xserver, but we need to maintain the old mapping
3030 * to stay compatible with older ones...
3033 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
3034 par->mmap_map[j].poff = base & PAGE_MASK;
3035 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3036 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3037 par->mmap_map[j].prot_flag = _PAGE_E;
3042 * Here comes the old framebuffer mapping with _PAGE_IE
3043 * set for the big endian half of the framebuffer...
3046 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
3047 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
3048 par->mmap_map[j].size = 0x800000;
3049 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3050 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
3055 par->mmap_map[j].voff = pbase & PAGE_MASK;
3056 par->mmap_map[j].poff = base & PAGE_MASK;
3057 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3058 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3059 par->mmap_map[j].prot_flag = _PAGE_E;
3063 if((ret = correct_chipset(par)))
3066 if (IS_XL(pdev->device)) {
3068 * Fix PROMs idea of MEM_CNTL settings...
3070 mem = aty_ld_le32(MEM_CNTL, par);
3071 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
3072 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
3073 switch (mem & 0x0f) {
3075 mem = (mem & ~(0x0f)) | 2;
3078 mem = (mem & ~(0x0f)) | 3;
3081 mem = (mem & ~(0x0f)) | 4;
3084 mem = (mem & ~(0x0f)) | 5;
3089 if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
3090 mem &= ~(0x00700000);
3092 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
3093 aty_st_le32(MEM_CNTL, mem, par);
3097 * If this is the console device, we will set default video
3098 * settings to what the PROM left us with.
3100 node = prom_getchild(prom_root_node);
3101 node = prom_searchsiblings(node, "aliases");
3103 len = prom_getproperty(node, "screen", prop, sizeof(prop));
3106 node = prom_finddevice(prop);
3111 pcp = pdev->sysdata;
3112 if (node == pcp->prom_node->node) {
3113 struct fb_var_screeninfo *var = &default_var;
3114 unsigned int N, P, Q, M, T, R;
3115 u32 v_total, h_total;
3120 crtc.vxres = prom_getintdefault(node, "width", 1024);
3121 crtc.vyres = prom_getintdefault(node, "height", 768);
3122 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
3123 var->xoffset = var->yoffset = 0;
3124 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3125 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3126 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3127 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3128 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3129 aty_crtc_to_var(&crtc, var);
3131 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3132 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3135 * Read the PLL to figure actual Refresh Rate.
3137 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3138 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3139 for (i = 0; i < 16; i++)
3140 pll_regs[i] = aty_ld_pll_ct(i, par);
3143 * PLL Reference Divider M:
3148 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3150 N = pll_regs[7 + (clock_cntl & 3)];
3153 * PLL Post Divider P (Dependant on CLOCK_CNTL):
3155 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3169 * where R is XTALIN (= 14318 or 29498 kHz).
3171 if (IS_XL(pdev->device))
3178 default_var.pixclock = 1000000000 / T;
3184 #else /* __sparc__ */
3187 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3188 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3190 u32 driv_inf_tab, sig;
3193 /* To support an LCD panel, we should know it's dimensions and
3194 * it's desired pixel clock.
3195 * There are two ways to do it:
3196 * - Check the startup video mode and calculate the panel
3197 * size from it. This is unreliable.
3198 * - Read it from the driver information table in the video BIOS.
3200 /* Address of driver information table is at offset 0x78. */
3201 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3203 /* Check for the driver information table signature. */
3204 sig = (*(u32 *)driv_inf_tab);
3205 if ((sig == 0x54504c24) || /* Rage LT pro */
3206 (sig == 0x544d5224) || /* Rage mobility */
3207 (sig == 0x54435824) || /* Rage XC */
3208 (sig == 0x544c5824)) { /* Rage XL */
3209 PRINTKI("BIOS contains driver information table.\n");
3210 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3213 par->lcd_table = bios_base + lcd_ofs;
3217 if (par->lcd_table != 0) {
3220 char refresh_rates_buf[100];
3221 int id, tech, f, i, m, default_refresh_rate;
3226 u16 width, height, panel_type, refresh_rates;
3229 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3230 /* The most important information is the panel size at
3231 * offset 25 and 27, but there's some other nice information
3232 * which we print to the screen.
3234 id = *(u8 *)par->lcd_table;
3235 strncpy(model,(char *)par->lcd_table+1,24);
3238 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3239 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3240 panel_type = *(u16 *)(par->lcd_table+29);
3242 txtcolour = "colour";
3244 txtcolour = "monochrome";
3246 txtdual = "dual (split) ";
3249 tech = (panel_type>>2) & 63;
3252 txtmonitor = "passive matrix";
3255 txtmonitor = "active matrix";
3258 txtmonitor = "active addressed STN";
3264 txtmonitor = "plasma";
3267 txtmonitor = "unknown";
3269 format = *(u32 *)(par->lcd_table+57);
3270 if (tech == 0 || tech == 2) {
3271 switch (format & 7) {
3273 txtformat = "12 bit interface";
3276 txtformat = "16 bit interface";
3279 txtformat = "24 bit interface";
3282 txtformat = "unkown format";
3285 switch (format & 7) {
3287 txtformat = "8 colours";
3290 txtformat = "512 colours";
3293 txtformat = "4096 colours";
3296 txtformat = "262144 colours (LT mode)";
3299 txtformat = "16777216 colours";
3302 txtformat = "262144 colours (FDPI-2 mode)";
3305 txtformat = "unkown format";
3308 PRINTKI("%s%s %s monitor detected: %s\n",
3309 txtdual ,txtcolour, txtmonitor, model);
3310 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3311 id, width, height, txtformat);
3312 refresh_rates_buf[0] = 0;
3313 refresh_rates = *(u16 *)(par->lcd_table+62);
3316 for (i=0;i<16;i++) {
3317 if (refresh_rates & m) {
3319 sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3322 sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3324 strcat(refresh_rates_buf,strbuf);
3328 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3329 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3330 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3331 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3332 /* We now need to determine the crtc parameters for the
3333 * LCD monitor. This is tricky, because they are not stored
3334 * individually in the BIOS. Instead, the BIOS contains a
3335 * table of display modes that work for this monitor.
3337 * The idea is that we search for a mode of the same dimensions
3338 * as the dimensions of the LCD monitor. Say our LCD monitor
3339 * is 800x600 pixels, we search for a 800x600 monitor.
3340 * The CRTC parameters we find here are the ones that we need
3341 * to use to simulate other resolutions on the LCD screen.
3343 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3344 while (*lcdmodeptr != 0) {
3346 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3347 modeptr = bios_base + *lcdmodeptr;
3349 mwidth = *((u16 *)(modeptr+0));
3350 mheight = *((u16 *)(modeptr+2));
3352 if (mwidth == width && mheight == height) {
3353 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3354 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3355 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3356 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3357 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3358 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3360 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3361 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3362 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3363 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3365 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3366 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3367 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3368 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3374 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3375 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3376 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3377 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3383 if (*lcdmodeptr == 0) {
3384 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3385 /* To do: Switch to CRT if possible. */
3387 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3388 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3390 par->lcd_hdisp + par->lcd_right_margin,
3391 par->lcd_hdisp + par->lcd_right_margin
3392 + par->lcd_hsync_dly + par->lcd_hsync_len,
3395 par->lcd_vdisp + par->lcd_lower_margin,
3396 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3398 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3400 par->lcd_hblank_len - (par->lcd_right_margin +
3401 par->lcd_hsync_dly + par->lcd_hsync_len),
3403 par->lcd_right_margin,
3405 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3407 par->lcd_lower_margin,
3408 par->lcd_vsync_len);
3412 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3414 static int __devinit init_from_bios(struct atyfb_par *par)
3416 u32 bios_base, rom_addr;
3419 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3420 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3422 /* The BIOS starts with 0xaa55. */
3423 if (*((u16 *)bios_base) == 0xaa55) {
3426 u16 rom_table_offset, freq_table_offset;
3427 PLL_BLOCK_MACH64 pll_block;
3429 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3431 /* check for frequncy table */
3432 bios_ptr = (u8*)bios_base;
3433 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3434 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3435 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3437 PRINTKI("BIOS frequency table:\n");
3438 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3439 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3440 pll_block.ref_freq, pll_block.ref_divider);
3441 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3442 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3443 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3445 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3446 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3447 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3448 par->pll_limits.ref_div = pll_block.ref_divider;
3449 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3450 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3451 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3452 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3453 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3454 aty_init_lcd(par, bios_base);
3458 PRINTKE("no BIOS frequency table found, use parameters\n");
3461 iounmap((void* __iomem )bios_base);
3465 #endif /* __i386__ */
3467 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3469 struct atyfb_par *par = info->par;
3471 unsigned long raddr;
3472 struct resource *rrp;
3475 raddr = addr + 0x7ff000UL;
3476 rrp = &pdev->resource[2];
3477 if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3478 par->aux_start = rrp->start;
3479 par->aux_size = rrp->end - rrp->start + 1;
3481 PRINTKI("using auxiliary register aperture\n");
3484 info->fix.mmio_start = raddr;
3485 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3486 if (par->ati_regbase == 0)
3489 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3490 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3493 * Enable memory-space accesses using config-space
3496 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3497 if (!(tmp & PCI_COMMAND_MEMORY)) {
3498 tmp |= PCI_COMMAND_MEMORY;
3499 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3502 /* Use the big-endian aperture */
3506 /* Map in frame buffer */
3507 info->fix.smem_start = addr;
3508 info->screen_base = ioremap(addr, 0x800000);
3509 if (info->screen_base == NULL) {
3511 goto atyfb_setup_generic_fail;
3514 if((ret = correct_chipset(par)))
3515 goto atyfb_setup_generic_fail;
3517 if((ret = init_from_bios(par)))
3518 goto atyfb_setup_generic_fail;
3520 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3521 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3523 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3525 /* according to ATI, we should use clock 3 for acelerated mode */
3526 par->clk_wr_offset = 3;
3530 atyfb_setup_generic_fail:
3531 iounmap(par->ati_regbase);
3532 par->ati_regbase = NULL;
3536 #endif /* !__sparc__ */
3538 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3540 unsigned long addr, res_start, res_size;
3541 struct fb_info *info;
3542 struct resource *rp;
3543 struct atyfb_par *par;
3544 int i, rc = -ENOMEM;
3546 for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
3547 if (pdev->device == aty_chips[i].pci_id)
3553 /* Enable device in PCI config */
3554 if (pci_enable_device(pdev)) {
3555 PRINTKE("Cannot enable PCI device\n");
3559 /* Find which resource to use */
3560 rp = &pdev->resource[0];
3561 if (rp->flags & IORESOURCE_IO)
3562 rp = &pdev->resource[1];
3568 res_start = rp->start;
3569 res_size = rp->end - rp->start + 1;
3570 if (!request_mem_region (res_start, res_size, "atyfb"))
3573 /* Allocate framebuffer */
3574 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3576 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3580 info->fix = atyfb_fix;
3581 info->device = &pdev->dev;
3582 par->pci_id = aty_chips[i].pci_id;
3583 par->res_start = res_start;
3584 par->res_size = res_size;
3585 par->irq = pdev->irq;
3588 /* Setup "info" structure */
3590 rc = atyfb_setup_sparc(pdev, info, addr);
3592 rc = atyfb_setup_generic(pdev, info, addr);
3595 goto err_release_mem;
3597 pci_set_drvdata(pdev, info);
3599 /* Init chip & register framebuffer */
3600 if (aty_init(info, "PCI"))
3601 goto err_release_io;
3605 prom_palette = atyfb_palette;
3608 * Add /dev/fb mmap values.
3610 par->mmap_map[0].voff = 0x8000000000000000UL;
3611 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3612 par->mmap_map[0].size = info->fix.smem_len;
3613 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3614 par->mmap_map[0].prot_flag = _PAGE_E;
3615 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3616 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3617 par->mmap_map[1].size = PAGE_SIZE;
3618 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3619 par->mmap_map[1].prot_flag = _PAGE_E;
3620 #endif /* __sparc__ */
3626 kfree(par->mmap_map);
3628 if (par->ati_regbase)
3629 iounmap(par->ati_regbase);
3630 if (info->screen_base)
3631 iounmap(info->screen_base);
3635 release_mem_region(par->aux_start, par->aux_size);
3637 release_mem_region(par->res_start, par->res_size);
3638 framebuffer_release(info);
3643 #endif /* CONFIG_PCI */
3647 static int __devinit atyfb_atari_probe(void)
3649 struct atyfb_par *par;
3650 struct fb_info *info;
3654 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3655 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3656 !phys_guiregbase[m64_num]) {
3657 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3661 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3663 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3668 info->fix = atyfb_fix;
3670 par->irq = (unsigned int) -1; /* something invalid */
3673 * Map the video memory (physical address given) to somewhere in the
3674 * kernel address space.
3676 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3677 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3678 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3680 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3682 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3683 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3685 switch (clock_r & 0x003F) {
3687 par->clk_wr_offset = 3; /* */
3690 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3693 par->clk_wr_offset = 1; /* */
3696 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3700 if (aty_init(info, "ISA bus")) {
3701 framebuffer_release(info);
3702 /* This is insufficient! kernel_map has added two large chunks!! */
3708 #endif /* CONFIG_ATARI */
3710 static void __devexit atyfb_remove(struct fb_info *info)
3712 struct atyfb_par *par = (struct atyfb_par *) info->par;
3714 /* restore video mode */
3715 aty_set_crtc(par, &saved_crtc);
3716 par->pll_ops->set_pll(info, &saved_pll);
3718 #ifdef CONFIG_FB_ATY_BACKLIGHT
3719 if (M64_HAS(MOBIL_BUS))
3723 unregister_framebuffer(info);
3726 if (par->mtrr_reg >= 0) {
3727 mtrr_del(par->mtrr_reg, 0, 0);
3730 if (par->mtrr_aper >= 0) {
3731 mtrr_del(par->mtrr_aper, 0, 0);
3732 par->mtrr_aper = -1;
3736 if (par->ati_regbase)
3737 iounmap(par->ati_regbase);
3738 if (info->screen_base)
3739 iounmap(info->screen_base);
3741 if (info->sprite.addr)
3742 iounmap(info->sprite.addr);
3746 kfree(par->mmap_map);
3749 release_mem_region(par->aux_start, par->aux_size);
3752 release_mem_region(par->res_start, par->res_size);
3754 framebuffer_release(info);
3759 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3761 struct fb_info *info = pci_get_drvdata(pdev);
3767 * This driver uses its own matching table. That will be more difficult
3768 * to fix, so for now, we just match against any ATI ID and let the
3769 * probe() function find out what's up. That also mean we don't have
3770 * a module ID table though.
3772 static struct pci_device_id atyfb_pci_tbl[] = {
3773 { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3774 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3778 static struct pci_driver atyfb_driver = {
3780 .id_table = atyfb_pci_tbl,
3781 .probe = atyfb_pci_probe,
3782 .remove = __devexit_p(atyfb_pci_remove),
3784 .suspend = atyfb_pci_suspend,
3785 .resume = atyfb_pci_resume,
3786 #endif /* CONFIG_PM */
3789 #endif /* CONFIG_PCI */
3792 static int __devinit atyfb_setup(char *options)
3796 if (!options || !*options)
3799 while ((this_opt = strsep(&options, ",")) != NULL) {
3800 if (!strncmp(this_opt, "noaccel", 7)) {
3803 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3806 } else if (!strncmp(this_opt, "vram:", 5))
3807 vram = simple_strtoul(this_opt + 5, NULL, 0);
3808 else if (!strncmp(this_opt, "pll:", 4))
3809 pll = simple_strtoul(this_opt + 4, NULL, 0);
3810 else if (!strncmp(this_opt, "mclk:", 5))
3811 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3812 else if (!strncmp(this_opt, "xclk:", 5))
3813 xclk = simple_strtoul(this_opt+5, NULL, 0);
3814 else if (!strncmp(this_opt, "comp_sync:", 10))
3815 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3817 else if (!strncmp(this_opt, "vmode:", 6)) {
3818 unsigned int vmode =
3819 simple_strtoul(this_opt + 6, NULL, 0);
3820 if (vmode > 0 && vmode <= VMODE_MAX)
3821 default_vmode = vmode;
3822 } else if (!strncmp(this_opt, "cmode:", 6)) {
3823 unsigned int cmode =
3824 simple_strtoul(this_opt + 6, NULL, 0);
3828 default_cmode = CMODE_8;
3832 default_cmode = CMODE_16;
3836 default_cmode = CMODE_32;
3843 * Why do we need this silly Mach64 argument?
3844 * We are already here because of mach64= so its redundant.
3846 else if (MACH_IS_ATARI
3847 && (!strncmp(this_opt, "Mach64:", 7))) {
3848 static unsigned char m64_num;
3849 static char mach64_str[80];
3850 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3851 if (!store_video_par(mach64_str, m64_num)) {
3853 mach64_count = m64_num;
3864 static int __devinit atyfb_init(void)
3867 char *option = NULL;
3869 if (fb_get_options("atyfb", &option))
3871 atyfb_setup(option);
3875 pci_register_driver(&atyfb_driver);
3878 atyfb_atari_probe();
3883 static void __exit atyfb_exit(void)
3886 pci_unregister_driver(&atyfb_driver);
3890 module_init(atyfb_init);
3891 module_exit(atyfb_exit);
3893 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3894 MODULE_LICENSE("GPL");
3895 module_param(noaccel, bool, 0);
3896 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3897 module_param(vram, int, 0);
3898 MODULE_PARM_DESC(vram, "int: override size of video ram");
3899 module_param(pll, int, 0);
3900 MODULE_PARM_DESC(pll, "int: override video clock");
3901 module_param(mclk, int, 0);
3902 MODULE_PARM_DESC(mclk, "int: override memory clock");
3903 module_param(xclk, int, 0);
3904 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3905 module_param(comp_sync, int, 0);
3906 MODULE_PARM_DESC(comp_sync,
3907 "Set composite sync signal to low (0) or high (1)");
3908 module_param(mode, charp, 0);
3909 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3911 module_param(nomtrr, bool, 0);
3912 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
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